Semiconductor Devices

Abstract

To provide a semiconductor device suitable for miniaturization with high reliability.SOLUTION: A semiconductor device includes transistors 100 and 130, and a capacitor element 150. The transistor 100 includes a semiconductor layer 101. The semiconductor layer 101 exists over the capacitor element 150. The capacitor element 150 includes a plug 121 functioning as a first electrode electrically connected to the transistor 100.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The invention relates to the manufacture or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or any of these devices. The present invention relates to a driving method for the above-mentioned liquid crystal display device or a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "device" refers to a device in general. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. devices, storage devices, imaging devices, electro-optical devices, power generation devices (thin-film solar cells, organic thin-film solar cells) and the like), and electronic devices may include semiconductor devices. [Background technology]

[0003] The technology of constructing transistors using semiconductor materials is attracting attention. Electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) Silicon-based semiconductor materials are widely used as semiconductor materials for transistors. However, oxide semiconductors are attracting attention as other materials.

[0004] For example, zinc oxide or In-Ga-Zn oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating transistors using this method have been disclosed (see Patent Documents 1 and 2).

[0005] In recent years, with the increasing performance, miniaturization, and weight reduction of electronic devices, Demand is increasing for integrated circuits in which semiconductor elements such as transistors are densely integrated. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device that is suitable for miniaturization. An object of the present invention is to provide a semiconductor device with a reduced circuit area.

[0008] Another object is to provide a highly reliable semiconductor device. Another object of the present invention is to provide a memory device with good electrical characteristics. Another object of the present invention is to provide a semiconductor device having a novel structure. One of the objectives is to provide a facility for

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including a capacitor and a first transistor. The semiconductor device has a first semiconductor layer, the first semiconductor layer being located above a capacitance element, and the capacitance element is The semiconductor device has a first electrode electrically connected to a transistor. In this case, the capacitance element is composed of m layers (m is a natural number of 3 or more) of conductive layers and n layers (n is a natural number) The first insulating film is sandwiched between the first conductive layer and the second conductive layer, and the second insulating film is The first conductive layer is sandwiched between the second conductive layer and the third conductive layer, and the first conductive layer and the third conductive layer are electrically connected. It is preferable.

[0011] Alternatively, one embodiment of the present invention is a semiconductor device including a capacitor, a first transistor, and a second transistor. The first transistor has a first semiconductor layer, and the capacitance element has n layers (n is a natural number). ) insulating film and k layers (k is a natural number of 2 or more) of conductive layers, It is sandwiched between at least two conductive layers, and the first transistor is connected to the second transistor. The first semiconductor layer is located above the capacitor element, and the n-layer ( n is a natural number) is located between the first transistor and the second transistor, The capacitor has a first electrode connected to either the source or the drain of the first transistor. The semiconductor device has the following.

[0012] In the above structure, the insulating film of the n-layer is formed of at least one of hydrogen, water, and oxygen. In the above structure, the insulating film of the n-layer preferably has a function of blocking Silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, It is preferable that the material contains at least one of hafnium oxynitride and hafnium nitride.

[0013] In the above structure, the capacitor and the first transistor preferably overlap each other.

[0014] In the above structure, the first transistor has a first opening provided in the first semiconductor layer. Preferably, the first electrode is in contact with the first opening.

[0015] In the above structure, the first transistor has a first conductive layer and a second conductive layer. The first conductive layer and the second conductive layer are in contact with the first semiconductor layer, and the first transistor is active. An opening is provided in the first semiconductor layer and the first conductive layer, and the first electrode is It is preferable that the conductive layer and the opening provided in the first conductive layer are in contact with each other. [Effects of the Invention]

[0016] According to one embodiment of the present invention, a semiconductor device suitable for miniaturization can be provided. A semiconductor device with a reduced path area can be provided.

[0017] Furthermore, a highly reliable semiconductor device can be provided. Furthermore, a semiconductor device having a memory element with good retention characteristics can be provided. It is also possible to provide a semiconductor device with a novel configuration.

[0018] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other effects from the descriptions in the aspects and claims. [Brief explanation of the drawings]

[0019] [Figure 1] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A and 1B are a circuit diagram and a top view of a transistor according to one embodiment of the present invention. [Figure 6] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A and 1B are diagrams illustrating a band structure of a part of a transistor according to one embodiment of the present invention and a diagram illustrating a current path during conduction. [Figure 19]Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Figure 20] 1A and 1B are diagrams showing nanobeam electron diffraction patterns of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus; [Figure 21] An example of structural analysis using transmission electron diffraction measurements, and a planar TEM image. [Figure 22] FIG. 1 is a circuit diagram according to an embodiment. [Figure 23] 1 shows an example of the configuration of an RF tag according to an embodiment. [Figure 24] 1 shows an example of the configuration of a CPU according to an embodiment. [Figure 25] FIG. 2 is a circuit diagram of a memory element according to an embodiment. [Figure 26] 1A and 1B are a top view and a circuit diagram of a display device according to an embodiment. [Figure 27] 1. An electronic device according to an embodiment. [Figure 28] 10 shows an example of how an RF tag is used according to an embodiment. [Figure 29] FIG. 1 is a circuit diagram illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 30] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 31] 1A and 1B are diagrams showing semiconductor devices. [Figure 32] FIG. 1 is a top view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 33] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 34] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 35] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 36] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 37] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 38] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 39] Electron diffraction pattern of CAAC-OS. [Figure 40] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 41] Schematic diagram illustrating the film formation model of CAAC-OS and nc-OS. [Figure 42] A diagram explaining InGaZnO4 crystals and pellets. [Figure 43] Schematic diagram illustrating a film formation model of CAAC-OS. DETAILED DESCRIPTION OF THE INVENTION

[0020] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0021] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be assigned.

[0022] In each figure described in this specification, the size, layer thickness, or area of ​​each component is The figures may be exaggerated for clarity and are not necessarily limited to that scale. stomach.

[0023] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not a numerical limitation.

[0024] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be called an "insulator." In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily an "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0025] Also, even if a material is written as a "semiconductor," if the material has a sufficiently high conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily a "conductor" Similarly, the term "conductor" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0026] A transistor is a type of semiconductor device that controls the amplification of current and voltage, and conduction or non-conduction. In this specification, the transistor can be , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT) ) is included.

[0027] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°. refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0028] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0029] (Embodiment 1) [Example of laminated structure] An example of a stacked layer structure that can be applied to a semiconductor device of one embodiment of the present invention will be described below with reference to FIG. This will be explained using:

[0030] The stacked layer structure shown in FIG. 1A includes a transistor 100 and a capacitor 150. The transistor 100 is located above the capacitance element 150. The capacitance element 150 is also It is electrically connected to resistor 100.

[0031] The semiconductor layer 101 of the transistor 100 includes a low resistance region 171a and a low resistance region The low resistance region 171a and the low resistance region 171b may be a source region or a It is preferable that the low resistance region 171a and the low resistance region 171b function as a drain region. The resistive region 171b may be doped with impurities. The resistance of 101 can be reduced. The impurities to be added are, for example, argon and boron. , carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium, titanium Tungsten, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, germanium Aluminum, arsenic, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum One or more selected from the group consisting of tungsten, cerium, neodymium, hafnium, tantalum, and tungsten The low resistance region 171a and the low resistance region 171b are preferably doped with, for example, The above impurity element is introduced into the semiconductor layer 101 at a concentration of 5×10 19 atoms / cm 3 That's all, I prefer 1×10 20 atoms / cm 3 More preferably, 2 × 10 20 atoms / cm 3 More preferably, 5 × 10 20 atoms / cm 3 This is an area that includes the above.

[0032] The stacked layer structure illustrated in FIG. 1A may include a transistor 130. It is preferable to have a barrier film 111 between the transistor 100 and the transistor 130 . The capacitor element 150 has a conductive layer 151 and a conductive layer 152. The barrier film 111 is It has a structure sandwiched between conductive layers 152 .

[0033] Here, FIG. 1(B) shows a cross section taken along the dashed line AB shown in FIG. 1(A). The cross section at the dashed line AB is, for example, the cross section passing through the dashed line AB and shown in FIG. 1(A). It should be noted that in Figure 1(B), some reference numerals are omitted. However, for the parts indicated by the same hatching as in Figure 1(A), please refer to Figure 1(A), for example. stomach.

[0034] The transistor 130 is made of a first semiconductor material. 00 is configured to include a second semiconductor material. The first semiconductor material and the second semiconductor material are They may be made of the same material, but are preferably made of different semiconductor materials.

[0035] Semiconductors that can be used as the first or second semiconductor material include: , for example, semiconductor materials such as silicon, germanium, gallium, and arsenic; Compound semiconductor materials containing nium, gallium, arsenic, aluminum, etc., and organic semiconductor materials or an oxide semiconductor material.

[0036] Here, single crystal silicon is used as the first semiconductor material and oxide is used as the second semiconductor material. The case where a semiconductor is used will be described.

[0037] The transistor 100 includes a semiconductor layer 101 made of a second semiconductor material, a gate insulating film 1 02, a gate electrode 103, a plug 121 and a plug 122. The plug 12 and the insulating film 113 are formed to cover the transistor 100. The insulating film 113, the insulating film 112, and the semiconductor layer 101 are in contact with the openings formed therein. The plug 121 is connected to the capacitor 150. That is, the plug 121 is connected to the insulating film 113, the insulating film 112, and the and is formed to penetrate the semiconductor layer 101 .

[0038] The barrier film 111 has a function of preventing water and hydrogen from diffusing from the lower layer to the upper layer. It is preferable that the barrier film 111 has low oxygen permeability. The barrier film 111 is provided between an electrode or wiring provided above it and an electrode or It may have openings or plugs for electrical connection with wiring. For example, The plug 121 electrically connects to the conductive layer 151. The term "suppressing the diffusion of hydrogen" refers to, for example, silicon oxide, which is generally used as an insulating film. Compared to other materials, it is difficult for water and hydrogen to diffuse or has low permeability. Low permeability means that the permeability of oxygen is lower than that of silicon oxide, which is generally used as an insulating film. Indicates low permeability.

[0039] As with the barrier film 111, the insulating film 112 is preferably made of a material that does not easily diffuse water or hydrogen. In particular, it is preferable to use a material that is less permeable to oxygen for the insulating film 112. The insulating film 112 may have a stacked structure of two or more layers. The film 112 has a two-layer laminate structure, and the lower layer is made of, for example, silicon oxide, silicon oxynitride, or silicon nitride. Silicon nitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide The upper layer may be made of aluminum nitride or aluminum nitride. It is preferable to use a material in which hydrogen is difficult to diffuse. The insulating film 114 is a semiconductor film formed through the gate insulating film 102, which is an insulating film from which oxygen is released by heating, similar to the insulating film 114. Oxygen may also be supplied from above the conductor layer 101 .

[0040] By covering the semiconductor layer 101 with the insulating film 112 containing a material that is difficult for oxygen to permeate, This can prevent oxygen from being released from 101 above the insulating film 112. Furthermore, oxygen desorbed from the insulating film 114 can be confined below the insulating film 112. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

[0041] In addition, the insulating film 112, which is impermeable to water and hydrogen, prevents the oxide semiconductor from being exposed to the outside. The inclusion of impurities such as water and hydrogen can be suppressed, and fluctuations in the electrical characteristics of the transistor 100 can be reduced. This suppresses the generation of the ions, thereby achieving a highly reliable transistor.

[0042] Note that, below the insulating film 112, there is a film from which oxygen is desorbed by heating, similar to the insulating film 114. An insulating film is provided, and oxygen is supplied from above the semiconductor layer 101 via the gate insulating film 102. This may also be configured as follows.

[0043] In addition, the capacitor 150 is preferably formed so as to overlap with the transistor 100. By increasing the overlapping area between the capacitor element 150 and the transistor 100, The area of ​​the device can be reduced.

[0044] The semiconductor device shown in FIG. 1 has an insulating film 114 between the transistor 100 and the capacitor element 150. The insulating film 114 preferably contains an oxide. Preferably, the oxide material contains more oxygen than the stoichiometric composition. It is preferable to use an oxide containing a large amount of oxygen. When the insulating film 114 is used, oxygen released from the insulating film 114 is supplied to the oxide semiconductor. As a result, the electrical characteristics of the second transistor can be improved. Fluctuations can be suppressed and reliability can be improved.

[0045] Here, it is preferable to reduce hydrogen, water, etc. as much as possible in the layer below the barrier film 111. It is preferable to suppress the desorption of gases. Hydrogen and water are released from the oxide semiconductor. This may cause fluctuations in the electrical characteristics of the lower layer through the barrier film 111. The barrier film 111 can prevent hydrogen and water from diffusing from the barrier film 111 to the upper layer. Hydrogen and water may diffuse into the upper layer through openings, plugs, etc. provided in the film 111. do.

[0046] In order to reduce the amount of hydrogen and water contained in each layer located below the barrier film 111, In order to suppress the desorption of gases, the barrier film 111 is formed before or after the barrier film 111 is formed. Immediately after forming an opening for forming an electrical layer or the like, the water contained in the layer below the barrier film 111 is It is preferable to carry out a heat treatment to remove oxygen and water or to suppress desorption of gases. The heat resistance of conductive films constituting semiconductor devices and the electrical characteristics of transistors do not deteriorate. The higher the temperature of the heat treatment, the more preferable it is. The temperature is preferably 490°C or higher, more preferably 530°C or higher, but is preferably 650°C or higher. It may be carried out for 1 hour or more under an inert gas atmosphere or a reduced pressure atmosphere, preferably It is preferable to perform the heat treatment for 5 hours or more, more preferably 10 hours or more. The thickness may be determined by taking into consideration the heat resistance of the wiring or electrode material located below 11. For example, if the material has low heat resistance, the temperature should be 550°C or less, or 600°C or less, or 6 The temperature may be 50°C or less, or 800°C or less. It is sufficient to carry out this at least once, but it is more preferable to carry out this multiple times.

[0047] The insulating film provided below the barrier film 111 is analyzed by thermal desorption spectroscopy (TDS analysis). The amount of hydrogen molecules desorbed at a substrate surface temperature of 400°C measured by the At 0°C, the amount of hydrogen molecules released is preferably 130% or less, more preferably 110% or less. Alternatively, TDS analysis showed that the amount of desorption of hydrogen molecules at a substrate surface temperature of 450°C was 350 ° C., it is preferable that the amount of desorption is 130% or less, and more preferably 110% or less.

[0048] It is also preferable that the water and hydrogen contained in the barrier film 111 itself be reduced. For example, the barrier film 111 is preferably a film containing TDS molecules. The surface temperature of the substrate was measured by the analysis of hydrogen molecules (M / z=2) in the range of 20 to 600°C. The amount of desorption is 2×10 15 pieces / cm 2 Less than 1 x 10 15 pieces / cm 2 Less than, more than Preferably 5 x 10 14 pieces / cm 2 It is preferable to use a material for the barrier film 111 that has a resistance of less than 1000 MPa. Alternatively, TDS analysis shows that the water vapor deposition rate is higher in the range of 20℃ to 600℃. The desorption amount of the molecule (M / z=18) is 1×10 16 pieces / cm 2 Less than 5 x 10 1 5 pieces / cm 2 less than 2 x 10 12 pieces / cm 2 Barrier film material less than 1 It is preferable to use 11.

[0049] In addition, when single crystal silicon is used for the semiconductor layer of the transistor 130, the heat treatment The principle is to terminate the unpaired bonds (also called dangling bonds) of silicon with hydrogen. The hydrogenation process can also be used to remove the transistor 13. The water contained in the gate insulating film of 110 and other insulating films formed below the barrier film 111 Some of the atoms are released and diffuse into the semiconductor layer of the first transistor, forming dangling bonds in the silicon. By terminating the bond, the reliability of the first transistor can be improved.

[0050] Materials that can be used for the barrier film 111 include aluminum oxide, hafnium oxide, and the like. Titanium, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), steel titanate The so-called h, such as rontium (SrTiO3) or (Ba,Sr)TiO3 (BST) Insulating films containing igh-k materials can be used as a single layer or a laminate. The coating may be made of, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, or the like. Silicon, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, gas oxide Alternatively, these insulating films may be nitrided to form oxynitride films. Silicon oxide, silicon oxynitride, or silicon nitride is laminated on the insulating film. In particular, aluminum oxide is preferred because it has excellent barrier properties against water and hydrogen. stomach.

[0051] The barrier film 111 includes a layer of a material that is difficult for water and hydrogen to permeate, as well as a layer containing other insulating materials. For example, a layer containing silicon oxide or silicon oxynitride, a metal Layers containing oxides may be stacked.

[0052] Furthermore, it is preferable that the barrier film 111 is made of a material that is difficult for oxygen to permeate. The material has excellent barrier properties against oxygen as well as hydrogen and water. By using the insulating film 114, oxygen released when the insulating film 114 is heated is released to a lower layer than the barrier film 111. As a result, the diffusion of the ions from the insulating film 114 into the transistor can be suppressed. This increases the amount of oxygen that can be supplied to the semiconductor layer of the transistor 100.

[0053] In this way, the concentration of hydrogen and water contained in each layer located below the barrier film 111 is reduced. The barrier film 111 reduces the amount of hydrogen and water, or suppresses desorbed gases. This prevents hydrogen and water from diffusing into the transistor 100. The hydrogen and water contents in each layer constituting the transistor 100 are extremely low. For example, the insulating film 114, the semiconductor layer 101 of the transistor 100, or is the hydrogen concentration in the gate insulating film 102 is 5×10 18 cm -3 Less than 1x, preferably 10 18 cm -3 less than 3×10 17 cm -3 to reduce it to less than can be done.

[0054] With the above configuration, both the first transistor and the second transistor have high It is possible to achieve both high reliability and high reliability, thereby realizing a highly reliable semiconductor device.

[0055] The conductive layer 152 may be disposed so as to overlap the channel region of the transistor 100. An example of this case is shown in Figure 34(A) and Figure 34(B). Figure 34(B) shows the same as Figure 3 4(A) is a cross section taken along the dashed line AB. For example, the gate electrode may have the following function: By supplying a constant potential, the threshold voltage of the transistor 100 can be controlled. Yes, it is possible.

[0056] Further, an example of a stacked structure that can be applied to a semiconductor device of one embodiment of the present invention is shown in FIGS. 3, as shown in Figures 4(A) and (B). As shown in Figure 2, the capacitive element 150 is made up of three or more conductive layers. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b may be formed by laminating them. The capacitor element 150 is electrically connected via the plug 121, the plug 126, and the plug 127. Although not shown, the conductive layer 152, the conductive layer 154a and the conductive layer 154b form one of the electrodes. The electrode layer 154c is electrically connected to the capacitor element 150 and forms the other electrode of the capacitor element 150.

[0057] As shown in FIG. 3, a conductive layer may be formed on both sides of the plug 126 or the plug 127. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b are connected to the plug 121 and the plug 126. and electrically connected via a plug 127 to form one electrode of the capacitor element 150. Although not shown, the conductive layer 152, the conductive layer 152b, the conductive layer 154a, and the conductive layer 154 b, the conductive layer 154c and the conductive layer 154d are electrically connected to each other, and the other electrode of the capacitance element 150 forms a pole.

[0058] As shown in FIG. 4A, the transistor 100 has a conductive layer in contact with the semiconductor layer 101. 4(A) and 4(B) may have a conductive layer 104a and a conductive layer 104b. The cross section is taken along the dashed line AB. The conductive layer 104a and the conductive layer 104b are connected to the source electrode. The transistor 100 has a conductive layer 105 which functions as a gate electrode or a drain electrode. The conductive layer 105 may function as a second gate of the transistor 100. A voltage lower or higher than that of the source electrode is applied to the conductive layer 105, The threshold voltage may be shifted in a positive or negative direction. By shifting the threshold voltage of the transistor in the positive direction, the transistor In some cases, the transistor is in a non-conducting state (off state), which means that the transistor is normally off. The voltage applied to the conductive layer 105 may be variable or fixed. When the voltage applied to 105 is variable, a circuit for controlling the voltage is connected to the conductive layer 105. Good too.

[0059] The conductive layer 105 may be connected to the gate electrode 103 .

[0060] [Configuration example] FIG. 5A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device includes a transistor 100, a transistor 130, a capacitor element 150, and wiring. BL, wiring WL, and wiring CL.

[0061] One of the source and drain of the transistor 130 is electrically connected to the wiring BL, and the other The first side is electrically connected to the wiring SL, and the gate is connected to the source or drain of the transistor 100. The transistor 100 is electrically connected to one electrode of the capacitor 150. The other of the source and drain is electrically connected to the wiring BL, and the gate is electrically connected to the wiring WL. The other electrode of the capacitor 150 is electrically connected to the wiring CL. It is electrically connected to the second gate of the transistor 100. the source or drain of the transistor 100 and one of the electrodes of the capacitor 150. The node between the poles is called node FN.

[0062] The semiconductor device illustrated in FIG. 5A is arranged when the transistor 100 is in a conductive state (on state). A potential corresponding to the potential of the line BL is applied to the node FN. When the transistor is in the OFF state, the potential of the node FN is maintained. The semiconductor device shown in (A) functions as a memory cell of a memory device. The liquid crystal element and organic EL (Electroluminescence) When a display element such as a GaN film is included, the semiconductor device of FIG. 5A functions as a pixel of the display device. It can also be made to function.

[0063] The conductive state or non-conductive state of the transistor 100 is selected by applying a signal to the wiring WL or the wiring BG. It can be controlled by the potential applied to the wiring WL or the wiring BG. The threshold voltage of the transistor 100 can be controlled by the above. By using a transistor with a small off-state current, the node F Therefore, the potential of N can be maintained for a long period of time. Since the frequency of switching can be reduced, a semiconductor device with low power consumption can be realized. Note that a transistor including an oxide semiconductor is an example of a transistor with low off-state current. Sta. is mentioned.

[0064] The wiring CL is supplied with a constant potential such as a reference potential, a ground potential, or an arbitrary fixed potential. At this time, the apparent threshold voltage of the transistor 100 is The apparent threshold voltage fluctuation causes the conduction state of transistor 130 to change. By utilizing the change in the non-conducting state, the potential information held in the node FN is used as data. can be read out.

[0065] The potential held at node FN is 3.15×10 for 10 years at 85°C. 8 seconds) To maintain the capacitance, the off-state current per 1 fF and the channel width of the transistor per 1 μm must be The current value is 4.3 yA (1 yA is 10 -24 A) is preferably less than At this time, it is preferable that the allowable fluctuation in the potential of the node FN is within 0.5 V. Alternatively, it is preferable that the off-state current is less than 1.5 yA at 95°C. In the semiconductor device of the present invention, the hydrogen concentration in the layer below the barrier film is sufficiently reduced. As a result, the transistor using the oxide semiconductor in the upper layer has such an extremely low onset. A high current can be achieved.

[0066] In addition, by increasing the capacitance, the potential can be held at the node FN for a longer period of time. In other words, the retention time can be extended.

[0067] By arranging the semiconductor devices shown in FIG. 5A in a matrix, a memory device (memory cell Arrays) can be configured.

[0068] 6(A) and 6(B) show cross-sectional configurations of semiconductor devices that can realize the circuit shown in FIG. 5(A). 6(B) shows an example of the cross section taken along the dashed line AB shown in FIG.

[0069] The semiconductor device shown in FIGS. 6A and 6B includes a transistor 130 and a transistor 100. The transistor 100 is provided above the transistor 130. At least one barrier film is provided between the transistor 130 and the transistor 100. The semiconductor device may also have a plurality of barrier films. 1 and 2 show examples in which the semiconductor device has barrier films 111a to 111e. 5B shows a top view of the transistor 100. A cross section taken along dashed line XX' shown in FIG. is shown as the transistor 100 in FIG. 6A. Also, the dashed line Y-Y′ shown in FIG. A cross section of this is shown as a transistor 100 in FIG.

[0070] [First Transistor] The transistor 130 is provided on a semiconductor substrate 131 and is made up of a part of the semiconductor substrate 131. The semiconductor layer 132, the gate insulating film 134, the gate electrode 135, and the source region or drain region are The low resistance layer 133a and the low resistance layer 133b function as an in-region. The illustrated semiconductor device may include a transistor 160. The transistor 160 is a transistor. The capacitor 130 is mounted on a semiconductor substrate 131 .

[0071] The transistor 130 may be either a p-channel type or an n-channel type, depending on the circuit configuration and An appropriate transistor may be used depending on the driving method.

[0072] The region where the channel of the semiconductor layer 132 is formed and the region nearby, the source region or the drain region In the low resistance layer 133a and the low resistance layer 133b which become the drain region, a silicon-based semiconductor It is preferable that the semiconductor material contains a semiconductor such as silicon dioxide, and it is preferable that the semiconductor material contains single crystal silicon. e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may be formed of a material having a crystal structure such as GaAlAs (gallium aluminum arsenide). The structure may be made of strained silicon, or GaAs and AlGaAs, etc. By using the above, the transistor 130 is a HEMT (High Electron Mob It may also be called a "ability transistor."

[0073] Transistor 130 also includes region 176, which is an LDD (lightly doped drain) region. a and region 176b.

[0074] The low resistance layer 133a and the low resistance layer 133b are made of a semiconductor material applied to the semiconductor layer 132. In addition, elements that impart n-type conductivity, such as phosphorus, or p-type conductivity, such as boron, are added. Contains elements that

[0075] The gate electrode 135 is made of an element that provides n-type conductivity, such as phosphorus, or a p-type element, such as boron. Semiconductor materials such as silicon containing elements that impart electrical conductivity, metal materials, alloy materials, or Conductive materials such as metal oxide materials can be used. In particular, It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. It is preferable to use a ten.

[0076] Here, instead of the transistor 130 and the transistor 160, a transistor as shown in FIG. A transistor 190 and a transistor 191 may be used. The cross section shown in FIG. 16B is a cross section of the transistor 190 and the transistor 191. The semiconductor layer 132 (part of the semiconductor substrate) in which the channel is formed has a convex shape, and its side surfaces and A gate insulating film 134 and a gate electrode 135 are provided along the upper surface of the semiconductor substrate 130. The transistors 190 and 191 utilize the protruding portions of the semiconductor substrate. Therefore, it is also called a FIN type transistor. In this case, a part of the semiconductor substrate may have an insulating film that functions as a mask. The case where a convex portion is formed by processing is shown, but the semiconductor layer having a convex shape by processing the SOI substrate is also shown. may be formed.

[0077] The transistor 130 is covered with an insulating film 136, an insulating film 137, and an insulating film 138 in this order. They are provided in a stacked manner.

[0078] The insulating film 136 is formed by insulating the low resistance layer 133a and the low resistance layer 133b during the manufacturing process of the semiconductor device. The insulating film 13 functions as a protective film when activating the conductive element added to b. 6 may not be provided if not required.

[0079] When the semiconductor layer 132 is made of a silicon-based semiconductor material, the insulating film 137 is made of an insulating material containing hydrogen. The insulating film 137 containing hydrogen is provided over the transistor 130, and By performing heat treatment, hydrogen in the insulating film 137 causes dangling bonds in the semiconductor layer 132 to is terminated, which can improve the reliability of the transistor 130.

[0080] The insulating film 138 smooths out any steps caused by the transistor 130 and other components disposed below it. The upper surface of the insulating film 138 functions as a planarizing layer to improve the flatness of the upper surface. For this purpose, CMP (Chemical Mechanical Polishing) method is used. The surface may be planarized by a planarization process.

[0081] The insulating films 136, 137, and 138 are provided with the low resistance layer 133a and the low resistance layer 133b. a plug 140 electrically connecting to the gate electrode 135 of the transistor 130 and the like; A plug 139 or the like may be embedded to provide an electrical connection.

[0082] [Capacitive element] A barrier film 111 is provided between the transistor 130 and the transistor 100. The barrier film may be a single layer or may be a multi-layer as shown in FIG. 6. In the example of the semiconductor device shown in FIG. 1, five layers of barrier films 111a to 111e are provided. When a barrier film is used as an insulating film for a capacitance element, the capacitance can be increased by making the film thickness thinner. On the other hand, there is a risk that the barrier properties may be reduced by making the film thinner. Therefore, by stacking multiple thin barrier films, the capacity can be increased and the barrier properties can be improved. This can improve the characteristics of the transistor 100 and the transistor 130. can.

[0083] Conductive layer 151, conductive layer 152, conductive layer 153a, and conductive layer 153 are formed on either side of the barrier film. b and conductive layers 154a to 154e are provided to form the capacitor 150. The plug 121, the plug 126 and the plug 127 are electrically connected. 26 is provided in an opening formed in the barrier film 111b, the insulating film 115b and the barrier film 111c. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b are connected to the plug 127 and the plug. The plug 126 is electrically connected to the conductive layer 104a of the transistor 100 via the plug 121. The conductive layer 151 is formed so as to fill the opening provided in the insulating film 115a. Similarly, the conductive layers 154a and 154b are connected to the insulating film 115b, and the conductive layer 153a is connected to the insulating film 115b. The insulating film 115c is provided with the conductive layer 154c and the conductive layer 154d is provided with the insulating film 115d. The insulating film 115e is formed with the insulating film 53b so as to be embedded in the openings provided therein. .

[0084] 7 shows a cross section taken along the dashed line CD in FIG. The conductive layer 154b and the conductive layer 154d are electrically connected to the plug 128. The plug 128 is electrically connected to the plug 129 through the plugs 129a to 129d. 28 is connected to wiring 142 via a plug 141.

[0085] An insulating film 114 is provided to cover the barrier film 111, the conductive layer 152, the conductive layer 154e, etc. are.

[0086] The top surface of the insulating film 114 is preferably planarized by the above-described planarization treatment.

[0087] The insulating film 114 is preferably formed using an oxide material from which oxygen is partly released by heating. .

[0088] As an oxide material that releases oxygen by heating, it is possible to It is preferable to use an oxide containing more oxygen than the stoichiometric composition. When an oxide film containing oxygen is heated, some of the oxygen is released. Oxide films containing more oxygen than Oxygen converted to oxygen atoms in the ion absorption spectroscopy analysis The amount of desorption is 1.0×10 18 atoms / cm 3 or more, preferably 3.0 × 10 20 at oms / cm3 The oxide film is as described above. The temperature is preferably in the range of 100°C to 700°C, or 100°C to 500°C. stomach.

[0089] For example, such a material may include silicon oxide or silicon oxynitride. Alternatively, a metal oxide can be used. Aluminum, aluminum oxynitride, gallium oxide, gallium oxynitride, yttria Usable are yttrium oxide nitride, hafnium oxide, hafnium oxide nitride, etc. In this specification, silicon oxynitride refers to a material containing more oxygen than nitrogen as its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. Indicates the material with the highest content.

[0090] [Second Transistor] On top of the insulating film 114, the semiconductor layer 101 of the transistor 100 is provided.

[0091] The transistor 100 includes a semiconductor layer 101 in contact with the upper surface of an insulating film 114 and a conductive layer 104. a and conductive layer 104b, and a gate insulating film 102 on the semiconductor layer 101, and a gate insulating film 10 The transistor 1 has a gate electrode 103 that overlaps with the semiconductor layer 101 via the gate electrode 103. 00, insulating films 112, 113, and 116 are provided. The transistor 100 may have a conductive layer 105 that functions as a second gate electrode. .

[0092] The semiconductor layer 101 may be formed as a single layer. 00, a stacked structure of semiconductor layers 101a, 101b, and 101c The transistor 100 shown in FIG. The semiconductor layer 101b is in contact with the upper surface of the semiconductor layer 101a, and the semiconductor layer 101b is in contact with the upper surface of the semiconductor layer 101b. The conductive layer 104a and the conductive layer 104b are separated in the region overlapping with the semiconductor layer 101b. A semiconductor layer 101c is in contact with the upper surface of the conductor layer 101b, and a gate insulating film is formed on the semiconductor layer 101c. 102 and the semiconductor layer 101b via the gate insulating film 102 and the semiconductor layer 101c. The transistor 100 shown in FIG. The conductive layer 105 functions as an electrode. The conductive layer 105 forms a part of the capacitor 150. The semiconductor layer 101a may be formed simultaneously with the insulating film 114 and the conductive layer 152. The semiconductor layer 101c is provided between the semiconductor layer 101b and the gate electrode 101c. The conductive layer 104a and the conductive layer 104b are provided between the gate insulating film 102. , contacts the upper surface of the semiconductor layer 101b and contacts the lower surface of the semiconductor layer 101c.

[0093] The transistor 100 is covered with insulating films 112, 113, and 116. It is provided.

[0094] As shown in FIG. 6A, the side surface of the semiconductor layer 101b is connected to the conductive layer 104a and the conductive layer 104b. The electric field of the gate electrode 103 electrically connects the semiconductor layer 101b to the gate electrode 104b. The electric field of a conductor can electrically surround a semiconductor. This structure is called the surrounded channel (s-channel) structure. Therefore, a channel may be formed in the entire semiconductor layer 101b (bulk). The s-channel structure allows a large current to flow between the source and drain of the transistor. This allows the current (on-state current) to be increased during conduction.

[0095] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. Preferably, the transistor has a channel width of 20 nm or less. or 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. It has a region.

[0096] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is in the on state). The source (source region or source electrode) in the region where the channel is formed. The distance between the transistor and the drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one of the values, maximum and minimum, in the region where the channel is formed. The value is the average value.

[0097] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the gate electrode (the area where current flows) or the area where the channel is formed. The length of the part where the source and drain face each other is called the length of one transistor. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one of the values, maximum and minimum, in the region where the channel is formed. The value is the average value.

[0098] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in a transistor with a fine, three-dimensional structure, the upper surface of the semiconductor The ratio of the channel region formed on the side of the semiconductor to the ratio of the channel region formed on the inside of the semiconductor In this case, the apparent channel width shown in the top view may be The effective channel width where the channel is actually formed is larger than the actual channel width.

[0099] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width if the channel conditions are not precisely known. .

[0100] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent thickness is the length of the part where the source and drain face each other in the region where the The channel width is referred to as "Surrounded Channel Width (SCW)". In this specification, when simply referred to as the channel width, This may refer to the enclosed channel width or apparent channel width. In the detailed description, when simply referred to as a channel width, it may refer to an effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, and enclosure The channel width can be determined by acquiring a cross-sectional TEM image and analyzing the image. , values ​​can be determined.

[0101] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0102] At least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) ) is a surface or side of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). The surface is provided on at least a part (or all) of the face, upper face, and / or lower face.

[0103] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) The surface of the semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), In contact with at least a portion (or all) of the side, top, and / or bottom surfaces; or At least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) At least a portion of the semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a) or all of the above.

[0104] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) The surface of the semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), It is electrically connected to at least a part (or all) of the side, top, and / or bottom surfaces. Alternatively, at least a portion (or All of the semiconductor layers (including the semiconductor layer 101b and / or the semiconductor layer 101a) are The wiring is electrically connected to a part (or all) of the wiring.

[0105] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) The surface of the semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), Located adjacent to at least a part (or all) of the side, top, and / or bottom surfaces. Alternatively, at least a portion (or All of the semiconductor layers (including the semiconductor layer 101b and / or the semiconductor layer 101a) are Some (or all) of them are located close to each other.

[0106] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) The surface of the semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), It is disposed laterally on at least a portion (or all) of the side, top, and / or bottom surfaces. Alternatively, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) ) is at least one of the semiconductor layers such as the semiconductor layer 101b (and / or the semiconductor layer 101a). It is located on part (or all) of the side.

[0107] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) The surface of the semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), It is arranged diagonally above at least a part (or all) of the side, top, and / or bottom surfaces. Alternatively, at least a portion (or All of the semiconductor layers (including the semiconductor layer 101b and / or the semiconductor layer 101a) are Both are located diagonally above part (or all) of the

[0108] Alternatively, at least a part (or the whole) of the conductive layer 104a (and / or the conductive layer 104b) The surface of the semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), It is disposed above at least a portion (or all) of the side, top, and / or bottom surfaces. Alternatively, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) ) is at least one of the semiconductor layers such as the semiconductor layer 101b (and / or the semiconductor layer 101a). It is located on the upper side of part (or all) of the

[0109] The semiconductor layer 101 is made of a semiconductor such as a silicon-based semiconductor in a region where a channel is formed. In particular, the semiconductor layer 101 may contain a material having a band gap larger than that of silicon. Preferably, the semiconductor layer 101 includes an oxide semiconductor. A semiconductor material with a wider band gap and lower carrier density than silicon is called The use of such a compound is preferable because it can reduce the current in the off state of the transistor.

[0110] By using such materials for the semiconductor layer, fluctuations in electrical characteristics are suppressed, and reliability is improved. High-performance transistors can be realized.

[0111] The preferred oxide semiconductors applicable to the semiconductor layer and their forming methods are as follows: This will be explained in detail in a later embodiment.

[0112] In this specification and the like, when the term "substantially intrinsic" is used, the carrier density of the oxide semiconductor layer is , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 x 10 13 / cm 3 less than 8 × 10 11 / cm 3 less than 1×10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 End By making the oxide semiconductor layer highly purified and intrinsic, it is possible to form a stable transistor. Electrical properties can be imparted.

[0113] The semiconductor layer 101b may be formed of, for example, In:Ga:Zn=1:1:1 or 3:1:2. When using an In-Ga-Zn-based oxide with an atomic ratio, semiconductor layer 101a or semiconductor layer 10 1c can be, for example, an In-Ga-Zn-based oxide with an atomic ratio such as In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1:6: 4, 1:6:8, 1:6:10, or 1:9:6. Note that the atomic ratios of semiconductor layer 101b, semiconductor layer 101a, and semiconductor layer 101c each include a variation of plus or minus 20% of the above atomic ratio as an error. Also, semiconductor layer 101a and semiconductor layer 101c may use materials with the same composition or materials with different compositions.

[0114]

[0115]

[0116]

[0117] It is preferable to use an oxide having an atomic ratio of 1 to 6. By setting the value of the target to 6 or less, the CAAC-OS film described later can be easily formed. Typical examples of atomic ratios of metal elements are In:M:Zn=1:3:4, 1:3:6, 1: Examples include 3:8.

[0116] When oxide semiconductors are deposited by sputtering, the atomic ratio of the target may deviate from the target atomic ratio. In particular, zinc may form a film with a higher atomic ratio than the target. Specifically, the ratio of the number of atoms of zinc contained in the target to 4 may become smaller. It may be between 0 atomic% and 90 atomic%.

[0117] One of the conductive layers 104a and 104b functions as a source electrode and the other functions as a drain electrode. It functions as an electrode.

[0118] The plug 121 is formed by the conductive layer 104a, the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c. 01c, the conductive layer 151 is electrically connected to the insulating film 114 through an opening provided in the barrier film 111. The conductive layer 104a is electrically connected to the conductive layer 151 via the plug 121. Connect to.

[0119] The conductive layer 104a and the conductive layer 104b are made of aluminum, titanium, chromium, nickel, copper, or the like. , yttrium, zirconium, molybdenum, silver, tantalum, or tungsten Metals or alloys containing metals as the main component are used in a single layer structure or a multilayer structure. For example, Single layer structure of aluminum film containing silicon, two layer structure of aluminum film laminated on titanium film Two-layer structure with aluminum film laminated on tungsten film, copper-magnesium-aluminum Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film, Two-layer structure in which a copper film is laminated on a titanium film or titanium nitride film and the titanium An aluminum film or a copper film is laminated on the titanium nitride film or the titanium nitride film, and then a titanium film or a copper film is laminated on the aluminum film or the copper film. A three-layer structure in which a titanium film or titanium nitride film is formed, a molybdenum film or molybdenum nitride film, and An aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film. There is also a three-layer structure in which a molybdenum film or a molybdenum nitride film is formed on top of the above. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0120] The gate insulating film 102 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, nitride Silicon or the like may be used, and the layer may be a laminated layer or a single layer.

[0121] The gate insulating film 102 is made of hafnium silicate (HfSiO x ), nitrogen is added Added hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium Luminate (HfAl x O y N z ), using high-k materials such as yttrium oxide Good too.

[0122] The gate insulating film 102 may be made of aluminum oxide, magnesium oxide, or silicon oxide. Silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, silicon oxide oxides such as tantalum oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide insulating film, silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide The insulating film can be formed using a nitride insulating film such as the above, or a film made of a mixture of the above materials.

[0123] The gate insulating film 102 is made of an acid having a stoichiometric composition, similar to the insulating film 114. It is preferable to use an oxide insulating film containing more oxygen than silicon.

[0124] In addition, when a specific material is used for the gate insulating film, electrons are captured in the gate insulating film under specific conditions. For example, silicon oxide and hafnium oxide can be used to increase the threshold voltage. Like the stacked film of hafnium, a part of the gate insulating film is made of hafnium oxide, aluminum oxide, and oxide. By using a material with many electron capture levels, such as tantalum, and by using it at a higher temperature (the operating temperature of the semiconductor device), Or higher than the storage temperature, or 125°C or higher and 450°C or lower, typically 1 Under the temperature range of 50°C to 300°C, the potential of the gate electrode is set to the potential of the source electrode and drain electrode. By maintaining a higher state for at least one second, typically at least one minute, the gate voltage is released from the semiconductor layer. Electrons move towards the poles, and some of them are captured by the electron capture levels.

[0125] In this way, a transistor that has captured the necessary number of electrons in the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The process for adding the conductive layer may be performed during the manufacturing process of the transistor.

[0126] For example, forming wiring metal that connects to the source electrode or drain electrode of a transistor After the wafer processing, or after the wafer dicing process. It is advisable to carry out this at any stage before shipping from the factory, such as after packaging. It is preferred that the subsequent exposure to temperatures above 125°C is not carried out for more than one hour.

[0127] The gate electrode 103 is made of, for example, aluminum, chromium, copper, tantalum, titanium, or molybdenum. a metal selected from the group consisting of tungsten, tungsten, or an alloy containing the above-mentioned metals, or It can be formed by using an alloy of metals. In addition, impurity elements such as phosphorus may be used. Semiconductors such as polycrystalline silicon doped with silicon, and silicides such as nickel silicide The gate electrode 103 may have a single layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a silicon film on an aluminum film, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film, titanium nitride Two-layer structure with tungsten film stacked on top of film, tantalum nitride film or tungsten nitride film A two-layer structure with a tungsten film laminated on top of the titanium film, and an aluminum film on top of the titanium film. There are three-layer structures, such as a laminated aluminum film and a titanium film on top of that. Choose from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium An alloy film made of one or more of the above metals or a nitride film may also be used.

[0128] The gate electrode 103 is made of indium tin oxide or indium containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as indium tin oxide may also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0129] In addition, an In-Ga-Zn-based oxynitride semiconductor is formed between the gate electrode 103 and the gate insulating film 102. Conductor film, In-Sn oxynitride semiconductor film, In-Ga oxynitride semiconductor film, In-Zn Oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (I These films may have a resistivity of 5 eV or more, preferably 5.5 eV or more. Since the work function is higher than the electron affinity of the oxide semiconductor, The threshold voltage of the transistor using the material can be shifted to the positive side, For example, an In-Ga-Zn oxynitride semiconductor can be used. When a semiconductor film is used, the nitrogen concentration is at least higher than that of the semiconductor layer 101, specifically, 7 atomic % or more. The above In-Ga-Zn oxynitride semiconductor film is used.

[0130] The insulating film 112 may be made of a material that is difficult for water and hydrogen to diffuse into, similar to the barrier film 111. It is particularly preferable to use a material that is less permeable to oxygen for the insulating film 112. It's nice.

[0131] By covering the semiconductor layer 101 with the insulating film 112 containing a material that is difficult for oxygen to permeate, This can prevent oxygen from being released from 101 above the insulating film 112. Furthermore, oxygen desorbed from the insulating film 114 can be confined below the insulating film 112. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

[0132] In addition, the insulating film 112, which is impermeable to water and hydrogen, prevents the oxide semiconductor from being exposed to the outside. The inclusion of impurities such as water and hydrogen can be suppressed, and fluctuations in the electrical characteristics of the transistor 100 can be reduced. This suppresses the generation of the ions, thereby achieving a highly reliable transistor.

[0133] Note that, below the insulating film 112, there is a film from which oxygen is desorbed by heating, similar to the insulating film 114. An insulating film is provided, and oxygen is supplied from above the semiconductor layer 101 via the gate insulating film 102. This may also be configured as follows.

[0134] As shown in FIG. 6B, in the cross section of the transistor in the channel width direction, The electrode 103 is provided on the upper surface and side surfaces of the semiconductor layer 101b, The channel is formed not only near the top surface of 01b but also near the side surface, and the effective channel width is In particular, the semiconductor layer 10 The width of 1b is extremely small (for example, 50 nm or less, preferably 30 nm or less, more preferably In the case where the thickness is 20 nm or less, the region where the channel is formed extends to the inside of the semiconductor layer 101b. As the size of the device decreases, its contribution to the on-current increases.

[0135] 17A and 17B illustrate an example of a transistor 100 included in a semiconductor device. The transistor 100 shown in Figs. 17(A) and 17(B) is the same as the transistor 100 shown in Fig. 6. In comparison, the semiconductor layer 101c is provided in contact with the lower surfaces of the conductive layers 104a and 104b. The main difference is that the dashed line A in FIG. 17(A) is used. -B is the cross section.

[0136] With this configuration, the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 10 When forming each film that makes up 1c, the films are formed continuously without being exposed to the atmosphere. Therefore, the number of interface defects can be reduced.

[0137] The transistor 100 may have the structure shown in FIG. After forming the semiconductor layer 101a and the semiconductor layer 101b, the semiconductor layer 101c is formed. The side surfaces of the semiconductor layer 101a and the semiconductor layer 101b are covered with the semiconductor layer 101c. The transistor 100 may have a structure shown in FIG. 35(B). 35(A) is different from FIG. 35(A) in that the gate electrode 103, the conductive layer 104a, and the gate The electrode 103 and the conductive layer 104b are overlapped, whereas in FIG. 35(B) the gate electrode 1 The conductive layer 104a and the conductive layer 104b do not overlap in the cross section shown in FIG. Not possible.

[0138] 6(A), (B) and 17(A), (B), the semiconductor layer 101b is in contact with the semiconductor layer 101b. The configuration in which the conductor layer 101a and the semiconductor layer 101c are provided has been described. Alternatively, one or both of the semiconductor layers 101c may be omitted.

[0139] In the configuration shown in FIG. 6B, the end portions of the gate insulating film 102 and the semiconductor layer 101c are roughly The gate electrode 103 is positioned inside the gate insulating film. As an example of a transistor 100 shown in FIG. 17(C), the gate insulating layer The insulating film 102, the semiconductor layer 101c, and the gate electrode 103 are processed so that their edges are approximately aligned. Alternatively, as in the example of the transistor 100 shown in FIG. The insulating film 102, the semiconductor layer 101c, and the gate electrode are heated so that their edges do not coincide with each other. It may be possible to carry out construction work.

[0140] This concludes the description of transistor 100.

[0141] The insulating film 116 covering the transistor 100 serves as a planarizing layer that covers the uneven shape of the underlying layer. The insulating film 113 also functions as a protective film when the insulating film 116 is formed. The insulating film 113 may not be provided if it is not necessary.

[0142] The insulating film 112, the insulating film 113, and the insulating film 116 are provided with a conductive layer 104b. Plugs 123, 122, etc. are embedded.

[0143] On the insulating film 116, wiring 124 and the like are provided to electrically connect with the plug 123. There are.

[0144] Here, the wiring 124 shown in FIG. 6A corresponds to the wiring BL shown in FIG. 5. Similarly, The wiring 166 shown in (B) corresponds to the wiring BG, and the wiring 142 shown in FIG. 7 corresponds to the wiring CL. Although not shown, the wiring connected to the gate electrode 103 in FIG. 6 corresponds to the wiring WL. The low resistance layer 133b of the transistor 130 corresponds to the wiring SL. the gate electrode 135 of the capacitor 130, and the plug 121 which functions as the first electrode of the capacitor element 150. , and the node including the conductive layer 104a of the transistor 100 is a node F shown in FIG. Equivalent to N.

[0145] 6, the insulating film 137 provided on the insulating film 136 containing hydrogen is a burr It is preferable to provide an insulating film 137 containing the same material as the insulating film 111. By adopting such a configuration, water and hydrogen remaining in the insulating film 136 containing hydrogen are diffused upward. In this case, the insulating film 137 is formed before and after the insulating film 137 is formed. After forming the barrier film 137 and before forming the barrier film 111, water and hydrogen are removed. The heat treatment for this purpose may be carried out two or more times in total.

[0146] The wirings such as the wiring 124, the wiring 142, the wiring 166, etc. are made of a metal material, an alloy material, or In particular, conductive materials such as metal oxide materials can be used. It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. It is preferable to use stainless steel.

[0147] In addition, the conductive layer 125, the conductive layer 151, the conductive layer 152, the conductive layer 153a, and the conductive layer 153b , conductive layers such as the conductive layers 154a to 154e, plugs 121 to 123, plugs Plug 126 to plug 128, plug 129a to plug 129d, plug 139 to plug The plugs such as the lug 141, the plug 164, and the plug 165 are made of metal materials, alloy materials, etc. In particular, materials having heat resistance and conductivity such as metal oxide materials can be used. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both excellent thermal conductivity and good thermal conductivity. It is preferable to use tungsten. Also, materials such as titanium nitride and titanium can be used in place of other materials. For example, by using titanium nitride or titanium, In addition, the adhesiveness of the conductive layer 125, the conductive layer 151, the conductive layer 152, Conductive layers such as the conductive layer 153a, the conductive layer 153b, and the conductive layers 154a to 154e, and Lugs 121 to 123, plugs 126 to 128, plugs 129a to 129b 9d, plugs 139 to 141, plug 164, plug 165, etc. It is preferable that they are embedded in the velum and that the upper surface of each is flattened.

[0148] Here, the plug 121 is connected to the semiconductor layer 101, the conductive layer 104a, and the First, the semiconductor layer 101 and the conductive layer 102 of the transistor 100 are in contact with each other. 4a, which is connected to the source region or drain region of the transistor 100. In addition, by being in contact with the conductive layer 151, The plug 121 penetrates the transistor 100 and functions as a wiring that connects to the electrode. By reaching the conductive layer 151, which is one electrode of the element 150, The electrode of the capacitor 150 is connected to the source region or the drain region of the transistor 100. It can also serve as wiring.

[0149] Similarly, the plug 122 connects the semiconductor layer 101, the conductive layer 104b and the First, the semiconductor layer 101 and the conductive layer 102 of the transistor 100 are in contact with each other. 4b, which is connected to the source or drain region of the transistor 100. In addition, the conductive layer 125 functions as a wiring. The plug 122 functions as a wiring connecting to the source region or the drain region of the transistor. By passing through the transistor 100 and reaching the conductive layer 125, a single plug can be used to connect the transistor The wiring connected to the source region or drain region of the transistor 130 and the wiring connected to the source region or drain region of the transistor 100 are connected to the wiring connected to the source region or drain region of the transistor 130. The insulating film can also serve as a wiring connected to the source electrode or drain electrode.

[0150] Next, an example in which the circuit area can be reduced by using the plugs 121 and 122 will be explained with reference to FIG. 31 does not use the plug 121 and the plug 122. For the barrier film 211a, refer to the description of the barrier film 111. The insulating film 115a is described with reference to the insulating film 115a. The contact 221 with the semiconductor layer 50 is formed outside the semiconductor layer 101b. Similarly, the conductive layer 104b and the source region of the transistor 130 Alternatively, the contact 222 with the conductive layer connected to the drain region is formed on the semiconductor layer 101b. It is formed on the outside, which increases the device area.

[0151] In the example of the configuration shown in FIG. 30A, one side of the capacitor 150 is connected through the transistor 100. a plug 121 that connects to the electrode of the transistor 100 and the electrode of the transistor 130; A plug 12 connected to the conductive layer 251a electrically connected to the source electrode or the drain region 2 is used. The barrier films 211a to 211f are the same as those of the barrier film 111. For the insulating films 215a to 215f, see the description of the insulating film 115a. The conductive layer 251 is the same as the conductive layer 151. The conductive layer 251a is the same as the conductive layer 12. Please refer to the description of 5. Note that FIG. 30(B) is a diagram in which two of the configurations shown in FIG. 30(A) are arranged side by side. 30 shows an example in which the conductive layer 104a and the conductive layer 104b are not provided. However, it may be provided.

[0152] In FIG. 31, the contact 221 between the conductive layer 104a and the capacitor element 150 and the plug Since two contacts are provided, 321 and contact 223 of conductive layer 104a, On the other hand, in FIG. 30, the plug 121 can serve as the two contacts. Similarly, in FIG. 31, a contact 222 between the conductive layer 104b and the conductive layer 251a, Two contacts are provided: a plug 322 and a contact 224 to the conductive layer 104b. 30, the role of the two contacts is played by the plug 122. In this way, by using the plug 121 and the plug 122, the structure shown in FIG. In the fabrication, the capacitor element 150 can be fabricated with a width similar to that of the transistor 100. The footprint of the child can be reduced.

[0153] Next, in the cross-sectional view shown in FIG. 30, a top view of the layers 281 to 287 is shown in FIG. 32(A). 31. In addition, in the cross-sectional view shown in FIG. 31, a top view of the layers 291 to 295 is shown in FIG. 32(B). Each top view shows the minimum structural unit of a memory cell. By doing so, it can be seen that the area can be reduced to about half compared to FIG.

[0154] Also, as shown in the cross section of the semiconductor device in FIG. 33, an insulating film 261 is provided for planarization. The plugs 121 and 122 may be formed from the above.

[0155] The semiconductor device of one embodiment of the present invention includes a transistor 130 and a first transistor 130. Since the transistor 100 is located above the transistor 100, by stacking these, The area occupied by the element can be reduced. This reduces the area occupied by the elements. A semiconductor device having favorable characteristics can be provided. When used in a semiconductor device having a memory, etc., it increases the memory capacity even with a small circuit area, and It is possible to provide a semiconductor device having a memory with good retention characteristics. The barrier film 111 provided between the gate 130 and the transistor 100 Impurities such as water and hydrogen present in the lower layer can be prevented from diffusing toward the transistor 100. Furthermore, a wiring having a part functioning as a first electrode and a part functioning as a second electrode are sandwiched between the barrier film 111. A wiring functioning as a second electrode is provided to form the capacitor 150. The capacitor element 150 can be easily manufactured without adding a separate process for manufacturing the capacitor element 150. This can be done.

[0156] The above is a description of the configuration example.

[0157] [Example of manufacturing method] An example of a method for manufacturing the semiconductor device shown in the above configuration example will be described below with reference to FIGS. 8 to 12. This will be explained using a cross-sectional view of the above.

[0158] First, a semiconductor substrate 131 is prepared. The semiconductor substrate 131 is, for example, a single crystal silicon substrate. Silicon substrates (including p-type semiconductor substrates and n-type semiconductor substrates), silicon carbide and gallium nitride A compound semiconductor substrate made of silicon or the like can be used as the semiconductor substrate 131. In the following, single crystal silicon is used as the semiconductor substrate 131. This section explains what happens if:

[0159] Subsequently, an element isolation layer (not shown) is formed on the semiconductor substrate 131. The element isolation layer is formed by LOC. OS (Local Oxidation of Silicon) method or STI (Sh If the trench isolation method or mesa isolation method is used, good.

[0160] When forming p-type and n-type transistors on the same substrate, the semiconductor substrate 1 An n-well or p-well may be formed in a part of the n-type semiconductor substrate 13. 1 is doped with impurity elements such as boron to give it p-type conductivity, forming a p-well. An n-type transistor and a p-type transistor may be formed on the substrate.

[0161] Next, an insulating film that will become the gate insulating film 134 is formed on the semiconductor substrate 131. For example, The surface of the semiconductor substrate 131 is oxidized to form a silicon oxide film. Alternatively, the surface of the semiconductor substrate 131 is oxidized by a thermal oxidation method. After forming the silicon oxide film, a nitriding treatment is performed to nitride the surface of the silicon oxide film. By this, a stacked structure of a silicon oxide film and a silicon oxynitride film may be formed. Alternatively, silicon oxide, silicon oxynitride, or high-dielectric-constant materials (also known as high-k materials) Tantalum oxide, hafnium oxide, hafnium silicate, zirconium oxide, Metal oxides such as aluminum oxide and titanium oxide, or rare earth oxides such as lanthanum oxide Other materials may also be used.

[0162] The insulating film is formed by sputtering, CVD (Chemical Vapor Deposition), sition) method (thermal CVD method, MOCVD (Metal Organic CVD) method , PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo lecular beam epitaxy) method, ALD (Atomic Layer Deposition) method, or PLD (Pulsed Laser Deposit) Alternatively, the film may be formed by a film formation method such as an ion method.

[0163] Subsequently, a conductive film is formed to become the gate electrode 135. The conductive film is made of tantalum, tantalum, or the like. a metal selected from the group consisting of tin, titanium, molybdenum, chromium, niobium, etc., or It is preferable to use an alloy material or a compound material whose main component is a metal. The polycrystalline silicon to which the impurity is added can be used. A laminated structure of metal films may be used. Examples of metal nitrides include tungsten nitride and molybdenum nitride. By providing a metal nitride film, the density of the metal film can be improved. This can improve adhesion and prevent peeling.

[0164] Conductive films are formed by sputtering, evaporation, CVD (thermal CVD, MOCVD, PEC It is possible to form films by methods such as VD (including the VD method). It also reduces damage caused by plasma. For this purpose, thermal CVD, MOCVD or ALD is preferred.

[0165] Subsequently, a resist mask is formed on the conductive film by lithography or the like. The unnecessary part of the film is removed. Then, the resist mask is removed to reveal the gate electrode. 135 can be formed.

[0166] Here, a method for processing a film to be processed will be described. When processing a film to be processed finely, Various microfabrication techniques can be used. For example, A method of slimming the resist mask may also be used. A dummy pattern was formed by a lithography method or the like, and a sidewall was formed on the dummy pattern. After that, the dummy pattern is removed, and the remaining sidewalls are used as a resist mask. The film to be processed may be etched. In addition, when etching the film to be processed, a high aspect ratio To achieve this, it is preferable to use anisotropic dry etching. Alternatively, a hard mask made of a metal film may be used.

[0167] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) or g-line (wavelength 43 6nm), H-line (wavelength 405nm), or a mixture of these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Alternatively, the exposure may be performed by an immersion exposure technique. Light (EUV: Extreme Ultraviolet) or X-rays may also be used. Instead of light used for exposure, electron beams can also be used. The use of an electron beam is preferable because it allows for extremely fine processing. When exposure is performed by scanning a beam such as a photomask, no photomask is required.

[0168] In addition, before forming the resist film that will become the resist mask, the film to be processed and the resist film are closely An organic resin film having a function of improving adhesion may be formed. By using a pin coating method or the like, the step of the lower layer is covered and the surface is flattened. This makes it possible to reduce variations in the thickness of the resist mask provided on the organic resin film. In particular, when fine processing is performed, the organic resin film is required to have a high resistance to the light used for exposure. It is preferable to use a material that functions as an anti-reflection film. As the resin film, for example, BARC (Bottom Anti-Reflection The organic resin film is removed at the same time as the resist mask is removed. Alternatively, it may be removed after removing the resist mask.

[0169] After the gate electrode 135 is formed, a sidewall is formed to cover the side surface of the gate electrode 135. The sidewall may be formed by depositing an insulating film thicker than the gate electrode 135, and then Anisotropic etching is performed to leave the insulating film only on the side of the gate electrode 135. It can be formed by:

[0170] FIG. 8(A) shows an example in which the gate insulating film is not etched when the sidewall is formed. 1, the insulating film that will become the gate insulating film 134 is also etched at the same time when the sidewall is formed. In this case, the gate insulating film 13 is formed under the gate electrode 135 and the sidewall. 4 is formed.

[0171] Next, the gate electrode 135 (and sidewalls) of the semiconductor substrate 131 is provided. In the region where there is no conductivity, elements such as phosphorus that give n-type conductivity or boron that give p-type conductivity are added. The element to be added is added. The cross-sectional view at this stage is shown in FIG. 8(A).

[0172] Subsequently, after forming the insulating film 136, the above-mentioned element for imparting conductivity is activated. A first heat treatment is carried out.

[0173] The insulating film 136 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon nitride. Silicon, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride The insulating film 136 may be formed by a sputtering method. , CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method Alternatively, the insulating film can be formed by a PLD method or the like. In particular, the insulating film can be formed by a CVD method, preferably a Alternatively, it is preferable to form the film by plasma CVD, since this can improve the coating property. In addition, to reduce damage caused by plasma, thermal CVD, MOCVD or A The LD method is preferred.

[0174] The first heat treatment is performed in an inert gas atmosphere such as a rare gas or a nitrogen gas atmosphere, or in a reduced pressure atmosphere. The heating can be performed at a temperature of, for example, 400° C. or higher but lower than the strain point of the substrate.

[0175] At this stage, the transistor 130 is formed. The transistor 160 may be formed in a similar manner.

[0176] Subsequently, an insulating film 137 and an insulating film 138 are formed.

[0177] The insulating film 137 may be made of a material that can be used for the insulating film 136, as well as a nitrogen containing oxygen and hydrogen. By using silicon nitride (SiNOH), the amount of hydrogen released by heating can be increased. The insulating film 138 is preferably made of a material that can be used for the insulating film 136. In addition, TEOS (Tetra-Ethyl-Ortho-Silicate) or Silicon oxide with good step coverage, formed by reacting silane with oxygen or nitrous oxide. It is preferable to use a material such as fluorine.

[0178] The insulating film 137 and the insulating film 138 are formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD, PECVD, etc.), MBE, ALD, or PLD methods are used. In particular, the insulating film can be formed by a CVD method, preferably a plasma CVD method. Therefore, forming a film is preferable because it can improve the coverage. To reduce damage, thermal CVD, MOCVD, or ALD is preferred.

[0179] Next, the upper surface of the insulating film 138 is planarized by using a CMP method or the like. In this case, it is not necessary to perform planarization by CMP or the like. The planarization film can be formed by, for example, atmospheric pressure CVD or coating. Examples of films that can be formed using the VD method include BPSG (Boron Phosphorus Glycol), Also, it can be formed using a coating method. Examples of such films include HSQ (hydrogen silsesquioxane).

[0180] Then, the dangling bonds in the semiconductor layer 132 are removed by hydrogen released from the insulating film 137. The second heat treatment is performed to terminate the layers. By desorbing the water and hydrogen contained in the fuel, the water and hydrogen contents can be reduced.

[0181] The second heat treatment can be carried out under the conditions exemplified in the description of the laminated structure above. The conditions described for the heat treatment in 1 can be used.

[0182] Subsequently, the low resistance layer 133a and the low resistance layer 133b are formed on the insulating film 136, the insulating film 137, and the insulating film 138. An opening is formed that reaches the layer 133b and the gate electrode 135 (see FIG. 8(B)). Thereafter, a conductive film 181 that will become the plug 139 and the like is formed so as to fill the opening (see FIG. 8(C)). After that, the conductive film 181 is subjected to a planarization process so that the upper surface of the insulating film 138 is exposed. By this, plugs 139 and 140 are formed (see FIG. 8(D)). The formation of 81 can be performed by, for example, sputtering, CVD (thermal CVD, MOCVD, PEC The layer can be formed by using a method such as MBE, ALD, or PLD. do.

[0183] Subsequently, an insulating film 115e is formed on the insulating film 138, and an opening is formed. A conductive film is formed to fill the gap, and a flat layer is formed on the conductive film so that the upper surface of the insulating film 115e is exposed. By carrying out a smoothing treatment, the conductive layer 144 and the conductive layer 153b are formed (FIG. 8(E) 6, the conductive layer 153b functions as an electrode of the capacitor.

[0184] Next, a barrier film 111e is formed, and then an insulating film 115d is formed (see FIG. 9(A)). Next, an opening is formed in the insulating film 115d. Then, a conductive film is formed to fill the opening. and then performing a planarization treatment on the conductive film so that the upper surface of the insulating film 115e is exposed. As a result, the conductive layers 154d and 154e are formed (see FIG. 9B). In the example shown in FIG. 1, the conductive layer 154d and the conductive layer 154e function as electrodes of the capacitor element. After that, a barrier film 111d is formed (see FIG. 9(C)).

[0185] Subsequently, openings are formed in the barrier film 111d, the insulating film 115d, and the barrier film 111e. Thereafter, a conductive film that will become a plug 127 or the like is formed so as to fill the opening, and the barrier film 111 The conductive film is planarized so that the upper surface of the plug 127 and the Then, plugs 145 and the like are formed (see FIG. 9(D)).

[0186] Next, the insulating film 115c is formed (see FIG. 10(A)). An opening is then formed in the insulating film 115c. The conductive film is subjected to a planarization process so that the surface is exposed, thereby forming the conductive layer 146 and the conductive The conductive layer 153a and the like are formed (see FIG. 10B). It functions as such.

[0187] Next, the conductive layer 154a, the conductive layer 154b, the plug 126 and the plug 147 are formed as shown in FIG. After fabricating the barrier film 111a using the same method as that shown in FIG. After forming an opening in a region in contact with the conductive layer 143, a conductive film is formed. A resist mask is formed on the conductive film, and unnecessary portions of the conductive film are removed by etching. By removing the mask, the conductive layer 152, the conductive layer 154e, and the second gate electrode are left. A conductive layer 105 that functions as a conductive layer can be formed (see FIG. 10C).

[0188] Here, in Figure 9(D), the barrier film 111d has been subjected to a planarization process. As shown in FIGS. 10A to 10C, the barrier film 111d may be used as an insulating film for the capacitor element. Alternatively, the steps of FIG. 9(D) to FIG. 10(C) may be replaced by steps of FIG. 13(A) to 14(B) may be replaced by the process shown in FIG. 14(C). For example, a film may be formed on the surface of the substrate by a CMP method or the like. When chemical treatment is carried out, damage may occur to the surface of the film. If so, remove the damaged film or surface area of ​​the film as described below. Then, by forming an insulating film for the capacitor element again, the capacitance characteristics can be further improved. This can be done.

[0189] FIG. 13A shows the barrier film 111d and the plug 12 as described in FIG. 9D. 13(B) shows the state in which the conductive film 7 is subjected to a planarization process. The barrier film 111d is removed by etching or the like. Then, the barrier film 111f is formed. Next, a resist mask is formed and etching is performed to remove the barrier film 111f. Among them, openings are provided in the barrier film 111f on the plugs such as the plug 127 and the plug 145. After that, the resist mask is removed (see FIG. 13(C)).

[0190] Next, an insulating film 115c is formed. After that, a resist mask is formed and etching is performed. Then, a conductive layer is formed in the insulating film 115c so as to fill the opening. Then, a layer 146, a conductive layer 153a, and the like are formed (see FIG. 14A).

[0191] Next, a barrier film 111c is formed, and then an insulating film 115b is formed. The layer 154c, the conductive layer 154d, the barrier film 111f, the plug 127 and the plug 145 are formed. The conductive layer 154a, the conductive layer 154b, the barrier film 111g, and the The plug 126 and the plug 147 are formed.

[0192] Next, the insulating film 115a is formed. After that, the conductive layer 146 and the conductive layer 153a are formed. The conductive layer 125 and the conductive layer 151 are formed using the same method as described above. After that, an opening is formed in the barrier film 111a, and then a conductive film is formed. Then, a conductive layer 105, a conductive layer 152, and a conductive layer 154e are formed using a resist mask or the like. (See FIG. 14(B)). The above is the process of FIG. 9(D) to FIG. 10(C) in FIG. This is an explanation of the case where the steps are replaced with those of FIG. 14(A) to FIG. 14(B).

[0193] The insulating films 115a to 115e are formed using the same material and method as the insulating film 136. It can be formed.

[0194] The barrier films 111a to 111g are formed by, for example, sputtering or CVD (thermal C (including VD, MOCVD, PECVD, etc.), MBE, ALD, or PLD methods In particular, the insulating film can be formed by a CVD method, preferably a plasma C The VD method is preferable because it can improve the coating property. To reduce damage caused by ions, thermal CVD, MOCVD, or ALD methods are preferred. The materials that can be used for the barrier films 111a to 111g are Please refer to the description in the above.

[0195] After the insulating film 115e is formed, third heat treatment is preferably performed. This allows the water and hydrogen contained in each layer to be desorbed, thereby reducing the water and hydrogen content. The third heat treatment is performed immediately before the formation of the barrier film 111e, and the barrier film 11 After thoroughly removing hydrogen and water contained in the layer below 1e, a barrier film 111e is formed. By doing so, water and hydrogen will be re-diffused to the lower layer side of the barrier film 111e in a later process. This can suppress the above.

[0196] The third heat treatment can be carried out under the conditions exemplified in the description of the laminated structure above. The conditions for the heat treatment described in Section 1 can be used. After the film 115d is formed, a similar heat treatment may be performed after the formation of each insulating film. .

[0197] At this stage, the capacitor element 150 is formed. The capacitor element 150 has a portion of the first electrode. The conductive layer 152 and the conductive layers 154a to 154e function as a second electrode. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b function as a conductive layer. The barrier film 111a is made up of barrier films 111a to 111e.

[0198] Next, the insulating film 114 is formed. The insulating film 114 is formed by, for example, a sputtering method or a CVD method. (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD or PL In particular, the insulating film can be formed by a CVD method, preferably a Plasma method. The deposition by the Zuma CVD method is preferable because it can improve the coating properties. To reduce damage caused by plasma, thermal CVD, MOCVD, or ALD are preferred. Desirable.

[0199] In order to make the insulating film 114 contain excess oxygen, for example, the insulating film 11 is heated in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 114 after the film formation to make it contain excess oxygen. Alternatively, a region having the above structure may be formed, or both methods may be combined.

[0200] For example, the insulating film 114 after deposition may contain oxygen (at least oxygen radicals, oxygen atoms, and oxygen ions). The oxygen-introducing method includes introducing oxygen into the silicon dioxide gas to form a region containing excess oxygen. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Plasma treatment or the like can be used.

[0201] The oxygen introduction treatment can be performed using a gas containing oxygen. Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. In the oxygen introduction process, a rare gas may be contained in the oxygen-containing gas. For example, a mixture of carbon dioxide, hydrogen and argon may be used. stomach.

[0202] After forming the insulating film 114, the CMP method or the like is used to improve the flatness of the upper surface. A flattening process may also be performed.

[0203] Next, a semiconductor film that will become the semiconductor layer 101a and a semiconductor film that will become the semiconductor layer 101b are formed in this order. It is preferable that the semiconductor film is continuously formed without being exposed to the air. The semiconductor that will become the semiconductor layer 101a and the semiconductor that will become the semiconductor layer 101b are formed by sputtering. The film may be formed by a method such as a CVD method, an MBE method, a PLD method, or an ALD method.

[0204] The semiconductors to be used for the semiconductor layer 101a and the semiconductor layer 101b are as follows: When forming an In-Ga-Zn oxide layer by MOCVD, trime is used as the source gas. Examples of suitable materials include trimethylindium, trimethylgallium, and dimethylzinc. The combination of raw material gases is not limited to the above, and trimethylindium may be replaced with triethylindium. Also, triethylgallium may be used in place of trimethylgallium. Dimethyl zinc may be replaced by diethyl zinc.

[0205] After the semiconductor film is formed, a fourth heat treatment is preferably performed. At a temperature of 650°C or less, preferably 300°C to 500°C, in an inert gas atmosphere, The heat treatment may be carried out in an atmosphere containing 10 ppm or more of reactive gas or under reduced pressure. The atmosphere is an inert gas atmosphere, and then an oxidizing gas is introduced to replace the oxygen that has been removed. The heat treatment may be carried out in an atmosphere containing 10 ppm or more of fluorine. Alternatively, after processing the semiconductor film to form island-shaped semiconductor layers 101a and 101b, By the heat treatment, oxygen is supplied from the insulating film 114 or the oxide film to the semiconductor film. This can reduce oxygen vacancies in the semiconductor film.

[0206] After that, a resist mask is formed and unnecessary portions are removed by etching. By removing the resist mask, the island-shaped semiconductor layer 101a and the island-shaped semiconductor layer 101b are formed. A stacked structure of the above can be formed (see FIG. 11(A)). During etching, a part of the insulating film 114 is etched, and the semiconductor layer 101a and the semiconductor layer 101b are removed. The insulating film 114 in the area not covered by the insulating film b may become thinner. It is preferable to form the insulating film 114 thick in advance so that it is not lost by the etching. stomach.

[0207] Thereafter, the conductive film 104 is formed (see FIG. 11(B)). For example, sputtering method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.) The insulating layer can be formed by using the MBE method, the ALD method, the PLD method, or the like. When the insulating film is formed by a CVD method, preferably a plasma CVD method, the coating property is improved. In order to reduce damage caused by plasma, thermal CVD and M The OCVD method or the ALD method is preferred.

[0208] Next, a resist mask is formed, and unnecessary portions of the conductive film 104 are removed by etching. After that, the resist mask is removed, and the conductive layers 104a and 104b are formed. Here, when the conductive film is etched, a part of the semiconductor layer 101b and the upper part of the insulating film 114 are etched. The portions that do not overlap with the conductive layer 104a and the conductive layer 104b are thinned. Therefore, the thickness of the semiconductor film or the like that will become the semiconductor layer 101b is determined by the etching depth. It is preferable to form the insulating film thick in advance in consideration of the above.

[0209] Next, a gate insulating film 102 and a semiconductor layer 101c are formed, a resist mask is formed, and an etching Then, the resist mask is removed. A conductive film is formed (see FIG. 12(A)). After that, a resist mask is formed and etching is performed. The conductive film is processed by etching, and then the resist mask is removed to form the gate electrode 103. The semiconductor that becomes the semiconductor layer 101c is formed by sputtering, CVD, MBE or P The film may be formed using the LD method, ALD method, or the like.

[0210] As a semiconductor for the semiconductor layer 101c, an In-Ga-Zn oxide layer was grown by MOCVD. When forming a film by this method, trimethylindium, trimethylgallium and The combination of source gases is not limited to the above, and may be any of the following: Triethylindium or the like may be used instead of trimethylindium. Triethylgallium may be used instead of ethylgallium. Additionally, diethyl zinc may be used.

[0211] At this stage, transistor 100 is formed.

[0212] Next, the insulating film 112 is formed. The insulating film 112 is formed by, for example, a sputtering method or a CVD method. (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD or PL In particular, the insulating film can be formed by a CVD method, preferably a Plasma method. The deposition by the Zuma CVD method is preferable because it can improve the coating properties. To reduce damage caused by plasma, thermal CVD, MOCVD, or ALD are preferred. Desirable.

[0213] After the insulating film 112 is formed, fifth heat treatment is preferably performed. Oxygen is supplied to the semiconductor layer 101 from the film 114, etc., and oxygen vacancies in the semiconductor layer 101 are reduced. At this time, the oxygen released from the insulating film 114 can be reduced. and the insulating film 112, and is blocked by the layer below the barrier film 111 and the insulating film 114. Since the oxygen does not diffuse to the upper layer, the oxygen can be effectively trapped. The amount of oxygen that can be supplied to the conductor layer 101 can be increased, and oxygen deficiency in the semiconductor layer 101 can be reduced. The loss can be effectively reduced.

[0214] The insulating film 112 may have a stacked structure of two or more layers. 112 has a two-layer laminated structure, and the lower layer is made of, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. Silicon, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride The upper layer may be made of a material such as aluminum or aluminum nitride. It is preferable to use a material that does not easily diffuse hydrogen. The insulating film 102 is a semiconductor insulating film that releases oxygen when heated, similar to the insulating film 14. Oxygen may also be supplied from the upper side of the body layer 101 .

[0215] Subsequently, an insulating film 113 is formed. The insulating film 113 is made of, for example, silicon oxide or silicon oxynitride. Silicon, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, Aluminum nitride oxide, aluminum nitride, or the like may be used, and the layer may be formed as a laminate or a single layer. The insulating film 113 is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, P It can be formed by using the MBE method, ALD method, PLD method, etc. In particular, when the film is formed by the CVD method, preferably the plasma CVD method, good coating properties can be obtained. In addition, in order to reduce damage caused by plasma, Thermal CVD, MOCVD or ALD is preferred.

[0216] Next, as shown in FIG. 12(B), the insulating film 113, the insulating film 112, the gate insulating film 10 2, conductive layer 104a, conductive layer 104b, semiconductor layer 101b, semiconductor layer 101a and insulating layer An opening is provided in the film 114. Next, a conductive film is formed so as to fill the opening, and then a resist is formed. The unnecessary portions are removed using a resist mask, and the resist mask is removed to form the plug 121 and the plug Here, the plug 121 is formed by insulating film 113, insulating film 112, gate insulating film 113, and the like. The insulating film 102, the semiconductor layer 101c, the conductive layer 104a, the semiconductor layer 101b, and the semiconductor layer 101a , which is formed to penetrate the insulating film 114 and the barrier film 111a and is connected to the conductive layer 151. Here, the plug 121 and the conductive layer 104a are in contact with each other at the side of the plug 121. Similarly, the plug 122 is connected to the insulating film 113, the insulating film 112, the gate insulating film 102, and the semiconductor Conductor layer 101c, conductive layer 104b, semiconductor layer 101b, semiconductor layer 101a, insulating film 114 and a conductive layer 104b formed to penetrate the barrier film 111a and connect to the conductive layer 125. is connected by contacting the side of the plug 122.

[0217] Subsequently, the insulating film 116 is formed. The insulating film 116 is made of, for example, silicon oxide or silicon oxynitride. Silicon, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, Aluminum nitride oxide, aluminum nitride, or the like may be used, and the layer may be formed as a laminate or a single layer. The insulating film 116 is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, P It can be formed by using the MBE method, ALD method, PLD method, etc. When an organic insulating material such as an organic resin is used as the insulating film 116, the insulating film 116 can be formed by spin coating. Alternatively, the insulating film 116 may be formed by a coating method. It is preferable to perform planarization treatment on the upper surface. The materials and forming methods shown in 8 may also be used.

[0218] Subsequently, in the same manner as above, a plug 122 is formed in the insulating film 116. Forms 3rd class.

[0219] Subsequently, a conductive film is formed on the insulating film 116. After that, a resist is formed by the same method as above. A mask is formed, and unnecessary portions of the conductive film are removed by etching. By removing the mask, wiring 124 and the like can be formed (see FIG. 12(B)). .

[0220] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0221] When the semiconductor layer 101a and the semiconductor layer 101b are formed, the conductive film 104 is formed. Then, a resist mask is formed, the conductive film 104 is etched, and then the semiconductor layer 101a The semiconductor layer that will become the semiconductor layer 101b and the semiconductor layer that will become the semiconductor layer 101b are formed by etching. 5(A) may be used. After that, the conductive film 104 is processed again to form the conductive layer 104a and 12 and 13, the transistor 100 is formed. can have a structure as shown in FIG. 15(B).

[0222] In addition, a transistor 100 having a structure different from that of the transistor 100 shown in FIG. As an example of a manufacturing method, a manufacturing method of the transistor 100 shown in FIG. 1 will be briefly described below. will be explained.

[0223] First, a semiconductor film that will become the semiconductor layer 101 is formed on the insulating film 114, and then a resist mask or the like is applied. Then, etching is performed to form the semiconductor layer 101. Next, the gate insulating film 102 and an insulating film and a conductive film to be the gate electrode 103 are formed, a resist mask and the like are formed, Etching is carried out to form the gate electrode 103 and the gate insulating film 102 .

[0224] Next, the low resistance region 171a and the low resistance region 171b are formed. The semiconductor layer has low resistance. The carrier density can be increased by, for example, adding impurities. For example, ion implantation is a method for increasing the carrier density. The element can be added using a gas injector. Examples of elements that can be used include argon, Boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium Titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, Magnesium, arsenic, yttrium, zirconium, niobium, molybdenum, indium, tin , lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten It is preferred to add one or more of them.

[0225] In such a low resistance region, it is possible to trap unwanted hydrogen, for example. By trapping unnecessary hydrogen in the low resistance layer, the hydrogen concentration in the channel region can be reduced. As a result, good transistor characteristics can be obtained.

[0226] Next, the insulating film 112 and the insulating film 113 are formed. The gate electrode 121 and the plug 122 are formed by the above steps. 00 can be created.

[0227] (Embodiment 2) In this embodiment, a compound semiconductor that can be suitably used for the transistor 100 described in Embodiment 1 is The oxide semiconductor will be described.

[0228] Here, as shown in FIG. 6 as an example, a semiconductor layer 101a is an oxide semiconductor, a semiconductor 101b and semiconductor layer 101c are stacked. The oxide semiconductor that can be used for the semiconductor layer 101a may be a single layer. A structure that does not have either or both of the conductor layer 101b and the semiconductor layer 101c. You may do so.

[0229] The semiconductor layer 101b is, for example, an oxide semiconductor containing indium. For example, when b contains indium, the carrier mobility (electron mobility) increases. The semiconductor layer 101b preferably contains an element M. The element M is preferably aluminum, Gallium, yttrium, or tin can be used as the other elements M. These include boron, silicon, titanium, iron, nickel, germanium, yttrium, and zirconium. Sodium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten However, there are cases where the element M can be a combination of multiple of the elements mentioned above. The element M is, for example, an element that has a high bond energy with oxygen. The element M is an element having a higher bond energy than indium. It is an element that has the function of widening the energy gap of semiconductors. O1b preferably contains zinc. When an oxide semiconductor contains zinc, it may be easily crystallized. There is a match.

[0230] However, the semiconductor layer 101b is not limited to an oxide semiconductor containing indium. Layer 101b is made of an indium-containing material such as zinc tin oxide or gallium tin oxide. First, oxide semiconductors containing zinc, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. It doesn't matter which one it is.

[0231] The semiconductor layer 101b is made of, for example, an oxide with a large energy gap. The energy gap of 101b is, for example, 2.5 eV or more and 4.2 eV or less, preferably The voltage is set to 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0232] For example, the semiconductor layer 101a and the semiconductor layer 101c are made of the same material as the semiconductor layer 101b. The semiconductor layer 1 is an oxide semiconductor composed of one or more elements other than silicon. The semiconductor layers 101a and 101b are formed from one or more elements other than oxygen. Since the semiconductor layer 101c is formed, the interface between the semiconductor layer 101a and the semiconductor layer 101b and In addition, an interface state is unlikely to be formed at the interface between the semiconductor layer 101b and the semiconductor layer 101c. .

[0233] The semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c are made of at least indium. When the semiconductor layer 101a is an In-M-Zn oxide, In and When the sum of In and M is 100 atomic %, preferably In is less than 50 atomic % , M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is When the semiconductor layer 101b is an In-M-Zn oxide, When the sum of In and M is 100 atomic %, In is preferably 25 atomic %. ic% or more, M is less than 75 atomic %, and more preferably In is 34 atomic % In addition, the semiconductor layer 101c is made of In-M-Zn oxide. In the case of a compound, when the sum of In and M is 100 atomic %, preferably In is 5 0 atomic %, M is 50 atomic % or more, and more preferably In is 25 atomic % or more. The semiconductor layer 101c is made to have a thickness of less than 100 atomic % and a thickness of 75 atomic % or more. The same oxide as that of the base layer 101a may be used.

[0234] The semiconductor layer 101b has a larger electron affinity than the semiconductor layer 101a and the semiconductor layer 101c. For example, the semiconductor layer 101b is made of a semiconductor layer 101a and a semiconductor The electron affinity of the layer 101c is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV and more preferably, oxides having a larger valence of 0.15 eV or more and 0.4 eV or less. The electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0235] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor layer 101c contains indium gallium oxide. The Ga atom ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more. More preferably, it is set to 90% or more.

[0236] At this time, when an electric field is applied to the gate electrode, the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c are A channel is formed in the semiconductor layer 101b of the conductor layer 101c, which has a large electron affinity.

[0237] The band structure is shown in FIG. 18(A). The energy of the bottom of the conduction band of each layer (denoted as Ec) and The energy at the top of the valence band (denoted as Ev) is shown.

[0238] Here, between the semiconductor layer 101a and the semiconductor layer 101b, there is a semiconductor layer 101a and a semiconductor layer 101b. In some cases, the semiconductor layer 101b and the semiconductor layer 101b may have a mixed region. Between the semiconductor layer 101b and the semiconductor layer 101c, there may be a mixed region of the semiconductor layer 101b and the semiconductor layer 101c. The interfacial state density is low in the mixed region. and the semiconductor layer 101c have a continuous energy distribution near the interfaces. This results in a band structure where the transition occurs (also called a continuous junction).

[0239] In FIG. 18A, the semiconductor layer 101a and the second semiconductor layer 101c have the same Ec. However, they may be different. For example, the semiconductor layer 101a The Ec of the semiconductor layer 101c may have a higher energy than that of the semiconductor layer 101b.

[0240] At this time, the electrons are not in the semiconductor layer 101a and the semiconductor layer 101c, but in the semiconductor layer 101b (see FIG. 18(B)). the interface state density at the interface between the semiconductor layer 101a and the semiconductor layer 101b; By reducing the interface state density at the interface with 101c, The movement of electrons is less hindered, which allows the on-state current of the transistor to be increased. .

[0241] When the transistor has an s-channel structure, the entire semiconductor layer 101b Therefore, the thicker the semiconductor layer 101b, the larger the channel region. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor. For example, it is possible to set the thickness to 20 nm or more, preferably 40 nm or more, and more preferably 60 nm or more. More preferably, the semiconductor layer 101b may have a region with a thickness of 100 nm or more. However, since the productivity of semiconductor devices may decrease, for example, 300 nm or less, A semiconductor having a region with a thickness of preferably 200 nm or less, more preferably 150 nm or less This may be called layer 101b.

[0242] In addition, in order to increase the on-current of the transistor, the thickness of the semiconductor layer 101c is small. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 nm. The semiconductor layer 101c may have the following regions: The semiconductor layer 101b on which the hole is formed is doped with elements other than oxygen (hydrogen, Therefore, the semiconductor layer 10 It is preferable that 1c has a certain thickness, for example, 0.3 nm or more, preferably The semiconductor layer 101c has a region with a thickness of 1 nm or more, more preferably 2 nm or more. In addition, the semiconductor layer 101c can prevent outward diffusion of oxygen released from the insulating film 102 and the like. To suppress this, it is preferable that the material has oxygen blocking properties.

[0243] In order to increase reliability, the semiconductor layer 101a is thick and the semiconductor layer 101c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 4 The semiconductor layer 101a has a region with a thickness of 0 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor layer 101a, the thickness of the semiconductor layer 101a can be increased. The distance from the interface with a to the semiconductor layer 101b where the channel is formed can be increased. However, since the productivity of the semiconductor device may decrease, for example, 200 nm or less is preferred. The semiconductor layer 1 has a region with a thickness of 120 nm or less, and more preferably 80 nm or less. Just use 01a.

[0244] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the elements become donors, generating electrons as carriers. Therefore, the threshold voltage of the oxide semiconductor film is shifted in the negative direction. After that, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to remove impurities to achieve high purity so that the impurities are not included as much as possible.

[0245] Note that dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film Oxygen may also decrease at the same time. A process of adding oxygen to oxides to compensate for the increased oxygen deficiency caused by oxidation. In this specification and the like, when oxygen is supplied to an oxide semiconductor film, The oxygen addition treatment may be referred to as an oxygen addition treatment, or a treatment for adding oxygen to an oxide semiconductor film at a stoichiometric ratio. When the amount is greater than the composition, it is sometimes referred to as a hyperoxygenation treatment.

[0246] In this way, the oxide semiconductor film is dehydrated by dehydration treatment (dehydrogenation treatment). By removing oxygen and filling the oxygen vacancies through oxygen addition treatment, the i-type (intrinsic) or The oxide semiconductor film can be an oxide semiconductor film that is very close to i-type and is substantially i-type (intrinsic). Note that the term "substantially intrinsic" means that there are very few carriers derived from donors in the oxide semiconductor film. (close to zero), and the carrier density is 1×10 17 / cm 3 Below, 1×10 16 / cm 3 below , 1×10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 Below , particularly preferably 8 × 10 11 / cm 3 less than 1×10 11 / cm 3 Not yet less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all. This means that...

[0247] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film can be For example, a transistor using an oxide semiconductor film can be The drain current when the capacitor is off is 1×10 at room temperature (approximately 25°C). -18 Below A, Preferably 1 x 10 -21 A or less, more preferably 1×10-24 A or below, or 85 1 x 10 at °C -15 A or less, preferably 1×10 -18 A or less, more preferably 1x 10 -21 A or less. Note that the transistor being in the off state is an n-channel In the case of a transistor of this type, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. In general, if the gate voltage is 1V or more, 2V or more, or 3V or more less than the threshold voltage, , the transistor is turned off.

[0248] The structure of the oxide semiconductor film will be described below.

[0249] Oxide semiconductor films are classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Alternatively, oxide semiconductors can be divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. The non-single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor film, polycrystalline oxide Semiconductor films, microcrystalline oxide semiconductor films, amorphous oxide semiconductor films, etc. The oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline Oxide semiconductors, etc.

[0250] First, we will explain the CAAC-OS film. These oxide semiconductors are called "Oxide Semiconductors with Axis-Aligned Nanocrystals" It is also possible.

[0251] The CAAC-OS film is an oxide film having multiple crystal parts (also called pellets) aligned along the c-axis. It is one of the semiconductor films.

[0252] The CAAC-OS film was observed under a transmission electron microscope (TEM). A bright-field image and diffraction pattern of CAAC-OS were obtained using a tron ​​microscope. When observing the composite analytical image (also called a high-resolution TEM image), multiple pellets can be seen. On the other hand, high-resolution TEM images reveal the boundaries between pellets, i.e., grain boundaries (gray Therefore, it is not possible to clearly confirm the boundary between the two. It can be said that the S film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0253] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When observed, it can be confirmed that metal atoms are arranged in layers in the crystalline part. Each layer of the CAAC-OS film is formed on a surface (also called a surface to be formed) or on a concave surface of the upper surface. The shape reflects the convexity and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0254] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystalline region. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0255] FIG. 19(a) is a cross-sectional TEM image of the CAAC-OS film. This is a cross-sectional TEM image of 19(a) enlarged, with the atomic arrangement emphasized for easier understanding. The key is displayed.

[0256] Figure 19(c) shows the area surrounded by a circle (diameter approximately 4 mm) between AO and A' in Figure 19(a). The local Fourier transform image of the c-axis orientation in each region is shown in Figure 19(c). In addition, the c-axis orientation is different between A-O and O-A', so different graphs are formed. The c-axis angles between the A and A crystals are 14.3° and 16. 6°, 26.4°, and so on. Between these, the angle of the c-axis gradually changes to -18.3°, -17.6°, and -15.9°. It is clear that things are changing.

[0257] When electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, a thickness of 1 nm to 30 nm on the top surface of the CAAC-OS film is observed. When electron diffraction using an electron beam (also called nanobeam electron diffraction) is performed, spots are observed. (See Figure 20(A)).

[0258] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that this is the case.

[0259] Most of the crystals in the CAAC-OS film are cubic crystals with sides of less than 100 nm. Therefore, the crystal part in the CAAC-OS film has a side length of 10 This also includes cases where the size fits within a cube of less than 5 nm, or less than 3 nm. However, multiple crystals in the CAAC-OS film are connected to form a single large crystal domain. For example, in a planar TEM image, 2 Over 5μm 2 or more than 1000μm 2 Crystal regions with more than this size may be observed.

[0260] X-ray diffraction (XRD) of the CAAC-OS film When structural analysis is performed using this device, for example, CAAC-OS with InGaZnO4 crystals can be seen. In the out-of-plane analysis of the film, the diffraction angle (2θ) peaks around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that the direction is roughly vertical.

[0261] On the other hand, the in-p X-rays incident on the CAAC-OS film are perpendicular to the c-axis. In the Lane analysis, a peak may appear around 2θ of 56°. The crystal structure of InGaZnO4 is composed of a single crystal of InGaZnO4. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to 2θ. Even when the φ is fixed at around 56° and scanned, no clear peak appears.

[0262] From the above, it can be concluded that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is a plane parallel to the ab plane of the crystal.

[0263] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization treatment such as a heat treatment. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is to be formed. Therefore, for example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the face or top surface.

[0264] Furthermore, the distribution of c-axis oriented crystals in the CAAC-OS film does not need to be uniform. For example, the crystalline part of the CAAC-OS film is grown from the top surface of the CAAC-OS film. Therefore, when the crystal is formed, the region near the top surface has a crystal orientation that is more c-axis oriented than the region near the surface on which the crystal is formed. In addition, the CAAC-OS film containing impurities may have a high percentage of impurities. The region where the ZnO was added was transformed, and regions with different proportions of c-axis oriented crystals were formed. This may also occur.

[0265] In addition, the out-of-plane structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the NMR method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have crystalline structure. It is preferable that the peak is exhibited at 2θ of about 36° and that the peak is not exhibited at 2θ of about 36°.

[0266] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is made of an element other than the main component, such as silicon or a transition metal element. The elements such as ZnO, which have stronger bonding strength with oxygen than the metal elements constituting the oxide semiconductor film, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Because the diameter (or molecular radius) is large, when the molecule is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement of the oxide semiconductor film, which may result in a decrease in crystallinity. The pure material may act as a carrier trap or a carrier generation source.

[0267] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films can act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0268] The low impurity concentration and low defect level density (low oxygen vacancies) are called high-purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the film has a small number of carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics (noise) such that the threshold voltage is negative. It is also called "marine.") It is rare for it to become pure or substantially pure. An intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it is fixed. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may be the case.

[0269] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. There is little gender variation.

[0270] Figure 36(A) shows a high-resolution T image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image shown here is a spherical aberration correction (SAC) image. The spherical aberration correction function was used. High-resolution TEM images are specifically called Cs-corrected high-resolution TEM images. The observation was performed using, for example, an atomic resolution analytical electron microscope such as JEM-ARM200F manufactured by JEOL Ltd. This can be done by:

[0271] An enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 36(A) is shown in FIG. 36(B). From Figure 36(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). The surface reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0272] As shown in Figure 36(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 36(B) and Figure 36(C). Therefore, the size of each pellet is about 1 nm to 3 nm, and the pellets are It can be seen that the size of the gap caused by the tilt is about 0.8 nm. The rheotomes can also be called nanocrystals (nc).

[0273] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See Figure 36(D)). The inclination between the pellets observed in Figure 36(C) The location where the crack occurs corresponds to the area 5161 shown in FIG. 36(D).

[0274] In addition, Figure 37(A) shows the Cs of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in Figure 37(A). Enlarged Cs-corrected high-resolution TEM images are shown in Figure 37(B), Figure 37(C), and Figure 37(D), respectively. 37(D). From Fig. 37(B), Fig. 37(C) and Fig. 37(D), the pellet It can be seen that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0275] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When structural analysis is performed using the out-of-plane method, the results are as shown in Figure 38(A). A peak may appear at a diffraction angle (2θ) of around 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0276] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31° In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the center of the crystal grains indicate that some of the CAAC-OS grains do not have a c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0277] On the other hand, in-plan X-ray irradiation is performed on the CAAC-OS in a direction approximately perpendicular to the c-axis. When structural analysis is performed using the e method, a peak appears at 2θ around 56°. This peak is due to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was fixed at approximately 100°, and the analysis was performed while rotating the sample around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in Figure 38(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ is When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in Figure 38(C). Therefore, from the structural analysis using XRD, it is clear that CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0278] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 39(A) is generated. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, electron diffraction also reveals The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately on the surface to be formed or on the upper surface. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm is incident is shown in Figure 39(B). (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also reveals It is clear that the a-axis and b-axis of the pellets contained in the CAAC-OS do not have any orientation. The first ring in FIG. 39(B) is the (010) plane of the InGaZnO4 crystal. The second ring in Figure 39(B) is thought to be due to the (100) plane. This is thought to be due to the (110) plane.

[0279] Next, the polycrystalline oxide semiconductor film will be described.

[0280] In the polycrystalline oxide semiconductor film, crystal grains can be confirmed in the TEM observation image. The crystal grains contained in the crystalline oxide semiconductor film are, for example, 2 nm or more in a TEM observation image. The particle size is 00 nm or less, 3 nm to 100 nm or 5 nm to 50 nm. In addition, in the polycrystalline oxide semiconductor film, the grain boundaries can be confirmed in the TEM observation image. This may be the case.

[0281] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientation between the plurality of crystal grains is In addition, when an XRD device is used for a polycrystalline oxide semiconductor film, When structural analysis is performed, for example, the out of polycrystalline oxide semiconductor film having InGaZnO4 crystals In the t-of-plane analysis, there is a peak at 2θ around 31° and a peak at 2θ around 36°. peak or other peaks may appear.

[0282] A polycrystalline oxide semiconductor film has high crystallinity and therefore may have high electron mobility. Therefore, a transistor using a polycrystalline oxide semiconductor film has high field-effect mobility. However, in a polycrystalline oxide semiconductor film, impurities may segregate at the grain boundaries. The grain boundaries of the polycrystalline oxide semiconductor film become defect states. Since the oxide semiconductor film may become a carrier trap or a carrier generation source, The transistors using the CAAC-OS film showed a small change in electrical characteristics compared to the transistors using the CAAC-OS film. may result in a transistor with low reliability.

[0283] Next, a microcrystalline oxide semiconductor film will be described.

[0284] In the microcrystalline oxide semiconductor film, crystal parts can be clearly seen in the TEM image. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 nm or less, or 1 nm to 3 nm. The oxide semiconductor film having nc-OS (nanocrystalline O The nc-OS film is called an oxide semiconductor film. In EM observation images, it may not be possible to clearly identify the grain boundaries. It is possible that the origin of the pellets in CAAC-OS is the same. The crystalline part of nc-OS is sometimes called a pellet.

[0285] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analytical method. For example, when an X-ray beam with a diameter larger than the crystal part (pellet) is irradiated onto an nc-OS film, When structural analysis is performed using the XRD equipment used, the out-of-plane method In the nc-OS film, no peaks indicating crystal planes were detected. Electron diffraction using an electron beam with a large probe diameter (e.g., 50 nm or more) (selected area electron diffraction) When nc- is performed, a halo-like diffraction pattern is observed. For the OS film, an electron beam with a probe diameter close to or smaller than the pellet size is used. When nanobeam electron diffraction is performed on the nc-OS film, spots are observed. When beam electron diffraction is performed, a circular (ring-shaped) area of ​​high brightness is observed. Furthermore, multiple spots may be observed within the ring-shaped area (Figure 20). See (B). ).

[0286] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, and therefore, nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0287] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0288] Therefore, the nc-OS film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film with high carrier density may have high electron mobility. In some cases, a transistor using an nc-OS film has high field-effect mobility. The nc-OS film has a higher defect density than the CAAC-OS film, which leads to a higher carrier transport. Therefore, the transistor using the nc-OS film is Compared to transistors using OS films, the electrical characteristics fluctuate greatly and the reliability is low. However, the nc-OS film can be formed even if it contains a relatively large amount of impurities. Therefore, it is easier to form than the CAAC-OS film, and it is suitable for some applications. Therefore, a semiconductor having a transistor using an nc-OS film can be The devices may be manufacturable.

[0289] Next, the amorphous oxide semiconductor film will be described.

[0290] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and does not have a crystalline portion. An example is an oxide semiconductor film that has an amorphous state like quartz.

[0291] In the amorphous oxide semiconductor film, no crystalline portion can be confirmed in the TEM observation image.

[0292] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of- In the analysis by the plane method, no peaks indicating crystal planes are detected. When electron diffraction is performed on a semiconductor film, a halo pattern is observed. When nanobeam electron diffraction is performed on a semiconductor film, no spots are observed, and a halo pattern is observed. is observed.

[0293] The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration. In addition, the amorphous oxide semiconductor film has a high density of defect states.

[0294] An oxide semiconductor film with a high impurity concentration and a high density of defect states has carrier traps and The oxide semiconductor film is a common source of CO2.

[0295] Therefore, the amorphous oxide semiconductor film has a higher carrier density than the nc-OS film. Therefore, a transistor using an amorphous oxide semiconductor film may not be able to Therefore, it is difficult to obtain normally-on electrical characteristics from transistors that require normally-on electrical characteristics. The amorphous oxide semiconductor film may be preferably used as a photoresist. Therefore, when an amorphous oxide semiconductor film is used, the carrier traps may increase. The transistors using the CAAC-OS film and the nc-OS film have the following characteristics: The electrical characteristics vary greatly, resulting in a transistor with low reliability.

[0296] Note that the oxide semiconductor film has a structure that exhibits physical properties intermediate between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may be formed, particularly, by using an amorphous oxide. amorphous-like oxide semiconductors (a-like OS) This is called an iconductor membrane.

[0297] In the a-like OS film, voids are observed in high-resolution TEM images. In addition, crystals may not be clearly visible in high-resolution TEM images. The a-like OS film has regions where crystals are visible and regions where no crystals are visible. Crystallization occurs when a small amount of electrons is irradiated, similar to the amount observed with a TEM, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the amount of precipitation is so small that it can be observed by TEM. Almost no crystallization due to electron irradiation is observed.

[0298] The size of the crystalline parts of the a-like OS film and the nc-OS film was measured using a high-resolution This can be done using TEM images. For example, InGaZnO4 crystals have a layered structure. There are two Ga-Zn-O layers between the In-O layers. The device has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned along the c-axis. It has a layered structure. Therefore, the distance between adjacent layers is (009) The lattice spacing (also called the d value) is approximately the same as that of the Therefore, focusing on the lattice fringes in the high-resolution TEM image, In the area where the spacing is 0.28 nm or more and 0.30 nm or less, each lattice fringe is In It corresponds to the ab plane of the GaZnO4 crystal.

[0299] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0300] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Prepare CAAC-OS (referred to as sample B) and CAAC-OS (referred to as sample C). The sample is also an In-Ga-Zn oxide.

[0301] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all of the samples have crystalline parts.

[0302] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0303] Figure 40 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of eOS grows in size according to the cumulative amount of electron irradiation. As shown in Figure 40 (1), the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was sized at 4.2 × 10 8 e - / nm 2On the other hand, in the nc-OS, the size of the crystals grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 40, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. You will realize something.

[0304] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC-O. It can be seen that the structure is unstable compared to S.

[0305] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS and CAAC is 78.6% or more and less than 92.3% of that of the original. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0306] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the conductive film is known, the density can be determined by comparing it with the density of a single crystal with the same composition. For example, the structure of the oxide semiconductor film can be estimated by using the following formula: The density of the -like OS film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film is 92.3% or more of the density of the crystal. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is However, it is difficult to form the film.

[0307] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atom In the oxide semiconductor film that satisfies the [atomic ratio], single-crystal InGaZnO with a rhombohedral crystal structure The density of 4 is 6.357 g / cm 3 Therefore, for example, In:Ga:Zn=1:1: In an oxide semiconductor film that satisfies the atomic ratio of 1, the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1 In the oxide semiconductor film satisfying the atomic ratio of 0.1 to 1, the density and CAAC of the nc-OS film were The density of the -OS film is 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0308] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions may be used in any proportion. By combining single crystals with the desired composition, the density corresponding to the single crystal of the desired composition can be calculated. The density of a single crystal of a desired composition varies depending on the ratio of the single crystals of different compositions combined. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate it by combining the above.

[0309] Next, a single crystal oxide semiconductor film will be described.

[0310] The single-crystal oxide semiconductor film has a low impurity concentration and a low density of defect states (few oxygen vacancies). Therefore, the carrier density can be reduced. A transistor using a crystalline oxide semiconductor film rarely has normally-on electrical characteristics. Furthermore, since the single-crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, Therefore, in the case of a transistor using a single-crystal oxide semiconductor film, the number of carrier traps may be reduced. The transistor has small fluctuations in electrical characteristics and is highly reliable.

[0311] Note that the oxide semiconductor film has a high density when it has few defects. High crystallinity increases density. In addition, the oxide semiconductor film has a low concentration of impurities such as hydrogen. The density of a single-crystal oxide semiconductor film is higher than that of a CAAC-OS film. The CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. The conductor film has a higher density than the microcrystalline oxide semiconductor film. The density is higher than that of an crystalline oxide semiconductor film.

[0312] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may be a laminate film having two or more kinds of films.

[0313] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0314] FIG. 41(A) shows how a CAAC-OS film is formed by sputtering. FIG.

[0315] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130. The magnetic field is generated by the magnet. The magnetic field of the magnet is used to increase the deposition rate. The sputtering method is called magnetron sputtering.

[0316] The substrate 5120 is disposed facing the target 5130, and the distance between them is d (target The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the film deposition chamber is set to 0.02m or more and 0.5m or less. Most of the film deposition gas (e.g., oxygen) It is filled with a gas mixture containing hydrogen, argon, or oxygen at a ratio of 5% by volume or more, and The pressure is controlled to be in the range of 0.1 Pa to 100 Pa, preferably in the range of 0.1 Pa to 10 Pa. By applying a voltage above a certain level to the target 5130, discharge begins and plasma is generated. It is noted that a high density plasma region is formed near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 The ions 5101 are, for example, positive ions of oxygen (O + ) and argon cations (A r + ) etc.

[0317] Here, the target 5130 has a polycrystalline structure having a plurality of crystal grains, and any of the crystal grains The crystal grains include cleavage planes. The crystal structure of InGaZnO4 is shown in Fig. 42(A). This is the structure of an InGaZnO4 crystal. In the Ga-Zn-O layer, the oxygen atoms in each layer are arranged in close proximity. And because the oxygen atom has a negative charge, the two adjacent G Repulsion occurs between the a-Zn-O layers. As a result, the InGaZnO4 crystals The cleavage plane is located between the two Ga-Zn-O layers.

[0318] Ions 5101 generated in the high-density plasma region are applied to the target 5130 side by the electric field. The cleavage plane is accelerated and eventually collides with the target 5130. At this time, flat or pellet-like particles are formed from the cleavage plane. Pellets 5100a and 5100b, which are pellet-shaped sputtered particles, are peeled off and struck. The pellets 5100a and 5100b are the particles of the ions 5101. The impact of a collision can cause distortion in the structure.

[0319] The pellet 5100a is a flat or pellet-shaped pellet having a triangular, for example, equilateral triangular, plane. The pellet 5100b has a hexagonal, for example, regular hexagonal, plane. The sputtered particles are in the form of a plate or pellet. Pellet 5100b and other flat or pellet-shaped sputter particles are collectively referred to as pellet 5. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon. For example, a triangle (e.g., an equilateral triangle) may be formed. In some cases, two squares (e.g., a diamond) are joined together to form a rectangle.

[0320] The thickness of the pellet 5100 is determined depending on the type of deposition gas, etc. The reason for this will be described later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferable to thick cubes. The thickness of the 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The pellet 5100 is (1) in FIG. For example, the target 51 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are bombarded onto the surface 30, a Ga-Zn-O layer and a A pellet 5100 having three layers, an In-O layer and a Ga-Zn-O layer, is exfoliated. (C) shows the structure of the exfoliated pellet 5100 observed from a direction parallel to the c-axis. The 5100 is a nano-structure having two Ga-Zn-O layers (pan) and an In-O layer (core). It can also be called a no-size sandwich structure.

[0321] As the pellet 5100 passes through the plasma, the sides may become negatively or positively charged. The pellet 5100 may, for example, be negatively charged due to the oxygen atoms located on its sides. The sides have charges of the same polarity, which causes repulsion between the charges, forming a flat or pellet-like shape. It is possible to maintain the shape of the CAAC-OS. In the case of oxides, the oxygen atoms bonded to the indium atoms may be negatively charged. Or, an oxygen atom bonded to an indium atom, a gallium atom, or a zinc atom is negatively charged. In addition, when the pellet 5100 passes through the plasma, it may When it grows by bonding with sodium atoms, gallium atoms, zinc atoms, and oxygen atoms, etc. The difference in size between (2) and (1) in Figure 40 above corresponds to the growth in the plasma. Here, when the substrate 5120 is at room temperature, the pellets on the substrate 5120 Since the growth of 5100 is difficult to occur, it becomes nc-OS (see Figure 41(B)). Therefore, nc-OS can be deposited even on a large substrate (5120). In order to grow the pellet 5100 in plasma, the sputtering method is required. Increasing the film formation power is effective. The structure of 00 can be stabilized.

[0322] As shown in Figures 41(A) and 41(B), for example, pellet 5100 is a plasma It flies through the air like a kite and flutters up onto the substrate 5120. Pellet 51 Because 00 is electrically charged, it approaches an area where other pellets 5100 have already accumulated. Here, on the upper surface of the substrate 5120, a repulsive force is generated. In addition, the substrate 5120 and the target 51 Since a potential difference is applied between the substrate 5120 and the target 5130, the Therefore, the pellet 5100 is placed on the upper surface of the substrate 5120 in a magnetic The force (Lorentz force) is exerted by the action of the electric field and the electric current. This can be understood using the left-hand rule.

[0323] The pellet 5100 has a larger mass than a single atom. In order to move the object, it is important to apply some kind of force from the outside. It is possible that the force is generated by the action of the electric field and the electric current. To provide sufficient force to move the top surface of substrate 5120, The magnetic field parallel to the upper surface of the plate 5120 is 10 G or more, preferably 20 G or more, and more preferably It is advisable to provide an area where the resistance is 30 G or more, and more preferably 50 G or more. On the upper surface of the substrate 5120, a magnetic field parallel to the upper surface of the substrate 5120 is applied to the upper surface of the substrate 5120. At least 1.5 times, preferably at least 2 times, more preferably at least 3 times the magnetic field perpendicular to the surface It is preferable to provide an area where the difference is 5 times or more.

[0324] At this time, the magnet and the substrate 5120 move or rotate relative to each other. Therefore, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. On the upper surface of 5120, the pellet 5100 is subjected to forces from various directions and is moved in various directions. It can be moved.

[0325] Also, when the substrate 5120 is heated as shown in FIG. 41(A), the pellet 5100 The resistance due to friction between the substrate 5120 and the pellets is small. The pellet 5100 glides over the top surface of the substrate 5120. The movement occurs with the flat surface facing the substrate 5120. When the particles reach the side of the pellet 5100, the sides are joined together. The oxygen atom on the side of 0 is released. The released oxygen atom Since the electron vacancies may be filled, the CAAC-OS has a low defect level density. The temperature of the upper surface of 5120 is, for example, 100°C or more and less than 500°C, 150°C or more and less than 450°C. or 170° C. or higher and lower than 400° C. Even in this case, it is possible to form a CAAC-OS film.

[0326] Furthermore, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged, The structural distortion caused by the collision of the ions 5101 is relaxed. 00 is almost a single crystal. Pellet 5100 is almost a single crystal, Even if the pellets 5100 are heated after being bonded together, the pellets 5100 themselves do not expand or contract. Therefore, the gaps between the pellets 5100 widen, causing the grains to shrink. It does not form defects such as boundaries or crevasse formation.

[0327] In addition, the CAAC-OS is not made of a single-crystal oxide semiconductor. The aggregates of pellet 5100 (nanocrystals) are arranged like piles of bricks or blocks. In addition, there are no grain boundaries between the pellets 5100. The CAAC-OS was deformed, such as shrinking, due to heating during film formation, heating after film formation, or bending. Even in such cases, it is possible to relieve local stress or release strain. This structure is suitable for use in flexible semiconductor devices. The resulting arrangement resembles randomly stacked nanocrystals.

[0328] When target 5130 is sputtered by ions 5101, not only pellet 5100 but also However, zinc oxide may peel off. Zinc oxide is lighter than pellet 5100, so Therefore, it first reaches the upper surface of the substrate 5120. A zinc oxide layer 5102 having a thickness of 0.5 nm to 2 nm is formed. A schematic cross-sectional view is shown in Figure 43.

[0329] As shown in FIG. 43(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are piled up. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the particles slide on pellet 5105b. In another aspect of 5a, a plurality of particles 5103 detached from the target along with zinc oxide. However, due to the heat from the substrate 5120, it is crystallized to form a region 5105a1. The particles 5103 may include oxygen, zinc, indium, and gallium, among others.

[0330] As shown in FIG. 43(B), the region 5105a1 is integrated with the pellet 5105a. The pellet 5105c has a side surface that is the same as that of the pellet 5105a. It is arranged so as to be in contact with another side surface of 105b.

[0331] Next, as shown in FIG. 43(C), a pellet 5105d is further formed on the pellet 5105a2. and pellet 5105b, and then on pellet 5105a2 and pellet 51 It slides on the other side of the pellet 5105c. The pellet 5105e slides over the zinc oxide layer 5102.

[0332] As shown in FIG. 43(D), the pellet 5105d has a side surface similar to that of the pellet 510. The pellet 5105e is placed so that its side faces the pellet. Also, the other side of the pellet 5105d is arranged so as to be in contact with the other side of the pellet 5105c. In the process, a plurality of particles 5103 peeled off from the target 5130 together with zinc oxide are deposited on the substrate. Heat from 5120 causes crystallization, forming region 5105d1.

[0333] As described above, the piled pellets are arranged so that they come into contact with each other, and the particles are formed on the side surfaces of the pellets. As a result of this growth, a CAAC-OS is formed on the substrate 5120. The individual pellets of C-OS are larger than those of nc-OS. The difference in size between (1) and (2) corresponds to the growth after deposition.

[0334] In addition, the gaps between the pellets become extremely small, so that one large pellet is formed. One large pellet may have a single crystal structure. The thickness is 10 nm or more and 200 nm or less, or 15 nm or more and 100 nm or less, as viewed from the top surface, or In some cases, the thickness may be between 20 nm and 50 nm. In some nitride semiconductors, the channel formation region may fit into one large pellet. That is, the region having a single crystal structure can be used as a channel forming region. As the size of the dot increases, the region having a single crystal structure becomes the channel formation region of the transistor, It may be used as a source region and a drain region.

[0335] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. This may improve the frequency characteristics of the transistor.

[0336] Based on the above model, it is considered that the pellet 5100 accumulates on the substrate 5120. CAAC-OS can be formed even when the surface to be formed does not have a crystalline structure. This indicates that the growth mechanism is different from epitaxial growth. C-OS does not require laser crystallization and can be deposited uniformly even on large glass substrates. For example, if the structure of the upper surface (surface to be formed) of the substrate 5120 is an amorphous structure (for example, non-crystalline), It is possible to form a CAAC-OS film even on a silicon dioxide (crystalline silicon dioxide).

[0337] In addition, even if the upper surface of the substrate 5120 on which the formation is to be performed is uneven, the CAAC-OS For example, the pellets 5100 are arranged along the shape of the upper surface of the substrate 5120. If the surface is atomically flat, the pellet 5100 will be placed on a flat surface parallel to the ab plane. If the pellet 5100 has a uniform thickness, the thickness is uniform and flat, and A layer with high crystallinity is formed. Then, this layer is stacked n levels (n is a natural number). This allows the CAAC-OS to be obtained.

[0338] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 510 The structure is made up of n layers (n is a natural number) of layers in which 0s are arranged along the unevenness. Since the surface 20 has unevenness, gaps tend to occur between the pellets 5100. However, even in this case, intermolecular forces act between the pellets 5100, and unevenness Therefore, even if there are unevenness, the gaps between the pellets are arranged as small as possible. A CAAC-OS having high crystallinity can be obtained.

[0339] Since the CAAC-OS film is formed using this model, the sputtered particles have a small thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0340] The film formation model shown above allows for the formation of highly crystalline films even on a surface with an amorphous structure. A CAAC-OS having the formula:

[0341] When an oxide semiconductor film has multiple structures, the structure can be resolved by using nanobeam electron diffraction. analysis may be possible.

[0342] FIG. 20C shows an electron gun chamber 610, an optical system 612 below the electron gun chamber 610, and an optical system 613 below the electron gun chamber 610. 12, a sample chamber 614, an optical system 616, and a viewfinder 618. An observation room 620, a camera 618 installed in the observation room 620, and a film below the observation room 620. The transmission electron diffraction measurement apparatus shown has a chamber 622. The camera 618 is located inside the observation chamber 620. The film chamber 622 does not necessarily have to be provided.

[0343] FIG. 20(D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. 20(C). Inside the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 610 The electrons are irradiated onto a substance 628 placed in a sample chamber 614 via an optical system 612. The electrons passing through 28 are projected onto a fluorescent screen 63 installed inside an observation chamber 620 via an optical system 616. On the fluorescent screen 632, a pattern appears according to the intensity of the incident electrons. A transmission electron diffraction pattern can be measured.

[0344] The camera 618 is set facing the fluorescent screen 632 and captures the pattern that appears on the fluorescent screen 632. The center of the lens of the camera 618 and the center of the fluorescent screen 632 can be photographed. The angle between the line passing through the center and the upper surface of the fluorescent screen 632 is, for example, 15° or more and 80° or less. , 30° to 75° or 45° to 70°. The smaller the angle, the The transmission electron diffraction pattern taken by MERA 618 is highly distorted. If this angle is known, it is possible to correct distortions in the obtained transmission electron diffraction pattern. There are cases where the camera 618 may be installed in the film chamber 622. For example, The camera 618 is installed in the film chamber 622 so as to face the incident direction of the electrons 624. In this case, a transmission electron diffraction pattern with little distortion is captured from the rear surface of the fluorescent screen 632. It is possible.

[0345] In the sample chamber 614, a holder for fixing a substance 628 as a sample is installed. The holder is constructed to be transparent to electrons passing through the material 628. For example, the holder may have a function to move the substance 628 in the X-axis, Y-axis, Z-axis, etc. The movement function can be, for example, 1 nm to 10 nm, 5 nm to 50 nm, or 10 nm or more. Ranges such as 100nm or less, 50nm to 500nm, and 100nm to 1μm. These ranges are optimal depending on the structure of the substance 628. Just set it as follows.

[0346] Next, the transmission electron diffraction pattern of the substance is measured using the above-mentioned transmission electron diffraction measurement device. This article explains how to do this.

[0347] For example, as shown in FIG. 20(D), the irradiation position of the electron 624, which is a nanobeam, in the material By changing the position (scanning), we can observe how the structure of a material changes. In this case, if the substance 628 is a CAAC-OS film, as shown in FIG. Alternatively, if the material 628 is an nc-OS film, a diffraction pattern similar to that shown in FIG. A diffraction pattern similar to that shown in B) is observed.

[0348] By the way, even if the material 628 is a CAAC-OS film, it may be partially an nc-OS film. Therefore, the quality of the CAAC-OS film can be evaluated. is the ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CA It can be expressed as follows: For example, a high-quality CAAC-OS film can be If so, the CAAC conversion rate is 50% or more, preferably 80% or more, and more preferably 90% or more. % or more, and more preferably 95% or more. The percentage of the area where CAAC is observed is referred to as the non-CAAC rate.

[0349] As an example, immediately after film formation (denoted as as-sputtered), or in an atmosphere containing oxygen The top surface of each sample with the CAAC-OS film after the heat treatment at 450°C in air was scanned. Transmission electron diffraction patterns were acquired while scanning at a speed of 5 nm / s for 60 seconds. The diffraction pattern was observed while scanning, and the observed diffraction pattern was captured as a still image every 0.5 seconds. The CAAC rate was calculated by converting the electron beam into the probe diameter of 1n. The nano-beam electron beam of 1000 nm was used. The same measurements were carried out on six samples. The AC conversion rate was calculated using the average value of six samples.

[0350] The CAAC conversion rate for each sample is shown in Figure 21(A). The AAC conversion rate was 75.7% (non-CAAC conversion rate was 24.3%). The CAAC content of the treated CAAC-OS membrane was 85.3% (non-CAAC content was 14.7%). It can be seen that the CAAC conversion rate is higher after heat treatment at 450°C than immediately after film formation. That is, the non-CAAC rate is reduced by heat treatment at a high temperature (for example, 400°C or higher). It can be seen that the CAAC conversion rate increases (the CAAC conversion rate increases). It can be seen that a CAAC-OS film with a high CAAC content can be obtained even with the SiO2 solution.

[0351] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. The amorphous oxide semiconductor film was not observed in the measurement area. Therefore, the heat treatment did not produce a region with a structure similar to that of the nc-OS film. However, it is suggested that the structure of the adjacent region influences the rearrangement and formation of CAAC. .

[0352] 21(B) and 21(C) show the CAAC- 21(B) and 21(C) are planar TEM images of the OS film. It can be seen that the CAAC-OS film after the heat treatment at 50°C has a more uniform film quality. It can be seen that the film quality of the CAAC-OS film is improved by heat treatment at a low temperature.

[0353] This measurement method makes it possible to analyze the structure of oxide semiconductor films with multiple structures. This may be the case.

[0354] The CAAC-OS film can be formed, for example, by the following method.

[0355] The CAAC-OS film can be formed by sputtering a polycrystalline oxide semiconductor target. The film is formed by sputtering using the RF sputtering method, D C sputtering, AC sputtering, or the like can be used. To improve the uniformity of the distribution, film composition distribution, or crystallinity distribution, It is preferable to use DC sputtering or AC sputtering.

[0356] By increasing the substrate temperature during film formation, migration of sputtered particles after reaching the substrate is prevented. Specifically, the substrate temperature is set to 100°C or higher and 740°C or lower, preferably 200°C or higher. The film is formed at a temperature of 500°C or less. By increasing the substrate temperature during film formation, the sputtering particles When the particles reach the substrate, migration occurs on the substrate, and the sputtered particles are flattened. At this time, the sputtering particles are positively charged, The ring particles repel each other while adhering to the substrate, resulting in uneven sputtering. Therefore, a CAAC-OS film with a uniform thickness can be formed without overlapping.

[0357] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0358] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition can be reduced. The oxygen ratio in the film forming gas is 30% by volume or more, preferably 100% by volume or more. Expressed as volume %.

[0359] Alternatively, the CAAC-OS film is formed by the following method.

[0360] First, a first oxide semiconductor film is formed to a thickness of 1 nm or more and less than 10 nm. The semiconductor film is formed by sputtering. Specifically, the substrate temperature is set to 100°C or higher. The temperature is set to 500°C or less, preferably 150°C to 450°C, and the oxygen ratio in the deposition gas is set to 30 The film is formed at a concentration of at least 100% by volume, preferably 100% by volume.

[0361] Next, heat treatment is performed to convert the first oxide semiconductor film into a first CAAC-OS film having high crystallinity. The temperature of the heat treatment is 350°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heat treatment time is 1 minute to 24 hours, preferably 6 minutes to 4 hours. The heat treatment may be carried out in an inert atmosphere or an oxidizing atmosphere. Alternatively, heat treatment is performed in an inert atmosphere, and then heat treatment is performed in an oxidizing atmosphere. By the heat treatment in the atmosphere, the impurity concentration of the first oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies are generated in the first oxide semiconductor film by heat treatment in an inert atmosphere. In this case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. Heat treatment can be carried out at a pressure of 1000 Pa or less, 100 Pa or less, 10 Pa or less, or The step of removing the oxide semiconductor film from the first oxide semiconductor film may be performed under a reduced pressure of 1 Pa or less. can be reduced in an even shorter time.

[0362] The first oxide semiconductor film has a thickness of 1 nm or more and less than 10 nm. Compared with a thickness of 0 nm or more, it can be easily crystallized by heat treatment.

[0363] Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is formed to a thickness of 10 nm or more. The second oxide semiconductor film is formed to a thickness of 0 nm or less by sputtering. Specifically, the substrate temperature is set to 100°C or higher and 500°C or lower, preferably 150°C or higher and 450°C or lower. The oxygen content in the deposition gas is 30% by volume or more, preferably 100% by volume. To film.

[0364] Next, heat treatment is performed to form a second oxide semiconductor film from the first CAAC-OS film by solid-phase growth. The second CAAC-OS film was obtained by heating at a temperature of 350 The temperature is set to 740°C or higher, preferably 450°C or higher and 650°C or lower. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be carried out in an inert atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is carried out in an inert atmosphere. After that, heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the nitride semiconductor film can be reduced in a short time. Oxygen vacancies may be generated in the second oxide semiconductor film by the heat treatment. The oxygen deficiency can be reduced by heat treatment in a reactive atmosphere. It may be carried out under reduced pressure of 000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the second oxide semiconductor film can be reduced in a shorter time. Cut.

[0365] In this manner, a CAAC-OS film having a total thickness of 10 nm or more is formed. can be done.

[0366] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0367] (Embodiment 3) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. This will be explained with reference to the following.

[0368] [Circuit configuration example] In the configuration shown in Embodiment 1, the connection configuration of the transistors, wirings, and electrodes may be changed. By using the semiconductor device according to one embodiment of the present invention, various circuits can be configured. An example of a circuit configuration that can be realized by using the device will be described.

[0369] [CMOS Circuit] The circuit diagram shown in FIG. 22A includes a p-channel transistor 2200 and an n-channel transistor The transistors 2100 are connected in series and the gates of the transistors are connected together. The figure shows the configuration of an OS circuit. In the figure, the transistors to which the second semiconductor material is applied are are indicated with the symbol "OS."

[0370] [Analog Switch] The circuit diagram shown in FIG. 22B shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called analog switch.

[0371] [Example of storage device] By using a transistor according to one embodiment of the present invention, it is possible to keep the stored contents even when power is not supplied. An example of a semiconductor device (memory device) that can retain data and has no limit on the number of times it can be written is shown in Figure 2. Shown in 2.

[0372] The semiconductor device shown in FIG. 22C includes a transistor 3200 using a first semiconductor material and The semiconductor device includes a transistor 3300 and a capacitor 3400 made of a second semiconductor material. Note that the transistor 3300 is any of the transistors exemplified in the above embodiments. It is possible.

[0373] In this embodiment, the transistor 3300 is a transistor having a semiconductor layer including an oxide semiconductor. The transistor 3300 has an off-state current Since the capacitance is small, it is possible to retain memory contents for a long period of time by using this. In other words, no refresh operation is required, or the frequency of refresh operation is extremely low. Therefore, it is possible to reduce the power consumption of the semiconductor memory device. can.

[0374] In FIG. 22C, a first wiring 3001 is connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode of the transistor 3300 or The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the The other of the source electrode and the drain electrode of the transistor 3300 is connected to a capacitor 3400 The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. and is electrically connected.

[0375] In the semiconductor device shown in FIG. 22C, the potential of the gate electrode of the transistor 3200 is maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0376] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitor element 3400. That is, the gate electrode of the transistor 3200 is A predetermined charge is applied (write). Here, two different potential levels are applied. Either a low-level charge or a high-level charge is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By turning the transistor 3300 to the off state, the The charge applied to the gate electrode is retained (retention).

[0377] Since the off-state current of the transistor 3300 is extremely small, the gate The charge on the electrode is maintained for a long period of time.

[0378] Next, reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode of the transistor 3200, the second wiring 3002 has different potentials. Generally, if the transistor 3200 is an n-channel type, the transistor 320 The apparent threshold voltage V when a high level charge is applied to the gate electrode of th_ H is the state when a low level charge is applied to the gate electrode of transistor 3200. Threshold V th_L Here, the apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L Between By setting the potential V0 at the gate electrode of the transistor 3200, the charge applied to the gate electrode of the transistor 3200 can be determined. For example, if a high level charge is applied during writing, The potential of the fifth wiring 3005 is V0 (>V th_H ), then transistor 3200 is " When a low level charge is applied, the fifth wiring 3005 is in the "ON state." The potential is V0( <V th_L ), transistor 3200 remains in the "off state" Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be seen.

[0379] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless ofth_ H A smaller potential may be applied to the fifth wiring 3005. Alternatively, depending on the state of the gate electrode, The potential at which transistor 3200 remains "on," i.e., V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0380] The semiconductor device shown in FIG. 22D is different from the semiconductor device shown in FIG. 2 mainly in that the transistor 3200 is not provided. In this case, the same operations as above are performed to write and store information. It is possible to create

[0381] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in a floating state and the capacitor element 3400 are electrically connected to each other. As a result, the potential of the third wiring 3003 is The amount of change in the potential of the third wiring 3003 is the potential of one of the electrodes of the capacitor 3400. (or the charge stored in the capacitor 3400).

[0382] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the The capacitance component of the third wiring 3003 is CB, and the capacitance of the third wiring 3003 before the charge is redistributed is If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB ×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of one of the electrodes of the element 3400 takes two states, V1 and V0 (V1>V0), then: The potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (=( It can be seen that this is higher than (CB×VB0+C×V0) / (CB+C)).

[0383] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0384] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cells. The transistor 3300 is a transistor in which a second semiconductor material is applied. The transistor may be stacked on the driver circuit.

[0385] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By applying transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is not required or the refresh operation is Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, even if there is no power supply (however, it is desirable that the potential is fixed), Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0386] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem of element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. Therefore, the problem of deterioration of the gate insulating film does not occur at all. In this device, there is no limit to the number of times it can be rewritten, which is a problem with conventional non-volatile memory. Reliability will be dramatically improved. Furthermore, the on / off state of the transistor determines the information Since the data is written in the memory, high-speed operation can be easily achieved.

[0387] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0388] (Fourth embodiment) In this embodiment, an example of a semiconductor device including a transistor according to one embodiment of the present invention will be described. FIG. 29 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. Here is an example.

[0389] The semiconductor device shown in FIG. 29 includes a capacitor 660a, a capacitor 660b, and a transistor 661a, transistor 661b, transistor 662a, and transistor 662b , an inverter 663a, an inverter 663b, a wiring BL, a wiring BLB, and a wiring W L, wiring CL, and wiring GL.

[0390] In the semiconductor device shown in FIG. 29, an inverter 663a and an inverter 663b are connected in a ring. The output of inverter 663b is a memory cell that forms a flip-flop by connecting the The node from which the output signal is output is node VN1, and the output signal of inverter 663a is output. The node VN2 is the node where the memory cells are arranged in a matrix. , a memory device (memory cell array) can be configured.

[0391] One of the source and drain of the transistor 662a is electrically connected to the wiring BL. The other drain is electrically connected to a node VN1, and the gate is electrically connected to a wiring WL. One of the source and drain of the transistor 662b is electrically connected to the node VN2. The other of the source and drain is electrically connected to the wiring BLB, and the gate is electrically connected to the wiring WL. To be continued.

[0392] One of the source and drain of the transistor 661a is electrically connected to the node VN1. The other of the source and drain is electrically connected to one electrode of the capacitor element 660a, and the gate is connected to a wiring GL. Here, the other of the source and drain of the transistor 661a and A node between one electrode of the capacitor 660a and the transistor 660b is referred to as a node NVN1. One of the source and drain of 661b is electrically connected to the node VN2. The other electrode of the capacitor 660b is electrically connected to one electrode of the capacitor 660b, and the gate of the capacitor 660b is electrically connected to the wiring GL. Here, the other of the source and drain of the transistor 661b and the capacitor element 660 The node between one electrode of b and is defined as node NVN2.

[0393] The other electrode of the capacitor 660a is electrically connected to the wiring CL. One electrode is electrically connected to the wiring CL.

[0394] The conductive and non-conductive states of the transistors 662a and 662b are selected as follows: The potential can be controlled by applying a potential to the wiring WL. The selection of the conductive state or non-conductive state of the transistor 661b is controlled by the potential applied to the wiring GL. It is possible.

[0395] The writing, holding and reading of the memory cell shown in FIG. 29 will be described below.

[0396] When writing, first, a voltage corresponding to data 0 or data 1 is applied to the wiring BL and wiring BLB. Apply a voltage.

[0397] For example, if you want to write data 1, set the line BL to a high-level power supply potential (VDD), The wiring BLB is set to the ground potential. Next, the transistor 662a and the transistor 662b are connected to the wiring WL. A potential (VH) equal to or higher than the potential obtained by adding VDD to the threshold voltage of 62b is applied.

[0398] Next, the potential of the wiring WL is set to the threshold voltage of the transistor 662a and the transistor 662b. By setting it to less than 1, the data 1 written to the flip-flop is held.

[0399] When reading, the wiring BL and the wiring BLB are set to VDD in advance. By applying VH to the BL line, the BL line remains at VDD, but the BLB line The wiring BL The potential difference between the line BLB and the line BLB is amplified by a sense amplifier (not shown). Data 1 can be read.

[0400] If you want to write data 0, set the line BL to the ground potential and the line BLB to VDD. Then, VH is applied to the wiring WL. a, by making it less than the threshold voltage of the transistor 662b, it is possible to write to the flip-flop. When reading, the line BL and line BLB are set to VD By applying VH to the wiring WL, the wiring BLB remains at VDD, but The line BL is discharged through the transistor 662b and the inverter 663b to the ground potential. The potential difference between the wiring BL and the wiring BLB is amplified by a sense amplifier and maintained. The stored data 0 can be read.

[0401] Therefore, the semiconductor device shown in FIG. 29 is a so-called SRAM (Static Random Access Memory). SRAM functions as a high-speed access memory (HSRAM). Therefore, the data is retained by the refresh operation. Power consumption can be reduced. In addition, since no capacitance element is used in the flip-flop, Therefore, it is suitable for applications requiring high speed operation.

[0402] In addition, the semiconductor device shown in FIG. 29 receives the voltage from the node VN1 through the transistor 661a. Data can be written to the node NVN1. Similarly, the transistor 661b It is possible to write data from node VN2 to node NVN2 via The data written thereto makes the transistor 661a or the transistor 661b non-conductive. For example, even if the supply of power supply potential is stopped, the nodes VN1 and VN2 are maintained. In some cases, the data of node VN1 and node VN2 can be retained.

[0403] Unlike conventional SRAM, in which data is immediately lost when the supply of power supply potential is stopped, The semiconductor device shown in FIG. 1 can retain data even after the supply of power supply potential is stopped. By turning on or off the power supply potential as needed, a semiconductor device with low power consumption can be realized. For example, by using the semiconductor device shown in FIG. 29 in the memory area of ​​the CPU, It is also possible to reduce the power consumption of the PU.

[0404] The period for which data is held at the nodes NVN1 and NVN2 is determined by the transistor It can be seen that the change is due to the off-current of the transistor 661a and the transistor 661b. Therefore, in order to extend the data retention period, the transistor 661a and the transistor A transistor with low off-state current may be used for 661b. This can be achieved by increasing the capacitance of capacitor 660a and capacitor 660b.

[0405] For example, the transistor 100 and the capacitor 150 described in Embodiment 1 may be If the capacitor 661a and the capacitor 660a are used, the node NVN1 will Similarly, the transistor 100 and the capacitor 150 When the transistor 661b and the capacitor 660b are used, a long Therefore, the data can be held for a long period of time. For transistor 661b, see the description of transistor 100. In addition, the capacitance elements 660a and 660b are the same as those of the capacitance element 150. Please refer to the description below.

[0406] As described in the above embodiment, the transistor 100 is provided with the plug 121 and the plug By using the delay 122, the occupancy of the elements including the transistor 100 and the capacitance element 150 can be The area can be reduced. b, the capacitor element 660a and the capacitor element 660b are the transistors described in the above embodiment. Therefore, the semiconductor device shown in FIG. can be fabricated without significantly increasing the area occupied by conventional SRAM. The transistor 662a, the transistor 662b, and the inverter 663a may be included. The transistors included in the inverter 663b and the transistors included in the inverter 663c are Please refer to the description of the transistor 130.

[0407] As described above, the semiconductor device according to one embodiment of the present invention has high performance relative to the area it occupies. It is also clear that this is a semiconductor device with high productivity.

[0408] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0409] (Embodiment 5) In this embodiment, the R The F tag will be explained with reference to FIG.

[0410] The RF tag in this embodiment has a memory circuit inside, and stores necessary information in the memory circuit. It stores information and transmits and receives information to and from the outside using non-contact means, such as wireless communication. Due to these characteristics, RF tags can identify items by reading their individual information. It can be used for individual authentication systems, etc. Extremely high reliability is required. Here, RF tags are used to identify items, for example, as IDs. It may also be an RFID tag that recognizes the identifying information to be revealed.

[0411] The structure of an RF tag will be described with reference to Fig. 23. Fig. 23 shows an example of the structure of an RF tag. FIG.

[0412] As shown in FIG. 23, an RF tag 800 includes a communicator 801 (such as an interrogator, reader / writer, etc.). 803 is transmitted from an antenna 802 connected to The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 804, and a 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectifying action included in the demodulation circuit 807 is sufficiently suppressed. A material capable of controlling the temperature, such as an oxide semiconductor, may be used. This suppresses the degradation of rectification caused by reverse current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linearity. The data transmission format is a pair of coils arranged facing each other and communicating by mutual induction. electromagnetic coupling method, which communicates by induced electromagnetic fields; electromagnetic induction method, which communicates by using radio waves; The RF tag 800 shown in this embodiment is compatible with any of these methods. It can also be used in formulas.

[0413] Next, the configuration of each circuit will be explained. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 adjusts the input AC signal generated by receiving a radio signal with the antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is averaged by a capacitive element provided in the subsequent stage. The rectifier circuit 805 is a circuit for generating an input potential by smoothing the input voltage. A limiter circuit may be provided on the output side. When the internally generated voltage is large, power above a certain level is not input to the subsequent circuit. This is a circuit for controlling the

[0414] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generator uses the rising edge of the stable power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0415] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0416] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for doing this.

[0417] The above-mentioned circuits can be selected or removed as needed.

[0418] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. Furthermore, the memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, It is also possible to eliminate the difference in maximum communication distance when reading and writing data. and suppressing malfunctions or erroneous writing caused by a power shortage when writing data. This can be done.

[0419] The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the manufacturer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to all the RF tags produced, we will assign a unique number to only the good products that are shipped. This means that the unique numbers of products will be discontinuous after shipment. This makes it easier to manage customers' needs after products are shipped.

[0420] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0421] (Embodiment 6) In this embodiment, at least the transistors described in the embodiment can be used. Next, a CPU including the storage device described in the previous embodiment will be described.

[0422] FIG. 24 shows a CPU using the transistors described in the previous embodiments at least in part. FIG. 1 is a block diagram showing an example of a configuration.

[0423] The CPU shown in FIG. 24 includes an ALU 1191 (Arithmetic and logic unit) on a board 1190. tic logic unit, arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 24 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their use. For example, the CPU or the configuration including the arithmetic circuit shown in FIG. 24 is regarded as one core, and the core is divided into multiple It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by a calculation circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0424] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0425] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0426] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals that control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generator generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0427] In the CPU shown in FIG. 24, a memory cell is provided in the register 1196. The transistor described in the above embodiment can be used as the memory cell of the memory cell 1196. Cut.

[0428] In the CPU shown in FIG. 24, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0429] FIG. 25 is a circuit diagram of an example of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as needed. The transistor 1209 is an oxide semiconductor. Preferably, the transistor has a channel formed in the semiconductor layer.

[0430] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of power supply voltage to the memory element 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0431] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 3 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of the transistor 1213 (i.e., the on-state or off-state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the transistor 1214. The switch 1204 is connected to the gate of the transistor 1214. The control signal RD input to the first terminal determines whether or not the first terminal is electrically connected to the second terminal. The on or off state of transistor 1214 is selected.

[0432] One of the source and drain of the transistor 1209 is connected to one of the pair of electrodes of the capacitor 1208. The gate of the transistor 1210 is electrically connected to one of the gates of the transistor 1210. The part is designated as node M2. One of the source and drain of the transistor 1210 is connected to the low power supply voltage. The other is electrically connected to a wiring (for example, a GND line) that can supply a voltage. The first terminal of the transistor 1203 (one of the source and drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the other terminal of the switch 1204 (the source and drain of the transistor 1214) The second terminal of the switch 1204 (one of the terminals of the transistor 1214) is electrically connected to the The other of the source and drain) is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) the input terminal of the logic element 1206 and one of the pair of electrodes of the capacitor 1207. , are electrically connected. Here, the connection point is referred to as node M1. The other electrode of the pair may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a The pair of electrodes of the capacitor 1208 are electrically connected to a wiring (for example, a GND line). The other terminal may be configured to receive a constant potential. For example, a low power supply potential (GND The capacitor element 12 may be configured to receive a high power supply potential (VDD, etc.) or a high power supply potential (VDD, etc.). The other of the pair of electrodes 08 is connected to a wiring (e.g., GN D line).

[0433] The capacitors 1207 and 1208 are formed by using parasitic capacitances of transistors and wirings. It is also possible to omit this by actively using

[0434] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are connected to a control signal R, which is different from the control signal WE. D selects the conductive state or non-conductive state between the first terminal and the second terminal, and one When the first terminal and the second terminal of the switch are in a conductive state, the first terminal of the other switch and The second terminals are in a non-conductive state.

[0435] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 25, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. and input to the circuit 1201.

[0436] In FIG. 25, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the other drain is passed through the logic element 1206 and the circuit 1220. Although an example of inputting the signal to the circuit 1201 is shown, this is not limiting. The signal output from the other of the source and drain of the transistor 1213 is It may be input to the circuit 1201 without being inverted. For example, If there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal, In this case, the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) can be input to the node.

[0437] In addition, in FIG. 25, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed on a layer or substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed in oxide semiconductor layers. Alternatively, the storage element 1200 may be a transistor 1209 or a In addition, a transistor in which a channel is formed in an oxide semiconductor layer may be included. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It may also be a transistor formed by

[0438] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0439] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0440] In addition, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer increases depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using the transistor as the transistor 1209, Even when the power supply voltage is not supplied to the capacitor 1200, the signal held in the capacitor 1208 is maintained for a long period of time. In this way, the memory element 1200 can maintain its stored contents ( It is possible to retain the data.

[0441] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the following operation, after the power supply voltage is supplied again, the circuit 1201 This can shorten the time it takes to restore the original data.

[0442] In the circuit 1202, the signal held by the capacitor 1208 is transferred to the transistor. Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the capacitor 1208 is opened, the signal held by the capacitor 1208 is transferred to the transistor 1210 (ON state or OFF state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0443] Such a storage element 1200 may be a register or cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one of the components of the processor, In addition, power can be stopped for a short period of time in multiple logic circuits, reducing power consumption. can be suppressed.

[0444] In this embodiment, the storage element 1200 is used as a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSIs such as LSIs and PLDs (Programmable Logic Devices), It can also be applied to RF (Radio Frequency) tags.

[0445] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0446] (Embodiment 7) In this embodiment, a structural example of a display panel according to one embodiment of the present invention will be described.

[0447] [Configuration example] FIG. 26A is a top view of a display panel of one embodiment of the present invention, and FIG. 26B is a top view of a display panel of one embodiment of the present invention. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. 26C is a circuit diagram illustrating a display panel according to one embodiment of the present invention. A circuit for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel. Figure.

[0448] The transistors disposed in the pixel portion can be formed according to the above-described embodiment modes. In addition, since the transistor can be easily made into an n-channel type, the n-channel transistor in the driver circuit can be easily made into an n-channel type. A part of the driver circuit can be configured with a panel-type transistor, and the transistors in the pixel section can be In this way, the transistor shown in the above embodiment mode is formed in the pixel portion and the driver circuit. By using the capacitor, a highly reliable display device can be provided.

[0449] An example of a block diagram of an active matrix display device is shown in FIG. On this substrate 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 703, and a The pixel portion 701 has a signal line driver circuit 703 and a signal line driver circuit 704. A plurality of scanning lines are arranged extending from a first scanning line driving circuit 702 and a second scanning line driving circuit 704. The scanning lines are arranged extending from the second scanning line driving circuit 703. In the area, pixels each having a display element are arranged in a matrix. The substrate 700 of the device is a connection board such as an FPC (Flexible Printed Circuit). It is connected to a timing control circuit (also called a controller or control IC) via a connection. do.

[0450] In FIG. 26A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal The line driver circuit 704 is formed on the same substrate 700 as the pixel portion 701. The number of components such as drive circuits to be provided is reduced, which contributes to cost reduction. 700 If an external drive circuit is provided, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve reliability or yield.

[0451] [LCD panel] An example of the circuit configuration of a pixel is shown in Figure 26(B). 1 shows a pixel circuit that can be applied to the pixel of FIG.

[0452] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels of the multi-domain designed pixel to be moved. The signals applied to the electrode layers can be controlled independently.

[0453] The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are separated so that different gate signals can be applied. The source electrode layer or drain electrode layer 714 functioning as a transistor 716 is Transistor 716 and transistor 717 are used in common. The transistor 100 described in the above embodiment can be used as appropriate. Therefore, a high-quality liquid crystal display panel can be provided.

[0454] A first pixel electrode layer electrically connected to the transistor 716 and a second pixel electrode layer electrically connected to the transistor 717 are The shape of the second pixel electrode layer that is electrically connected to the first pixel electrode layer will be described. The shape of the pixel electrode layer is separated by slits. The first pixel electrode layer spreads in a V-shape. The second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0455] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the gate electrode of the transistor 717 is connected to the gate wiring 712. The gate electrode of the gate electrode 712 is connected to the gate wiring 713. 3, different gate signals are applied to transistors 716 and 717. By varying the voltage, the orientation of the liquid crystal can be controlled.

[0456] Also, the capacitor wiring 710, the gate insulating film functioning as a dielectric, and the first pixel electrode layer Alternatively, a storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0457] The multi-domain structure has a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. can be.

[0458] It should be noted that the pixel circuit shown in FIG. 26(B) is not limited to this. For example, The pixel shown may be newly equipped with a switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit. etc. may be added.

[0459] [Organic EL panel] Another example of the circuit configuration of a pixel is shown in FIG. 26(C). 1 shows the pixel structure of the display panel.

[0460] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of the pair of electrodes. and holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, When the excited state returns to the ground state, light is emitted. The optical element is called a current-excited light-emitting element.

[0461] FIG. 26(C) is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. can be used for the channel formation region of an n-channel transistor. The pixel circuit can be applied with digital time gray scale driving.

[0462] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, and explain.

[0463] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light emitting element. The switching transistor 721 has a gate element 724 and a capacitor element 723. The source electrode layer is connected to the scan line 726, and the first electrode (one of the source electrode layer and the drain electrode layer) is connected to the scan line 726. The first electrode (the other of the source electrode layer and the drain electrode layer) is connected to a signal line 725, and the second electrode (the other of the source electrode layer and the drain electrode layer) is connected to a It is connected to the gate electrode layer of the driving transistor 722. The gate electrode layer is connected to a power supply line 727 through a capacitor element 723, and the first electrode is connected to the power supply line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light emitting element 724 corresponds to the common electrode 728. The common electrode 728 is formed on the same substrate. It is electrically connected to the common potential line formed thereon.

[0464] The switching transistor 721 and the driving transistor 722 are the same as those in the above embodiment. The transistor 100 described later can be used as appropriate. It is possible to provide a functional EL display panel.

[0465] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727, for example, GN The low power supply potential can be set to D, 0V, etc. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the minimum voltage. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage of 24 refers to the voltage required to achieve the desired brightness, and is at least Includes threshold voltage.

[0466] The capacitor 723 is substituted for the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the gate electrode layer and the insulating layer.

[0467] Next, a description will be given of the signal input to the driving transistor 722. Voltage input voltage driving In this method, the driving transistor 722 is in two states: fully on or off. A video signal that becomes a pixel value is input to the driving transistor 722. In order to operate the motor 722 in the linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive A signal line 725 is connected to the gate electrode layer of the transistor 722. A voltage equal to or greater than the threshold voltage Vth of the driving transistor 722 is applied.

[0468] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 7 24 plus the threshold voltage Vth of the driving transistor 722. In addition, a video signal is input so that the driving transistor 722 operates in the saturation region. This causes a current to flow through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is passed to the light emitting element 724. Furthermore, analog gradation driving can be performed.

[0469] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. 6(C) in the pixel circuit, a switch, a resistor, a capacitor, a sensor, a transistor or a logic A logic circuit or the like may be added.

[0470] When the transistors exemplified in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0471] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0472] (Embodiment 8) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, and the like. Image playback device (typically DVD: Digital Versatile Disk) c) a device having a display that can play back a recording medium such as a In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used As such, mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras cameras such as digital still cameras, goggle-type displays (head-mounted displays), Play), navigation systems, sound reproduction equipment (car audio, digital audio copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. show.

[0473] FIG. 27A shows a portable game machine, which includes a housing 901, a housing 902, a display portion 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 27(A) has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. stomach.

[0474] FIG. 27(B) shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit The first display unit 91 has a first display unit 913, a second display unit 914, a connection unit 915, an operation key 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The display may be switched according to the angle between the first display unit 913 and the second display unit 912. and a display having a function as a position input device added to at least one of the first display unit 914 and the second display unit 915. The function as a position input device can be achieved by touching the display device. Alternatively, the function as a position input device can be added by providing a panel. It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel section of the display device. This can be done.

[0475] FIG. 27C shows a notebook personal computer, which includes a housing 921, a display portion 922, It has a keyboard 923, a pointing device 924, and the like.

[0476] FIG. 27(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, a freezer compartment door 933, and a It has 33 etc.

[0477] FIG. 27(E) shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. , operation keys 944, a lens 945, a connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 42.

[0478] FIG. 27(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, It has Light 954 etc.

[0479] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0480] (Embodiment 9) In this embodiment, a usage example of an RF tag according to one embodiment of the present invention will be described with reference to FIG. RF tags are used in a wide range of applications, including banknotes, coins, securities, and unregistered Bonds, certificates (driver's licenses, resident cards, etc., see Figure 28(A)), packaging containers (wrapping paper bottles, etc., see Figure 28(C), recording media (DVDs, video tapes, etc., see Figure 28(B)) (See Figure 28(D)), vehicles (bicycles, etc.), personal belongings (bags, glasses, etc.), food, Plants, animals, the human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronic devices ( LCD displays, EL displays, televisions, or mobile phones) or other items It can be attached to tags (see Figure 28(E) and Figure 28(F)) that are attached to each item. can.

[0481] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface. It is fixed to the object. For example, if it is a book, it is embedded in the paper and the packaging is made of organic resin. If so, the RF tag according to one aspect of the present invention is embedded in the organic resin and fixed to each article. The GU4000 is small, thin, and lightweight, so even after it is fixed to an object, it does not lose its shape. It does not impair the design of banknotes, coins, securities, bearer bonds, or certificates. By providing an RF tag 4000 according to one embodiment of the present invention to a document or the like, an authentication function is provided. By utilizing this authentication function, it is possible to prevent counterfeiting. The present invention can be applied to vessels, recording media, personal belongings, food, clothing, household goods, electronic devices, etc. By attaching an RF tag according to one aspect, the efficiency of a system such as an inspection system can be improved. Furthermore, even in the case of vehicles, the RF tag according to one aspect of the present invention can be attached. This can improve security against theft and the like.

[0482] As described above, the RF tag according to one aspect of the present invention can be used for the applications listed in this embodiment. This reduces the operating power consumption, including that for writing and reading information, thereby extending the maximum communication distance. It is also possible to keep the information for a very long time even when the power is cut off. Since it can be retained for a long period of time, it can be used suitably for applications where writing and reading are not performed frequently. can.

[0483] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Explanation of symbols]

[0484] 624 electronic 628 Substance 100 transistors 101 Semiconductor layer 101a Semiconductor layer 101b Semiconductor layer 101c Semiconductor layer 102 Gate insulating film 103 gate electrode 104a conductive layer 104b Conductive layer 105 Conductive layer 111 Barrier Film 111a Barrier film 111b Barrier film 111c Barrier Film 111d Barrier film 111e Barrier Film 111f Barrier Film 111g Barrier film 112 insulating film 113 Insulating film 114 insulating film 115a insulating film 115b insulating film 115c insulating film 115d insulating film 115e insulating film 116 Insulating film 121 Plug 122 Plug 123 Plug 124 Wiring 125 Conductive Layer 126 Plug 127 Plug 128 plug 129a plug 129b plug 129c plug 129d plug 130 transistors 131 Semiconductor substrate 132 Semiconductor layer 133a Low resistance layer 133b Low resistance layer 134 Gate insulating film 135 gate electrode 136 Insulating Film 137 Insulating Film 138 insulating film 139 Plug 140 plug 141 Plug 142 Wiring 143 Conductive Layer 144 Conductive Layer 145 plug 146 Conductive Layer 147 Plug 150 Capacitive element 151 Conductive layer 152 Conductive layer 152b Conductive layer 153a conductive layer 153b Conductive layer 154a conductive layer 154b Conductive layer 154c conductive layer 154d conductive layer 154e conductive layer 160 transistors 164 plug 165 plug 166 Wiring 176a area 176b area 171a Low resistance region 171b Low resistance region 181 Conductive film 190 transistors 191 transistors 211a Barrier film 211b Barrier film 211c Barrier film 211d Barrier film 211e Barrier film 211f Barrier film 215a Insulating film 215b insulating film 215c insulating film 215d insulating film 215e insulating film 215f insulating film 251 Conductive Layer 251a Conductive layer 251b Conductive layer 251c conductive layer 251d conductive layer 251e conductive layer 261 Insulating Film 281 layers 282 layers 283 layers 284 layers 285 layers 286 layers 287 layers 288 layers 289 layers 290 layers 291 layers 292 layers 293 layers 294 layers 295 layers 321 Plug 322 Plug 610 Electron Gun Room 612 Optical system 614 Sample Room 616 Optical system 618 Camera 620 Observation Room 622 Film Room 632 Fluorescent screen 660a Capacitor 660b Capacitive element 661a Transistor 661b Transistor 662a Transistor 662b transistor 663a inverter 663b inverter 700 boards 701 Pixel section 702 Scanning line driving circuit 703 Scanning line driving circuit 704 Signal Line Driver Circuit 710 Capacitance wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode layer 716 Transistor 717 Transistor 718 Liquid Crystal Devices 719 Liquid Crystal Devices 720 pixels 721 Switching Transistor 722 Drive transistor 723 Capacitor 724 Light-emitting element 725 signal line 726 scan lines 727 Power line 728 Common electrode 800 RF tags 801 Communication Device 802 antenna 803 wireless signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 chassis 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 lens 946 Connection 951 body 952 wheels 953 Dashboard 954 Light 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 2100 transistors 2200 transistors 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitor 4000 RF tags 5100 pellets 5100a pellets 5100b pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellets 5105a1 area 5105a2 pellets 5105b Pellets 5105c Pellets 5105d Pellets 5105d1 area 5105e Pellets 5120 board 5130 Target 5161 area

Claims

1. a first transistor; a second transistor; and a capacitive element; a first insulating film; a second insulating film; a third insulating film; a first conductive layer; and a second conductive layer; the first insulating film has a region located above a gate electrode of the first transistor, the second insulating film has a region located above the first insulating film, the third insulating film has a region located above the second insulating film, the first conductive layer has a region located above the third insulating film, the first terminal and the second terminal of the capacitance element have regions located above the third insulating film; the first terminal and the second terminal of the capacitive element have regions located below a channel formation region of the second transistor; a source electrode or a drain electrode of the second transistor is always electrically connected to a first terminal or a second terminal of the capacitance element; The second conductive layer penetrates a semiconductor in which the second transistor is formed, and is always electrically connected to the first conductive layer.

2. a first transistor; a second transistor; and a capacitive element; a first insulating film; a second insulating film; a third insulating film; a first conductive layer; and a second conductive layer; and a third conductive layer; the first insulating film has a region located above a gate electrode of the first transistor, the second insulating film has a region located above the first insulating film, the third insulating film has a region located above the second insulating film, the first conductive layer has a region located above the third insulating film, the first terminal and the second terminal of the capacitance element have regions located above the third insulating film; the first terminal and the second terminal of the capacitive element have regions located below a channel formation region of the second transistor; a source electrode or a drain electrode of the second transistor is always electrically connected to a first terminal or a second terminal of the capacitance element; the third conductive layer has a region located above a channel formation region of the second transistor, the second conductive layer penetrates a semiconductor in which the second transistor is formed and is always electrically connected to the first conductive layer; The third conductive layer is always electrically connected to the second conductive layer.

3. In claim 1 or claim 2, a channel formation region of the first transistor having single crystal silicon;

4. In any one of claims 1 to 3, the first insulating film contains oxygen and silicon; the second insulating film contains nitrogen and silicon, The third insulating film comprises oxygen and silicon.

5. In any one of claims 1 to 4, The semiconductor device, wherein the third insulating film is a planarizing film.

Images