Electronic Devices

Abstract

To provide an electronic device capable of suppressing a leakage current between a substrate and wiring.SOLUTION: An electronic device includes: a substrate; a first silicon nitride film provided onto the substrate; a silicon oxide film provided onto the first silicon nitride film; a capacitor provided onto the silicon oxide film; and wiring electrically connected to the capacitor. The wiring is separated from the first silicon nitride film, and the outer edge of the silicon oxide film is existed in an inner side of the outer edge of the first silicon nitride film in a plan view.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to electronic devices. [Background technology]

[0002] A method for manufacturing a capacitor having an MIM (Metal-Insulator-Metal) structure (MIM capacitor) has been proposed (Patent Documents 1 and 2). Also known is an integrated passive device (IPD) that includes a capacitor. In an IPD, an insulating film is formed on a substrate, and wiring connected to the capacitor is formed on the insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-207945 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-56887 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional IPDs, leakage current can flow between the substrate and the wiring.

[0005] An object of the present disclosure is to provide an electronic device that can suppress leakage current between a substrate and wiring. [Means for solving the problem]

[0006] The electronic device of the present disclosure includes a substrate, a first silicon nitride film provided on the substrate, a silicon oxide film provided on the first silicon nitride film, and a second silicon oxide film provided on the silicon oxide film. a first electrode provided on the silicon oxide film, a dielectric film provided on the first electrode, and a second electrode provided on the dielectric film. a capacitor; The first electrode electrically connected to No. 1 Wiring and a second wiring electrically connected to the second electrode of the capacitor;and No. 1 wiring and the second wiring is separated from the first silicon nitride film, and the outer edge of the silicon oxide film is located inside the outer edge of the first silicon nitride film in a plan view. the dielectric film includes a first dielectric film provided on the first electrode and a second dielectric film connected to the first dielectric film and provided between the silicon oxide film and the first wiring and the second wiring; a first opening is formed in the first silicon nitride film; a second opening connected to the first opening is formed in the silicon oxide film; a third opening connected to the second opening is formed in the second dielectric film; the first wiring has a first portion located inside the first opening, inside the second opening, and inside the third opening; and an inner wall surface of the second opening is provided at a position away from the first portion and away from the inner wall surfaces of the first opening and the third opening. . [Effects of the Invention]

[0007] According to the present disclosure, leakage current between the substrate and the wiring can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing an electronic device according to the first embodiment. [Figure 2] FIG. 2 is a top view showing the electronic device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view showing the electronic device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 1) illustrating the method for manufacturing the electronic device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 2) illustrating the method for manufacturing the electronic device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 3) illustrating the method for manufacturing the electronic device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 4) illustrating the method for manufacturing the electronic device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 5) illustrating the method for manufacturing the electronic device according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 6) illustrating the method for manufacturing the electronic device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 7) illustrating the method for manufacturing an electronic device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 8) illustrating the method for manufacturing an electronic device according to the first embodiment. [Figure 12]FIG. 12 is a ninth cross-sectional view illustrating the method for manufacturing an electronic device according to the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 10) illustrating the method for manufacturing the electronic device according to the first embodiment. [Figure 14] FIG. 14 is a top view showing the electronic device according to the second embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing an electronic device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] An electronic device according to one embodiment of the present disclosure includes a substrate, a first silicon nitride film provided on the substrate, a silicon oxide film provided on the first silicon nitride film, a capacitor provided on the silicon oxide film, and wiring electrically connected to the capacitor, the wiring being spaced apart from the first silicon nitride film, and the outer edge of the silicon oxide film being inside the outer edge of the first silicon nitride film in a planar view.

[0011] The wiring is separated from the first silicon nitride film. For example, a silicon oxide film may be present between the wiring and the first silicon nitride film in the thickness direction. This allows for suppression of leakage current between the wiring and the substrate. Furthermore, in a plan view, the outer edge of the silicon oxide film is inside the outer edge of the first silicon nitride film, so the outer edge of the silicon oxide film does not directly contact the substrate. If the outer edge of the silicon oxide film were to directly contact the substrate, peeling could occur starting from the interface between them, but this method suppresses peeling.

[0012] [2] In [1], the capacitor may have a first electrode provided on the silicon oxide film, a dielectric film provided on the first electrode, and a second electrode provided on the dielectric film, and the dielectric film may also be provided between the silicon oxide film and the wiring. In this case, irregularities following the shape of the dielectric film can be reduced. This makes it easier to alleviate restrictions on the placement of other elements on the substrate. Furthermore, compared to when the dielectric film is provided only around the capacitor, leakage current between the wiring and the substrate can be further suppressed. Furthermore, when multiple capacitors are provided, leakage current between the multiple capacitors can be easily suppressed.

[0013] [3] In [2], a second silicon nitride film may be provided to cover the capacitor, and the second silicon nitride film may be in direct contact with the first silicon nitride film outside the outer edge of the silicon oxide film. In this case, peeling is particularly easily suppressed.

[0014] [4] In [2] or [3], the distance between the outer edge of the dielectric film and the outer edge of the first silicon nitride film in a plan view may be 0.5 μm or more and 5 μm or less. If wiring is provided above the dielectric film, if this distance is too large, the first silicon nitride film may become unnecessarily large. If this distance is too small, it may be difficult to bring the second silicon nitride film into direct contact with the first silicon nitride film.

[0015] [5] In any of [1] to [4], the distance between the outer edge of the silicon oxide film and the outer edge of the first silicon nitride film in a plan view may be 0.5 μm or more and 10 μm or less. If wiring is provided above the silicon oxide film, if this distance is too large, the first silicon nitride film may become unnecessarily large. If this distance is too small, it may be difficult to bring the second silicon nitride film into direct contact with the first silicon nitride film.

[0016] [6] In any one of [1] to [5], a passivation film may be provided that covers the first silicon nitride film, the silicon oxide film, the capacitor, and the wiring. In this case, the passivation film can protect the first silicon nitride film, the silicon oxide film, the capacitor, and the wiring.

[0017] [7] In any one of [6], the passivation film may be a polyimide film. In this case, the passivation film is easy to form.

[0018] [8] In any one of [1] to [7], an inductor and a resistor may be connected to the capacitor. In this case, an IPD can be configured.

[0019] [9] An electronic device according to another embodiment of the present disclosure includes a substrate, a first silicon nitride film provided on the substrate, a silicon oxide film provided on the first silicon nitride film, a capacitor provided on the silicon oxide film, a second silicon nitride film covering the capacitor, and wiring electrically connected to the capacitor, wherein the capacitor has a first electrode provided on the silicon oxide film, a dielectric film provided on the first electrode, and a second electrode provided on the dielectric film, the wiring is spaced apart from the first silicon nitride film, and the dielectric film is also provided between the silicon oxide film and the wiring, an outer edge of the silicon oxide film is located inside an outer edge of the first silicon nitride film in a planar view, a distance between the outer edges of the silicon oxide film and the first silicon nitride film is 0.5 μm or more and 10 μm or less in a planar view, and the second silicon nitride film is in direct contact with the first silicon nitride film outside the outer edge of the silicon oxide film. In this case, too, it is possible to suppress leakage current between the wiring and the substrate, and it is also possible to suppress peeling of the silicon oxide film and the like.

[0020] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be assigned the same reference numerals to avoid redundant description. In this disclosure, a planar view refers to viewing an object along a direction perpendicular to the main surface of a substrate.

[0021] (First embodiment) First, a first embodiment will be described. The first embodiment relates to an electronic device including a capacitor. FIG. 1 is a circuit diagram showing the electronic device according to the first embodiment. FIG. 2 is a top view showing the electronic device according to the first embodiment. FIG. 3 is a cross-sectional view showing the electronic device according to the first embodiment. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 2.

[0022] 1 and 2, the electronic device 100 according to the first embodiment mainly includes a capacitor 110, an inductor 120, a resistive element 130, a pad 141, a pad 142, and a node 143. The inductor 120 is connected between the pad 141 and the node 143. The resistive element 130 is connected between the pad 142 and the node 143. Therefore, the inductor 120 and the resistive element 130 are electrically connected in series between the pad 141 and the pad 142. The capacitor 110 is connected between the node 143 and ground.

[0023] The electronic device 100 has wiring 41, wiring 42, wiring 43, wiring 44, and wiring 45. Wire 41 connects pad 142 and resistive element 130. Wire 42 connects resistive element 130 and inductor 120. Wire 43 connects wire 42 and capacitor 110. Wire 44 connects capacitor 110 and conductive via 49 (see FIG. 3). Conductive via 49 is grounded. Wire 45 connects inductor 120 and pad 141.

[0024] The electronic device 100 includes a substrate 11, a silicon nitride (SiN) film 12, and a silicon oxide (SiO x) film 13, a lower electrode 21, a dielectric film 22, an upper electrode 23, a silicon nitride film 31, a silicon nitride film 32, and a passivation film 33.

[0025] The substrate 11 is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, or a sapphire (Al2O3) substrate. The planar shape of the substrate 11 is rectangular. As shown in FIG. 3, the substrate 11 has a first main surface 11A and a second main surface 11B parallel to the XY plane. The first main surface 11A is located above (on the Z1 side of) the second main surface 11B. The substrate 11 further has two side surfaces parallel to the YZ plane and two side surfaces parallel to the ZX plane.

[0026] In plan view, the silicon nitride film 12 overlaps almost the entire first main surface 11A. In plan view, the outer edge 12E of the silicon nitride film 12 is inside the outer edge 11E of the substrate 11. The thickness of the silicon nitride film 12 is, for example, 50 nm or more and 200 nm or less. In FIG. 2, the outer edge 12E of the silicon nitride film 12 is indicated by a two-dot chain line, but the silicon nitride film 12 is omitted. The silicon nitride film 12 is an example of a first silicon nitride film.

[0027] The silicon oxide film 13 overlaps almost the entire first main surface 11A in plan view. In plan view, the outer edge 13E of the silicon oxide film 13 is inside the outer edge 12E of the silicon nitride film 12. In plan view, the distance between the outer edge 13E of the silicon oxide film 13 and the outer edge 12E of the silicon nitride film 12 is, for example, 0.5 μm or more and 10 μm or less. The thickness of the silicon oxide film 13 is, for example, 100 nm or more and 300 nm or less. In FIG. 2, the outer edge 13E of the silicon oxide film 13 is indicated by a two-dot chain line, but the silicon oxide film 13 is omitted.

[0028] The lower electrode 21 is provided on the silicon oxide film 13. The lower electrode 21 includes, for example, a gold-based metal layer. The lower electrode 21 may have a single-layer structure or a multi-layer structure. The thickness of the lower electrode 21 is, for example, 200 nm or more and 300 nm or less. The planar shape of the lower electrode 21 is, for example, a rectangle with the X1-X2 direction as the longitudinal direction and the Y1-Y2 direction as the lateral direction, as shown in FIG. 2 .

[0029] The dielectric film 22 is provided on the lower electrode 21 and the silicon oxide film 13. In a plan view, the dielectric film 22 overlaps almost the entire first main surface 11A. In a plan view, an outer edge 22E of the dielectric film 22 is located between the outer edge 12E of the silicon nitride film 12 and the outer edge 13E of the silicon oxide film 13. In a plan view, the distance between the outer edge 22E of the dielectric film 22 and the outer edge 12E of the silicon nitride film 12 is, for example, 0.5 μm or more and 5 μm or less. The dielectric film 22 covers the upper surface of the silicon oxide film 13. The dielectric film 22 is, for example, a silicon nitride film. The thickness of the dielectric film 22 is, for example, 100 nm or more and 300 nm or less. In FIG. 2, the outer edge 22E of the dielectric film 22 is indicated by a two-dot chain line, but the dielectric film 22 is omitted.

[0030] The upper electrode 23 is provided on the dielectric film 22. The upper electrode 23 includes, for example, a gold-based metal layer. The upper electrode 23 may have a single-layer structure or a multi-layer structure. The thickness of the upper electrode 23 is, for example, 200 nm to 300 nm. The planar shape of the upper electrode 23 is, for example, a rectangle with the X1-X2 direction as the longitudinal direction and the Y1-Y2 direction as the lateral direction, as shown in FIG. 2. In plan view, the outer edge of the upper electrode 23 is inside the outer edge of the lower electrode 21.

[0031] The lower electrode 21, the dielectric film 22, and the upper electrode 23 are included in the capacitor 110. The capacitor 110 is a so-called MIM capacitor. The lower electrode 21 is an example of a first electrode, and the upper electrode 23 is an example of a second electrode.

[0032] A through-hole 51 penetrating the substrate 11 is formed in the substrate 11. The through-hole 51 is located, for example, on the X1 side of the lower electrode 21. An opening 52 penetrating the silicon nitride film 12 is formed in the silicon nitride film 12. The opening 52 is continuous with the through-hole 51. An opening 53 penetrating the silicon oxide film 13 is formed in the silicon oxide film 13. The opening 53 is continuous with the opening 52. Openings 54 and 55 penetrating the dielectric film 22 are formed in the dielectric film 22. The opening 54 is continuous with the opening 53. The lower electrode 21 is exposed from the opening 55.

[0033] A conductive via 49 is provided in the through hole 51. The conductive via 49 has a surface (the surface on the Z1 side) that is flush with the first main surface 11A and a surface (the surface on the Z2 side) that is flush with the second main surface 11B. The material of the conductive via 49 includes, for example, a copper or gold-based metal.

[0034] The silicon nitride film 31 covers the silicon nitride film 12, the silicon oxide film 13, the bottom electrode 21, the dielectric film 22, and the top electrode 23. The silicon nitride film 31 also covers the inner wall surfaces of the openings 52, 53, 54, and 55. The silicon nitride film 31 is in direct contact with the silicon nitride film 12 outside the outer edge 13E of the silicon oxide film 13. The silicon nitride film 31 is omitted in FIG. 2. The silicon nitride film 31 is an example of a second silicon nitride film.

[0035] Openings 61, 62, and 63 penetrating the silicon nitride film 31 are formed in the silicon nitride film 31. The opening 61 is located inside the openings 52, 53, and 54, and exposes the Z1 side surface of the conductive via 49 from the opening 61. The opening 62 is located inside the opening 55, and exposes the lower electrode 21 from the opening 62. The upper electrode 23 is exposed from the opening 63.

[0036] Wiring 43 is in direct contact with upper electrode 23 through opening 63. Wiring 43 is connected to wiring 42 on silicon nitride film 31. The intersection of wiring 42 and wiring 43 corresponds to node 143. Wiring 44 is in direct contact with lower electrode 21 through openings 62 and 55, and is in direct contact with conductive via 49 through openings 61, 54, 53, and 52.

[0037] Resistance element 130 is provided between silicon oxide film 13 and dielectric film 22. Openings 71 and 72 are formed in silicon nitride film 31 and dielectric film 22, respectively, so as to penetrate silicon nitride film 31 and dielectric film 22 and reach resistance element 130. Wiring 41 is connected to resistance element 130 through opening 71, and wiring 42 is connected to resistance element 130 through opening 72.

[0038] Inductor 120 is connected to wiring 42 and 45 on silicon nitride film 31. Pad 142 is connected to wiring 41 on silicon nitride film 31, and pad 141 is connected to wiring 45 on silicon nitride film 31. Inductor 120 includes, for example, a gold-based metal layer. Pads 141 and 142 include, for example, a gold-based metal layer.

[0039] The wirings 41, 42, 43, 44, and 45 are spaced apart from the silicon nitride film 12. In other words, the wirings 41, 42, 43, 44, and 45 are not in direct contact with the silicon nitride film 12. The inductor 120 is also spaced apart from the silicon nitride film 12. In other words, the inductor 120 is not in direct contact with the silicon nitride film 12.

[0040] The silicon nitride film 32 covers the upper, side and lower surfaces of the wirings 41, 42, 43, 44 and 45. The silicon nitride film 32 also covers the upper surface of the silicon nitride film 31. The silicon nitride film 32 is omitted in Figure 2. The silicon nitride film 32 is an example of a second silicon nitride film.

[0041] The passivation film 33 is, for example, a polyimide film. The passivation film 33 covers the substrate 11, the silicon nitride film 12, the silicon oxide film 13, the lower electrode 21, the dielectric film 22, the upper electrode 23, the silicon nitride films 31 and 32, and the wirings 41, 42, 43, 44, and 45. The passivation film 33 overlaps almost the entire first main surface 11A in plan view. In plan view, the outer edge 33E of the passivation film 33 is inside the outer edge 11E of the substrate 11. In plan view, the outer edge 12E of the silicon nitride film 12 is inside the outer edge 33E of the passivation film 33. In plan view, the distance between the outer edge 12E of the silicon nitride film 12 and the outer edge 33E of the passivation film 33 is, for example, 1.5 μm or more and 15 μm or less. In plan view, the outer edge 13E of the silicon oxide film 13 is located inside the outer edge 33E of the passivation film 33. In plan view, the distance between the outer edge 13E of the silicon oxide film 13 and the outer edge 33E of the passivation film 33 is, for example, 2 μm or more and 25 μm or less. In plan view, the outer edge 22E of the dielectric film 22 is located inside the outer edge 33E of the passivation film 33. In plan view, the distance between the outer edge 22E of the dielectric film 22 and the outer edge 33E of the passivation film 33 is, for example, 2 μm or more and 23 μm or less. The thickness of the passivation film 33 is, for example, 3 μm or more and 10 μm or less. In FIG. 2, the outer edge 33E of the passivation film 33 is indicated by a two-dot chain line, but the passivation film 33 is omitted.

[0042] Openings 73 and 74 are formed in the passivation film 33 and the silicon nitride film 32. The opening 73 passes through the passivation film 33 and the silicon nitride film 32 and reaches the pad 142. The opening 74 passes through the passivation film 33 and the silicon nitride film 32 and reaches the pad 141.

[0043] 1, the gate of a field effect transistor 151 is connected to a pad 142, and a microstrip line 152 is connected to the pad 141. The source of the field effect transistor 151 is grounded, and a microstrip line 153 is connected to the drain.

[0044] Next, a method for manufacturing the electronic device 100 according to the first embodiment will be described, focusing on the periphery of the capacitor 110. Figures 4 to 13 are cross-sectional views showing the method for manufacturing the electronic device 100 according to the first embodiment.

[0045] 4, a silicon nitride film 12 is formed on the first main surface 11A of the substrate 11, and an opening 52 is formed in the silicon nitride film 12. When forming the opening 52, the silicon nitride film 12 is removed from a portion of the substrate 11 that will become a scribe region. The silicon nitride film 12 is formed by, for example, chemical vapor deposition (CVD).

[0046] 5, a silicon oxide film 13 is formed on the silicon nitride film 12 and the substrate 11. The silicon oxide film 13 is formed by, for example, a CVD method.

[0047] 6, the lower electrode 21 is formed on the silicon oxide film 13. The lower electrode 21 is formed by, for example, sputtering or vapor deposition.

[0048] 7, a dielectric film 22 is formed on the lower electrode 21 and the silicon oxide film 13. The dielectric film 22 is formed by, for example, a CVD method.

[0049] Next, as shown in FIG. 8 , an opening 54 is formed in the dielectric film 22. The opening 54 is formed by dry etching using, for example, a fluorine-based gas. Subsequently, an opening 53 is formed in the silicon oxide film 13. The opening 53 is formed using, for example, a hydrofluoric acid-based solution such as diluted hydrofluoric acid. When forming the opening 53, the etching mask used when forming the opening 54 may be used as is. When forming the opening 54, the outer edge 22E of the dielectric film 22 is positioned inside the outer edge 12E of the silicon nitride film 12 in a planar view. Furthermore, when forming the opening 53, the outer edge 13E of the silicon oxide film 13 is positioned inside the outer edge 22E of the dielectric film 22 in a planar view. At this time, the distance between the outer edge 13E of the silicon oxide film 13 and the outer edge 12E of the silicon nitride film 12 is, for example, 0.5 μm or more and 10 μm or less. Subsequently, an opening 55 is formed in the dielectric film 22. The opening 55 is formed by dry etching using, for example, a fluorine-based gas.

[0050] 9, an upper electrode 23 is formed on the dielectric film 22. The upper electrode 23 is formed by, for example, a vapor deposition method combined with lift-off. A capacitor 110 including the lower electrode 21, the dielectric film 22, and the upper electrode 23 is formed.

[0051] 10, a silicon nitride film 31 is formed on the upper electrode 23 and the dielectric film 22, and openings 61, 62, and 63 are formed in the silicon nitride film 31. When forming the openings 61, 62, and 63, the silicon nitride film 31 is removed from the portions that will become the scribe regions of the substrate 11. The silicon nitride film 31 is formed by, for example, a CVD method.

[0052] Next, as shown in Fig. 11, wirings 41, 42, 43, 44, and 45 are formed (see also Fig. 2). Next, a silicon nitride film 32 is formed.

[0053] Next, a passivation film 33 is formed as shown in Fig. 12. When the passivation film 33 is a polyimide film, the passivation film 33 can be formed by, for example, forming a coating film, exposing it to light, and developing it.

[0054] 13, a through hole 51 is formed in the substrate 11, extending from the second main surface 11B to the first main surface 11A. Next, a conductive via 49 is formed in the through hole 51.

[0055] In this manner, the electronic device 100 according to the first embodiment can be manufactured.

[0056] In the electronic device 100, the wirings 41, 42, 43, 44, and 45 are spaced apart from the silicon nitride film 12. For example, in the thickness direction, the silicon oxide film 13 is present between the wirings 41, 42, 43, 44, and 45 and the silicon nitride film 12. Therefore, leakage current between the wirings 41, 42, 43, 44, and 45 and the substrate 11 can be suppressed.

[0057] In terms of the manufacturing method, if silicon oxide film 13 is provided only below capacitor 110, pinholes may occur in silicon nitride film 12 during etching of silicon oxide film 13. In this embodiment, silicon oxide film 13 is formed widely, which narrows the area in silicon nitride film 12 where pinholes occur, and wiring 41, 42, 43, 44, and 45 can be formed avoiding the area where pinholes occur. This makes it possible to suppress leakage current between wiring 41, 42, 43, 44, and 45 and substrate 11.

[0058] In plan view, outer edge 13E of silicon oxide film 13 is located inside outer edge 12E of silicon nitride film 12, and therefore outer edge 13E of silicon oxide film 13 does not directly contact substrate 11. If outer edge 13E of silicon oxide film 13 were in direct contact with substrate 11, there is a risk of peeling starting from the interface between them, but according to this embodiment, peeling can be suppressed. In particular, when silicon nitride films 31 and 32 are in direct contact with silicon nitride film 12 outside outer edge 13E of silicon oxide film 13, peeling is easily suppressed.

[0059] The passivation film 33 can protect the inside of the electronic device 100. When the passivation film 33 is a polyimide film, it is easy to form the passivation film 33. The larger the thermal expansion coefficient between the passivation film 33 and the substrate 11, the more likely the electronic device 100 to warp. Warping of the electronic device 100 generates stress that induces peeling of the silicon oxide film 13 and the like, but according to this embodiment, peeling can be suppressed even when such stress is generated.

[0060] Not only the silicon oxide film 13 but also the dielectric film 22 is formed over a wide area, and the dielectric film 22 is also provided between the silicon oxide film 13 and the wirings 41, 42, 43, 44, and 45 in the thickness direction. Therefore, compared to when the dielectric film 22 is provided only around the capacitor 110, unevenness following the shape of the dielectric film 22 can be reduced. Therefore, even when determining the layout of the inductor 120 and the resistor 130 while taking unevenness into consideration, the inductor 120 and the resistor 130 can be easily arranged in a narrow area. This facilitates miniaturization of the electronic device 100. Furthermore, compared to when the dielectric film 22 is provided only around the capacitor 110, leakage current between the wirings 41, 42, 43, 44, and 45 and the substrate 11 can be further suppressed. Furthermore, when multiple capacitors 110 are provided, leakage current between the multiple capacitors 110 can be easily suppressed.

[0061] With the capacitor 110, inductor 120 and resistive element 130 properly connected, the electronic device 100 can be used as an IPD.

[0062] In plan view, the distance between outer edge 13E of silicon oxide film 13 and outer edge 12E of silicon nitride film 12 is preferably 0.5 μm or more and 10 μm or less, more preferably 2 μm or more and 8 μm or less. When wiring 41, 42, 43, 44, and 45 are formed above silicon oxide film 13, if this distance is too large, silicon nitride film 12 may become unnecessarily large. If this distance is too small, it may be difficult to bring silicon nitride film 31 into direct contact with silicon nitride film 12.

[0063] Furthermore, in plan view, the distance between the outer edge 22E of the dielectric film 22 and the outer edge 12E of the silicon nitride film 12 is preferably 0.5 μm or more and 5 μm or less, more preferably 1.5 μm or more and 4 μm or less. When the wirings 41, 42, 43, 44, and 45 are formed above the dielectric film 22, if this distance is too large, the silicon nitride film 12 may become unnecessarily large. If this distance is too small, it may be difficult to bring the silicon nitride film 31 into direct contact with the silicon nitride film 12.

[0064] (Second embodiment) Next, a second embodiment will be described. The second embodiment relates to an electronic device including a capacitor. FIG. 14 is a top view showing the electronic device according to the second embodiment. FIG. 15 is a cross-sectional view showing the electronic device according to the second embodiment. FIG. 15 corresponds to a cross-sectional view taken along line XV-XV in FIG. 14. As with FIG. 2, some components are omitted in FIG. 14.

[0065] 14 and 15, the electronic device 200 according to the second embodiment differs from the first embodiment mainly in the shape of the dielectric film 22. That is, in the first embodiment, the dielectric film 22 is provided widely, but in the second embodiment, the dielectric film 22 is provided only around the capacitor 110. In addition, due to the difference in the shape of the dielectric film 22, the shapes of the wiring 43, the wiring 44, the silicon nitride film 31, the silicon nitride film 32, and the passivation film 33 also differ slightly from those of the first embodiment.

[0066] Other configurations of the second embodiment are the same as those of the first embodiment.

[0067] The second embodiment also provides at least the same effects as the first embodiment in suppressing leakage current and peeling.

[0068] It should be noted that the electronic device to which the present disclosure is applied is not limited to an IPD, and for example, the present disclosure may be applied to a monolithic microwave integrated circuit (MMIC).

[0069] The first silicon nitride film may have a multi-layer structure, i.e., the first silicon nitride film may be made up of a plurality of silicon nitride films, in which case the resistor element 130 may be disposed between the plurality of silicon nitride films.

[0070] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0071] 11: Circuit board 11A: 1st main surface 11B: 2nd main surface 11E, 12E, 13E, 22E, 33E: outer edge 12: Silicon nitride film 13: Silicon oxide film 21: Lower electrode 22: Dielectric film 23: Upper electrode 31, 32: Silicon nitride film 33: Passivation film 41, 42, 43, 44, 45: Wiring 49: Conductive via 51:Through hole 52, 53, 54, 55, 61, 62, 63, 71, 72, 73, 74: Openings 100, 200: Electronic devices 110: Capacitor 120: Inductor 130: Resistive element 141, 142: Pad 143: Node 151: Field effect transistor 152, 153: Microstrip line

Claims

1. A substrate; a first silicon nitride film disposed on the substrate; a silicon oxide film provided on the first silicon nitride film; a capacitor provided on the silicon oxide film, the capacitor having a first electrode provided on the silicon oxide film, a dielectric film provided on the first electrode, and a second electrode provided on the dielectric film; a first wiring electrically connected to the first electrode of the capacitor; a second wiring electrically connected to the second electrode of the capacitor; and the first wiring and the second wiring are spaced apart from the first silicon nitride film; an outer edge of the silicon oxide film is located inside an outer edge of the first silicon nitride film in a plan view; the dielectric film includes a first dielectric film provided on the first electrode, and a second dielectric film connected to the first dielectric film and provided between the silicon oxide film and the first wiring and the second wiring; a first opening is formed in the first silicon nitride film; a second opening communicating with the first opening is formed in the silicon oxide film; a third opening communicating with the second opening is formed in the second dielectric film; the first wiring has a first portion located inside the first opening, inside the second opening, and inside the third opening; an inner wall surface of the second opening is provided at a position farther from the first portion than the inner wall surfaces of the first opening and the third opening.

2. a second silicon nitride film covering the capacitor; 2. The electronic device according to claim 1, wherein the second silicon nitride film is in direct contact with the first silicon nitride film outside the outer edge of the silicon oxide film.

3. An electronic device as described in claim 2, wherein the film thickness of the second silicon nitride film between the silicon oxide film and the first portion inside the second opening in a direction parallel to the top surface of the substrate is greater than the film thickness of the second silicon nitride film between the second dielectric film and the first portion inside the third opening.

4. 4. The electronic device according to claim 2, wherein the distance between the outer edge of the dielectric film and the outer edge of the first silicon nitride film is 0.5 μm or more and 5 μm or less in plan view.

5. 3. The electronic device according to claim 1, wherein the distance between the outer edge of the silicon oxide film and the outer edge of the first silicon nitride film is 0.5 μm or more and 10 μm or less in plan view.

6. 3. The electronic device according to claim 1, further comprising a passivation film covering the first silicon nitride film, the silicon oxide film, the capacitor, the first wiring, and the second wiring.

7. 7. The electronic device according to claim 6, wherein the passivation film is a polyimide film.

8. 3. The electronic device according to claim 1, further comprising an inductor and a resistor connected to the capacitor.

9. A substrate; a first silicon nitride film disposed on the substrate; a silicon oxide film provided on the first silicon nitride film; a capacitor provided on the silicon oxide film; a second silicon nitride film covering the capacitor; a first wiring and a second wiring; and The capacitor is a first electrode provided on the silicon oxide film; a dielectric film provided on the first electrode; a second electrode provided on the dielectric film; and the first wiring is electrically connected to the first electrode, the second wiring is electrically connected to the second electrode, the first wiring and the second wiring are spaced apart from the first silicon nitride film; the dielectric film includes a first dielectric film provided on the first electrode, and a second dielectric film connected to the first dielectric film and provided between the silicon oxide film and the first wiring and the second wiring; an outer edge of the silicon oxide film is located inside an outer edge of the first silicon nitride film and an outer edge of the second dielectric film in a plan view; a distance between an outer edge of the silicon oxide film and an outer edge of the first silicon nitride film in a plan view is 0.5 μm or more and 10 μm or less; a distance between an outer edge of the first silicon nitride film and an outer edge of the second dielectric film is 0.5 μm or more and 5 μm or less in a plan view; An electronic device in which the second silicon nitride film is in direct contact with the first silicon nitride film outside the outer edge of the silicon oxide film.

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