Tension generating device and semiconductor manufacturing device

Abstract

To obtain a tension generation device capable of suppressing damages or a recess of a wafer front surface, and a semiconductor manufacturing device.SOLUTION: A tension generation device comprises: a plurality of electrode pairs each having a first electrode and a second electrode; and a voltage application part that is constructed so as to apply a voltage between the first electrode and the second electrode of each of the plurality of electrode pairs in a state where each of the plurality of electrode pairs is arranged so as to sandwich an end part of a wafer between the first electrode and the second electrode in a direction that is vertical to a main surface of the wafer, and the first electrode and the second electrode are projected to an outer side from the wafer in view of a direction that is vertical to the main surface of the wafer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a tension generating device and a semiconductor manufacturing device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor exposure apparatus. In this apparatus, when a deformed wafer is attached to an electrostatic chuck, a force is applied in the radial direction of the wafer in advance, forcibly deforming the wafer to a mechanically nearly flat state. The wafer is then placed on the electrostatic chuck in this state and electrostatically adsorbed, thereby correcting the wafer to a predetermined flatness. One example of a forced deformation means is one that is installed on a wafer transfer hand, mechanically clamps the wafer at multiple points on the outer periphery, and applies a force in the radial direction of the wafer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-224054 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the wafer is held and force is applied by a mechanical clamp, which causes mechanical force to act in the normal direction of the wafer, which may cause scratches or dents on the wafer surface and lead to cracks in the wafer.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a tension generating device and a semiconductor manufacturing apparatus that can suppress scratches or dents on the wafer surface. [Means for solving the problem]

[0006] A tension generating device according to the present disclosure includes a plurality of electrode pairs, each having a first electrode and a second electrode, and a voltage application unit configured to apply a voltage between the first electrode and the second electrode of each of the plurality of electrode pairs, in a state in which each of the plurality of electrode pairs is arranged such that an edge of the wafer is sandwiched between the first electrode and the second electrode in a direction perpendicular to the main surface of the wafer, and the first electrode and the second electrode protrude outward beyond the wafer when viewed in the direction perpendicular to the main surface of the wafer. [Effects of the Invention]

[0007] The tension generator and semiconductor manufacturing apparatus according to the present disclosure can generate tension only in the radial direction of the wafer by applying voltage, thereby suppressing scratches or dents on the wafer surface. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a tension generating device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the tension generating mechanism according to the first embodiment. [Figure 3] 5A to 5C are diagrams illustrating a mechanism of tension generation according to the first embodiment. [Figure 4] 5A to 5C are diagrams illustrating a mechanism of tension generation according to the first embodiment. [Figure 5] FIG. 1 is a diagram illustrating a configuration of a semiconductor manufacturing apparatus according to a first embodiment. [Figure 6] FIG. 2 is a diagram illustrating a configuration in which the semiconductor manufacturing apparatus according to the first embodiment is a sputtering apparatus. [Figure 7] 2A to 2C are diagrams illustrating an example of a moving mechanism according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The tension generator and semiconductor manufacturing apparatus according to each embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0010] Embodiment 1 FIG. 1 is a plan view of a tension generator 100 according to a first embodiment. FIG. 1 shows a state in which a wafer 1 is placed on the tension generator 100. The tension generator 100 is, for example, part of a semiconductor manufacturing apparatus described below. The tension generator 100 is used, for example, to fix and hold a substrate such as a semiconductor wafer on an electrostatic chuck. In particular, the tension generator 100 is used to effectively correct warpage of the substrate.

[0011] The tension generating device 100 has multiple tension generating mechanisms 2. In the example of FIG. 1, two tension generating mechanisms 2a and 2b are arranged at positions 180 degrees apart on the wafer 1 as tension generating mechanisms 2 for pulling the wafer 1. To pull the wafer 1 uniformly in the radial direction, the tension generating mechanisms 2 may be arranged at three or more locations on the wafer 1. In this embodiment, two tension generating mechanisms 2a and 2b are provided for the convenience of transferring the wafer 1 onto the stage.

[0012] FIG. 2 is a cross-sectional view of a tension generating mechanism 2 according to the first embodiment. FIG. 2 shows the outer periphery of a wafer 1. Each of the multiple tension generating mechanisms 2 has an electrode pair 10. Each of the electrode pairs 10 has a first electrode 11 and a second electrode 12. An insulating layer 14 is provided on the surfaces of the first electrode 11 and the second electrode 12. In the example of FIG. 2, the first electrode 11 contacts the wafer 1 via the insulating layer 14, and the second electrode 12 is separated from the wafer 1. The portion of the wafer 1 supported by the tension generating mechanism 2 is preferably a portion of the wafer 1 that is not generally used as a chip, and is several millimeters from the outermost periphery.

[0013] The insulating layer 14 is made of, for example, a material softer than silicon. Coating the first electrode 11 and the second electrode 12 with such a material can prevent scratches and dents from occurring on the wafer 1. Specifically, the insulating layer 14 preferably has a Young's modulus lower than 130 GPa. The insulating layer 14 is formed of, for example, a PI (Polyimide)-based, fluorine-based, silicone-based, or acrylic-based material. The insulating layer 14 may be provided on the surface of at least one of the first electrode 11 and the second electrode 12 that faces the wafer 1. For example, the insulating layer 14 may be provided only on the second electrode 12 that contacts the wafer 1 in FIG. 2. Alternatively, the insulating layer 14 may not be provided.

[0014] The first electrode 11 and the second electrode 12 are held by base members 21 and 22, respectively. The base member 21 supports the edge of the wafer 1. The base member 22 is disposed above the edge of the wafer 1. The base member 22 has an eave-like shape.

[0015] The voltage application unit is configured to apply a voltage between the first electrode 11 and the second electrode 12 of each of the plurality of electrode pairs 10. The voltage application unit is, for example, a power supply 50 for applying a voltage between the first electrode 11 and the second electrode 12. The voltage application unit may be a circuit such as wiring that connects the power supply 50 to the first electrode 11 and the second electrode 12. The power supply 50 is a DC power supply, an AC power supply, a pulse power supply, or the like.

[0016] 2, each of the electrode pairs 10 is arranged such that the first electrode 11 and the second electrode 12 sandwich an edge of the wafer 1 in a direction perpendicular to the main surface of the wafer. Furthermore, when viewed from a direction perpendicular to the main surface of the wafer 1, the first electrode 11 and the second electrode 12 protrude outward beyond the wafer 1. With the electrode pairs 10 arranged in this manner, the voltage application unit is configured to apply a voltage between the first electrode 11 and the second electrode 12 of each of the multiple electrode pairs 10.

[0017] Moreover, the first electrode 11 and the second electrode 12 are preferably configured to apply a voltage in a direction perpendicular to the main surface of the wafer 1. In other words, it is preferable that a voltage is applied so that an electric field is generated in the normal direction of the wafer 1.

[0018] 3 and 4 are diagrams illustrating the mechanism of tension generation according to the first embodiment. As shown in FIG. 3, when a voltage is applied to the electrode pair 10, electrostatic energy accumulates between the first electrode 11 and the second electrode 12. Furthermore, positive and negative charges inside the wafer 1 are attracted to the negative and positive poles, respectively, causing polarization. At this time, the electrostatic forces in the vertical direction indicated by arrows 81 in FIG. 3 cancel each other out. Meanwhile, a tension F is exerted on the wafer 1 in the radial direction of the wafer by the electrostatic force indicated by arrows 82.

[0019] The tension F will be further explained using Figure 4. In Figures 2 and 4, L is the length of the first electrode 11 and the second electrode 12, x is the sandwiched length of the wafer 1, and d is the distance between the electrode pair 10. When the wafer 1 is partially inserted between the electrode pair 10, that is, when L > x, the electrostatic energy between the electrode pair 10 decreases due to polarization of the wafer 1. The deeper the wafer 1 is inserted between the electrode pair 10, the lower the electrostatic energy accumulated between the electrode pair 10. Therefore, a force is generated in the wafer 1 in a direction that reduces the electrostatic energy. This force acts to pull the wafer 1 between the electrode pair 10. In other words, a tension F is applied to the wafer 1. As a result, the wafer 1 is pulled in the outer circumferential direction, and warping of the wafer 1 can be corrected.

[0020] There is no relation between the direction of connection to the power source 50 and the direction in which the tension F is generated. In other words, either the first electrode 11 or the second electrode 12 may be the positive electrode.

[0021] The tension F generated in the wafer 1 can be expressed by the following equation (1): r is the relative dielectric constant of Si = 12, ε0 is the dielectric constant of vacuum = 8.8 × 10 -12 , a is the electrode width, and V is the voltage applied between the first electrode 11 and the second electrode 12.

[0022]

number

[0023] Furthermore, when L=x, the electrostatic energy does not decrease even if the wafer 1 penetrates deeper into the electrode pair 10. As a result, the force F that draws the wafer 1 between the electrode pair 10 is no longer generated. Therefore, it is necessary for L>x, that is, for the first electrode 11 and the second electrode 12 to protrude outward from the wafer 1 when viewed from a direction perpendicular to the main surface of the wafer 1.

[0024] To correct the bending of the wafer 1, it is sufficient to generate a tension in the radial direction with the same magnitude as the minimum buckling load. The minimum buckling load is expressed by the following formula (2).

[0025]

number

[0026] Here, if Si Young's modulus E = 200 GPa, d = wafer thickness = 100 μm, a = 30 mm, diameter l of wafer 1 = 300 mm, and V = 2 kV, then from equations (1) and (2), the tension F and the minimum buckling load F m Both are ~6×10 -2 [N]. For this reason, it can be seen that warping can be suppressed, for example, by setting d = 100 μm. As shown in formula (1), as the distance d increases, the applied voltage V required to generate the same tension F increases. Also, a power supply of about several kV is a general-purpose power supply generally used in electrostatic chucking stages. Considering parameters such as voltage V and distance d, warping can be suppressed if the distance d between the first electrode 11 and the second electrode 12 when voltage V is applied is, for example, between 40 μm and 200 μm.

[0027] FIG. 5 is a diagram illustrating the configuration of a semiconductor manufacturing apparatus 200 according to the first embodiment. The semiconductor manufacturing apparatus 200 includes a tension generator 100 and a chuck stage 5. The chuck stage 5 is, for example, an electrostatic chuck. The tension generator 100 of this embodiment applies tension F in the radial direction of a deformed wafer 1', thereby correcting the deformation as in the case of the wafer 1. As shown in FIG. 4, the wafer 1 is corrected above the chuck stage 5, for example, and then mounted on the chuck stage 5. This allows the wafer 1 to be uniformly attracted to the chuck stage 5.

[0028] 6 is a diagram illustrating the configuration of a sputtering apparatus when semiconductor manufacturing apparatus 200 according to the first embodiment is a sputtering apparatus. In semiconductor manufacturing apparatus 200, a sputtering target 4, a chuck stage 5, and a tension generating mechanism 2 are housed in a housing 3. A vacuum is created inside housing 3 by a vacuum pump 36. Wafer 1 is placed on base member 21 by a transfer hand (not shown). Thereafter, base member 22 approaches wafer 1.

[0029] In this state, a DC voltage is applied between the electrode pair 10 by the power supply 50. This generates tension in the wafer 1, correcting any warpage of the wafer 1. The wafer 1, while still under tension, is placed on the chuck stage 5 by the movement mechanism 30 and held by the chuck stage 5. In this state, by turning off the voltage of the power supply 50, the wafer 1 can be placed on the chuck stage 5 with warpage of the wafer 1 suppressed. Therefore, the wafer 1 can be placed evenly on the electrostatic chuck stage.

[0030] 6, the moving mechanism 30 has a portion 31 that moves the base member 21 up and down, and a portion 32 that moves the base member 22 up and down. In this embodiment, the warpage of the wafer 1 is corrected above the chuck stage 5. Therefore, it is sufficient for the moving mechanism 30 to be able to move the base members 21 and 22 up and down.

[0031] 7 is a diagram illustrating an example of the movement mechanism 30 according to embodiment 1. The portions 31 and 32 of the movement mechanism 30 can be realized by combining, for example, an elastic bellows 34 and an actuator 35 such as a stepping motor.

[0032] The tension generating mechanism 2 does not have to be provided above the chuck stage 5, and the position at which warpage of the wafer 1 relative to the chuck stage 5 is corrected is not limited. The moving mechanism 30 is not limited to one that moves up and down, and may be configured so that the wafer 1 in a state in which tension is applied by the tension generating device 100 can be placed on the chuck stage 5. In the example of FIG. 6, a moving mechanism 30 is provided for each tension generating mechanism 2. However, the present invention is not limited to this, and a common moving mechanism 30 may be provided for multiple tension generating mechanisms 2.

[0033] As described above, according to this embodiment, instead of deforming the wafer by mechanical force, tension can be generated only in the radial direction of the wafer 1 by applying a voltage. Therefore, warpage of the wafer 1 can be corrected while suppressing scratches or dents on the wafer surface.

[0034] In the present embodiment, a configuration has been described in which the wafer 1 is mounted on the first electrode 11 and the second electrode 12 is spaced apart from the wafer 1. By spaced apart at least one of the first electrode 11 and the second electrode 12 from the wafer 1, it is possible to further prevent scratches or dents from occurring on the wafer 1. This is not limiting, and a voltage may be applied to the electrode pair 10 with both the first electrode 11 and the second electrode 12 spaced apart from the wafer 1. In this case, a separate member for holding the wafer 1 may be provided. Furthermore, a voltage may be applied to the electrode pair 10 with both the first electrode 11 and the second electrode 12 in contact with the wafer 1, as long as scratches or dents are not caused on the wafer 1.

[0035] The voltage application unit may be configured to be able to apply voltages of different magnitudes to the plurality of electrode pairs 10. The voltage application unit may also be configured to be able to apply voltages to the plurality of electrode pairs 10 at different times. This makes it possible to adjust the balance of the tension applied to the wafer and the wafer position. In addition, although a power supply 50 is provided for each tension generating mechanism 2 in the above example, a common power supply 50 may be provided for the plurality of tension generating mechanisms 2.

[0036] In the present embodiment, an example has been described in which the wafer 1 is a silicon wafer. However, the present invention is not limited to this, and the wafer 1 may be formed of a wide bandgap semiconductor. The wide bandgap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

[0037] The technical features described in this embodiment may be used in appropriate combination.

[0038] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) a plurality of electrode pairs, each having a first electrode and a second electrode; a voltage application unit configured to apply a voltage between the first electrode and the second electrode of each of the plurality of electrode pairs in a state in which each of the plurality of electrode pairs is arranged so that an edge of the wafer is sandwiched between the first electrode and the second electrode in a direction perpendicular to the main surface of the wafer, and the first electrode and the second electrode protrude outward beyond the wafer when viewed in the direction perpendicular to the main surface of the wafer; A tension generating device comprising: (Appendix 2) 2. The tension generating device according to claim 1, wherein tension is exerted on the wafer by applying the voltage between the first electrode and the second electrode. (Appendix 3) 3. The tension generating device according to claim 1, wherein the first electrode and the second electrode are configured to apply the voltage in a direction perpendicular to the main surface of the wafer. (Appendix 4) 4. The tension generator according to claim 1, wherein at least one of the first electrode and the second electrode is spaced apart from the wafer. (Appendix 5) 5. The tension generator according to any one of claims 1 to 4, wherein the distance between the first electrode and the second electrode is 40 μm or more and 200 μm or less while the voltage is being applied. (Appendix 6) an insulating layer is provided on a surface of at least one of the first electrode and the second electrode that faces the wafer; 6. The tension generator according to any one of claims 1 to 5, wherein the insulating layer has a Young's modulus lower than 130 GPa. (Appendix 7) 7. The tension generating device according to any one of claims 1 to 6, wherein the voltage application unit is configured to be able to apply voltages of different magnitudes to the plurality of electrode pairs. (Appendix 8) 8. The tension generating device according to any one of claims 1 to 7, wherein the voltage application unit is configured to be able to apply voltages to the plurality of electrode pairs at different timings. (Appendix 9) 9. The tension generator according to any one of claims 1 to 8, wherein the wafer is formed of a wide band gap semiconductor. (Appendix 10) 10. The semiconductor device according to claim 9, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond. (Appendix 11) A tension generating device according to any one of appendices 1 to 10; A chuck stage and a moving mechanism configured to place the wafer on the chuck stage while the tension is applied by the tension generating device; A semiconductor manufacturing apparatus comprising: [Explanation of symbols]

[0039] 1, 1' wafer, 2, 2a, 2b tension generating mechanism, 3 housing, 4 sputtering target, 5 chuck stage, 10 electrode pair, 11 first electrode, 12 second electrode, 14 insulating layer, 21, 22 base member, 30 moving mechanism, 31, 32 part, 34 bellows, 35 actuator, 36 vacuum pump, 50 power supply, 100 tension generating device, 200 semiconductor manufacturing equipment

Claims

1. a plurality of electrode pairs each having a first electrode and a second electrode; a voltage application unit configured to apply a voltage between the first electrode and the second electrode of each of the plurality of electrode pairs in a state in which each of the plurality of electrode pairs is arranged so that an edge of the wafer is sandwiched between the first electrode and the second electrode in a direction perpendicular to the main surface of the wafer, and the first electrode and the second electrode protrude outward beyond the wafer when viewed in the direction perpendicular to the main surface of the wafer; A tension generating device comprising:

2. 2. The tension generator according to claim 1, wherein tension is applied to the wafer by applying the voltage between the first electrode and the second electrode.

3. 3. The tension generator according to claim 1, wherein the first electrode and the second electrode are configured to apply the voltage in a direction perpendicular to the main surface of the wafer.

4. 3. The tension generator according to claim 1, wherein at least one of the first electrode and the second electrode is spaced apart from the wafer.

5. 3. The tension generator according to claim 1, wherein the distance between the first electrode and the second electrode is 40 μm or more and 200 μm or less while the voltage is being applied.

6. an insulating layer is provided on a surface of at least one of the first electrode and the second electrode that faces the wafer; 3. The tension generator according to claim 1, wherein the insulating layer has a Young's modulus lower than 130 GPa.

7. 3. The tension generating device according to claim 1, wherein the voltage application unit is configured to be able to apply voltages of different magnitudes to the plurality of electrode pairs.

8. 3. The tension generator according to claim 1, wherein the voltage application unit is configured to be able to apply voltages to the plurality of electrode pairs at different timings.

9. 3. The tension generator according to claim 1, wherein the wafer is made of a wide band gap semiconductor.

10. 10. The tension generator according to claim 9, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

11. The tension generating device according to claim 1 or 2; A chuck stage and a moving mechanism configured to place the wafer on the chuck stage while the tension is applied by the tension generating device; A semiconductor manufacturing apparatus comprising:

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