Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device and a method of manufacturing the same capable of suppressing deterioration in forward characteristics of a parasitic diode or achieving suppression of deterioration in forward characteristics of the parasitic diode, improvement in short circuit resistance, and reduction in resistance of an incorporated SBD (Schottky Barrier Diode).SOLUTION: A trench type SBD 30 is configured by: a Schottky trench 31 between gate trenches 7 adjacent to each other; and a conductive film 32 that buries the Schottky trenches 31. The conductive film 32 is configured by first and second metal films 32a and 32b formed of different materials. The first metal film 32a is a titanium film, a nickel film, or a tungsten film in Schottky contact with an n-type current diffusion region 3 at a side wall of the Schottky trench 31. The second metal film 32b is an aluminum film or a tungsten film having an electric resistivity lower than that of the first metal film 32a, being buried at the central part side of the Schottky trench 31 from the first metal film 32a so as to extend in a straight line in a depth direction Z.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices using silicon carbide (SiC) as a semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) are known in which a trench-gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a trench-type Schottky barrier diode (SBD) are integrated into the same semiconductor substrate (semiconductor chip).

[0003] In a MOSFET with an integrated SBD on the same semiconductor substrate, the integrated SBD, which has a lower forward voltage than the parasitic diode (body diode) formed at the pn junction between the MOSFET's base region and drift region, preferentially operates during MOSFET switching operation. This reduces the reverse recovery loss of the parasitic diode. Furthermore, the expansion of stacking faults that occur when the parasitic diode is forward-currented is suppressed by the voltage distribution associated with the operation of the integrated SBD, thereby suppressing the degradation of the parasitic diode's forward characteristics.

[0004] Figure 9 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device 110 shown in Figure 9 is a trench-gate type MOSFET in which a trench-type SBD 130 is embedded in the same semiconductor substrate 140 made of silicon carbide. The semiconductor substrate 140 has a trench (hereinafter referred to as a gate trench) 107 in which the gate electrode 109 of the MOSFET is embedded, and a trench (hereinafter referred to as a Schottky trench) 131 in which the conductive film 132 of the trench-type SBD 130 is embedded.

[0005] The source electrode 112 of the MOSFET is composed of a nickel silicide (NiSi) film 121, a titanium nitride (TiN) film 122, a titanium (Ti) film 123, and an aluminum (Al) film 124 provided on the front surface of the semiconductor substrate 140. The nickel silicide film 121 is provided on the front surface of the semiconductor substrate 140 in the portion exposed to the contact hole of the interlayer insulating film 111, n + Type source region 105 and p ++ The titanium nitride film 122 is in ohmic contact with the type contact region 106. The titanium nitride film 122 covers only the surface of the interlayer insulating film 111.

[0006] The titanium film 123 covers the nickel silicide film 121 and the titanium nitride film 122. The aluminum film 124 is embedded in the contact holes of the interlayer insulating film 111 and is n through the titanium film 123 and the nickel silicide film 121. + Type source region 105 and p ++ It is electrically connected to the type contact region 106. Reference numerals 101, 102, 104, 108, 113, and 114 indicate the n of the MOSFET, respectively. + Type drain region, n - p-type drift region, p-type base region, gate insulating film, p + These are the type region and the drain electrode.

[0007] The trench-type SBD130 comprises a Schottky trench 131 and a conductive film 132 embedded inside the Schottky trench 131. The trench-type SBD130 is a diode that utilizes the rectifying properties of a Schottky barrier formed at the junction surfaces 133 (two locations enclosed by dashed-dotted circles) between the conductive film 132 and the n-type current diffusion region 103 on both side walls of the Schottky trench 131. The conductive film 132 is a single-layer titanium film and is electrically connected in contact with the titanium film 123 and aluminum film 124 that constitute the source electrode 112.

[0008] As a conventional trench-gate MOSFET with an integrated SBD, an apparatus has been proposed that includes a metal layer that makes Schottky contact with the drift region at the sidewall of a Schottky trench provided between adjacent gate trenches, and a source electrode that fills the Schottky trench (see, for example, Patent Document 1 below). Patent Document 1 below discloses that the material of the metal layer that makes Schottky contact with the drift region is titanium, nickel, gold, tungsten, platinum, or chromium, and the material of the source electrode is aluminum. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2020-077664 [Overview of the project] [Problems that the invention aims to solve]

[0010] In conventional silicon carbide semiconductor devices 110 (see Figure 9), the trench-type SBD 130 is made easier to operate by using a single metal such as titanium or nickel (Ni), which has a low Schottky barrier, as the material for the conductive film 132 embedded in the Schottky trench 131, thereby suppressing the degradation of the forward characteristics of the parasitic diodes of the MOSFET. However, titanium and nickel have higher resistivity compared to aluminum (Al), which is a common electrode material for MOSFETs. Because the current path of the trench-type SBD 130 is lengthened in the depth direction by the Schottky trench 131, there is a risk that the trench-type SBD 130 will have high resistance.

[0011] Furthermore, it has been confirmed that using titanium or nickel, which have low Schottky barriers, as the material for the conductive film 132 embedded in the Schottky trench 131 reduces the short-circuit withstand capability of the MOSFET. On the other hand, using metals other than titanium and nickel for the conductive film 132 to increase the short-circuit withstand capability of the MOSFET results in a decrease in the Schottky characteristics of the trench-type SBD 130. Therefore, it is difficult to achieve both suppression of forward characteristic degradation of the parasitic diodes of the MOSFET, improvement of the short-circuit withstand capability of the MOSFET, and low resistance of the trench-type SBD 130.

[0012] The present invention aims to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device, which have an SBD embedded in the same semiconductor substrate, in order to solve the problems of the prior art described above, and which suppresses the degradation of the forward characteristics of the parasitic diode, or suppresses the degradation of the forward characteristics of the parasitic diode and improves the short-circuit withstand capability, and also enables the embedded SBD to be made low-resistance. [Means for solving the problem]

[0013] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features: A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between the front surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the front surface of the semiconductor substrate and the second semiconductor region. Multiple trenches are From the front surface of the semiconductor substrate The third semiconductor region and the second semiconductor region Beyond The first semiconductor region is reached. The aforementioned multiple no to Some of the wrenches It is a trench coat. Trench 1 teeth, internal niGe A gate electrode is provided via a thermal insulating film. The aforementioned multiple no to A second trench, which is different from the first trench among the wrenches. InsideA conductive film is embedded within it. The conductive film is formed by laminating multiple metal films made of different materials.

[0014] The first electrode is electrically connected to the second semiconductor region, the third semiconductor region, and the conductive film. The second electrode is provided on the back surface of the semiconductor substrate. A Schottky barrier diode is provided that utilizes the rectifying properties of the Schottky barrier formed at the junction between the conductive film and the first semiconductor region. The conductive film comprises a first metal film and a second metal film. The first metal film is provided along the inner wall of the second trench and makes Schottky contact with the first semiconductor region at the inner wall of the second trench. The second metal film is provided closer to the center of the second trench than the first metal film. The second metal film has a lower electrical resistivity than the first metal film. The first metal film is a nickel film. The second metal film is a tungsten film.

[0015] Also, In order to solve the above-mentioned problems and achieve the objectives of the present invention, The silicon carbide semiconductor device according to this invention is It has the following characteristics: A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between the front surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the front surface of the semiconductor substrate and the second semiconductor region. Multiple trenches are From the front surface of the semiconductor substrate The third semiconductor region and the second semiconductor region Beyond The first semiconductor region is reached. The aforementioned multiple no to Some of the wrenches It is a trench coat. Trench 1 teeth, internal niGe A gate electrode is provided via a thermal insulating film. The aforementioned multiple no to A second trench, which is different from the first trench among the wrenches. Inside A conductive film is embedded within it. The conductive film is formed by laminating multiple metal films made of different materials.

[0016] The first electrode is electrically connected to the second semiconductor region, the third semiconductor region, and the conductive film. The second electrode is provided on the back surface of the semiconductor substrate. A Schottky barrier diode is provided that utilizes the rectifying properties of the Schottky barrier formed at the junction between the conductive film and the first semiconductor region. The conductive film comprises a first metal film, a second metal film, and a third metal film. The first metal film is provided along the inner wall of the second trench and makes Schottky contact with the first semiconductor region at the inner wall of the second trench. The second and third metal films are provided closer to the center of the second trench than the first metal film. The second metal film has a lower electrical resistivity than the first metal film. The third metal film has a higher melting point than the second metal film.

[0017] Furthermore, in the silicon carbide semiconductor device according to this invention, the third metal film is embedded on the bottom surface side of the second trench, closer to the center of the second trench than the first metal film. The second metal film is embedded on the first electrode side, closer to the center of the second trench than the first metal film and closer to the first electrode than the third metal film.

[0018] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the first metal film is a titanium film or a nickel film, the second metal film is an aluminum film, and the third metal film is a tungsten film.

[0019] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the first metal film is provided only on the first semiconductor region on the inner wall of the second trench.

[0020] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the thickness of the first metal film is thicker at the bottom surface portion of the second trench than at the side wall portion of the second trench.

[0021] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the thickness of the first metal film is 100 nm or more and 200 nm or less.

[0022] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention is a method for manufacturing a silicon carbide semiconductor device according to the present invention, comprising a deposition step of depositing a plurality of metal films inside the second trench to form the conductive film. The deposition step is characterized in that the tungsten film among the plurality of metal films of the conductive film is formed by chemical vapor deposition.

[0023] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention is a method for manufacturing a silicon carbide semiconductor device according to the present invention, comprising a deposition step of depositing a plurality of metal films inside the second trench to form the conductive film. In the deposition step, the aluminum film among the plurality of metal films of the conductive film is formed by a reflow sputtering method. [Effects of the Invention]

[0024] The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention have the effect of suppressing the degradation of the forward characteristics of parasitic diodes, or suppressing the degradation of the forward characteristics of parasitic diodes and improving the short-circuit withstand capability, as well as reducing the resistance of the built-in SBD. [Brief explanation of the drawing]

[0025] [Figure 1] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 2] This is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. [Figure 3] Figure 1 is a cross-sectional view showing another example of a trench-type SBD. [Figure 4]Figure 1 is a cross-sectional view showing another example of a trench-type SBD. [Figure 5] Figure 1 is an explanatory diagram showing the operation of a trench-type SBD during reverse recovery. [Figure 6] Figure 9 is an explanatory diagram showing the operation of a trench-type SBD during reverse recovery. [Figure 7] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 8] Figure 7 is a cross-sectional view showing another example of a trench-type SBD. [Figure 9] This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. [Modes for carrying out the invention]

[0026] Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these prefixes. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0027] (Embodiment 1) The structure of a silicon carbide (SiC) semiconductor device according to Embodiment 1 will now be described. Figure 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 1 shows the state of the active region 51 in Figure 2. Figure 2 is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. Figure 2 shows the layout of the gate trench 7 and Schottky trench 31. The gate insulating film 8 is omitted from the illustration in Figure 2. Figures 3 and 4 are cross-sectional views showing another example of the trench-type SBD in Figure 1.

[0028] The silicon carbide semiconductor device 10 according to Embodiment 1 shown in FIGS. 1 and 2 is a vertical MOSFET with a trench gate structure having a trench-type SBD 30 built in the same semiconductor substrate (semiconductor chip) 40 made of silicon carbide. In the active region 51, on the front surface side of the semiconductor substrate 40, a trench (gate trench: first trench) 7 in which a gate electrode 9 constituting the trench gate structure of the MOSFET is embedded, and a trench (Schottky trench: second trench) 31 in which the trench-type SBD 30 is embedded, are provided.

[0029] The active region 51 is a region where the main current (drift current) flows when the MOSFET is in the on state, and a plurality of unit cells (functional units of the device) of the MOSFET are arranged adjacent to each other. FIG. 1 shows a part of the plurality of unit cells of the active region 51. The edge termination region 52 is a region between the active region 51 and the end (chip end) of the semiconductor substrate 40, surrounds the active region ither of the semiconductor substrate 40, and relaxes the electric field on the front surface side of the semiconductor substrate 40 to maintain the breakdown voltage. The breakdown voltage is the limit voltage at which the silicon carbide semiconductor device 10 does not malfunction or break down.

[0030] In the edge termination region 52, a breakdown voltage structure such as a field limiting ring (FLR) or a junction termination extension (JTE) structure is arranged. The trench-type SBD 30 has a function of preventing deterioration of the forward characteristics of a parasitic diode (body diode) formed by a pn junction between a p-type contact region 6, a p-type base region (second semiconductor region) 4 and a p ++ -type region 13, and an n-type current diffusion region 3, an n + -type drift region (first semiconductor region) 2 and an n - -type drain region 1. + The semiconductor substrate 40 is an n

[0031] -type starting substrate 41 on the front surface, and an n + -type layer is formed on the front surface of the n -The silicon carbide layers 42 and 43, which form the p-type drift region 2 and the p-type base region 4, are grown epitaxially in sequence. The main surface of the semiconductor substrate 40 on the side of the p-type silicon carbide layer 43 is considered the front surface, and n + The main surface on the starting substrate 41 side is considered the back surface. A trench gate structure MOS gate is provided on the front surface side of the semiconductor substrate 40. The MOS gate has a p-type base region 4, n + Type source region (third semiconductor region) 5, p ++ It consists of a type contact region 6, a gate trench 7, a gate insulating film 8, and a gate electrode 9.

[0032] n + The starting substrate 41 is n + This is type drain region 1. - Type drift region 2 is n - The type silicon carbide layer 42, as described later, p + This is the portion excluding the type region 13 and the n-type current diffusion region 3 described later, p + Type 13 and n-type current diffusion region 3 and n + These regions are provided in contact with the starting substrate 41. The p-type base region 4 is the n of the p-type silicon carbide layer 43, which will be described later. + Type source area 5 and p described later ++ This is the portion excluding the contact area 6, and is the front surface of the semiconductor substrate 40 and n - It is located between the drift region 2 and the other region.

[0033] n + Type source region 5 and p ++ The type contact region 6 is selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 4. + Type source region 5 and p ++ The p-type contact region 6 is in contact with the p-type base region 4 and is exposed on the front surface of the semiconductor substrate 40. ++ The type contact area 6 does not need to be provided. ++ If a type contact area 6 is not provided, p ++ Instead of the type contact region 6, the p-type base region 4 is exposed on the front surface of the semiconductor substrate 40.

[0034] n - Between the p-type drift region 2 and the p-type base region 4, n - An n-type current diffusion region 3 is provided adjacent to the p-type drift region 2 and the p-type base region 4. The n-type current diffusion region 3 is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. The n-type current diffusion region 3 is adjacent to the gate trench 7 and the Schottky trench 31 (described later) in a direction parallel to the top surface of the semiconductor substrate 40, and is n-type in the direction of the bottom surface of these trenches. + It reaches a deep position on the drain region 1 side.

[0035] p + The mold region 13 is n greater than the bottom surface of the gate trench 7. + Multiple p-type drain regions are provided at a deep position on the drain region 1 side, separated from the p-type base region 4. + Each mold region 13 faces the bottom surface of a different gate trench 7 in the depth direction Z. + The mold region 13 may be exposed to the bottom surface of the gate trench 7. Exposure to the bottom surface of the gate trench 7 means that it is provided so as to surround the bottom surface of the gate trench 7 at a position opposite to the bottom surface of the gate trench 7, and is in contact with the gate insulating film 8 at the bottom surface of the gate trench 7.

[0036] As mentioned above, p + The mold region 13 is n greater than the bottom surface of the gate trench 7. + It is sufficient that the drain region 1 side reaches a deep position, p + The depth of type region 13 can be changed in various ways. For example, p + The n-type region 13 extends to a deeper position than the n-type current diffusion region 3 (see Figure 1), or n + The drain region 1 is terminated at the same depth as the n-type current diffusion region 3 (not shown). - Touching type drift region 2, or n + The drain region 1 may terminate at a shallower position than the n-type current diffusion region 3, and may be surrounded by the n-type current diffusion region 3 (not shown).

[0037] p + The n-type region 13 is electrically connected to the source electrode (first electrode) 12 in a part not shown in the figure, and has the function of depleting when the MOSFET is off, thereby mitigating the electric field applied to the bottom surface of the gate trench 7. The n-type current diffusion region 3 is not required. If the n-type current diffusion region 3 is not provided, the p-type base region 4 and n - It touches the drift region 2. + Type region 13 is n - It is surrounded by a type drift region 2. Furthermore, the n-type current diffusion region 3, which will be explained later, is n - This can be interpreted as type drift region 2.

[0038] The gate trench 7 has a depth of n in the Z direction. + The gate trench 7 penetrates the p-type source region 5 and the p-type base region 4 to reach the n-type current diffusion region 3. The gate trench 7 extends in a stripe shape in a first direction X parallel to the front surface of the semiconductor substrate 40, for example. Between adjacent gate trenches 7, the p-type base region 4, n + Type source area 5, p ++ Type contact area 6 and p + The mold region 13 extends linearly in the first direction X parallel to the gate trench 7. ++ The type contact regions 6 may be scattered in the first direction X parallel to the gate trench 7.

[0039] Inside the gate trench 7, a gate electrode 9 is provided via a gate insulating film 8. The space between the centers of all adjacent gate trenches 7 constitutes one unit cell of the trench-gate type MOSFET. Schottky trenches 31 are provided between each of the adjacent gate trenches 7, with a depth of Z in the p direction. ++ The Schottky trench 31 penetrates the p-type contact region 6 and the p-type base region 4 to reach the n-type current diffusion region 3. The Schottky trench 31 is, for example, shorter in length than the gate trench 7 and extends parallel to the gate trench 7 in the first direction X.

[0040] The Schottky trenches 31 and gate trenches 7 are arranged alternately and repeatedly in a second direction Y that is parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X. In the depth direction Z, at a position opposite the bottom surface of each Schottky trench 31, and in addition to that, exposed on the bottom surface, p near the bottom surface of the gate trench 7 + Similar to type region 13, each is p + A mold region 13 is selectively provided. Exposure to the bottom surface of the Schottky trench 31 means that the bottom surface of the Schottky trench 31 is surrounded and in contact with the conductive film 32, which will be described later.

[0041] A single unit cell of the trench-type SBD 30 is composed of a Schottky trench 31 and a conductive film 32 embedded in the Schottky trench 31. The trench-type SBD 30 is a diode that utilizes the rectifying properties of a Schottky barrier formed at the junction surface 33 (two locations enclosed by the dashed-dotted circles) between the conductive film 32 and the n-type current diffusion region 3 on the side wall of the Schottky trench 31. The trench-type SBD 30 extends in the first direction X along both side walls of the Schottky trench 31. It is preferable that the Schottky trench 31 is completely embedded with the conductive film 32.

[0042] The conductive film 32 is composed of multiple metal films of different materials, each individually embedded in the Schottky trench 31. That is, the multiple metal films constituting the conductive film 32 form layers inside the Schottky trench 31. The combination of multiple metal films constituting the conductive film 32 can be changed in various ways depending on the purpose (desired effect). For example, the combination of multiple metal films constituting the conductive film 32 is determined based on parameters such as the size of the Schottky barrier against silicon carbide, electrical resistivity, and melting point.

[0043] By combining multiple metal films that constitute the conductive film 32, it is possible to suppress the degradation of the forward characteristics of the parasitic diodes of the MOSFET (deactivation of the parasitic diodes), improve the short-circuit (source-gate short-circuit) withstand capability of the MOSFET, or both, while also reducing the resistance of the trench-type SBD 30 (improvement of the static characteristics of the trench-type SBD 30). To suppress the degradation of the forward characteristics of the parasitic diodes of the MOSFET, it is preferable to use a metal material with a relatively small Schottky barrier to silicon carbide compared to metals in general for the first metal film 32a, which will be described later.

[0044] To improve the short-circuit withstand capability of the MOSFET, it is preferable to use a metal material with a relatively large Schottky barrier to silicon carbide for the first metal film 32a, or to use a metal material that does not melt due to the heat generated by the semiconductor substrate 40 when the MOSFET is short-circuited for the second metal film 32b (described later), or to use first and second metal films 32a and 32b that use both of these metal materials, respectively. To reduce the resistance of the trench-type SBD 30, it is preferable to use a metal material with a lower electrical resistivity than the first metal film 32a for the second metal film 32b (described later).

[0045] Specifically, the conductive film 32 has an n-type current diffusion region 3 on the side wall of the Schottky trench 31 (if an n-type current diffusion region 3 is not provided, then n - The device includes a first metal film 32a that contacts the n-type drift region 2) and forms a Schottky barrier of, for example, 1.1 eV to 1.5 eV at the junction surface 33 with the n-type current diffusion region 3, and a second metal film 32b that has a lower electrical resistivity than the first metal film 32a. The first and second metal films 32a and 32b may have approximately the same Schottky barrier to silicon carbide.

[0046] The first metal film 32a is provided along the side wall of the Schottky trench 31 and makes Schottky contact with the n-type current diffusion region 3. The thickness t1 of the first metal film 32a on the side wall of the Schottky trench 31 should be formed to be as thin and substantially uniform as possible to obtain predetermined Schottky characteristics. By making the thickness t1 of the first metal film 32a substantially uniform, it is possible to suppress variations in the Schottky characteristics of the trench-type SBD 30. Substantially uniform thickness means that the thickness is the same within a range that includes the tolerance for process variation.

[0047] The thinner the thickness t1 of the sidewall portion of the first metal film 32a over the Schottky trench 31, the lower the electrical resistivity of the conductive film 32 can be. The width w of the Schottky trench 31 in the second direction Y is, for example, about 0.1 μm to 0.4 μm, and it is preferable to thin the thickness t1 of at least the sidewall portion of the first metal film 32a over the Schottky trench 31 to, for example, about 100 nm to 200 nm. The thickness t2 of the bottom portion of the Schottky trench 31 over the first metal film 32a may be thicker than the thickness t1 of the sidewall portion (Figure 4).

[0048] The first metal film 32a may be provided on the entire inner wall (side wall and bottom surface) of the Schottky trench 31 (Figure 1), or it may be provided only on the side wall of the Schottky trench 31 and not on the bottom surface of the Schottky trench 31 (not shown). The first metal film 32a only needs to be in contact with at least the n-type current diffusion region 3 on the side wall of the Schottky trench 31, and may be provided only on a part of the inner wall of the Schottky trench 31, for example, only on the bottom surface side from the pn junction surface between the p-type base region 4 and the n-type current diffusion region 3 (Figure 3).

[0049] By applying the trench-type SBD30 of Figure 4 to the trench-type SBD30 of Figure 3, the first metal film 32a is provided on the side and bottom surface of the Schottky trench 31, from the pn junction surface between the p-type base region 4 and the n-type current diffusion region 3 to the bottom surface side of the Schottky trench 31, and the thickness t2 of the bottom portion of the Schottky trench 31 may be made thicker than the thickness t1 of the side wall portion. In this case, the second metal film 32b is in contact with the silicon carbide portion (the region exposed on the inner wall of the Schottky trench 31) on the opening side and bottom surface of the Schottky trench 31.

[0050] The second metal film 32b is embedded on the first metal film 32a inside the Schottky trench 31. The second metal film 32b is embedded closer to the approximate center of the Schottky trench 31 (the center of the first and second directions X and Y) than the first metal film 32a, and extends linearly inside the Schottky trench 31 in the depth direction Z. When the first metal film 32a is provided on the entire inner wall of the Schottky trench 31, the second metal film 32b is completely surrounded by the first metal film 32a and does not come into contact with the silicon carbide portion.

[0051] The shorter the length of the second metal film 32b extending in the depth direction Z, the smaller the effect of reducing the resistance of the trench-type SBD 30. However, the second metal film 32b does not need to reach near the bottom surface of the Schottky trench 31. Figure 4 shows the case where the second metal film 32b terminates near the pn junction between the p-type base region 4 and the n-type current diffusion region 3 in the depth direction Z. Thus, the conductive film 32, formed by sequentially stacking the first and second metal films 32a and 32b, is embedded in the Schottky trench 31. The conductive film 32 is electrically connected to the source electrode 12, which will be described later.

[0052] For the materials of the first and second metal films 32a and 32b, various combinations of aluminum (Al), titanium (Ti), nickel (Ni), which are common electrode materials for MOSFETs (materials for the source electrode 12 and the drain electrode (second electrode) 14 described later), and tungsten (W), which is a material for wiring members, can be used. Titanium and aluminum have substantially the same Schottky barrier with respect to silicon carbide. Nickel and tungsten have a larger Schottky barrier with respect to silicon carbide than titanium and aluminum.

[0053] Aluminum and tungsten have lower electrical resistivity than titanium and nickel. Aluminum has a very low melting point compared to titanium, nickel, and tungsten. Tungsten has a higher melting point than titanium and nickel. Representing the magnitude (or high and low) of the physical properties between these metals with the element symbols of each metal and inequality signs, the Schottky barrier with respect to silicon carbide is Al≒Ti<W<Ni, the electrical resistivity is Al<W<Ni<Ti, and the melting point is Al≪Ni<Ti<W.

[0054] In this case, the first metal film 32a is a titanium film, a nickel film, or a tungsten film. The second metal film 32b is an aluminum film or a tungsten film. The titanium film and the nickel film are formed, for example, by a sputtering method. The aluminum film is formed, for example, by a reflow sputtering method in which it is softened by heat treatment (reflow) while being deposited by a sputtering method and embedded in the trench. The tungsten film is formed, for example, by a chemical vapor deposition (CVD) method.

[0055] The deterioration of the forward characteristics of the parasitic diode of the MOSFET is suppressed by the Schottky barrier of the first metal film 32a (titanium film, nickel film, or tungsten film). When the first metal film 32a is a titanium film, it may be formed simultaneously with the titanium film 23 of the source electrode 12. When the first metal film 32a is a nickel film or a tungsten film, the short-circuit withstand of the MOSFET is improved because the Schottky barrier is larger than that of the titanium film.

[0056] The conductivity of the trench-type SBD 30 is improved by the second metal film 32b (aluminum film or tungsten film), which has a lower electrical resistivity than the first metal film 32a. If the second metal film 32b is a tungsten film, it will not melt due to the heat generated by the semiconductor substrate 40 (e.g., high temperatures of 800°C or higher) when the MOSFET is short-circuited. Therefore, the short-circuit withstand capability of the MOSFET is improved. Even if the second metal film 32b is an aluminum film, it is preferable to form it using a method that provides high embedding into the Schottky trench 31, such as a reflow sputtering method, rather than forming it simultaneously with the aluminum film 24 of the source electrode 12.

[0057] The interlayer insulating film 11 is provided over the entire surface of the front surface of the semiconductor substrate 40 and covers the gate electrode 9. Between adjacent gate trenches 7, contact holes 11a are provided that penetrate the interlayer insulating film 11 in the depth direction Z and reach the semiconductor substrate 40. + Type source area 5, p ++ The contact region 6 and the conductive film 32 (at least the second metal film 32b) are exposed. The source electrode 12 is provided extending from the front surface of the semiconductor substrate 40 in the contact hole 11a to the surface of the interlayer insulating film 11.

[0058] The source electrode 12 is composed of a nickel silicide (NixSiy, where x and y are positive numbers) film 21, a titanium nitride (TiN) film 22, a titanium film 23, and an aluminum film 24, which are provided on the front surface of the semiconductor substrate 40. The nickel silicide film 21 is provided on the front surface of the semiconductor substrate 40 in the contact hole 11a, n + Type source region 5 and p ++ The titanium nitride film 22 is in ohmic contact with the type contact region 6. The titanium nitride film 22 is provided on the entire surface of the interlayer insulating film 111, covering only the surface of the interlayer insulating film 11.

[0059] The titanium film 23 is provided along the surface of the interlayer insulating film 11 from the front surface of the semiconductor substrate 40 in the contact hole 11a, covering the nickel silicide film 21 and the titanium nitride film 22. The aluminum film 24 is provided on top of the titanium film 23 and the conductive film 32 so as to fill the contact hole 11a. The aluminum film 24 is provided via the nickel silicide film 21, the titanium nitride film 22 and the titanium film 23. + Type source area 5, p ++ It is electrically connected to the type contact area 6.

[0060] The aluminum film 24 is in contact with the conductive film 32 (second metal film 32b, or both the first and second metal films 32a and 32b) of the trench-type SBD 30 and is electrically connected to the conductive film 32 (first and second metal films 32a and 32b). Instead of the aluminum film 24, an aluminum alloy film such as an aluminum-silicon (Al-Si) film may be provided. The back surface (n + A drain electrode 14 is provided on the back surface of the starting substrate 41, which makes ohmic contact with the back surface of the semiconductor substrate 40.

[0061] Next, the operation of the silicon carbide semiconductor device 10 according to Embodiment 1 will be described. Figure 5 is an explanatory diagram showing the operation of the trench-type SBD in Figure 1 during reverse recovery. Figure 6 is an explanatory diagram showing the operation of the trench-type SBD in Figure 9 (conventional silicon carbide semiconductor device 110) during reverse recovery. Figure 5 shows the vicinity of the trench-type SBD 30 in Figure 1. Although not shown, the trench-type SBD 30 in other examples in Figures 3 and 4 operates similarly to the trench-type SBD 30 in Figure 5. Figure 6 shows the vicinity of the trench-type SBD 130 in Figure 9.

[0062] As shown in Figure 5, in the silicon carbide semiconductor device 10 according to Embodiment 1, the p of the MOSFET ++ Type 6 contact area, p-type base area 4 and p + Type 13 region, n-type current diffusion region 3, n - Type drift regions 2 and n +When the parasitic diode formed at the pn junction with the drain region 1 is forward-biased, the trench-type SBD 30, whose forward voltage is set lower than that of the parasitic pn diode due to the Schottky barrier determined by the electrical properties of the first metal film 32a of the conductive film 32, conducts faster than the parasitic pn diode (not shown).

[0063] Therefore, the n-type current diffusion region 3, the p-type base region 4 and n inside the semiconductor substrate 40 + The vertical parasitic NPN bipolar transistor (body diode) formed in the source region 5 does not operate. As a result, the first metal film 32a of the conductive film 32 suppresses the degradation of the forward characteristics of the MOSFET's parasitic diode and reduces reverse recovery losses. Furthermore, if the first metal film 32a of the conductive film 32 is a nickel film or a tungsten film, the short-circuit withstand capability of the MOSFET can be further improved.

[0064] On the other hand, when the parasitic pn diode of the MOSFET is reverse-biased (reverse recovery), the trench-type SBD30 also reverses. During reverse recovery, n from the drain electrode 14 of the MOSFET. + Type drain region 1, n - The reverse recovery current I1, which flows in the direction toward the source electrode 12 (reverse direction) through the n-type drift region 2 and the n-type current diffusion region 3, flows toward the source electrode 12 via the second metal film 32b, which has a relatively lower electrical resistivity among the first and second metal films 32a and 32b of the conductive film 32 of the trench-type SBD 30, which has a shorter reverse recovery time than the parasitic pn diode.

[0065] During the reverse recovery of a parasitic pn diode in such a MOSFET, for example, in the conventional structure shown in Figure 6, the conductive film 132 embedded in the Schottky trench 131 of the trench-type SBD 130 is made of a single metal. As a result, the reverse recovery current I101 flows from the n-type current diffusion region 103 through the highly resistive conductive film 132 (single-layer titanium or nickel film) of the trench-type SBD 130 to the source electrode 112. Consequently, the amount of the reverse recovery current I1 becomes small, and the trench-type SBD 130 becomes highly resistive.

[0066] In contrast, in Embodiment 1, the reverse recovery current I1 passes through the first metal film 32a, which is provided along the side wall of the Schottky trench 31, in the thickness t1 direction, and flows through the second metal film 32b, which is located closer to the center of the Schottky trench 31 than the first metal film 32a and has a lower electrical resistivity than the first metal film 32a. As a result, the amount of the reverse recovery current I1 is easily maintained, and the thinner the thickness of the first metal film 32a, the lower the resistance of the trench-type SBD 30. Furthermore, if the second metal film 32b is a tungsten film, the second metal film 32b is less likely to melt when the MOSFET is short-circuited, thus further improving the short-circuit withstand capability of the MOSFET.

[0067] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to Embodiment 1 will be described. First, the n made of silicon carbide + Prepare a starting substrate (semiconductor wafer) 41. + The starting substrate 41 is n + Type drain region 1. Next, n + On the front surface of the mold starting substrate 41, the n after the product is completed - The thickness of the silicon carbide layer 42 is thinner than the product thickness d, n - A type silicon carbide layer 42 is epitaxially grown. Next, photolithography and ion implantation of p-type impurities are performed. - p + A type region 13 is selectively formed.

[0068] Next, p + After removing the ion implantation mask (not shown) used to form the n-type region 13, photolithography and ion implantation of n-type impurities were performed, for example, across the entire active region. - An n-type current diffusion region 3 is formed on the surface region of the type silicon carbide layer 42. The n-type current diffusion region 3 and p + The formation order with type region 13 may be reversed. n-type current diffusion region 3 and p +The ion implantation mask used for forming the type region 13 or the diffusion region formed by ion implantation described later may be, for example, an oxide film (SiO2 film) or a resist film.

[0069] n - The unimplanted portion remaining between the n-type silicon carbide layer 42, the n-type current diffusion region 3, and the p + type region 13 and the n + type starting substrate 41 becomes the n - type drift region 2. Next, after removing the ion implantation mask (not shown) used for forming the n-type current diffusion region 3, an additional n - type silicon carbide layer is epitaxially grown on the n - type silicon carbide layer 42 to increase the thickness, and the n - type silicon carbide layer 42 is made to the product thickness d. The impurity concentration of the portion where the thickness of the n - type silicon carbide layer 42 is increased may be, for example, substantially the same as the impurity concentration of the n - type drift region 2.

[0070] Next, by photolithography and ion implantation of p-type impurities, p-type impurities are selectively introduced into the portion where the thickness of the n - type silicon carbide layer 42 is increased to thicken the thickness of the p + type region 13. Next, after removing the ion implantation mask (not shown) used for forming the p + type region 13, by photolithography and ion implantation of n-type impurities, n-type impurities are introduced over the entire active region into the portion where the thickness of the n - type silicon carbide layer 42 is increased to thicken the thickness of the n-type current diffusion region 3. The formation order of the n-type current diffusion region 3 and the p + type region 13 may be interchanged.

[0071] Next, a p-type silicon carbide layer 43 is epitaxially grown on the surface of the n - type silicon carbide layer 42. Thereby, the n +A semiconductor substrate 40 is completed by sequentially epitaxially growing silicon carbide layers 42 and 43 on the front surface of a starting substrate 41. Next, the edge termination region 52 of the p-type silicon carbide layer 43 is removed by photolithography and etching, leaving the p-type silicon carbide layer 43 only in the active region 51. At the edge termination region 52, the front surface of the semiconductor substrate 40 has n - The silicon carbide layer 42 is exposed.

[0072] Next, the etching mask (not shown) used to partially remove the p-type silicon carbide layer 43 is removed. Then, the process of photolithography, ion implantation of impurities, and removal of the ion implantation mask (not shown) is repeated under different conditions, thereby generating n in the surface region of the p-type silicon carbide layer 43 in the active region 51. + Type source region 5 and p ++ Each type contact region 6 is selectively formed, and in the edge termination region 52 n - p that constitutes a pressure-resistant structure in the surface region of the type silicon carbide layer 42 - It forms a type region (not shown).

[0073] Next, by photolithography and etching, p in the depth direction Z is used. + At a position opposite to type region 13, n + A gate trench 7 penetrates the p-type source region 5 and the p-type base region 4 and reaches the n-type current diffusion region 3, and in the depth direction Z, p ++ A Schottky trench 31 is formed, penetrating the p-type contact region 6 and the p-type base region 4 and reaching the n-type current diffusion region 3. At this time, dry etching using an oxide film as an etching mask (not shown) may be used. Then, the etching mask used to form the trench is removed.

[0074] The gate trench 7 and the Schottky trench 31 may be formed simultaneously, or they may be formed in separate processes to achieve different depths. After the formation of the gate trench 7 and the Schottky trench 31, heat treatment in a hydrogen (H2) atmosphere may be performed to smooth the inner walls and upper ends of the gate trench 7 and the Schottky trench 31. The upper end of the trench is the boundary between the front surface of the semiconductor substrate 40 and the side wall of the trench.

[0075] Next, a sacrificial oxide film (not shown) is formed by sacrificial oxidation along the front surface of the semiconductor substrate 40 and the inner walls of the gate trench 7 and Schottky trench 31. Then, a deposited oxide film (not shown) is formed on the sacrificial oxide film on the front surface of the semiconductor substrate 40 by CVD. A field oxide film is formed on the front surface of the semiconductor substrate 40 by these sacrificial oxide film and deposited oxide film. The deposited oxide film is also deposited on the sacrificial oxide film inside the Schottky trench 31 and embedded in the Schottky trench 31.

[0076] Next, the field oxide film is selectively removed by photolithography and etching, leaving the field oxide film on the surface of the semiconductor substrate 40 in the edge termination region 52. At this time, in the active region 51, the inner wall of the gate trench 7 and n + Type source region 5 and p ++ The type contact region 6 is exposed. Inside the Schottky trench 31, a field oxide film (deposited oxide film) is left to protect the inner wall of the Schottky trench 31. Next, a gate insulating film 8 is formed along the inner wall of the gate trench 7.

[0077] Next, the interface properties between the gate insulating film 8 and silicon carbide (semiconductor substrate 40) are improved by, for example, heat treatment in a nitric oxide (NO) atmosphere (POA: Post Oxidation Annealing). Then, polysilicon (poly-Si) is deposited on the surface of the semiconductor substrate 40 to fill the gate trench 7 with polysilicon. At this time, a polysilicon layer is also formed on the surface of the semiconductor substrate 40, so this polysilicon layer is patterned to leave only the portion of the polysilicon layer that will become the gate electrode 9 inside the gate trench 7.

[0078] Next, after removing the patterning mask (not shown) for the polysilicon layer, a deposited oxide film that will become the interlayer insulating film 11 is deposited on the front surface of the semiconductor substrate 40 by CVD. Next, the interlayer insulating film 11 is selectively removed by photolithography and etching to open a contact hole 11a, and n + Type source region 5 and p ++ The contact area 6 is exposed again. Next, a nickel film, which will be the material film for the nickel silicide film 21, is deposited on the front surface of the semiconductor substrate 40 by sputtering.

[0079] Next, the portion of the nickel film on the surface of the semiconductor substrate 40 is silicided by heat treatment at a temperature of approximately 400°C to 600°C. Then, the portion of the nickel film that has not been silicided is removed by wet etching, for example, the portion of the nickel film above the interlayer insulating film 11 and the field oxide film. As a result, the silicided portion of the nickel film becomes a nickel silicide film 21, which remains on the surface of the semiconductor substrate 40 within the contact hole 11a.

[0080] Next, a nickel film and a titanium film are sequentially deposited on the back surface of the semiconductor substrate 40, and a drain electrode 14 is formed by silicide formation through heat treatment at a temperature of approximately 800°C to 1000°C.

[0081] Next, the interlayer insulating film 11 is selectively removed by photolithography and etching to remove the deposited oxide film inside the Schottky trench 31, exposing the inner wall of the Schottky trench 31. Then, a nickel film, which will be the material film for the first metal film 32a of the trench-type SBD 30, is deposited on the front surface of the semiconductor substrate 40 by sputtering. This nickel film is formed along the inner wall of the Schottky trench 31 and is in contact with the silicon carbide portion (semiconductor substrate 40) only at the inner wall of the Schottky trench 31. Next, the portion of the nickel film on the inner wall of the Schottky trench 31 is silicided by heat treatment at a temperature of approximately 400°C to 600°C.

[0082] Next, the non-silicided portions of the nickel film are removed, for example, by wet etching, to remove the parts of the nickel film other than the inner wall of the Schottky trench 31. As a result, the silicided portion of the nickel film becomes the first metal film 32a, which remains along the inner wall of the Schottky trench 31. If the first metal film 32a of the trench-type SBD 30 is a titanium film or a tungsten film, the steps of forming the nickel film along the inner wall of the Schottky trench 31 and silicideing this nickel film can be omitted, and the subsequent steps (from the formation of the titanium nitride film 22 onwards) can be performed after the formation of the drain electrode 14.

[0083] Next, a titanium nitride film 22 is deposited on the surface of the semiconductor substrate 40, for example by sputtering, leaving it only on the surface of the interlayer insulating film 11. Then, a titanium film 23 is deposited on the surface of the semiconductor substrate 40, for example by sputtering. The titanium film 23 covers the nickel silicide film 21 and the titanium nitride film 22. At this time, a titanium film is also formed on the inner wall of the Schottky trench 31. If the first metal film 32a of the trench-type SBD 30 is a titanium film, the sputtering time and other factors should be adjusted so as not to completely fill the inside of the Schottky trench 31 when depositing the titanium film 23, and the portion of this titanium film 23 formed along the inner wall of the Schottky trench 31 should be considered the first metal film 32a. If the first metal film 32a of the trench-type SBD 30 is a nickel film or a tungsten film, the titanium film on the inner wall of the Schottky trench 31 should be removed.

[0084] Next, the titanium film 23 is fired by annealing at, for example, a temperature of 400°C to 600°C. The titanium nitride film 22 and the titanium film 23 function as barrier metals. The barrier metals have the function of preventing mutual reactions between each metal film constituting the barrier metal or between regions facing each other across the barrier metal. The first metal film 32a on the inner wall of the Schottky trench 31 is not annealed. As a result, a Schottky barrier (Schottky junction) is formed at the junction surface 33 between the first metal film 32a of the conductive film 32 and the n-type current diffusion region 3.

[0085] Next, a second metal film 32b is deposited to embed the second metal film 32b on the first metal film 32a inside the Schottky trench 31. If the second metal film 32b of the trench-type SBD 30 is an aluminum film, the aluminum film is deposited by, for example, a reflow sputtering method. If the second metal film 32b of the trench-type SBD 30 is a tungsten film, the tungsten film is deposited by, for example, a CVD method. As a result, the Schottky trench 31 is filled with the second metal film 32b. In addition, the second metal film 32b is also formed on the front surface of the semiconductor substrate 40.

[0086] Next, the portion of the second metal film 32b that is on the surface of the semiconductor substrate 40 is removed by, for example, chemical mechanical polishing (CMP) or etching, leaving the second metal film 32b only inside the Schottky trench 31. The second metal film 32b may protrude outward (upward) from inside the Schottky trench 31. Through these steps, a trench-type SBD 30 is formed by embedding the conductive film 32, consisting of the first and second metal films 32a and 32b, into the Schottky trench 31.

[0087] Next, an aluminum film 24 is deposited on the titanium film 23 and the conductive film 32, for example, by physical vapor deposition (PVD) or CVD. Then, the aluminum film 24 is fired by heat treatment. The source electrode 12 is formed by the nickel silicide film 21, titanium nitride film 22, titanium film 23, and aluminum film 24. After that, the semiconductor substrate (semiconductor wafer) 40 is diced (cut) to separate it into individual chips, thereby completing the silicon carbide semiconductor device 10 shown in Figures 1 and 2.

[0088] As described above, according to Embodiment 1, the conductive film embedded in the Schottky trench of the trench-type SBD is composed of two metal films made of different materials (titanium film, nickel film, or tungsten film, and aluminum film, or tungsten film). The Schottky properties of the titanium film, nickel film, and tungsten film suppress the degradation of the forward characteristics of the parasitic diodes of the MOSFET. The Schottky properties of the nickel film and tungsten film improve the short-circuit withstand capability of the MOSFET. The low electrical resistivity of the aluminum film and tungsten film reduces the resistance of the trench-type SBD.

[0089] (Embodiment 2) The structure of the silicon carbide semiconductor device according to Embodiment 2 will now be described. Figure 7 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. Figure 7 shows only the area around the trench-type SBD 61 of the silicon carbide semiconductor device 60 according to Embodiment 2. Figure 8 is a cross-sectional view showing another example of the trench-type SBD in Figure 7. The configuration of the silicon carbide semiconductor device 60 according to Embodiment 2 shown in Figures 7 and 8, other than the conductive film 62 of the trench-type SBD 61, is the same as that of the silicon carbide semiconductor device 10 according to Embodiment 1 (see Figures 1 and 2).

[0090] The difference between the silicon carbide semiconductor device 60 according to Embodiment 2 and the silicon carbide semiconductor device 10 according to Embodiment 1 is that the conductive film 62 of the trench-type SBD 61 is composed of three metal films (hereinafter referred to as the first to third metal films) 32a to 32c. Specifically, in Embodiment 2, the first metal film 32a of the conductive film 62 is a titanium film or nickel film provided along the inner wall of the Schottky trench 31. The arrangement and function of the first metal film 32a of the conductive film 62 are the same as the first metal film 32a of Embodiment 1.

[0091] The second metal film 32b of the conductive film 62 is an aluminum film partially embedded on the central side of the Schottky trench 31 than the first metal film 32a. The function of the second metal film 32b of the conductive film 62 is the same as in Embodiment 1 when the second metal film 32b is an aluminum film. The third metal film 32c of the conductive film 62 is a tungsten film partially provided on the central side of the Schottky trench 31 than the first metal film 32a. The third metal film 32c of the conductive film 62 is the same as in Embodiment 1 when the second metal film 32b is a tungsten film.

[0092] The third metal film 32c may be provided along the entire inner wall of the Schottky trench 31 between the first metal film 32a and the second metal film 32b (Figure 7). In this case, the second metal film 32b is embedded closer to the center of the Schottky trench 31 than the third metal film 32c. Alternatively, the third metal film 32c may be embedded closer to the center of the Schottky trench 31 than the first metal film 32a, on the bottom side of the Schottky trench 31, and the second metal film 32b may be embedded closer to the source electrode 12 than the third metal film 32c (Figure 8).

[0093] In the trench-type SBD61 of Embodiment 2 shown in Figures 7 and 8, the high-melting-point third metal film 32c between the heat-generating area (near the bottom surface of the gate trench 7) and the low-melting-point second metal film 32b (aluminum film) constituting the conductive film 62 can delay the temperature rise of the second metal film 32b when the MOSFET is short-circuited. As a result, the second metal film 32b (aluminum film) is less likely to melt when the MOSFET is short-circuited, further improving the short-circuit withstand capability of the MOSFET.

[0094] In particular, in the trench-type SBD61 of Embodiment 2 shown in Figure 8, by placing a relatively thick third metal film 32c (tungsten film) near the bottom surface of the Schottky trench 31, the melting point of the conductive film 62 can be partially raised at a location close to the heat-generating point during a MOSFET short circuit (near the bottom surface of the gate trench 7). This further delays the temperature rise of the second metal film 32b during a MOSFET short circuit, making the second metal film 32b less likely to melt, and thus further improves the short-circuit withstand capability of the MOSFET.

[0095] The method for manufacturing the silicon carbide semiconductor device 60 according to Embodiment 2 is as follows: In the method for manufacturing the silicon carbide semiconductor device 10 according to Embodiment 1, after forming the first metal film 32a of the conductive film 62 along the inner wall of the Schottky trench 31, and before embedding the second metal film 32b (aluminum film) of the conductive film 62 into the Schottky trench 31 by reflow sputtering, the third metal film 32c (tungsten film) of the conductive film 62 is formed along the entire surface of the first metal film 32a by CVD, or embedded on the first metal film 32a on the bottom side of the Schottky trench 31.

[0096] The silicon carbide semiconductor device 60 according to Embodiment 2 may be modified by applying the configuration of the first metal film 32a of the trench-type SBD 30 shown in Figures 3 and 4. The first metal film 32a of the trench-type SBD 61 may be provided only on a part of the inner wall of the Schottky trench 31 (see Figure 3), or the thickness of the first metal film 32a of the trench-type SBD 61 may be made thicker at the bottom of the Schottky trench 31 than at the side wall (see Figure 4). When the first metal film 32a of the trench-type SBD 61 is provided only on a part of the inner wall of the Schottky trench 31 (see Figure 3), the third metal film 32c of the conductive film 62 may be in contact with the silicon carbide portion.

[0097] As described above, according to Embodiment 2, effects based on the physical properties (thermal properties, electrical properties) of three different first to third metal films (titanium film or nickel film, aluminum film, and tungsten film) that constitute the conductive film embedded in the Schottky trench of the trench-type SBD can be obtained. This makes it possible to obtain all the effects obtained in Embodiment 1 (suppression of forward characteristic degradation of parasitic diodes of the MOSFET, improvement of short-circuit withstand capability of the MOSFET, and reduction of resistance of the trench-type SBD 30).

[0098] In summary, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the invention. For example, in each of the embodiments described above, the dimensions and impurity concentrations of various parts within the semiconductor substrate can be set in various ways according to the required specifications. Furthermore, the present invention is applicable to semiconductor devices equipped with a trench-type SBD on the same semiconductor substrate as the MOSFET, and other elements and circuits may be provided on the semiconductor substrate. [Industrial applicability]

[0099] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices, power supply devices for various industrial machines, and the like. [Explanation of Symbols]

[0100] 1 n + Type drain region 2 n - Type drift region 3 n-type current diffusion region 4 p-type base region 5 n + Type source area 6 p ++ Type Contact Area 7 Gate Trench 8 gate insulating film 9. Postal Service 10,60 Silicon Carbide Semiconductor Devices 11 Interlayer insulating film 11a Contact Hole 12 Source electrodes 13 p + type area 14 Drain electrode 21 Nickel silicide film 22 Titanium nitride film 23 Titanium film 24 Aluminum film 30,61 Trench-type SBD 31. Schottky trench with trench-type SBD 32,62 Conductive film of trench-type SBD 32a A first metal film provided along the side wall of the Schottky trench, constituting the conductive film of the trench-type SBD. 32b,32c Second and third metal films located closer to the center of the Schottky trench than the first metal film, constituting the conductive film of the trench-type SBD. 33. Junction surface between the conductive film of the trench-type SBD and the n-type current diffusion region of the MOSFET 40 Semiconductor substrates 41 n + Mold starting substrate 42 n - mold silicon carbide layer 43 p-type silicon carbide layer 51 Active area 52 Edge Termination Region I1 Reverse recovery current of trench-type SBD t1 Thickness of the side wall portion of the Schottky trench of the first metal film in a trench-type SBD t2 Thickness of the bottom portion of the Schottky trench of the first metal film in a trench-type SBD w Schottky wrench width dn - Thickness of the silicon carbide layer X First direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z-direction (depth)

Claims

1. A semiconductor substrate made of silicon carbide, A first semiconductor region of a first conductivity type provided inside the semiconductor substrate, A second semiconductor region of a second conductivity type is provided between the front surface of the semiconductor substrate and the first semiconductor region, A third semiconductor region of a first conductivity type is selectively provided between the front surface of the semiconductor substrate and the second semiconductor region, A plurality of trenches extending from the front surface of the semiconductor substrate, beyond the third and second semiconductor regions, to the first semiconductor region, The first trench, which is one of the trenches among the plurality of trenches, has a gate electrode provided inside via a gate insulating film. Of the plurality of trenches, the second trench, which is different from the first trench, has a conductive film embedded inside it, which is made by laminating a plurality of metal films of different materials. A first electrode electrically connected to the second semiconductor region, the third semiconductor region, and the conductive film, A second electrode provided on the back surface of the semiconductor substrate, A Schottky barrier diode that utilizes the rectification properties of a Schottky barrier formed at the junction surface between the conductive film and the first semiconductor region, Equipped with, The conductive film is A first metal film is provided along the inner wall of the second trench and makes Schottky contact with the first semiconductor region at the inner wall of the second trench, It comprises a second metal film having a lower electrical resistivity than the first metal film, which is provided on the central side of the second trench than the first metal film, The first metal film is a nickel film. A silicon carbide semiconductor device characterized in that the second metal film is a tungsten film.

2. A semiconductor substrate made of silicon carbide, A first semiconductor region of a first conductivity type provided inside the semiconductor substrate, A second semiconductor region of a second conductivity type is provided between the front surface of the semiconductor substrate and the first semiconductor region, A third semiconductor region of a first conductivity type is selectively provided between the front surface of the semiconductor substrate and the second semiconductor region, A plurality of trenches extending from the front surface of the semiconductor substrate, beyond the third and second semiconductor regions, to the first semiconductor region, The first trench, which is one of the trenches among the plurality of trenches, has a gate electrode provided inside via a gate insulating film. Of the plurality of trenches, the second trench, which is different from the first trench, has a conductive film embedded inside it, which is made by laminating a plurality of metal films of different materials. A first electrode electrically connected to the second semiconductor region, the third semiconductor region, and the conductive film, A second electrode provided on the back surface of the semiconductor substrate, A Schottky barrier diode that utilizes the rectification properties of a Schottky barrier formed at the junction surface between the conductive film and the first semiconductor region, Equipped with, The conductive film is A first metal film is provided along the inner wall of the second trench and makes Schottky contact with the first semiconductor region at the inner wall of the second trench, A second metal film having lower electrical resistivity than the first metal film is provided on the central side of the second trench than the first metal film, It has a third metal film that is provided on the central side of the second trench than the first metal film and has a higher melting point than the second metal film, The silicon carbide semiconductor device is characterized in that the third metal film is a tungsten film.

3. The third metal film is embedded on the bottom surface side of the second trench, closer to the central part of the second trench than the first metal film, The silicon carbide semiconductor device according to claim 2, characterized in that the second metal film is embedded closer to the center of the second trench than the first metal film and closer to the first electrode than the third metal film.

4. The first metal film is a titanium film or a nickel film. The silicon carbide semiconductor device according to claim 2 or 3, characterized in that the second metal film is an aluminum film.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that the first metal film is provided only on the first semiconductor region on the inner wall of the second trench.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5, characterized in that the thickness of the first metal film is greater than the thickness of the side wall portion of the second trench at the bottom surface portion of the second trench.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that the thickness of the first metal film is 100 nm or more and 200 nm or less.

8. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 7, The process includes a deposition step of depositing a plurality of the metal films inside the second trench to form the conductive film, A method for manufacturing a silicon carbide semiconductor device, characterized in that, in the deposition step, a tungsten film among the plurality of metal films of the conductive film is formed by chemical vapor deposition.

9. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 7, The process includes a deposition step of depositing a plurality of the metal films inside the second trench to form the conductive film, A method for manufacturing a silicon carbide semiconductor device, characterized in that, in the deposition step, an aluminum film among the plurality of metal films of the conductive film is formed by a reflow sputtering method.

Images