Inrush current suppression circuit

Abstract

To provide a rush current suppression circuit capable of suppressing a rush current, and suppressing influence on a circuit characteristic.SOLUTION: A rush current suppression circuit comprises a normally-on transistor, a normally-off transistor serially connected with the normally-on transistor, a first drive circuit driving the normally-on transistor, a second drive circuit driving the normally-off transistor, a diode connected between an output of the first drive circuit and an output terminal of the normally-off transistor, a first power supply smoothing circuit smoothing a power supply current supplied to the first drive circuit and the second drive circuit, and a switching circuit switching between connection and disconnection of a current path via the first power supply smoothing circuit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to an inrush current suppression circuit.

Background Art

[0002] Conventionally, as one of the switching elements in a power conversion circuit, a configuration in which a GaN-N channel MOS transistor and a P channel LDMOS transistor are connected in series is known.

[0003] In the above configuration, after applying the voltage of the main circuit power supply, until the isolation power supply serving as a power supply such as a gate driver or UVLO is activated, the standby power of the circuit necessary to maintain the off state of the GaN-N channel MOS transistor and the off state of the P channel LDMOS transistor had to be obtained from the main circuit power supply.

[0004] Therefore, it is inevitably charged through the GaN-N channel MOS transistor, and a current flows through the diode connected between the gate of the GaN-N channel MOS transistor and the drain of the P channel LDMOS transistor. Depending on this current value, a diode with a large rated value has to be selected, which has affected circuit characteristics such as an increase in the terminal capacitance.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] Therefore, in the technology described in Patent Document 1, a transistor switch is provided at the node where the GaN-N channel MOS transistor and the P channel LDMOS transistor are wired to an isolated power supply. When the main circuit power supply is started, the switch is in the off state to block the current path, and after the isolated power supply is started, it is in the on state so as not to affect switching. However, if the transistor switch is turned off when the main circuit power supply is started, the current path is completely cut off. As a result, the standby power required to maintain the off state of the GaN-N channel MOS transistor and the P channel LDMOS transistor cannot be obtained, and the GaN-N channel MOS transistor and the P channel LDMOS transistor may turn on. Therefore, the P-channel LDMOS transistor was configured to have a resistor loaded between the gate and source to suppress the P-channel LDMOS transistor from turning on. However, depending on the resistance value of the resistor, there was a risk that it might affect the circuit characteristics or fail to prevent the P-channel LDMOS transistor from turning on.

[0007] The present invention has been made in view of the above, and aims to provide an inrush current suppression circuit that can suppress inrush current and suppress its influence on circuit characteristics. [Means for solving the problem]

[0008] The inrush current suppression circuit of the embodiment includes a normally-on transistor, a normally-off transistor connected in series with the normally-on transistor, a first drive circuit for driving the normally-on transistor, a second drive circuit for driving the normally-off transistor, a diode connected between the output of the first drive circuit and the output terminal of the normally-off transistor, and a first power supply smoothing circuit for smoothing the power supply current supplied to the first drive circuit and the second drive circuit. A switch circuit that switches between connecting and disconnecting the current path passing through the first power supply smoothing circuit, It is equipped with. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a schematic diagram illustrating the configuration of the power conversion circuit of the first embodiment. [Figure 2] Figure 2 is an explanatory diagram of an example of a conventional circuit configuration. [Figure 3] Figure 3 is an explanatory diagram of the operation of the first embodiment. [Figure 4] Figure 4 is an explanatory diagram of the switching timing of the switch circuit. [Figure 5] Figure 5 is an explanatory diagram of a modified example of the first embodiment. [Figure 6] Figure 6 is an explanatory diagram of a second modified example of the first embodiment. [Figure 7] Figure 7 is a schematic diagram of the power conversion circuit of the second embodiment. [Figure 8] Figure 8 is an explanatory diagram of the main components of the power conversion circuit of the second embodiment. [Figure 9] Figure 9 is an explanatory diagram of a second modified example of the second embodiment. [Modes for carrying out the invention]

[0010] Next, the embodiments will be described in detail with reference to the drawings. First, let me explain the purpose of this embodiment. In a power conversion circuit, as one of the switching elements, in a configuration where a GaN-N channel MOS transistor and a P channel LDMOS transistor are connected in series, the standby power required to maintain the off state of the GaN-N channel MOS transistor and the P channel LDMOS transistor from the time the voltage of the main circuit power supply is applied until the isolated power supply that powers the gate driver and UVLO starts up can only be obtained from the main circuit power supply.

[0011] Therefore, it is inevitable to capacitively charge through the GaN-N channel MOS transistor, and a current will flow through the diode connected between the gate of the GaN-N channel MOS transistor and the drain of the P-channel LDMOS transistor. Depending on the value of this current, it is necessary to select a diode with a large rated value, which affects circuit characteristics such as an increase in the inter-terminal capacitance.

[0012] Therefore, in the technology described in Patent Document 1, a transistor switch is provided at the node wired to the isolated power supply between the GaN-N channel MOS transistor and the P-channel LDMOS transistor. When the main circuit power supply is started, the current path is cut off in the off state, and after the isolated power supply is started, it is in the on state so as not to affect switching.

[0013] However, if the transistor switch is in the off state when the main circuit power supply is started, the current path will be completely cut off. For this reason, the standby power of the circuit required to maintain the off state of the GaN-N channel MOS transistor and the off state of the P-channel LDMOS transistor cannot be obtained, and the GaN-N channel MOS transistor and the P-channel LDMOS transistor can be turned on.

[0014] Therefore, a resistor is loaded between the gate and the source of the P-channel LDMOS transistor to suppress the P-channel LDMOS transistor from turning on. However, depending on the resistance value of the resistor, there is a possibility of affecting the circuit characteristics or not being able to suppress the P-channel LDMOS transistor from turning on.

[0015] Therefore, an object of the present embodiment is to provide an inrush current suppression circuit that can suppress the inrush current and suppress the influence on circuit characteristics. The following will be specifically described.

[0016] [1] First Embodiment FIG. 1 is a schematic configuration explanatory diagram of a power conversion circuit according to the first embodiment.

[0017] As shown in FIG. 1, the power conversion circuit 10 according to the first embodiment includes a digital isolator 11, an isolation power supply 12, a GaN transistor 13, a P-channel LDMOS transistor 14, a diode 15, a first gate driver 16, a second gate driver 17, a UVLO (Under Voltage Lock Out) circuit 18, a first capacitor 19, a second capacitor 20, and a switching transistor 21.

[0018] The digital isolator 11 outputs a digital signal to the input terminal of the first gate driver 16 in an insulated state. The GaN transistor 13 is a normally-on transistor. Its drain terminal is connected to the high-potential side power supply VDD1 of the DC power supply, its source terminal is connected to the high-potential side power supply VDD of the isolation power supply 12, and its gate terminal is connected to the output terminal of the first gate driver 16.

[0019] The P-channel LDMOS transistor 14 is a normally-off transistor. Its source terminal is connected to the GaN-N channel MOS transistor, its drain terminal is connected to the low-potential side power supply VSS1 of the DC power supply, and its gate terminal is connected to the output terminal of the second gate driver 17.

[0020] The anode terminal of the diode 15 is connected to the gate terminal of the GaN-N channel MOS transistor, and the cathode terminal is connected to the drain terminal of the P-channel LDMOS transistor 14.

[0021] The input terminal of the first gate driver 16 is connected to the output terminal of the digital isolator 11, the high-potential side power supply terminal is connected to the high-potential side power supply VDD of the isolation power supply 12, and the low-potential side power supply terminal is connected to the low-potential side power supply VSS of the isolation power supply 12.

[0022] Furthermore, the first gate driver 16 has a positive output terminal TOP and a negative output terminal TON, and the positive output terminal TOP and the negative output terminal TON are connected in common to the gate terminal of the GaN transistor 13.

[0023] The second gate driver 17 has an output terminal connected to the gate terminal of the P-channel LDMOS transistor 14, a high-potential power supply terminal connected to the high-potential power supply VDD of the isolated power supply 12, and a low-potential power supply terminal connected to the low-potential power supply VSS of the isolated power supply 12. The UVLO circuit 18 has a low-voltage malfunction prevention function and controls the second gate driver 17 based on the voltage of the isolated power supply 12 (high-potential side power supply VDD, low-potential side power supply VSS).

[0024] One end of the first capacitor 19 is connected to the high-potential side power supply VDD of the isolated power supply 12. The second capacitor 20 has one end connected to the high-potential side power supply VDD of the isolated power supply 12 and the other end connected to the low-potential side power supply VSS of the isolated power supply 12, and its capacitance is set to be smaller than that of the first capacitor 19.

[0025] The switching transistor 21 has its drain terminal connected to the other end of the first capacitor 19, its source terminal connected to the low-potential side power supply VSS of the isolated power supply 12, and its gate terminal connected to the power conversion circuit 10.

[0026] In the above configuration, the first gate driver 16 functions as the first drive circuit and is configured as an IC chip IC2.

[0027] Furthermore, the second gate driver 17 and the UVLO circuit 18 function as a second drive circuit. In this case, the second gate driver 17 and the UVLO circuit 18 are configured together with the diode 15 as an IC chip IC2. Furthermore, the first capacitor 19 functions as the first power supply smoothing circuit.

[0028] Furthermore, the second capacitor 20 functions as a second power supply smoothing circuit. Furthermore, the GaN transistor 13, the P-channel LDMOS transistor 14, and the IC chip (including the diode 15, the second gate driver 17, and the UVLO circuit 18) are mounted on the substrate SB.

[0029] Before describing the operation of the embodiment, we will now explain the problems of the conventional approach. Figure 2 is an explanatory diagram of an example of a conventional circuit configuration. When the main circuit power is turned on, the isolated power supply 12 does not start up immediately. Until the isolated power supply 12 starts up, the first gate driver 16, the second gate driver 17, the UVLO circuit 18, etc., which are operated by the isolated power supply 12, are not supplied with power and are therefore inoperable.

[0030] Therefore, the standby power required to maintain the off state of the GaN transistor 13 and the P-channel LDMOS transistor 14 can only be obtained from the main circuit power supply (high-potential power supply VDD1, low-potential power supply VSS1).

[0031] In other words, current flows through the following path: high-potential power supply VDD1 → drain terminal of GaN transistor 13 → source terminal of GaN transistor 13 → first capacitor 19 → low-potential output terminal OUTN of first gate driver 16 → anode terminal of diode 15 → cathode terminal of diode 15 → low-potential power supply VSS1.

[0032] This results in the GaN transistor 13 charging the first capacitor 19 and generating an instantaneous peak current (inrush current) that flows through the diode 15. Therefore, depending on the current value of this instantaneous peak current, it may be necessary to select a diode 15 with a larger rated value, which could lead to a larger inter-terminal capacitance and potentially affect the circuit characteristics. To avoid this, conventional designs have involved providing a transistor switch at the node where the GaN-N channel MOS transistor and the P channel LDMOS transistor are wired to an isolated power supply, thereby blocking the current path when the main circuit power supply is started, and furthermore, a resistor is loaded between the gate and source of the P channel LDMOS transistor to suppress it from turning on. However, depending on the resistance value of the resistor, while it may be possible to suppress the P channel LDMOS transistor from turning on, there was a risk that it would not be possible to suppress the P channel LDMOS transistor from turning on, such as affecting the circuit characteristics.

[0033] Next, we will describe the general operation of the first embodiment. Figure 3 is an explanatory diagram of the operation of the first embodiment. In this first embodiment, before the main circuit power is turned on, the gate terminal of the switching transistor 21 is set to the "L" level and is in the off state.

[0034] Therefore, the path from the high-potential side power supply VDD1 of the main circuit power supply → drain terminal of GaN transistor 13 → source terminal of GaN transistor 13 → first capacitor 19 → low-potential side output terminal OUTN of the first gate driver 16 → anode terminal of diode 15 → cathode terminal of diode 15 → low-potential side power supply VSS1 of the main circuit power supply is not formed. Simultaneously, the isolated power supply 12 is started up. As a result, once sufficient time has elapsed for the isolated power supply 12 to start up, the gate terminal of the GaN transistor 13 is turned off by setting it to an "L" level via the first gate driver 16 and the second gate driver 17, and the gate terminal of the P-channel LDMOS transistor 14 is turned on by setting it to an "L" level.

[0035] In this case, a current path is formed through the second capacitor 20, which has a much smaller capacitance than the first capacitor 19, and through the VDD-VSS capacitance of the UVLO circuit 18. However, because the capacitance is much smaller than that of the first capacitor 19, a large current will not flow, thus protecting the diode 15 and enabling stable operation. In contrast, the technology described in Patent Document 1 is unstable in operation because the current path is completely blocked.

[0036] Figure 4 is an explanatory diagram of the switching timing of the switch circuit. By the way, the signal to the switch circuit (switching transistor 21) needs to be an ON signal after preventing inrush current. At time t0, when the main circuit power supply (high-potential side power supply VDD1, low-potential side power supply VSS1) is applied, a voltage using the voltage of the main circuit power supply is generated in drivers such as the first gate driver and the second gate driver, and an inrush current flows during the voltage transition period of this main circuit power supply (time t0 to time t1).

[0037] After this voltage transition period (from time t0 to time t1) has elapsed, it is possible to turn on the switching transistor (switch circuit).

[0038] More specifically, the switching transistor (switch circuit) can be turned on during either the period when the voltage of the main circuit power supply is approximately the threshold voltage TR_Vth of the normally-on GaN transistor (specifically, for example, time t21 corresponding to switch switching signal A), or during the period when the voltage VPW of the isolated power supply, which is the power supply voltage for the first and second gate drivers (specifically, for example, time t22 corresponding to switch switching signal B).

[0039] Furthermore, before applying a switching signal to the first gate driver to initiate switching operation, it is necessary to apply an ON signal to the switching transistor (switch circuit) so that it is wired with low impedance.

[0040] In this case, the P-channel LDMOS transistor 14 is kept ON by continuously supplying a "H" level or "L" level DC potential to the second gate driver from the UVLO circuit 18, and the power conversion circuit is operated by applying a switching signal to the first gate driver 16 to turn the GaN transistor 13 ON / OFF.

[0041] Next, the gate terminal of switching transistor 21 is set to the "H" level. As a result, it becomes possible to power on the main circuit without generating an inrush current flowing through the diode 15, and a diode 15 with a rating that allows it to supply sufficient current during normal operation can be used, while suppressing an increase in inter-terminal capacitance and not affecting the circuit characteristics.

[0042] [1.1] First modified example of the first embodiment Figure 5 is an explanatory diagram of a modified example of the first embodiment. In the first embodiment described above, the switching transistor 21 was connected to the first capacitor 19 and the low-potential side power supply VSS of the isolated power supply 12. However, in a modified version of the first embodiment, as shown in Figure 5, the switching transistor 21A is connected to the first capacitor 19 and the high-potential side power supply VDD of the isolated power supply 12.

[0043] As a result, similar to the first embodiment, when the main circuit power is turned on, the path from high-potential power supply VDD1 → drain terminal of GaN transistor 13 → source terminal of GaN transistor 13 → first capacitor 19 → low-potential output terminal OUTN of first gate driver 16 → anode terminal of diode 15 → cathode terminal of diode 15 → low-potential power supply VSS1 is not formed. Once sufficient time has elapsed for the isolated power supply 12 to start up, the gate terminal of GaN transistor 13 and the gate terminal of P-channel LDMOS transistor 14 are turned on via the first gate driver 16 and the second gate driver 17, both at an "L" level.

[0044] Next, the gate terminal of the switching transistor 21A is set to the "L" level. As a result, the main circuit power supply can be turned on without generating an inrush current flowing through the diode 15, and a diode 15 with a rating that allows sufficient current to flow during normal operation can be used as the diode 15, suppressing an increase in inter-terminal capacitance and not affecting the circuit characteristics.

[0045] [1.2] Second modified example of the first embodiment Figure 6 is an explanatory diagram of a second modified example of the first embodiment. In the first embodiment and the first modified example of the first embodiment described above, a switching transistor 21 was provided at one terminal of the first capacitor 19. However, in the second modified example of the first embodiment, one terminal of the first capacitor 19 and the second capacitor 20 are connected in common, and a switching transistor 21 is provided between this connection point and the low-potential side power supply VSS of the isolated power supply 12.

[0046] According to the second modified example of the first embodiment, in addition to the first current path from the high-potential power supply VDD1 → drain terminal of GaN transistor 13 → source terminal of GaN transistor 13 → first capacitor 19 → low-potential output terminal OUTN of the first gate driver 16 → anode terminal of diode 15 → cathode terminal of diode 15 → low-potential power supply VSS1, the second current path from the high-potential power supply VDD1 → drain terminal of GaN transistor 13 → source terminal of GaN transistor 13 → second capacitor 20 → low-potential output terminal OUTN of the first gate driver 16 → anode terminal of diode 15 → cathode terminal of diode 15 → low-potential power supply VSS1 is also interrupted by the switching transistor 21. As a result, no inrush current flows through diode 15, and the inrush current flowing through the second path is also suppressed.

[0047] [1.3] Third Modification of the First Embodiment In the above explanation, the gate terminal of the switching transistor 21 was described as being connected to the power conversion circuit 10. More specifically, it can be connected to a controller (not shown) mounted on IC chip IC1 or IC chip IC2, and control signals can be input to the gate terminal for control. Alternatively, a separate control IC can be installed, and the gate terminals of this control IC's controller can be connected to input control signals for control.

[0048] [2] Second embodiment Figure 7 is a schematic diagram of the power conversion circuit of the second embodiment. In Figure 7, the same reference numerals are used for parts that are the same as those in the first embodiment of Figure 1.

[0049] As shown in Figure 7, the power conversion circuit 10B of the second embodiment includes a digital isolator 11, an isolated power supply 12, a GaN transistor 13, a P-channel LDMOS transistor 14, a diode 15, a first gate driver 16, a second gate driver 17, an UVLO (Under Voltage Lock Out) circuit 18, a first capacitor 19, a second capacitor 20, and a resistor 31.

[0050] The digital isolator 11 outputs the digital signal in an isolated state to the input terminal of the first gate driver 16. The GaN transistor 13 is a normally-on transistor, with its drain terminal connected to the high-potential side power supply VDD1 of the DC power supply, its source terminal connected to the high-potential side power supply VDD of the isolated power supply 12, and its gate terminal connected to the output terminal of the first gate driver 16.

[0051] The P-channel LDMOS transistor 14 is a normally-off transistor, with its source terminal connected to a GaN-N-channel MOS transistor, its drain terminal connected to the low-potential side power supply VSS1 of the DC power supply, and its gate terminal connected to the output terminal of the second gate driver 17.

[0052] Diode 15 has its anode terminal connected to the gate terminal of the GaN-N channel MOS transistor and its cathode terminal connected to the drain terminal of the P channel LDMOS transistor 14.

[0053] The first gate driver 16 has an input terminal connected to the output terminal of the digital isolator 11, a high-potential power supply terminal connected to the high-potential power supply VDD of the isolated power supply 12, and a low-potential power supply terminal connected to the low-potential power supply VSS of the isolated power supply 12.

[0054] Furthermore, the first gate driver 16 has a positive output terminal TOP and a negative output terminal TON, and the positive output terminal TOP and the negative output terminal TON are connected in common to the gate terminal of the GaN transistor 13.

[0055] The second gate driver 17 has an output terminal connected to the gate terminal of the P-channel LDMOS transistor 14, a high-potential power supply terminal connected to the high-potential power supply VDD of the isolated power supply 12, and a low-potential power supply terminal connected to the low-potential power supply VSS of the isolated power supply 12. The UVLO circuit 18 has a low-voltage malfunction prevention function and controls the second gate driver 17 based on the voltage of the isolated power supply 12 (high-potential side power supply VDD, low-potential side power supply VSS).

[0056] One end of the first capacitor 19 is connected to the high-potential side power supply VDD of the isolated power supply 12. The second capacitor 20 has one end connected to the high-potential side power supply VDD of the isolated power supply 12 and the other end connected to the low-potential side power supply VSS of the isolated power supply 12, and its capacitance is set to be smaller than that of the first capacitor 19.

[0057] Resistor 31 has one end connected to the other end of the first capacitor 19, and the other end connected to the high-potential side power supply VDD of the isolated power supply 12. In this case, the resistance value of resistor 31 is set to the lowest possible value that can suppress the inrush current.

[0058] Figure 8 is an explanatory diagram of the main components of the power conversion circuit of the second embodiment. As a result, when the main circuit power is turned on, as shown by the arrow in Figure 8, current flows through the current path from the high-potential side power supply VDD1 → the drain terminal of the GaN transistor 13 → the source terminal of the GaN transistor 13 → the resistor 31 → the first capacitor 19 → the low-potential side output terminal OUTN of the first gate driver 16 → the anode terminal of the diode 15 → the cathode terminal of the diode 15 → the low-potential side power supply VSS1, and it becomes possible to suppress the current flowing through this current path, i.e., the inrush current.

[0059] As a result, in this second embodiment as well, it is possible to suppress inrush current and reduce the impact on circuit characteristics.

[0060] [2.1] First modified example of the second embodiment In the second embodiment described above, the resistor 31 was connected between the first capacitor 19 and the high-potential side power supply VDD of the isolated power supply 12. However, the resistor 31 can be configured to be connected between the first capacitor 19 and the low-potential side power supply VSS of the isolated power supply 12.

[0061] As a result, when the main circuit power is turned on, the current that flows through the current path from the high-potential power supply VDD1 → the drain terminal of the GaN transistor 13 → the source terminal of the GaN transistor 13 → the first capacitor 19 → the resistor 31 → the low-potential output terminal OUTN of the first gate driver 16 → the anode terminal of the diode 15 → the cathode terminal of the diode 15 → the low-potential power supply VSS1 can be suppressed, and the inrush current that flows through this current path can be suppressed.

[0062] As a result, in the first modified example of this second embodiment, it is possible to suppress inrush current and reduce the impact on circuit characteristics.

[0063] [2.2] Second Modification of the Second Embodiment In the second embodiment and the first modified example of the second embodiment described above, the resistor 31 remains connected not only when the power is turned on, but also during normal operation.

[0064] Therefore, in order to suppress the impact on circuit characteristics, the range of selection is limited, and consequently, the effect of suppressing inrush current is also limited. Therefore, in this second modified example, a configuration is adopted in which a switching transistor 32 is provided in parallel with the resistor 31.

[0065] Figure 9 is an explanatory diagram of a second modified example of the second embodiment. As shown in Figure 9, the power conversion circuit 10B of the second embodiment includes a GaN transistor 13, a P-channel LDMOS transistor 14, a diode 15, a first gate driver 16, a second gate driver 17, a first capacitor 19, a second capacitor 20, a resistor 31, and a switching transistor 32.

[0066] Here, the switching transistor 32 is connected in parallel with the resistor 31, as shown in Figure 9. In the second modified example of this second embodiment, before the main circuit power is turned on, the gate terminal of the switching transistor 32 is set to the "L" level and is in the off state.

[0067] As a result, similar to the second embodiment, when the main circuit power is turned on, if current flows through the path from the high-potential power supply VDD1 → the drain terminal of the GaN transistor 13 → the source terminal of the GaN transistor 13 → the first capacitor 19 → the resistor 31 → the low-potential output terminal OUTN of the first gate driver 16 → the anode terminal of the diode 15 → the cathode terminal of the diode 15 → the low-potential power supply VSS1, it becomes possible to suppress the current flowing through this current path, i.e., the inrush current.

[0068] On the other hand, the path from high-potential power supply VDD1 → drain terminal of GaN transistor 13 → source terminal of GaN transistor 13 → first capacitor 19 → switching transistor 32 → low-potential output terminal OUTN of first gate driver 16 → anode terminal of diode 15 → cathode terminal of diode 15 → low-potential power supply VSS1 is not formed.

[0069] Therefore, once sufficient time has elapsed for the isolated power supply 12 to complete startup, the gate terminal of the GaN transistor 13 and the gate terminal of the P-channel LDMOS transistor 14 are turned ON by setting them to an "L" level via the first gate driver 16 and the second gate driver 17.

[0070] In parallel with this, the gate terminal of the switching transistor 32 is set to the "H" level. In this case, the on-resistance of the switching transistor 32 is sufficiently small compared to the resistance of resistor 31, so that current effectively flows only through the switching transistor 32.

[0071] Therefore, when the main circuit power is turned on, the resistor 31 prevents an inrush current from flowing through the diode 15, similar to the second embodiment, making it possible to turn on the main circuit power. Furthermore, when the first gate driver 16 and the second gate driver 17 are supplied with power from an isolated power supply, the switching transistor 32, which has a very low resistance, forms the current path, and therefore does not affect the circuit characteristics.

[0072] The above explanation describes the case where resistor 31 is provided between the first capacitor 19 and the low-potential side power supply VSS of the isolated power supply 12. However, similar effects can be obtained even if resistor 31 is provided between the first capacitor 19 and the high-potential side power supply VDD of the isolated power supply 12, or even if a switching transistor 32 is provided in parallel with resistor 31.

[0073] In the description of the second embodiment above, the case where a resistor is used as the current limiting unit was described, but it is also possible to use an inductor (for example, a coil) instead of a resistor.

[0074] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0075] In the above explanation, we described the case in which a switching transistor 32 (switching element) and a resistor 31 connected in parallel with the switching transistor 32 (switching element) are provided between the capacitor 19 (first power supply smoothing circuit) and the low-potential side power supply VSS (see Figure 9). However, it is also possible to configure the circuit to include a switching transistor (switching element: for example, a P-channel MOS transistor) provided between the capacitor 19 (first power supply smoothing circuit) and the high-potential side power supply VDD, and a resistive element connected in parallel with the switching transistor (switching element). Furthermore, it is also possible to configure the terminals on the low-potential power supply side of capacitor 19 (first power supply smoothing circuit) and the terminals on the low-potential side of capacitor 20 (second power supply smoothing circuit) to be commonly connected on the high-potential side of the switching element. [Explanation of symbols]

[0076] 10, 10A1, 10A2, 10B Power Conversion Circuit 11 Digital Isolators 12 Isolated power supply 13. GaN transistor (normally-on transistor) 14 P-channel LDMOS transistor (normally off transistor) 15 diodes 16. First gate driver (first drive circuit) 17. Second gate driver (second drive circuit) 18 UVLO circuit 19. First capacitor (first power supply smoothing circuit) 20. Second capacitor (second power supply smoothing circuit) 21 Switching Transistors 31. Resistor (current limiting section) 32 Switching transistor (current limiting section) OUTN Low-voltage output terminal TON Negative output terminal TOP (positive output terminal) TR threshold voltage VSS1 Low potential side power supply VDD1 High potential side power supply VDD High potential side power supply VSS Low potential side power supply

Claims

1. Normally-on transistors and A normally-on transistor connected in series with the normally-off transistor, A first drive circuit that drives the normally-on transistor, A second drive circuit that drives the normally-off transistor, A diode connected between the output of the first drive circuit and the output terminal of the normally-off transistor, A first power supply smoothing circuit that smooths the power supply current supplied to the first drive circuit and the second drive circuit, A switch circuit that switches between connecting and disconnecting the current path passing through the first power supply smoothing circuit, A second power supply smoothing circuit having a smaller capacitance than the first power supply smoothing circuit is connected in parallel to the first power supply smoothing circuit, An inrush current suppression circuit equipped with this feature.

2. The switch circuit is connected to either the high-potential side or the low-potential side of the first power supply smoothing circuit. The inrush current suppression circuit according to claim 1.

3. The terminal on the high-potential power supply side of the first power supply smoothing circuit and the terminal on the high-potential side of the second power supply smoothing circuit are commonly connected on the low-potential side of the switch circuit. The inrush current suppression circuit according to claim 1.

4. The current path includes the first drive circuit and the diode, The inrush current suppression circuit according to claim 1.

Images