System and method for automatically identifying defect-based test coverage gaps in semiconductor devices

Abstract

Automatically identifying defect-based test coverage gaps in semiconductor devices includes determining a plurality of apparent killer defects on one or more semiconductor devices having a plurality of semiconductor dies based on characteristic measurements of the one or more semiconductor devices acquired by one or more semiconductor manufacturing subsystems, and determining at least one semiconductor die that passes at least one test based on test measurements acquired by one or more test tool subsystems. Correlating the characteristic measurements with test measurements to determine the at least one apparent killer defect on the at least one semiconductor die that passes the at least one test, and determining one or more gap areas on the one or more semiconductor devices for defect-based test coverage based on the at least one apparent killer defect on the at least one semiconductor die that passes the at least one test.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more particularly, to systems and methods for automatically identifying defect-based test coverage gaps in semiconductor devices.

Background Art

[0002] Reference to Related Applications This application claims priority to Indian Provisional Application No. 202041055201 (filed on December 18, 2020) and U.S. Provisional Application No. 63 / 144,997 (filed on February 3, 2021), both of which are hereby incorporated by reference in their entirety.

[0003] The manufacture of semiconductor devices typically requires tens of thousands of processing steps to form a functioning device. During these processing steps, various inspections and / or measurement measurements can be performed to identify defects and / or monitor various parameters on the device. Electrical tests may also be performed to verify or evaluate the functionality of the device. However, some detected defects and measurement errors may not be severe enough to clearly indicate a device failure, while smaller variations can cause early reliability failures of the device after exposure to their operating environment. Users exposed to the risks of semiconductor devices in automotive, military, aerospace, and medical applications are starting to look for failure rates in the parts per billion (PPB) range that exceed the current parts per million (PPM) levels. The recognition and control of reliability defects are important in meeting the requirements of these industries as the need for semiconductor devices in automotive, military, aerospace, and medical applications continues to increase.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] Therefore, it may be desirable to provide systems and methods for detecting reliability defects. [Means for solving the problem]

[0006] A system according to one or more embodiments of the present disclosure is disclosed. In one exemplary embodiment, the system includes a controller communicatively coupled to one or more semiconductor manufacturing subsystems and one or more test tool subsystems. In another exemplary embodiment, the controller includes one or more processors configured to execute program instructions causing one or more processors to determine a plurality of apparent killer defects on one or more semiconductor devices based on characteristic measurements of one or more semiconductor devices acquired by one or more semiconductor manufacturing subsystems via a characterization subsystem. In another exemplary embodiment, the one or more semiconductor devices include a plurality of semiconductor dies. In another exemplary embodiment, the controller includes one or more processors configured to execute program instructions causing one or more processors to determine, via a test subsystem, at least one of a plurality of semiconductor dies that passes at least one of a plurality of tests based on test measurements acquired by one or more test tool subsystems. In another exemplary embodiment, the controller includes one or more processors configured to execute program instructions causing one or more processors to correlate characteristic measurements with test measurements in order to determine at least one apparent killer defect on at least one of a plurality of semiconductor dies that passes at least one of a plurality of tests. In another exemplary embodiment, the controller includes one or more processors configured to execute program instructions that cause one or more processors to determine via a location subsystem. One or more gap areas on one or more semiconductor devices for defect-based test coverage based on at least one obvious killer defect on at least one semiconductor die of a plurality of semiconductor dies pass at least one of a plurality of tests.

[0007] Methods according to one or more embodiments of the present disclosure are disclosed. In one exemplary embodiment, the method includes, but is not limited to, determining a plurality of apparent killer defects on one or more semiconductor devices based on characteristic measurements of one or more semiconductor devices obtained by one or more semiconductor manufacturing subsystems via a controller's characterization subsystem. In another exemplary embodiment, the one or more semiconductor devices include a plurality of semiconductor dies. In another exemplary embodiment, the method may include, but is not limited to, determining at least one of a plurality of semiconductor dies that passes at least one of a plurality of tests based on test measurements obtained by one or more test tool subsystems via a controller's test subsystem. In another exemplary embodiment, the method may include, but is not limited to, correlating characteristic measurements with test measurements via a controller's correlation subsystem to determine at least one apparent killer defect among a plurality of apparent killer defects on at least one of a plurality of semiconductor dies. In another exemplary embodiment, the method may include, but is not limited, determining one or more gap areas on one or more semiconductor devices for defect-based test coverage based on at least one obvious killer defect on at least one semiconductor die among a plurality of semiconductor dies that pass at least one of a plurality of tests, via a controller location subsystem.

[0008] A system according to one or more embodiments of the present disclosure is disclosed. In one exemplary embodiment, the system includes one or more semiconductor manufacturing subsystems. In another exemplary embodiment, the system includes one or more test tool subsystems. In another exemplary embodiment, the system includes a controller communicatively coupled to one or more semiconductor manufacturing subsystems and one or more test tool subsystems. In another exemplary embodiment, the controller includes one or more processors configured to execute program instructions causing one or more processors to determine, via a characterization subsystem, a plurality of apparent killer defects on one or more semiconductor devices based on characterization measurements of one or more semiconductor devices obtained by one or more semiconductor manufacturing subsystems. In another exemplary embodiment, one or more semiconductor devices include a plurality of semiconductor dies. In another exemplary embodiment, the controller includes one or more processors configured to execute program instructions causing one or more processors to determine, via a test subsystem, at least one of a plurality of semiconductor dies that passes at least one of a plurality of tests based on test measurements obtained by one or more test tool subsystems. In another exemplary embodiment, the controller includes one or more processors configured to execute program instructions via a correlation subsystem to cause one or more processors to correlate characteristic measurements with test measurements in order to determine at least one apparent killer defect among a plurality of apparent killer defects that pass at least one of a plurality of tests on at least one semiconductor die among a plurality of semiconductor dies. In another exemplary embodiment, the controller includes one or more processors configured to execute program instructions via a location subsystem to cause one or more processors to determine one or more gap areas on one or more semiconductor devices for defect-based test coverage based on at least one apparent killer defect on at least one semiconductor die among a plurality of semiconductor dies that pass at least one of a plurality of tests.

[0009] It should be understood that both the above summary and the following detailed description are illustrative and descriptive only and do not necessarily limit the claimed invention. The accompanying drawings incorporated into and constituting part of the specification illustrate embodiments of the invention and, together with the general description, help to illustrate the principles of the invention.

[0010] Many of the advantages of this disclosure can be better understood by those skilled in the art by referring to the accompanying drawings: [Brief explanation of the drawing]

[0011] [Figure 1] This flowchart illustrates steps performed in a method or process for automatically identifying defect-based test coverage gaps in semiconductor devices, according to one or more embodiments of the present disclosure. [Figure 2] This is a block diagram of a system for automatically identifying defect-based test coverage gaps in semiconductor devices, according to one or more embodiments of the present disclosure. [Figure 3A] This is a conceptual diagram of a killer defect in a semiconductor die that passes a test, according to one or more embodiments of the present disclosure. [Figure 3B] This is a conceptual diagram of a killer defect in a semiconductor die that passes a test, according to one or more embodiments of the present disclosure. [Figure 3C] This is a conceptual diagram of a killer defect in a semiconductor die that passes a test, according to one or more embodiments of the present disclosure. [Figure 3D] This is a conceptual diagram of a killer defect in a semiconductor die that passes a test, according to one or more embodiments of the present disclosure. [Figure 4A] This is a conceptual diagram of a semiconductor die layout according to one or more embodiments of the present disclosure. [Figure 4B] This is a conceptual diagram of a semiconductor die layout with superimposed killer defects according to one or more embodiments of the present disclosure. [Figure 4C]Conceptual diagram of a semiconductor die layout with killer defects overlapping potential defect-based test coverage gap areas according to one or more embodiments of the present disclosure. [Figure 5A] Chart illustrating the tendency of test coverage gaps over time according to one or more embodiments of the present disclosure. [Figure 5B] Chart showing the tendency of test coverage gaps for each product according to one or more embodiments of the present disclosure. [Figure 6] Flow diagram showing steps executed in a method or process for manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 7A] Block diagram of a system for manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 7B] Block diagram of a system for manufacturing a semiconductor device according to one or more embodiments of the present disclosure.

Embodiments for Carrying Out the Invention

[0012] Here, reference is made in detail to the disclosed subject matter shown in the accompanying drawings. The present disclosure has been specifically shown and described with respect to specific embodiments and their specific features. The embodiments described herein are to be construed as illustrative rather than limiting. It should be readily apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the present disclosure.

[0013] Defects occurring during the manufacturing process can have a wide - ranging impact on the performance of devices in the art. For example, "killer" defects can lead to immediate device failure. As another example, minor defects may have little or no impact on the performance of a device throughout its lifespan. As another example, a class of defects known as latent reliability defects (LRDs) may not lead to failures during manufacturing / testing or immediate device failure during operation, but may lead to early - life failures of the operating device when used in the field. Note that, in this specification, the terms "manufacturing process" and "manufacturing process" can be considered equivalent for the purposes of this disclosure, along with each respective variation of the term (such as "manufacturing line" and "manufacturing line", etc.).

[0014] Killer defects can occur at known or unknown locations within the design. Unknown locations are particularly problematic when there is susceptibility to reliability escapes from killer defects in the test gap. Developments related to the implementation of Inline Defect Part Average Testing (I - PAT) indicate that a relatively large percentage of reliability escapes may be due to obvious killer defects in the test coverage gap. In the case of a reliability escape, a semiconductor device may die functionally after processing, but the device manufacturer may not be able to make this determination due to limitations in testing. Examples of implementing 1 - PAT can be found in U.S. Patent 10,761,128 (September 1, 2020) and U.S. Patent Application 17 / 101,856 (November 23, 2020), which are each incorporated herein by reference in their entirety.

[0015] Test coverage gaps can arise from one of several sources. For example, a test coverage gap may arise in areas of semiconductor devices that are untestable due to the device's logical layout. Another example is a test coverage gap in areas of semiconductor devices (e.g., analog circuits) that are simply too difficult to measure comprehensively due to fault identification that is not merely a matter of correct on / off states. Yet another example is a test coverage gap in areas of semiconductor devices that are not tested due to cost considerations associated with the increased cost of testing that involves test coverage.

[0016] Older methods or processes for identifying high-risk areas for test coverage escapes on semiconductor devices can generally enable semiconductor manufacturers to achieve baseline reliability defect control at the parts per million (PPM) level, depending on the complexity and size of the chip. However, selected semiconductor manufacturers (e.g., automotive, military, aerospace, and medical semiconductor manufacturers) are actively pursuing new and innovative methods to identify the root causes of reliability failures and achieve parts per million (PPB) level baseline reliability defect control.

[0017] For example, older methods or processes include prediction methods such as test simulation software packages. However, prediction methods have varying degrees of effectiveness and are highly equipment-dependent. For instance, analog devices are far more difficult to predict than digital devices. In addition, certain areas of circuit layout are often considered "untestable," regardless of how much test time is allocated. Furthermore, prediction methods, by their very nature, cannot identify unexpected areas of test coverage gaps.

[0018] As another example, older methods or processes also involve tribal knowledge based on past semiconductor devices. This tribal knowledge based on past devices generally provides a good starting point for device manufacturers to design appropriate test strategies. However, it is neither comprehensive nor quantitative.

[0019] As another example, older methods or processes also include physical failure analysis (PFA) from stress tests or field reliability returns. For example, an automotive semiconductor manufacturer may be required to perform PFA on stress-tested dies or field reliability returns. The latter could be returns from Tier 1 component suppliers, assemblies at automotive OEMs, or guarantee field returns from end consumers. While a necessary task, PFA does not provide sufficient information to create a comprehensive picture of the device's test coverage gap. For example, the PPM number of failures is so small that it is difficult to gain a comprehensive understanding of baseline reliability Pareto from readily available field returns, and as a result, semiconductor manufacturers may only see a few pieces of the puzzle, potentially lacking statistical significance. As another example, field returns generally provide information that reflects the semiconductor manufacturer's reliability issues at the time the failed device was manufactured, but this may be from the past few years and no longer relevant to current designs. As yet another example, physical failure analysis is expensive, time-consuming, and often uncertain or inaccurate. As another example, the root cause of reliability failures is often destruction due to the activation of defects or incidental damage from PFA delay processes.

[0020] Embodiments of this disclosure relate to systems and methods for automatically identifying defect-based test coverage gaps in semiconductor devices. In particular, embodiments of this disclosure relate to enabling the automatic identification of previously unknown locations in a design that are highly sensitive to reliability and escape killer defects within the test gap. In addition, embodiments of this disclosure relate to using empirical defect data to systematically identify test coverage gaps. Furthermore, embodiments of this disclosure relate to providing new metrics for quantifying the risk of reliability avoidance on a per-device or over time as improvements are made. Furthermore, embodiments of this disclosure relate to demonstrating continuous improvement, evaluating the effectiveness of test program changes, and providing new metrics and / or charts for quantifying test gap differences between different devices in a product portfolio on a per-device or over time as improvements are made.

[0021] Figure 1 shows a method or process 100 for automatically identifying defect-based test coverage gaps in semiconductor devices, according to one or more embodiments of the present disclosure. Figure 2 shows a block diagram of a system 200 for automatically identifying defect-based test coverage gaps in semiconductor devices, according to one or more embodiments of the present disclosure. It should be noted herein that the steps of the method or process 100 may be implemented in whole or in part by the system 200 shown in Figure 2. However, it should be further recognized that the method or process 100 is not limited to the system 200 shown in Figure 2, in that additional or alternative system-level embodiments may perform all or part of the steps of the method or process 100.

[0022] In step 102, characterization measurements of one or more semiconductor devices are received. In some embodiments, system 200 receives information output by one or more semiconductor manufacturing subsystems 202. Characterization measurements can be performed during the manufacturing of one or more semiconductor devices. For example, one or more semiconductor manufacturing subsystems 202 may include, but are not limited to, one or more process tools configured to manufacture a semiconductor device comprising 1, 2, ... N layers manufactured according to several (e.g., tens of thousands) steps performed by several manufacturing processes. As another example, one or more semiconductor manufacturing subsystems 202 may include, but are not limited to, one or more inline defect inspection and / or measurement tools configured to evaluate the characterization of a semiconductor device. For example, one or more outputs may include, but are not limited to, baseline inspection (e.g., sampling-based inspection), screening inspection on key semiconductor device layers, etc. For the purposes of this disclosure, “characterization measurement” may mean either inline defect inspection or inline measurement measurement.

[0023] In step 104, one or more obvious killer defects on one or more semiconductor devices are determined based on specific measurements of one or more semiconductor devices. In some embodiments, the system 200 includes a characterization subsystem 204 or subsystem A. The characterization subsystem 204 can receive information output by one or more semiconductor manufacturing subsystems 202 that are generated following the characterization of the semiconductor devices. The characterization subsystem 204 can determine one or more obvious killer defects from the information by applying one or more processes to the received inline defect data to separate defects that are obvious killer defects from defects that have a low probability of affecting device performance. For example, the characterization subsystem 204 may implement deterministic and / or statistical thresholding techniques. As another example, advanced deep learning or machine learning techniques may be implemented with potentially large datasets and / or potential variability in detectability. Generally, machine learning techniques can be any technique known in the art, including but not limited to supervised learning, unsupervised learning, or other learning-based processes such as linear regression, neural networks or deep neural networks, heuristic-based models, etc. Note that in this specification, semiconductor dies or wafers without obvious killer defects may be flagged for further consideration (e.g., for other types of defects).

[0024] In step 106, test measurements of one or more semiconductor devices are received. In some embodiments, the system 200 receives information output by one or more test tool subsystems 206. Test measurements may be obtained for one or more semiconductor devices. For example, one or more test tool subsystems 206 may include, but are not limited to, one or more electrical test tools, one or more stress test tools, or equivalents. One or more test tool subsystems 206 may be configured to test semiconductor devices manufactured by one or more semiconductor manufacturing processes performed via one or more semiconductor manufacturing subsystems 202. For the purposes of this disclosure, “test” may be understood as a process of electrically evaluating the functionality of a device at the end of a manufacturing process (e.g., an electrical wafer sorting (EWS) process), the end of packaging (e.g., a unit probe process, a class probe process), and / or the end of final testing (e.g., after a burn-in process and other quality check processes). Note herein that non-pass semiconductor dies or wafers may be isolated from pass semiconductor dies or wafers and / or flagged for further testing.

[0025] In step 108, based on test measurements of one or more semiconductor devices, one or more semiconductor dies that pass one or more performed tests are determined. In some embodiments, the system 200 includes a test subsystem 208 or subsystem B. The test subsystem 208 can receive information output by one or more test tool subsystems 206 following the testing of semiconductor devices manufactured by one or more semiconductor manufacturing processes performed via one or more semiconductor manufacturing subsystems 202. The test subsystem 208 can separate semiconductor dies that pass the performed tests from semiconductor dies that do not pass the performed tests (including, but not limited to, probing, electrical testing, stress testing, etc.). For example, semiconductor dies may be assigned bin numbers during manufacturing, and subsystem B may separate semiconductor dies that pass the performed tests from semiconductor dies that do not pass the performed tests based on the bin numbers. For example, only semiconductor dies that pass all performed tests may be accepted by the test subsystem 208. Alternatively, any semiconductor die that passes a selected subset of the tests performed may be accepted by the test subsystem 208, the selected subset being less than the entire set of tests performed. It should be noted herein that non-passing semiconductor dies or wafers may be removed from consideration (e.g., discarded) and / or flagged for further testing.

[0026] In step 110, characterization measurements are correlated with test measurements to determine one or more apparent killer defects on one or more semiconductor dies of one or more semiconductor devices that pass one or more performed tests. In some embodiments, the system 200 includes a correlation subsystem 210 or subsystem C. The correlation subsystem 210 can receive information about apparent killer defects output by the characterization subsystem 204. The correlation subsystem 210 can receive information output by the test subsystem 208 with respect to semiconductor dies that pass a selected subset or all of the performed tests. The correlation subsystem 210 can correlate the information output by the characterization subsystem 204 with the information output by the test subsystem 208 to determine a subpopulation of apparent killer defects present on semiconductor dies that pass a selected subset or all of the performed tests.

[0027] Figures 3A to 3D illustrate conceptual diagrams of killer defects in a semiconductor die that can pass a selected subset or all of the tests performed by one or more test tool subsystems 206 according to one or more embodiments of the present disclosure. In Figure 3A, image 300 illustrates embedded particles 302 in pattern 304. In Figure 3B, image 310 illustrates a short-circuit bridge 312 in pattern 314. In Figure 3C, image 320 illustrates an instance 322 of copper plating underpolishing adjacent to pattern 324. In Figure 3D, image 330 illustrates a surface gap 332 in pattern 334.

[0028] In step 112, one or more gap areas for defect-based test coverage are determined based on one or more apparent killer defects on one or more semiconductor dies of one or more semiconductor devices that have passed one or more performed tests. In some embodiments, the system 200 includes a location subsystem 212 or subsystem D. The location subsystem 212 can receive information output by the correlation subsystem 210 about a subpopulation of apparent killer defects present on semiconductor dies that pass a selected subset or all of the performed tests. Gap areas in defect-based test coverage where the semiconductor die has not been adequately stressed to determine the defects can be determined by the system 200. The location subsystem 212 can analyze the location and frequency of apparent killer defects on semiconductor dies that pass a selected subset or all of the performed tests. For example, the location subsystem 212 can determine the systematic diffusion of one or more instances of gap areas across the semiconductor die in defect-based test coverage.

[0029] In step 114, one or more reports are generated for one or more gap areas in defect-based test coverage on one or more semiconductor devices. In some embodiments, the system 200 includes a results subsystem 214 or subsystem E. The results subsystem 214 can receive information output by the locating subsystem 212 about the location and / or frequency of apparent killer defects in semiconductor dies that pass a selected subset or all of the tests performed. The results subsystem 214 can render the results into a form configured to help semiconductor manufacturers take corrective actions and / or evaluate the effectiveness of test program changes, by creating reports that include one or more metrics and / or one or more charting functions. For example, examples of corrective actions may include, but are not limited to, a temporary reduction of test gaps by inspection screening (e.g., I-PAT) improvements caused by adjusting the test program to provide greater coverage of the determined gap areas in defect-based test coverage.

[0030] Examples of 1-PAT implementations can be found in U.S. Patent 10,761,128 (September 1, 2020) and U.S. Patent Application 17 / 101,856 (November 23, 2020), both of which have been previously incorporated herein in their entirety. The examples provided in the incorporated patents and applications focus on identifying specific dies at high risk for testing cover gaps for product disposal purposes (e.g., “screening”). However, it should be noted that this disclosure is intended to automatically identify systematically hazardous areas of a semiconductor device for the purpose of improving the inherent reliability of all chips in the semiconductor device and / or for direct mitigation efforts, and may not require screening data as input. In this regard, I-PAT may be implemented in this disclosure, but is not required.

[0031] Figures 4A-4C illustrate conceptual diagrams of outputs from the results subsystem 214 according to one or more embodiments of the present disclosure.

[0032] In Figure 4A, Image 400 illustrates one or more functional semiconductor die blocks 402 within a semiconductor die layout 404.

[0033] In Figure 4B, Image 410 illustrates one or more apparent killer defects 412 from all semiconductor dies to be analyzed following a selected subset or all of the tests performed, where one or more apparent killer defects 412 are overlaid on one or more functional semiconductor die blocks 402 within the semiconductor die layout 404. For example, Image 410 could represent apparent killer defects as determined by the characterization subsystem 204.

[0034] In Figure 4C, Image 420 shows one or more obvious killer defects 412 that passed through a selected subset or all of the tests performed within a gap area 422 in defect-based test coverage, where the gap area 422 is superimposed on one or more functional semiconductor die blocks 402 in a semiconductor die layout 404. For example, Image 420 may represent a gap area 422 determined by the correlation subsystem 210.

[0035] It should be noted that the exact layout and / or configuration of images 400, 410, and 420 are provided for illustrative purposes only. For example, the exact layout of the semiconductor die block 402 may differ from that illustrated in Figures 4A–4C. As another example, the graph diagram of the apparent killer defect 412 and / or gap region 422 may differ from that shown in Figures 4B and 4C. Therefore, the above description should not be construed as a limitation on the scope of this disclosure, but merely as an example.

[0036] Figures 5A and 5B show metrics generated in the form of graphical output from the results subsystem 214 to illustrate the improvement of a semiconductor device over time according to one or more embodiments of the present disclosure.

[0037] In Figure 5A, Chart 500 shows a specific tested semiconductor device design separated into pass percentages 502 and fail percentages 504 over a time range, where the fail percentage may represent a potential gap area in defect-based test coverage. For example, the time range may be quarters, months, weeks, days, etc. Mitigation steps are taken to adjust the manufacturing, characterization, and / or testing of the semiconductor device as shown in Figure 5A, so that the trend of test coverage gaps over time (e.g., an increase in the ratio between pass percentages 502 and fail percentages 504) can be improved.

[0038] In Figure 5B, Chart 510 shows several different tested semiconductor device designs (1)-(5) across a product line or portfolio, separated into pass percentages 502 and fail percentages 504 at a specific point in time and / or over a certain time range, where the fail percentages may represent potential gap areas in defect-based test coverage. As shown in Figure 5B, selected semiconductor devices (e.g., devices (2)-(4)) may be separated for use in higher threshold environments (e.g., automobiles requiring failure rates in the parts per billion (PPB) range), while other semiconductor devices (e.g., devices (1) and (5)) may be separated for use in lower threshold environments (e.g., televisions, smartphones, etc., requiring failure rates in the parts per million (PPM) range).

[0039] It should be noted that the exact layout and / or configuration of charts 500 and 510 are provided herein for illustrative purposes only. For example, charts 500 and 510 are more illustrative than bar graphs other than different types of data display devices (e.g., line plots, scatter plots, or other graphs) (as shown in Figure 5(a)). As another example, charts 500 and 510 may provide different information than those shown in Figures 5A and 5B. Therefore, the above description should not be construed as a limitation on the scope of this disclosure, but merely as an example.

[0040] While embodiments of this disclosure show that subsystems 204, 208, 210, 212, and 214 are separate or independent subsystems within system 200, it should be noted that one or more of subsystems 204, 208, 210, 212, and 214 may be combined or integrated subsystems. Therefore, the above description should not be construed as a limitation on the scope of this disclosure, but merely as an example.

[0041] In step 116, one or more adjustments are determined for at least one of the manufacturing, characterization, or testing of a semiconductor device based on one or more gap areas on one or more semiconductor devices for defect-based test coverage. In some embodiments, the system 200 may output information to an external system or subsystem, which includes corrective actions to modify the manufacturing, characterization, and / or testing of the semiconductor device. For example, a set of mitigation steps 216 may include target care areas (e.g., I-PAT care areas) provided in a feedforward loop to an external system or subsystem. For example, the target care areas may include detailed or fine-tuned inspections (e.g., generated via one or more control signals) for inking or scrapping the semiconductor die. As another example, a set of mitigation steps 218 may include modifications to a manufacturing process or method, a characterization process or method, a testing process or method, etc., provided in a feedback loop to an external system or subsystem. For example, a manufacturing process or method, a characterization process or method, a testing process or method, etc., can be adjusted based on the determined gap areas in the defect-based test coverage (e.g., via one or more control signals). It should be noted that, in this specification, either or both sets of mitigation steps 216 and 218 may be performed separately as independent processes, the sets of mitigation steps 216 and 218 may be performed in any order, or the sets of mitigation steps 216 and 218 may be performed simultaneously.

[0042] In some embodiments, system 200, one or more semiconductor manufacturing subsystems 202, and one or more test tool subsystems 206 are, for the purposes of this disclosure, parts of a semiconductor device manufacturing and defect-based test coverage gap identification system 220.

[0043] Figure 6 shows a method or process 600 for automatically identifying defect-based test coverage gaps in semiconductor devices according to one or more embodiments of the present disclosure. Figures 7A and 7B show block diagrams of a semiconductor device manufacturing and defect-based test coverage gap identification system 220, or "System 220," according to one or more embodiments of the present disclosure. Note that System 220 may be configured to perform processing steps for fabricating and / or analyzing semiconductor dies, as described throughout the present disclosure. Furthermore, note that the steps of Method or Process 600 may be implemented in whole or in part by System 220 shown in Figure 7. However, it is further recognized that Method or Process 600 is not limited to System 220 shown in Figure 7, in that additional or alternative system-level embodiments may perform all or part of the steps of Method or Process 600.

[0044] In step 602, characterization measurements of one or more semiconductor devices are obtained. In some embodiments, the system 220 includes one or more semiconductor manufacturing subsystems 202.

[0045] In one non-limiting example, one or more semiconductor manufacturing subsystems 202 may include at least one inspection tool 700 (e.g., an in-line sample analysis tool) for detecting defects in one or more layers of a sample 702. The system 220 may generally include any number or type of inspection tools 700. For example, the inspection tool 700 may include, but is not limited to, an optical inspection tool configured to detect defects based on interrogation of the sample 702 with light from any source such as a laser source, lamp source, X-ray source, or broadband plasma source. In another example, the inspection tool 700 may include, but is not limited to, a particle beam inspection tool configured to detect defects based on interrogation of the sample with one or more particle beams such as an electron beam, ion beam, or neutral particle beam. For example, the inspection tool 700 may include a transmission electron microscope (TEM) or a scanning electron microscope (SEM). For the purposes of this disclosure, it should be noted that in this specification, at least one inspection tool 700 may be a single inspection tool 700 or may represent a group of inspection tools 700.

[0046] In this specification, sample 702 may be a semiconductor wafer of multiple semiconductor wafers, each semiconductor wafer of the multiple semiconductor wafers may contain multiple layers, each layer of the multiple layers may contain multiple semiconductor dies, and each semiconductor die of the multiple semiconductor wafers may contain multiple blocks. In addition, in this specification, sample 702 may be a semiconductor die package formed from multiple semiconductor dies arranged in a 2.5D lateral combination of bare dies on a substrate inside an advanced die package or 3D die package.

[0047] For the purposes of this disclosure, the term “defect” may mean a physical defect found by an inline inspection tool, a measurement outlier, or other physical characteristic of a semiconductor device that is considered abnormal. A defect can be considered any deviation of a manufactured layer or a manufactured pattern within a layer from design characteristics, including but not limited to physical, mechanical, chemical, or optical properties. In addition, a defect can be considered any deviation in the alignment or bonding of components within a manufactured semiconductor die package. Furthermore, a defect can have any size relative to the semiconductor die or features thereon. Thus, a defect may be smaller than the semiconductor die (e.g., a scale of one or more patterned features) or larger than the semiconductor die (e.g., as part of a scratch or pattern on a wafer scale). For example, a defect may include deviations in the thickness or composition of a sample layer before or after patterning. As another example, a defect may include deviations in the size, shape, orientation, or position of a patterned feature. As another example, defects may include, but are not limited to, bridges (or lack thereof) between adjacent structures, pits, or holes, and may include defects associated with the lithography and / or etching steps. As yet another example, defects may include, but are not limited to, damaged portions of sample 702 such as scratches or chips. For example, 70% of defects (e.g., length of a scratch, depth of a pit, measured size or polarity of a defect) may be significant and considered. As yet another example, defects may include foreign matter introduced into sample 702. As yet another example, defects may be misaligned and / or misjoined package components on sample 702. Therefore, it should be understood that the examples of defects in this disclosure are provided for illustrative purposes only and should not be construed as limitations.

[0048] In another non-limiting example, one or more semiconductor manufacturing subsystems 202 include at least one measuring tool 704 (e.g., an in-line sample analysis tool) for measuring one or more properties of a sample 702 or one or more layers thereof. For example, the measuring tool 704 can evaluate properties such as, but not limited to, layer thickness, layer composition, critical dimension (CD), overlay, or lithography processing parameters (e.g., intensity or dose of illumination during a lithography step). In this regard, the measuring tool 704 can provide information regarding the manufacturing of the sample 702, one or more layers of the sample 702, or one or more dies of the sample 702, which may relate to the probability of manufacturing defects that could lead to reliability issues of the resulting manufactured device. For the purposes of this disclosure, it should be noted that in this specification, at least one measuring tool 704 may be a single measuring tool 704 or may represent a group of measuring tools 704.

[0049] In some embodiments, one or more semiconductor manufacturing subsystems 202 include at least one semiconductor manufacturing tool or process tool 706. For example, the process tool 706 may include any tool known in the art, including, but not limited to, etchers, scanners, steppers, cleaners, etc. For example, the manufacturing process may include manufacturing a plurality of dies distributed across the surface of a sample (e.g., a semiconductor wafer, etc.), each die comprising a plurality of patterned layers of material forming a device component. Each patterned layer may be formed by the process tool 706 through a series of steps including material deposition, lithography, etching to generate a pattern of interest, and / or one or more exposure steps (performed, e.g., by a scanner, stepper, etc.). As another example, the process tool 706 may include any tool known in the art configured to package and / or bond semiconductor dies into 2.5D and / or 3D semiconductor die packages. For example, the manufacturing process may include, but is not limited to, matching semiconductor dies and / or electrical components on semiconductor dies. In addition, the manufacturing process may include, but is not limited to, joining semiconductor dies and / or electrical components on semiconductor dies via hybrid bonding (e.g., die-to-die, die-to-wafer, wafer-to-wafer, etc.) solder, adhesive, fasteners, or equivalents. Note that for the purposes of this disclosure, at least one process tool 706 may be a single process tool 706 or may represent a group of process tools 706.

[0050] In step 604, test measurements are obtained for one or more semiconductor dies on one or more semiconductor devices. In some embodiments, the system 220 includes one or more test tool subsystems 206 for testing the functionality of one or more parts of a manufactured device.

[0051] In one non-limiting example, one or more test tool subsystems 206 may include any number or type of electrical test tools 708 to complete preliminary probing at the wafer level. For example, preliminary probing is not designed to attempt to force a failure at the wafer level.

[0052] In another non-limiting example, one or more test tool subsystems 206 may include any number or type of stress test tools 710 for testing, inspecting, or otherwise characterizing the properties of one or more parts of a manufactured device at any point in the manufacturing cycle. For example, the stress test tool 710 may include, but is not limited to, a pre-burn-in electrical wafer sort and final test (e.g., e-test) or post-burn-in electrical test configured to heat the sample 702 (e.g., an oven or other heat source) and cool the sample 702 (e.g., a freezer or other cold source) while operating the sample 702 with an incorrect voltage (e.g., a power supply).

[0053] In some embodiments, defects are identified after one or more processing steps (e.g., lithography, etching, alignment, bonding, etc.) performed on the target layer within the semiconductor die and / or semiconductor die package by one or more process tools 706, using any combination of a characterization subsystem 204 (e.g., inspection tool 700, measurement tool 704, etc.) and a test tool subsystem 206 (e.g., including an electrical test tool 708 and / or a stress test tool 710, etc.). In this regard, defect detection at various stages of the manufacturing process may be called in-line defect detection.

[0054] In step 606, the characteristic measurements and test measurements are automatically sent to a system to determine one or more gap areas within defect-based test coverage of one or more semiconductor devices.

[0055] In some embodiments, the system 220 includes a controller 712. The controller 712 may include one or more processors 714 configured to execute program instructions maintained on memory 716 (e.g., a storage medium, a memory device, etc.). Furthermore, the controller 712 may be communicatively coupled to any of the components of the system 220, including but not limited to inspection tools 700, measurement tools 704, electrical test tools 708 and / or stress test tools 710, and the system 200.

[0056] One or more steps of the method or process 100 may be performed automatically. For example, one or more processors 714 of the controller 712 may be configured to receive information for characterization measurements performed on a selected semiconductor device, determine one or more obvious killer defects from the information for inline inspection and measurement measurements, receive information for test measurements performed on the selected semiconductor device, and determine one or more semiconductor dies that pass the selected test from the test measurements performed on the selected semiconductor device. The information received for characterization measurements performed on the selected semiconductor device is correlated with the information received for test measurements taken on the selected semiconductor device, one or more gap areas for defect-based test coverage are determined from the correlated information, and / or one or more adjustments to the manufacturing, characterization, and / or testing of the semiconductor device based on the determined one or more gap areas. It should be noted herein that one or more steps of the method or process 100 may be performed continuously as new data is constantly available from characterization measurements.

[0057] One or more processors 714 of the controller 712 may include any processor or processing element known in the art. For the purposes of this disclosure, the terms “processor” or “processing element” may be broadly defined to include any device having one or more processing or logic elements (e.g., one or more microprocessor devices, one or more application-specific integrated circuit (ASIC) devices, one or more field-programmable gate arrays (FPGAs), or one or more digital signal processors (DSPs)). In this sense, one or more processors 714 of the controller 712 may include any device configured to execute algorithms and / or instructions (e.g., program instructions stored in memory). In one embodiment, one or more processors 714 of the controller 712 may be embodied as a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, a network computer, or any other computer system configured to execute a program that operates or is configured to operate with the components of the system 200, as described throughout this disclosure.

[0058] The memory 716 of the controller 712 may include any storage medium known in the art that is suitable for storing program instructions executable by each of the one or more associated processors 714 of the controller 712. For example, the memory 716 of the controller 712 may include a persistent memory medium. Another example is that the memory 716 of the controller 712 may include, but is not limited to, read-only memory (ROM), random access memory (RAM), magnetic or optical memory devices (e.g., disks), magnetic tape, solid-state drives, etc. Furthermore, it should be noted that the memory 716 of the controller 712 may be housed in a common controller housing together with the one or more processors 714. In one embodiment, the memory 716 of the controller 712 may be located remotely from the physical location of each of the one or more processors 714 of the controller 712. For example, each of the one or more processors 714 of the controller 712 may have access to remote memory (e.g., a server) accessible via a network (e.g., the internet, an intranet, etc.).

[0059] In another embodiment, the system 220 includes a user interface 718 coupled to the controller 712 (e.g., physically coupled, electrically coupled, communicatively coupled, etc.). For example, the user interface 718 may be a separate device coupled to the controller 712. In another example, the user interface 718 and the controller 712 may be located in a common or shared housing. However, it should be noted herein that the controller 712 may include, require, or not be coupled to the user interface 718.

[0060] The user interface 718 of the controller 712 may include, but is not limited to, one or more desktops, laptops, tablets, etc. The user interface 718 of the controller 712 may include a display used to display data from the system 200 to the user. The display of the user interface 718 of the controller 712 may include any display known in the art. For example, the display may include, but is not limited to, a liquid crystal display (LCD), an organic light-emitting diode (OLED) based display, or a CRT display. Those skilled in the art will recognize that any display device that can be integrated with the user interface 718 of the controller 712 is suitable for implementation in this disclosure. In another embodiment, the user may input selections and / or commands in response to data displayed to the user via a user input device of the user interface 718 of the controller 712.

[0061] In step 608, one or more control signals are generated for adjustments based on one or more gap areas in defect-based test coverage for at least one of the manufacturing, characterization, or testing of one or more semiconductor devices. For example, one or more control signals may adjust one or more semiconductor manufacturing subsystems 202 and / or one or more manufacturing processes or methods, or one or more characterization processes or methods employed by one or more semiconductor manufacturing subsystems 202, via either a feedforward loop (e.g., to correct current semiconductor devices) or a feedback loop (e.g., to adjust future semiconductor devices). As another example, one or more control signals may adjust one or more test processes or methods employed by one or more test tool subsystems 206 and / or one or more test tool subsystems 206, via either a feedforward loop (e.g., to correct current semiconductor devices) or a feedback loop (e.g., to adjust future semiconductor devices).

[0062] Embodiments of this disclosure illustrate steps of methods or processes 100, 600 performed by the controller 712, but it should be noted that some or all of the steps of methods or processes 100, 600 may be performed by a server or controller communicatively coupled to the controller 712. For example, the server or controller may include a processor and memory and other communicatively coupled components as described throughout this disclosure.

[0063] It should be noted that, for the purposes of this disclosure, the embodiments shown in Figure 7A and Figure 7B may be considered as parts of the same system 220, parts of different systems 220, or parts of different subsystems of different systems 220. For example, if system 220 includes inline characterization, the characterization tools 700, 704 and / or process tools 706 may be arranged to receive the sample 702 at different stages during the manufacturing of the sample 702. Furthermore, it should be noted that, for the purposes of this disclosure, the components within system 220 shown in Figure 7A and the components within system 220 shown in Figure 7B may communicate directly or via the controller 712.

[0064] It should be noted that, as herein, methods or processes 100 and 600 are not limited to the steps and / or substeps provided. Methods or processes 100 and 600 may include more or fewer steps and / or substeps. Methods or processes 100 and 600 may perform the steps and / or substeps concurrently. Methods or processes 100 and 600 may perform the steps and / or substeps sequentially, including in the order provided or in any other order. Therefore, the above description should not be construed as a limitation on the scope of this disclosure, but merely as an example.

[0065] In this regard, System 200 (and System 220) and Method or Process 100 can provide an economic trade-off between test time and the number of semiconductor die returns due to gap areas in defect-based test coverage. In addition, System 200 (and System 220) and Method or Process 100 can provide semiconductor manufacturers with an accurate empirical picture of semiconductor die areas with increased reliability risk, and / or quantitative comparisons between semiconductor device designs for percentage area of ​​defect-based test coverage gaps.

[0066] For example, System 200 (and System 220) and Method or Process 100 can provide improved insight into baseline test coverage gaps, helping automotive semiconductor device manufacturers reduce reliability failures from PPM to PPB ranges. Semiconductor failures are a number of failure items for automotive manufacturing, and this problem intensifies as semiconductor contents for automobiles grow (e.g., with the implementation of autonomous and electric vehicles). Similarly, reliability concerns are becoming increasingly important in industrial, biomedical, defense, aerospace, hyperscale data centers, and other fields. Identifying test coverage gaps leads to recognition of limitations in electrical test methods and therefore drives the adoption of inline defect screening inspections to mitigate these problems.

[0067] In one non-limiting example, inline characterization may be performed on selected (e.g., critical) layers. At user-selectable time intervals (e.g., every quarter, monthly, weekly), the system 200 can generate reports for all semiconductor devices monitored through one or more steps of the method or process 100 to provide a baseline of the test coverage gap across the semiconductor devices. For example, the report may alert if a selected area of ​​a semiconductor device has a statistically high level of apparent killer defects within the semiconductor die that pass all tests. Note that, as specified herein, reports may be automatically triggered when a predefined threshold is reached. Additionally, note that, as specified herein, the reporting frequency may be increased to understand improvements over time for devices under high scrutiny for reliability issues. Furthermore, note that, as specified herein, the test coverage gap may be reduced by modifying the test protocol through a Design of Experiment (DOE) study. Furthermore, it should be noted that System 200 may provide real-time feedback on the effectiveness of such changes and enable the use of System 200 and Method or Process 100 when qualifying new / future devices and / or during “safe startup” activities.

[0068] The benefits of this disclosure relate to systems and methods for automatically identifying defect-based test coverage gaps in semiconductor devices. In particular, the benefits of this disclosure relate to enabling the automatic identification of previously unknown locations in reliability-sensitive designs that escape killer defects within the test gap. The benefits of this disclosure also relate to systematically identifying test coverage gaps using empirical defect data. The benefits of this disclosure also relate to demonstrating continuous improvement, evaluating the effectiveness of test program changes, and providing new metrics and / or charting for quantifying test gap differences per device or between different devices in a product portfolio over time as improvements are made.

[0069] The subject matter described herein illustrates different components that, in some cases, are contained within or connected to other components. It should be understood that such depicted architectures are merely illustrative, and in practice, many other architectures can be implemented to achieve the same functionality. Conceptually, any arrangement of components to achieve the same function is effectively “associated” in such a way that the desired function is achieved. Thus, any two components in this specification combined to achieve a particular function, whether in architecture or as intermediate components, can be considered “associated” with each other in such a way that the desired function is achieved. Similarly, any two such associated components can also be considered “connected” or “joined” with each other in such a way that the desired functionality is achieved, and any two components that can be associated in such a way can also be considered “joinable” with each other in such a way that the desired functionality is achieved. Specific examples of joinable components include, but are not limited to, physically interactable and / or physically interacting components and / or wirelessly interactable and / or wirelessly interacting components and / or logically interactable and / or logically interacting components.

[0070] Many of the present disclosure and its associated advantages will be understood from the foregoing description, and it will become clear that various modifications can be made to the form, structure, and arrangement of the components without departing from the disclosed subject matter or sacrificing any of its material advantages. The described forms are for illustrative purposes only, and it is the intent of the following claims to encompass and include such modifications. Furthermore, it should be understood that the present invention is defined by the appended claims.

Claims

1. It is a system, A controller communicatively coupled to one or more semiconductor manufacturing subsystems and one or more test tool subsystems, wherein the controller includes one or more processors configured to execute program instructions. A step of determining a plurality of apparent killer defects on one or more semiconductor devices based on characteristic measurements of one or more semiconductor devices obtained by one or more semiconductor manufacturing subsystems via a characteristic measurement subsystem, wherein the one or more semiconductor devices include a plurality of semiconductor dies; A step of determining, via a test subsystem, at least one semiconductor die among a plurality of semiconductor dies that passes at least one of a plurality of tests, based on test measurements obtained by one or more test tool subsystems, The steps include: correlating the characteristic measurements with the test measurements via a correlation subsystem to determine at least one apparent killer defect among a plurality of apparent killer defects that pass at least one of a plurality of tests on at least one semiconductor die among the plurality of semiconductor dies; A step of determining one or more gap areas on one or more semiconductor devices for defect-based test coverage, based on at least one obvious killer defect that has passed at least one of a plurality of tests on at least one semiconductor die among the plurality of semiconductor dies, via a location subsystem. Execute, The gap area is determined by superimposing it on one or more functional semiconductor die blocks in the semiconductor die layout. The one or more processors described above are: The step of generating one or more reports based on one or more gap areas within defect-based test coverage on one or more semiconductor devices. Further configured to perform, The system includes at least one metric for adjusting at least one of the one or more semiconductor manufacturing subsystems or the one or more test tool subsystems to mitigate one or more gap areas on the one or more semiconductor devices for defect-based test coverage.

2. The one or more processors described above are: The step of receiving characteristic measurements obtained by the one or more semiconductor manufacturing subsystems during the manufacturing of the one or more semiconductor devices via the characteristic measurement subsystem. The system according to claim 1, further configured to perform the following:

3. The system according to claim 1, wherein the one or more characteristic measurement subsystems include one or more characteristic measurement tools configured to perform at least one of one or more inline defect inspection processes or one or more measurement processes.

4. The system according to claim 1, wherein the characteristic measurement subsystem is configured to determine a plurality of apparent killer defects on one or more semiconductor devices based on the characteristic measurement using at least one of advanced deep learning techniques or machine learning techniques.

5. The one or more processors described above are: The step of receiving test measurement values ​​of one or more semiconductor devices acquired by one or more test tool subsystems via the test subsystem. The system according to claim 1, further configured to perform the following:

6. The system according to claim 1, wherein the one or more test tool subsystems include one or more test tools configured to perform at least one of one or more electrical wafer sorting processes, unit probe processes, class probe processes, or final test processes.

7. The system according to claim 1, characterized in that at least one of the plurality of semiconductor dies passes all of the plurality of tests.

8. The system according to claim 1, wherein the location identification subsystem analyzes at least one of the locations or frequencies of at least one apparent killer defect among a plurality of apparent killer defects on at least one semiconductor die among the plurality of semiconductor dies, and passes at least one of a plurality of tests.

9. The system according to claim 1, wherein the one or more reports include at least one chart configured to evaluate the one or more gap areas on the one or more semiconductor devices for the defect-based test coverage.

10. The system according to claim 9, characterized in that the at least one chart is configured to compare the test coverage gap trend over a certain time range for a particular semiconductor device design.

11. The system according to claim 9, characterized in that the at least one chart is configured to compare test cover gaps for multiple semiconductor device designs.

12. The one or more processors described above are: The step of determining one or more adjustments to at least one of the manufacturing, characterization, or testing of a semiconductor device based on one or more gap areas on the one or more semiconductor devices for the defect-based test coverage. The system according to claim 1, further configured to perform the following:

13. The one or more processors described above are: A step of generating one or more control signals based on one or more adjustments to at least one of the manufacturing, characterization, or testing of the semiconductor device. The system according to claim 12, further configured to perform the following:

14. The system according to claim 13, characterized in that the one or more control signals are configured to target a selected inline defect partial mean inspection (l-PAT) care area on the semiconductor device.

15. It is a method, A step of determining a plurality of apparent killer defects on one or more semiconductor devices based on characteristic measurements of one or more semiconductor devices obtained by one or more semiconductor manufacturing subsystems via a controller characteristic measurement subsystem, wherein the one or more semiconductor devices include a plurality of semiconductor dies. The steps include determining at least one semiconductor die among a plurality of semiconductor dies that passes at least one of a plurality of tests, based on test measurements obtained by one or more test tool subsystems via the test subsystem of the controller, The steps of correlating the characteristic measurement with the test measurement in order to determine at least one apparent killer defect among a plurality of apparent killer defects that pass at least one of a plurality of tests on at least one semiconductor die among a plurality of semiconductor dies via the correlation subsystem of the controller, The steps include determining one or more gap areas on one or more semiconductor devices for defect-based test coverage, based on at least one obvious killer defect that has passed at least one of a plurality of tests on at least one semiconductor die among a plurality of semiconductor dies, via the controller's location subsystem, Includes, The gap area is determined by superimposing it on one or more functional semiconductor die blocks in the semiconductor die layout. moreover, The step of generating one or more reports based on one or more gap areas within defect-based test coverage on one or more semiconductor devices. Includes, The method comprising adjusting at least one of the one or more semiconductor manufacturing subsystems or the one or more test tool subsystems to mitigate one or more gap areas on the one or more semiconductor devices for defect-based test coverage.

16. The step of receiving the characteristic measurement values ​​obtained by the one or more semiconductor manufacturing subsystems during the manufacturing of the one or more semiconductor devices via the characteristic measurement subsystem of the controller. The method according to claim 15, further comprising:

17. The method according to 15, wherein the one or more characteristic measurement subsystems include one or more characteristic measurement tools configured to perform at least one of one or more inline defect inspection processes or one or more measurement processes.

18. The method according to 15, characterized in that the characteristic measurement subsystem is configured to determine a plurality of apparent killer defects on one or more semiconductor devices based on the characteristic measurement using at least one of advanced deep learning techniques or machine learning techniques.

19. The method according to claim 15, further comprising the step of receiving the test measurement values ​​of the one or more semiconductor devices acquired by the one or more test tool subsystems via the test subsystem of the controller.

20. The method according to 15, characterized in that the one or more test tool subsystems include one or more test tools configured to perform at least one of one or more electrical wafer sorting processes, unit probe processes, class probe processes, or final test processes.

21. The method according to 15, characterized in that at least one of the plurality of semiconductor dies passes all of the plurality of tests.

22. The method according to 15, wherein the location identification subsystem analyzes at least one of the locations or frequencies of at least one apparent killer defect among a plurality of apparent killer defects on at least one semiconductor die among the plurality of semiconductor dies, and passes at least one of a plurality of tests.

23. The method according to 15, wherein the one or more reports include at least one chart configured to evaluate one or more gap areas on the one or more semiconductor devices for the defect-based test coverage.

24. The method according to 23, characterized in that the at least one chart is configured to compare test coverage gap trends over a certain time range for a particular semiconductor device design.

25. The method according to 23, characterized in that the at least one chart is configured to compare test cover gaps for multiple semiconductor device designs.

26. The step of determining one or more adjustments to at least one of the manufacturing, characterization, or testing of a semiconductor device based on one or more gap areas on one or more semiconductor devices for defect-based test coverage via the controller. The method according to claim 15, further comprising:

27. The method according to claim 26, further comprising the step of generating one or more control signals via the controller based on one or more adjustments to at least one of the manufacturing, characterization, or testing of a semiconductor device.

28. The method according to 27, characterized in that the one or more control signals are configured to target a selected inline defect partial mean inspection (l-PAT) care area on a semiconductor device.

29. It is a system, One or more semiconductor manufacturing subsystems, One or more test tool subsystems, A controller communicatively coupled to one or more semiconductor manufacturing subsystems and one or more test tool subsystems, comprising one or more processors configured to execute program instructions, A step of determining a plurality of apparent killer defects on one or more semiconductor devices based on characteristic measurements of one or more semiconductor devices obtained by one or more semiconductor manufacturing subsystems via a characteristic measurement subsystem, wherein the one or more semiconductor devices include a plurality of semiconductor dies; A step of determining, via a test subsystem, at least one semiconductor die among a plurality of semiconductor dies that passes at least one of a plurality of tests, based on test measurements obtained by one or more test tool subsystems, The steps include: correlating the characteristic measurements with the test measurements via a correlation subsystem to determine at least one apparent killer defect among a plurality of apparent killer defects that pass at least one of a plurality of tests on at least one semiconductor die among a plurality of semiconductor dies; A step of determining one or more gap areas on one or more semiconductor devices for defect-based test coverage, based on at least one obvious killer defect that has passed at least one of a set of tests on at least one semiconductor die among a set of semiconductor dies, via a location subsystem. Execute, The gap area is determined by superimposing it on one or more functional semiconductor die blocks in the semiconductor die layout. The one or more processors described above are: The step of generating one or more reports based on one or more gap areas within defect-based test coverage on one or more semiconductor devices. Further configured to perform, The system includes at least one metric for adjusting at least one of the one or more semiconductor manufacturing subsystems or the one or more test tool subsystems to mitigate one or more gap areas on the one or more semiconductor devices for defect-based test coverage.

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