Photoelectric converter, photoelectric converter system, and mobile body

Abstract

This photoelectric conversion device comprises a first substrate provided with a plurality of avalanche photodiodes, a second substrate provided with a plurality of pixel circuits, and a third substrate provided with a signal processing circuit. The second substrate and the third substrate are laminated so that a third wiring structure is provided between two semiconductor layers of the second substrate and the third substrate. The photoelectric conversion device further comprises a first through-wire extending through the semiconductor layer of the third substrate.

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device, a photoelectric conversion system, and a moving body.

Background Art

[0002] There is known a photoelectric conversion device including a pixel array configured such that pixels each including a plurality of avalanche photodiodes (hereinafter, APD: Avalanche Photo Diode) are arranged two-dimensionally in a planar array. In each pixel, by applying a reverse bias voltage to a PN junction diode, a photoelectric charge caused by a single photon causes avalanche multiplication. There are at least two modes of operation of the APD. When a reverse bias voltage is supplied, there are a Geiger mode in which the potential difference between the anode and the cathode is operated at a potential difference greater than the breakdown voltage, and a linear mode in which the potential difference between the anode and the cathode is operated at a voltage difference near or below the breakdown voltage. Among these, an APD operating in the Geiger mode is called a SPAD (Single Photon Avalanche Diode).

[0003] Fig. 3B of Patent Document 1 describes a photoelectric conversion device having a SPAD array on a first substrate, a counter on a second substrate, and a storage on a third substrate, with the first substrate, the second substrate, and the third substrate laminated.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Patent Document 1 discloses a photoelectric conversion device in which a first substrate, a second substrate, and a third substrate are stacked, but the wiring structure for electrically connecting the second substrate and the third substrate has not been examined. Therefore, the present invention aims to propose a specific configuration for a photoelectric conversion device having three or more substrates equipped with avalanche photodiodes. [Means for solving the problem]

[0006] The photoelectric conversion device according to the present invention comprises a first substrate having a first semiconductor layer and a first wiring structure, each of which has an avalanche photodiode, the first substrate and the second substrate stacked such that the first and second wiring structures are provided between the first and second semiconductor layers, and the second substrate and the third substrate stacked such that the third wiring structure is provided between the second and third semiconductor layers, and a first through-wiring penetrates the third semiconductor layer. A first bump is electrically connected to the first through-wiring and is located on the side of the third semiconductor layer opposite to the side where the third wiring structure is provided, The first through-wiring and the first bump It is characterized by having a semiconductor element that overlaps with it in a plan view. [Effects of the Invention]

[0007] According to the present invention, a specific configuration of a photoelectric conversion device having a structure of three or more layers equipped with an avalanche photodiode can be proposed. [Brief explanation of the drawing]

[0008] [Figure 1] Block diagram of a photoelectric converter [Figure 2] Functional block diagram of the first circuit board [Figure 3] Functional block diagram of the second circuit board [Figure 4]Functional block diagram of the third substrate [Figure 5] Circuit diagram and functional block diagram of pixels [Figure 6] Diagram explaining the relationship between the operation of the APD and the output signal [Figure 7] Schematic diagram showing the electrical connection relationship between the first substrate and the second substrate in Embodiment 1 [Figure 8] Schematic diagram showing the electrical connection relationship between the second substrate and the third substrate in Embodiment 1 [Figure 9] Schematic diagram showing the electrical connection relationship between the third substrate and other substrates, etc. in Embodiment 1 [Figure 10] Cross-sectional view of the photoelectric conversion device in Embodiment 1 [Figure 11] Manufacturing process of the photoelectric conversion device in Embodiment 1 [Figure 12] Manufacturing process of the photoelectric conversion device in Embodiment 1 [Figure 13A] Manufacturing process of the photoelectric conversion device in Embodiment 1 [Figure 13B] Manufacturing process of the photoelectric conversion device in Embodiment 1 [Figure 14] Cross-sectional view of the photoelectric conversion device in Embodiment 2 [Figure 15] Cross-sectional view of the photoelectric conversion device in Embodiment 3 [Figure 16] Cross-sectional view of the photoelectric conversion device in Embodiment 4 [Figure 17] Cross-sectional view of the photoelectric conversion device in Embodiment 5 [Figure 18] Cross-sectional view of the photoelectric conversion device in Embodiment 6 [Figure 19] Cross-sectional view of the photoelectric conversion device in Embodiment 7 [Figure 20] Cross-sectional view of the photoelectric conversion device in Embodiment 8 [Figure 21] Cross-sectional view of the photoelectric conversion device in Embodiment 9 [Figure 22] Cross-sectional view of the photoelectric conversion device in Embodiment 10 [Figure 23] Schematic diagram showing the electrical connection relationship between the first substrate and the second substrate in Embodiment 11 [Figure 24] Schematic diagram showing the electrical connection relationship between the second substrate and the third substrate in Embodiment 11 [Figure 25] Schematic diagram showing the electrical connection relationship between the third substrate of Embodiment 11 and other substrates etc. [Figure 26] Schematic diagram showing the electrical connection relationship between the first substrate and the second substrate of Embodiment 12 [Figure 27] Schematic diagram showing the electrical connection relationship between the second substrate and the third substrate of Embodiment 12 [Figure 28] Schematic diagram showing the electrical connection relationship between the third substrate of Embodiment 12 and other substrates etc. [Figure 29] Cross-sectional view of the photoelectric conversion device of Embodiment 12 [Figure 30] Schematic diagram showing the electrical connection relationship between the second substrate and the third substrate of Embodiment 13 [Figure 31] Schematic diagram showing the electrical connection relationship between the third substrate of Embodiment 13 and other substrates etc. [Figure 32] Cross-sectional view of the photoelectric conversion device of Embodiment 13 [Figure 33] Cross-sectional view of the photoelectric conversion device of Embodiment 14 [Figure 34] Cross-sectional view of the photoelectric conversion device of Embodiment 14 [Figure 35] Cross-sectional view of the photoelectric conversion device of Embodiment 14 [Figure 36] Cross-sectional view of the photoelectric conversion device of Embodiment 14 [Figure 37] Cross-sectional view of the photoelectric conversion device of Embodiment 14 [Figure 38] Cross-sectional view of the photoelectric conversion device of Embodiment 14 [Figure 39] Cross-sectional view of the photoelectric conversion device of Embodiment 15 [Figure 40] Cross-sectional view of the photoelectric conversion device of Embodiment 16 [Figure 41] Cross-sectional view of the photoelectric conversion device of Embodiment 17 [Figure 42] Functional block diagram of the photoelectric conversion system of Embodiment 18 [Figure 43] Functional block diagram of the distance sensor of Embodiment 19 [Figure 44] Functional block diagram of the endoscopic surgery of Embodiment 20 [Figure 45A] Diagram of the photoelectric conversion system and the moving body of Embodiment 21 [Figure 45B] Diagram of the photoelectric conversion system and mobile body of Embodiment 21 [Figure 46A] Functional block diagram of endoscopic surgery in Embodiment 22 [Figure 46B] Functional block diagram of endoscopic surgery in Embodiment 22 [Modes for carrying out the invention]

[0009] The embodiments shown below are intended to embody the technical concept of the present invention and do not limit it. The size and positional relationships of the components shown in each drawing may be exaggerated for clarity of explanation. In the following description, identical components may be given the same number and their explanation may be omitted.

[0010] The following configuration relates to a photoelectric conversion device that includes a SPAD (Single Photon Avalanche Diode) for counting the number of photons incident on an avalanche diode. The photoelectric conversion device includes at least an avalanche diode.

[0011] In the following explanation, the anode of the avalanche diode is set to a fixed potential, and the signal is taken from the cathode side. Therefore, the semiconductor region of the first conductivity type, which has charges of the same conductivity type as the signal charge as the majority carriers, is an N-type semiconductor region, and the semiconductor region of the second conductivity type is a P-type semiconductor region. Note that the present invention also applies when the cathode of the avalanche diode is set to a fixed potential and the signal is taken from the anode side. In this case, the semiconductor region of the first conductivity type, which has charges of the same conductivity type as the signal charge as the majority carriers, is a P-type semiconductor region, and the semiconductor region of the second conductivity type is an N-type semiconductor region. The following explanation describes the case where one node of the avalanche diode is set to a fixed potential, but the potentials of both nodes may fluctuate.

[0012] In this specification, a plan view refers to viewing a semiconductor layer from a direction perpendicular to the light incident surface. A cross-sectional view refers to a surface perpendicular to the light incident surface of the semiconductor layer. If the light incident surface of the semiconductor layer is rough when viewed microscopically, the plan view is defined based on the light incident surface of the semiconductor layer as viewed macroscopically.

[0013] (Embodiment 1) Figure 1 shows an overall view of the photoelectric converter 100. The first substrate 1100, also called a sensor chip, is provided with a pixel region 12 in which pixels having a photoelectric conversion unit are arranged in two dimensions. A peripheral region 13 is provided between the pixel region 12 and the chip edge of the photoelectric converter 100. The second substrate 2100, also called a pixel circuit chip, is provided with a pixel circuit region 22 in which a pixel circuit that processes signals from the photoelectric conversion unit is arranged. The third substrate 3100, also called a signal processing chip, is provided with a signal processing circuit region 32 in which a signal processing circuit that processes signals from the pixel circuit is arranged. The photoelectric converter 100 is constructed by stacking the first substrate 1100, the second substrate 2100, and the third substrate 3100.

[0014] (First board) Figure 2 is a diagram of the configuration of the first substrate 1100. The first substrate is provided with a pixel region 12 in which pixels 101, each having a photoelectric conversion unit 102 including an avalanche photodiode (hereinafter referred to as APD), are arranged in a two-dimensional manner. The arrangement of pixels 101 in the pixel region 12 may also be arranged in a one-dimensional manner. Details of the photoelectric conversion unit 102 will be described later.

[0015] Pixel 101 is typically a pixel for forming an image, but when used in TOF (Time of Flight), it does not necessarily have to form an image. In other words, pixel 101 may be an element for measuring the time and amount of light that arrives.

[0016] (Second board) Figure 3 is a diagram of the configuration of the second substrate 2100. The second substrate 2100 has a pixel circuit section 201 for processing the charge photoelectrically converted by the photoelectric conversion section 102, a control pulse generation section 206, a horizontal scanning circuit section 203, a signal line 205, and a vertical scanning circuit section 202. The pixel circuit region 22 shown in Figure 2 is a region in which at least the pixel circuit section 201 is provided.

[0017] The photoelectric conversion unit 102 in Figure 2 and the pixel circuit unit 201 in Figure 3 are electrically connected via connecting wiring provided for each pixel.

[0018] The vertical scanning circuit section 202 receives control pulses supplied from the control pulse generation section 206 and supplies control pulses to each pixel. Logic circuits such as a shift register and an address decoder are used in the vertical scanning circuit section 202.

[0019] The signals output from the photoelectric conversion unit 102 of each pixel are processed by the pixel circuit unit 201.

[0020] The pixel circuit section 201 is equipped with a counter and memory, and digital values ​​are stored in the memory.

[0021] The horizontal scanning circuit unit 203 inputs control pulses to the pixel circuit unit 201 to sequentially select each column in order to read a signal from the memory of each pixel in which a digital signal is held.

[0022] Signals are output to signal line 205 from the pixel circuit unit 201 of the pixel selected by the vertical scanning circuit unit 202 for the selected column.

[0023] In Figures 2 and 3, one pixel circuit section 201 was provided corresponding to one pixel 101. However, the pixel circuit section 201 may be shared by multiple pixels 101, for example, and sequential signal processing may be performed. This makes it possible to save space in the pixel circuit area 22.

[0024] (Third board) Figure 4 is a diagram showing the configuration of the third circuit board 3100. The third circuit board 3100 includes a memory 301, a first signal processing unit 304, a second signal processing unit 305, and control circuit units 302 and 303.

[0025] Memory 301 records, for example, image data output from the horizontal scanning circuit unit 203. Memory 301 is, for example, SRAM (Static Random Access Memory) or DRAM.

[0026] The control circuits 302 and 303 control the recording and reading of information from the memory 301.

[0027] The first signal processing unit 304 performs various signal processing operations on the image data (image data to be processed) read from the memory 301. For example, if the image data to be processed is a color image, the first signal processing unit 304 converts the format of this image data to YUV image data, RGB image data, etc.

[0028] The first signal processing unit 304 performs processing on the image data to be processed, such as noise reduction and white balance adjustment, as needed. In addition, the first signal processing unit 304 performs various signal processing (also called preprocessing) on ​​the image data to be processed, which is necessary for the second signal processing unit 305 to process that image data.

[0029] When the photoelectric converter 100 is also used as a distance measuring device, the first signal processing unit 304 also functions as a distance measurement processing unit, for example. For example, it creates a histogram based on information obtained from the TDC circuit (Time to Digital Converter) described later, performs distance calculations, and outputs the results to the second signal processing unit 305. In the histogram, the horizontal axis represents time-related classes (bins), and the vertical axis represents the frequency in each class. The frequency is the number of times light was received within a predetermined light reception time. The histogram also contains counts based on reflected light and ambient light. Therefore, by setting a predetermined threshold, the count of the reflected light component and the count of the ambient light component are separated. The distance between the distance measuring device and the object to be measured is calculated from the light arrival time corresponding to the reflected light component.

[0030] The first signal processing unit 304 can generate three-dimensional distance image data from the distance calculated by the calculation. The three-dimensional distance image data can be generated solely from the information obtained by the distance measurement processing unit, or it may be three-dimensional distance image data generated by adding the calculation data acquired by the distance measurement processing unit to two-dimensional plane image data.

[0031] The second signal processing unit 305 is, for example, a DSP (Digital Signal Processor). The second signal processing unit 305 functions as a processing unit that executes various processes using a trained model created by machine learning by executing a program stored in memory 301. For example, the trained model is created by machine learning using a deep neural network (DNN). Such a trained model is also called a neural network computation model.

[0032] This trained model may be designed based on parameters generated by inputting training data, in which input signals corresponding to the output from pixel region 12 and labels for these input signals are linked, into a predetermined machine learning model. Furthermore, the predetermined machine learning model may be a training model utilizing a multi-layer neural network. Such a trained model is also called a multi-layer neural network model.

[0033] For example, the second signal processing unit 305 performs calculations based on the trained model stored in memory 301. The results obtained from such calculations (calculation results) are output to memory 301 or the like.

[0034] The calculation results include image data obtained by performing calculations using the trained model, and various information (metadata) obtained from that image data. The DSP14 may also incorporate a memory controller to control access to the memory 15.

[0035] The image data to be processed by the second signal processing unit 305 may be image data normally read from the pixel area 12, or it may be image data whose data size has been reduced by downsampling pixels. It may also be image data read with a smaller data size than usual by performing a readout with downsampling pixels from the pixel area 12.

[0036] Furthermore, the image data processed by the second signal processing unit 305 may also be three-dimensional distance image data. Three-dimensional distance data contains more information than two-dimensional image data, enabling high-precision object recognition and acquisition of high-precision object position information.

[0037] Thus, the memory 301 records, as needed, image data output from the horizontal scanning circuit unit 203, image data processed by the first signal processing unit 304, and calculation results obtained by the second signal processing unit 305. The memory 301 also stores the algorithm of the trained model executed by the second signal processing unit 305.

[0038] The second signal processing unit 305 can train a learning model by changing the weighting of various parameters within the learning model using training data, or it can prepare multiple learning models and change the learning model used depending on the content of the computational processing. Furthermore, the second signal processing unit 305 can acquire a trained learning model from an external device and execute the above-mentioned computational processing.

[0039] Furthermore, Figure 4 shows an example in which the memory 301, the first signal processing unit 304, and the second signal processing unit 305 are arranged in this order. However, as described above, the memory 301 stores information output from and input from the first signal processing unit 304 and the second signal processing unit 305. Therefore, it may be placed between the first signal processing unit 304 and the second signal processing unit 305. Alternatively, the second signal processing unit 305 may be placed between the memory 301 and the first signal processing unit 304.

[0040] The output unit 306 outputs image data output from the second signal processing unit 305, as well as image data and calculation results recorded in the memory 301.

[0041] Image data and calculation results output from output unit 306 are input to an application processor (not shown) that processes display and user interface. The application processor is configured using, for example, a CPU (Central Processing Unit) and executes an operating system and various application software. This application processor may also be equipped with functions such as a GPU (Graphics Processing Unit) or a baseband processor. The application processor performs various processing on the input image data and calculation results as needed, displays them to the user, and transmits them to an external cloud server via a predetermined network.

[0042] The network can be various types, such as the internet, wired LAN (Local Area Network), wireless LAN, mobile communication networks, or Bluetooth®. Furthermore, the destination for image data and calculation results is not limited to a cloud server; it can also be a single-server system, a file server for storing various types of data, or a communication terminal such as a mobile phone, or any other information processing device (system) with communication capabilities.

[0043] (APD and pixel circuitry) Figure 5 is a diagram that provides a more detailed explanation of the block diagram described in Figures 2 and 3.

[0044] In Figure 2, the photoelectric conversion unit 102 having the APD 103 is provided on the first substrate 1100, and the other components are provided on the second substrate 2100.

[0045] When light is incident on the APD103, charge pairs are generated through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD103. In addition, a voltage VH (second voltage), which is higher than the voltage VL supplied to the anode, is supplied to the cathode of the APD103.

[0046] A reverse bias voltage is supplied to the anode and cathode, causing the APD103 to perform avalanche multiplication. This voltage configuration causes the charge generated by the incident light to undergo avalanche multiplication, resulting in the generation of an avalanche current.

[0047] When a reverse bias voltage is supplied, the mode in which the anode and cathode potential difference is greater than the breakdown voltage is called Geiger mode. Conversely, the mode in which the anode and cathode potential difference is near or below the breakdown voltage is called linear mode. Of these, an APD operating in Geiger mode is called a SPAD. For example, if voltage VL (first voltage) is -30V and voltage VH (second voltage) is 1V, then the potential difference between the ground voltage (0V) and voltage VL (first voltage) is greater than the potential difference between the ground voltage and voltage VH (second voltage). Therefore, voltage VL (first voltage) is sometimes referred to as high voltage.

[0048] The quench element 211 is connected to the APD103 and a power supply that provides voltage VH. The quench element 211 has the function of converting the change in avalanche current generated in the APD103 into a voltage signal. When the signal is multiplied by avalanche multiplication, the quench element 211 functions as a load circuit (quench circuit) and suppresses the voltage supplied to the APD103, thereby suppressing avalanche multiplication (quench operation).

[0049] The signal processing unit 201 includes a waveform shaping unit 212, a circuit 213 (counter circuit), and a selection circuit 214. In this specification, the signal processing unit 201 may include any one of the waveform shaping unit 212, the circuit 213 (counter circuit), or the selection circuit 214.

[0050] The waveform shaping unit 212 shapes the potential change of the cathode of the APD103 obtained during photon detection and outputs a pulse signal. For example, an inverter circuit can be used as the waveform shaping unit 212. Figure 5 shows an example in which one inverter is used as the waveform shaping unit 212, but a circuit in which multiple inverters are connected in series may be used, or other circuits that have a waveform shaping effect may be used.

[0051] Circuit 213 (counter circuit) counts the pulse signal output from the waveform shaping unit 212 and holds the count value. When a control pulse pRES is supplied via the drive line 215, the signal held in circuit 213 (counter circuit) is reset. Since the circuit 213 (counter circuit) provided for each pixel is large in scale, it may be provided not only on the second board 2100 but also partially on the third board 3100.

[0052] The selection circuit 214 receives a control pulse pSEL from the vertical scanning circuit section 202 in Figure 3 via the drive line 216 in Figure 5, which switches the electrical connection between circuit 213 (counter circuit) and signal line 217. The selection circuit 214 includes, for example, a buffer circuit for outputting a signal.

[0053] If the quench element 211 is configured with, for example, a MOS transistor, a pulse with a clock period may be applied to the gate of this MOS transistor. In this case, a pulse with a predetermined clock period is input from a PLL (Phase Locked Loop) circuit (not shown) to the gate of the transistor constituting the quench element 211. For example, when the pulse from the PLL circuit is high level, and the quench element 211 is configured with a PMOS transistor, the quench element 211 is in the off state. In this case, no reverse bias is applied to the APD 103, and it enters non-detection mode. On the other hand, when the pulse from the PLL circuit is low level, the quench element 211 is in the on state, a reverse bias is applied to the APD 103, and it enters detection mode (standby mode). Since the clock pulse from this PLL circuit has a predetermined period, the output signal is forcibly reset with each clock period. Therefore, one photon is counted for each pulse, and even under high brightness conditions, it is possible to generate a number of signals corresponding to the number of incident photons. The PLL circuit is provided on one or more of the first board 1100, the second board 2100, and the third board 3100.

[0054] A switch such as a transistor may be placed between the quench element 211 and the APD 103, or between the photoelectric conversion unit 102 and the signal processing unit 201, to switch the electrical connection. Similarly, the supply of voltage VH or voltage VL to the photoelectric conversion unit 102 may be electrically switched using a switch such as a transistor.

[0055] The above describes a configuration in which circuit 213 is used as a counter circuit. On the other hand, instead of a counter circuit, circuit 213 may be used as a time-to-digital converter (TDC circuit) as a time measurement circuit. This constitutes a photoelectric converter 100 that acquires pulse detection timing.

[0056] At this time, the generation timing of the pulse signal output from the waveform shaping unit 212 is converted into a digital signal by the TDC circuit 213. The TDC circuit 213 is supplied with a control pulse pREF (reference signal) from the vertical scanning circuit unit 202 in Figure 3 via a drive line to measure the timing of the pulse signal. The TDC circuit 213 uses the control pulse pREF as a reference and acquires the signal as a digital signal when the input timing of the signal output from each pixel via the waveform shaping unit 212 is considered as a relative time.

[0057] The TDC circuit 213 includes, for example, an RS flip-flop, a coarse counter, and a fine counter. The drive pREF drives the light-emitting section and sets the RS flip-flop, which is reset by the signal pulses input from each pixel. This generates a signal with a pulse width corresponding to the time of flight of light. The generated signal is counted by the coarse counter and the fine counter, each having a predetermined time resolution. This results in the output of a digital code.

[0058] The PLL circuit that generates the drive pREF pulse for the TDC circuit 213 is provided on one or more of the first, second, or third boards 1100, 2100, or 3100. However, if the drive pREF pulse input to the TDC circuit is delayed, it will affect the accuracy of the information output from the TDC circuit 213. For this reason, it is preferable to provide the PLL circuit on the same board as the board on which the TDC circuit 213 is provided. For example, in this embodiment, the second board 2100 is provided with both the TDC circuit 213 and the PLL circuit that generates the pulse supplied to the TDC circuit 213.

[0059] Furthermore, the PLL circuit may also input signals to circuits provided on the third board 3100. In this case, the second board 2100 can be configured to have a PLL circuit for the TDC circuit 213, and the third board 3100 can be configured to have a PLL circuit for the circuits provided on the third board 3100. For example, it is conceivable to provide one PLL circuit on the second board 2100 and supply a pulse signal from the PLL circuit on the second board 2100 to the circuits on the third board 3100. However, in this case, the pulse signal will be supplied from the PLL circuit on the second board 2100 to the circuits on the third board 3100 via the TSV wiring connecting the second board 2100 and the third board 3100. Therefore, the wiring capacitance of the TSV wiring may affect the processing of the circuits on the third board 3100, for example, the high-speed processing of the signal processing circuit. Therefore, both a PLL circuit for the second board 2100 and a PLL circuit for the third board 3100 may be provided on each board.

[0060] Furthermore, although Figure 5 illustrates an example where the TDC circuit 213 is provided in one pixel, as will be explained later, the TDC circuit 213 may be shared by multiple pixels.

[0061] (APD operation and output signals) Figure 6 schematically shows the relationship between the operation of the APD and the output signal. Figure 6(a) is an excerpt of the APD 103, quench element 211, and waveform shaping unit 212 from Figure 5. Here, the input side of the waveform shaping unit 212 is denoted as nodeA and the output side as nodeB. Figure 6(b) shows the waveform change at nodeA in Figure 6(a), and Figure 6(c) shows the waveform change at nodeB in Figure 6(a).

[0062] Between times t0 and t1, a potential difference of VH-VL is applied to APD103 in Figure 6(a). When a photon is incident at time t1, an avalanche multiplication current flows through the quench element 211, and the voltage at nodeA drops. As the voltage drop increases further and the potential difference applied to APD103 decreases, the avalanche multiplication of APD103 stops, and the voltage level at nodeA stops dropping below a certain value. Subsequently, a current flows from voltage VL to nodeA to compensate for the voltage drop, and at time t3, nodeA settles to its original potential level.

[0063] At this point, any portion of the output waveform at nodeA that exceeds a certain threshold is reshaped by the waveform shaping unit 212 and output as a signal at nodeB.

[0064] In this embodiment, the third substrate 3100 is provided with a memory 301, control circuits 302 and 303, a first signal processing unit 304, and a second signal processing unit 305. In order to miniaturize the chip of the photoelectric converter 100, it is desirable to reduce the area of ​​the region other than the pixel region. Furthermore, since the avalanche photodiode has a pixel circuit that processes the signals of each photoelectric converter, multiple photoelectric converters are arranged on the first substrate 1100 and multiple pixel circuits are arranged on the second substrate 2100. As a result, in a plan view, the area of ​​the second substrate 2100 that overlaps with the pixel region becomes cramped, making it difficult to arrange the memory and signal processing units on the second substrate 2100. Therefore, in this embodiment, the memory and signal processing units are arranged on the third substrate 3100. The need to arrange the memory and signal processing units on the third substrate increases as the ratio of the pixel region area to the chip area of ​​the photoelectric converter increases in a plan view. For example, this need becomes particularly pronounced when the ratio of the pixel area to the chip area of ​​the photoelectric converter is 0.8 or higher.

[0065] The transistors constituting the memory and signal processing units on the third substrate 3100 are formed using a finer process than the transistors constituting the pixel circuits on the second substrate 2100. This is because these memory and signal processing units require a larger area than the pixel circuits. For example, the thickness of the gate oxide film of the transistors on the third substrate 3100 is thinner than the thickness of the gate oxide film of the transistors on the second substrate 2100. Alternatively, the gate length of the transistors on the third substrate 3100 is shorter than the gate length of the transistors on the second substrate 2100. Alternatively, the diameter of the via wiring between the interlayers of the wiring structure (third wiring structure) on the third substrate 3100 is smaller than the diameter of the via wiring between the interlayers of the wiring structure (second wiring structure) on the second substrate 2100. Alternatively, the wiring width and inter-wiring distance of the wiring structure (third wiring structure) of the third substrate 3100 are smaller than those of the wiring width and inter-wiring distance of the wiring structure (second wiring structure) of the second substrate 2100. Note that the above relationship between wiring width and inter-wiring distance is a comparison of the shortest wiring widths or the shortest inter-wiring distances on each substrate.

[0066] Furthermore, since an avalanche multiplication current flows through the quench element 211 provided on the second substrate 2100, if the quench element 211 is constructed using a MOS transistor, the thickness of the gate oxide film of this MOS transistor is increased to create a high-voltage element. For this reason, on the second substrate 2100, the process of the pixel circuit other than the quench element 211 needs to be miniaturized more than the process of the quench element 211. Regarding the device structure when the process is miniaturized, the matters described above are also provided for the quench element 211 on the second substrate and for the transistors of the other pixel circuits. For example, the thickness of the gate oxide film of the quench element 211 (MOS transistor) on the second substrate 2100 is thicker than the thickness of the gate oxide film of the transistor that constitutes a circuit other than the quench element 211 on the second substrate 2100. Furthermore, the thickness of the gate oxide film of the transistors constituting a circuit separate from the quench element 211 on the second substrate 2100 is greater than the thickness of the gate oxide film of the transistors in the circuit provided on the third substrate 3100.

[0067] Furthermore, the signal processing unit provided on the third substrate 3100 may be a processing unit using so-called "non-von Neumann" semiconductor technology, rather than a so-called "von Neumann" type processing unit.

[0068] (Connection relationships between each board) Figures 7 to 10 will be used to explain the electrical connection relationships from the first substrate to the third substrate in more detail. Figures 7 to 9 are plan views of the first substrate to the third substrate. Figure 10 is a cross-sectional view of the photoelectric conversion device 100 in which the first substrate to the third substrate are stacked.

[0069] (Cross-sectional view of a photoelectric converter) Figure 10 is a cross-sectional view of the photoelectric converter 100, in which light is incident from the upper side of Figure 10.

[0070] From the light incident side, the first substrate 1100, the second substrate 2100, and the third substrate 3100 are stacked.

[0071] The first substrate 1100 consists of a semiconductor layer 1110 (first semiconductor layer) and a wiring structure 1120 (first wiring structure) of the first substrate.

[0072] The second substrate 2100 consists of a semiconductor layer 2110 (second semiconductor layer) of the second substrate, a wiring structure 2120 (second wiring structure) of the second substrate, and a connecting layer 2130 for connecting the second wiring structure 2120 and the wiring structure 3120 (third wiring structure) of the third substrate.

[0073] The third substrate 3100 has a semiconductor layer 3110 (third semiconductor layer) and a third wiring structure 3120.

[0074] The first substrate 1100 and the second substrate 2100 are bonded together such that the first wiring structure 1120 and the second wiring structure 2120 are in contact with each other. The second substrate 2100 and the third substrate 3100 are bonded together via a connecting layer 2130 such that the second semiconductor layer 2110 and the third wiring structure 3120 are in contact with each other.

[0075] On the side of the third substrate 3100 opposite to the light incident surface, the package substrate 5120 is arranged via an insulating adhesive region 5110.

[0076] A first semiconductor region 1011 of a first conductivity type and a second semiconductor region 1012 of a second conductivity type are arranged in the first semiconductor layer 1110, forming a PN junction, and the APD103 shown in Figure 5 is constructed.

[0077] A third semiconductor region 1013 of the second conductivity type is formed on the light incident surface side of the second semiconductor region 1012. The impurity concentration in the third semiconductor region 1013 is lower than that in the second semiconductor region 1012.

[0078] Here, "impurity concentration" refers to the net impurity concentration compensated for by reverse-conductivity impurities. In other words, "impurity concentration" refers to the NET concentration. For example, the region where the doped impurity concentration of P-type is higher than that of N-type is a P-type semiconductor region. Conversely, the region where the doped impurity concentration of N-type is higher than that of P-type is an N-type semiconductor region.

[0079] Each pixel is separated by a fourth semiconductor region 1014 of the second conductivity type. Furthermore, a fifth semiconductor region 1015 of the second conductivity type is provided on the light incident side of the fourth semiconductor region 1014. The fifth semiconductor region 1015 is common to all pixels.

[0080] The fourth semiconductor region 1014 is supplied with the voltage VL (first voltage) shown in Figure 5, and the first semiconductor region 1011 is supplied with the voltage VH (second voltage) shown in Figure 5. The voltage supplied to the fourth semiconductor region 1014 and the voltage supplied to the first semiconductor region 1011 supply a reverse bias voltage to the second semiconductor region 1012 and the first semiconductor region 1011. This supplies a reverse bias voltage that causes the APD 103 to perform avalanche multiplication.

[0081] A pinning layer 1031 is provided on the light incident surface side of the fifth semiconductor region 1015. The pinning layer 1031 is a layer provided to suppress dark current. The pinning layer 1031 is formed using, for example, hafnium oxide (HfO2). The pinning layer 1031 may also be formed using zirconium dioxide (ZrO2), tantalum oxide (Ta2O5), etc. A microlens 1032 is provided on the pinning layer 1031 for each pixel. Although not shown, a color filter, a light-shielding film for a grid to optically separate each pixel, etc., may be provided between the microlens 1032 and the pinning layer 1031. The material of the light-shielding film can be any material that can block light, for example, tungsten (W), aluminum (Al), or copper (Cu) can be used.

[0082] As described above, in order to cause avalanche multiplication, a reverse bias voltage is supplied to the fourth semiconductor region 1014 and the first semiconductor region 1011. In Figure 10, the first via wiring (contact wiring) 1021a of the first substrate is electrically connected to the fourth semiconductor region 1014, and the wiring 1022a of the first wiring layer of the first substrate is electrically connected to the contact wiring 1021a. In addition, the wiring 1022a of the first wiring layer is electrically connected to wiring 1022b.

[0083] Here, the subscript 'a' after the code number indicates that it is wiring in a pixel region 12 where multiple photoelectric conversion units 102 are located. On the other hand, wiring located in areas other than the pixel region 12, or in areas other than those that overlap with the pixel region 12 in a plan view, is denoted by the subscript 'b'.

[0084] The wiring 1022a and wiring 1022b of the first wiring layer may be electrically connected via other wiring layers. Alternatively, in the first wiring layer, the wiring 1022a and wiring 1022b may be electrically connected by being formed continuously and integrally.

[0085] Wiring 1022b is electrically connected to the second via wiring 1023b of the first substrate. Via wiring 1023b is electrically connected to the joint 1040b of the first substrate. The joint 1040b of the first substrate is in contact with and electrically connected to the joint 2040b of the second substrate. This type of connection, where the joint 1040b exposed on the joint surface of the first substrate is connected to the joint 2040b exposed on the joint surface of the second substrate, is sometimes called a metal bonding (MB) structure or a metal joint. Furthermore, since this type of connection is often made between copper (Cu) materials, it is sometimes called a Cu-Cu joint (Cu-Cu bonding).

[0086] The junction 2040b of the second substrate is electrically connected to the second via wiring 2023b of the second substrate, and the second via wiring 2023b is electrically connected to the wiring 2022b of the first wiring layer of the second substrate. The wiring 2022b of the first wiring layer is electrically connected to the through-silicon via (TSV) wiring 5010. The TSV wiring 5010 is wiring that penetrates the semiconductor layer 2010 of the second substrate and the semiconductor layer 3010 of the third substrate. The TSV wiring 5010 is electrically connected to the wiring 3031 of the wiring layer on the TSV aperture side (opposite the light incident surface side) of the third substrate. The wiring 3031 is electrically connected to the electrode 5140 via the bump 5130.

[0087] Since the electrode 5140, which is electrically connected to the TSV wiring 5010, is supplied with voltage VL (first voltage), the above-described connection wiring configuration also supplies voltage VL (first voltage) to the fourth semiconductor region 1014.

[0088] On the other hand, the first semiconductor region 1011 is electrically connected to the first via wiring (contact wiring) 1021a of the first substrate, and the contact wiring 1021a is electrically connected to the wiring 1022a of the first wiring layer of the first substrate. Furthermore, the wiring 1022a of the first wiring layer is electrically connected to the second via wiring 1023a of the first substrate. The via wiring 1023a is electrically connected to the junction 1040a of the first substrate. The junction 1040a of the first substrate is in contact with and electrically connected to the junction 2040a of the second substrate. The junction 2040a of the second substrate is electrically connected to the second via wiring 2023a of the second substrate, and the second via wiring 2023a is electrically connected to the wiring 2022a of the first wiring layer of the second substrate. The wiring 2022a is electrically connected to the first via wiring (contact wiring) 2021 of the second substrate, and the contact wiring 2021 is electrically connected to the sixth semiconductor region 2011. The sixth semiconductor region 2011 is provided in the semiconductor layer 2010 of the second substrate, and each of the sixth semiconductor region 2011 is separated by an element isolation region 2012. For example, the sixth semiconductor region 2011 is part of the quench element 211. More specifically, if the quench element 211 is a MOS transistor, the sixth semiconductor region 2011 becomes the source or drain region of this MOS transistor. Although not shown in Figure 10, the second substrate 2100 is also provided with a waveform shaping unit 212, a counter circuit 213, and a selection circuit 214.

[0089] The sixth semiconductor region 2011 is electrically connected to 2022b through multiple wirings and semiconductor regions. Wiring 2022b of the first wiring layer is electrically connected to TSV wiring 5020. TSV wiring 5020 is wiring that penetrates semiconductor layer 2010 of the second substrate and semiconductor layer 3010 of the third substrate. TSV wiring 5020 is electrically connected to electrode 5140 via wiring 3031 and bump 5130.

[0090] Since the electrode 5140, which is electrically connected to the TSV wiring 5020, is supplied with voltage VH (second voltage), the first semiconductor region 1011 is also supplied with voltage VH (second voltage) due to the above connection wiring configuration.

[0091] Furthermore, the voltage supplied from the TSV wiring 5020 may be configured to supply voltage to pixel circuits such as the waveform shaping unit 212, the counter circuit 213, and the selection circuit 214. That is, the voltage VH (second voltage) becomes the drive voltage for the circuits provided on the second substrate 2100. Here, the drive voltage and the ground voltage are reference voltages, and the circuits are operated by the drive voltage and the ground voltage.

[0092] Furthermore, ground voltage may be supplied from the TSV wiring 5020 to the first board 1100 and the second board 2100. However, although the TSV wiring 5020 for the drive voltage and the TSV wiring 5020 for the ground voltage are shown in the same diagram for convenience, these are separate TSV wirings and are electrically isolated.

[0093] Furthermore, the above description shows an example in which the drive voltage for the avalanche photodiode provided on the first substrate 1100 and the drive voltage for the pixel circuit provided on the second substrate 2100 are supplied from the same TSV wiring 5020. However, it is also possible to provide a separate TSV wiring from the TSV wiring 5020 for the avalanche photodiode and configure it to supply the drive voltage to the pixel circuit provided on the second substrate 2100.

[0094] The signal line 217 shown in Figure 5 corresponds to at least a portion of the contact wiring 2021, wiring 2022a, and wiring 2022b in Figure 10, and these wirings are electrically connected to the TSV wiring 5040. The TSV wiring 5040 is electrically connected to the TSV wiring 5050 via wiring 3031. In other words, the TSV wirings 5040 and 5050 are wirings for inputting the signal output from the second board 2100 to the third board 3100.

[0095] The semiconductor layer 3010 of the third substrate shown in Figure 10 has a seventh semiconductor region 3011 formed thereon, and each of the seventh semiconductor regions 3011 is separated by an element isolation region 3012. The seventh semiconductor region 3011 constitutes transistors that make up the memory 301, the first signal processing unit 304, the second signal processing unit 305, etc. The wiring 3021 of the first via wiring (contact) of the third substrate is connected to the seventh semiconductor region 3011. Although not shown, the gate of a transistor provided on the third substrate is also connected to the wiring 3021 of the first via wiring (contact) of the third substrate. Wiring 3021 is connected to wiring 3022 of the first wiring layer of the third substrate. Note that Figure 10 only shows an example with one wiring layer, but there may be two or more wiring layers.

[0096] The wiring 3022 of the first wiring layer is electrically connected to the TSV wiring 5030. The TSV wiring 5030 is a wiring that penetrates the semiconductor layer 3010 of the third substrate. The TSV wiring 5030 is electrically connected to the electrode 5140 via wiring 3031 and bump 5130. The electrode 5140 connected to the TSV wiring 5030 is supplied with a drive voltage to a circuit provided on the third substrate. Alternatively, the TSV wiring 5030 may be a wiring that supplies a ground voltage to a circuit provided on the third substrate. However, for convenience, the TSV wiring 5030 for the drive voltage and the TSV wiring 5030 for the ground voltage are shown in the same diagram, but these are separate TSV wirings and are electrically isolated.

[0097] The TSV wiring 5020 is, for example, wiring that supplies the drive voltage to a pixel circuit provided on the second substrate 2100. Therefore, the potential of the TSV wiring 5020 may change due to the large current and voltage drop caused by avalanche multiplication. If a common TSV wiring is provided to supply the drive voltage to the second substrate 2100 and the third substrate 3100, the voltage supplied to the circuit on the third substrate 3100 may fluctuate, which may affect high-speed operation. Therefore, in this embodiment, the TSV wiring 5020 that supplies the drive voltage to the second substrate 2100 and the TSV wiring 5030 that supplies the drive voltage to the third substrate 3100 are made into separate wirings, thereby suppressing the impact on the third substrate 3100.

[0098] Furthermore, although the TSV wiring 5010, 5020, and 5030 are wirings supplied with a voltage having a predetermined voltage value from an external source, a power supply circuit that generates a voltage different from this predetermined voltage value may be provided inside the photoelectric converter 100. The power supply circuit can be provided on any one of the first board 1100, the second board 2100, the third board 3100, or on a combination of these boards.

[0099] Here, the number of wires connecting the wiring of the first wiring structure 1120 and the wiring of the second wiring structure 2120 via the bonding surface of the first substrate 1100 and the second substrate 2100 is defined as the first number of connections. Similarly, the number of wires connecting the wiring of the second wiring structure 2120 and the wiring of the third wiring structure 3120 via the bonding surface of the second substrate 2100 and the third substrate 3100 is defined as the second number of connections. In this case, the first number of connections is greater than the second number of connections. Furthermore, even focusing on the pixel region 12, the first number of connections is greater than the second number of connections.

[0100] (Connection relationship between the first and second boards) Figure 7 schematically shows the electrical connection relationship between the first substrate 1100 and the second substrate 2100 in a plan view. Pixels 101, each having a photoelectric conversion unit 102 including an APD, are arranged in a two-dimensional manner.

[0101] The connection region 121 shown in Figure 7 corresponds to the junction 1040a that electrically connects the first semiconductor region 1011 of each pixel 101 to the second substrate, as shown in Figure 10. In other words, in the pixel region 12, each pixel is electrically connected to the first substrate and the second substrate.

[0102] The wiring 161 shown in Figure 7 corresponds to the wiring 1022b in Figure 10. Furthermore, the connection area 151 corresponds to the junction 1040b which is electrically connected to the wiring 1022b in Figure 10.

[0103] The symbol 131 in Figure 7 indicates a unit (block) in which multiple pixels 101 share a predetermined circuit provided on the second substrate. For example, the predetermined circuit is a TDC circuit provided on the first substrate. That is, as shown in Figure 8 which will be explained below, in the example of Figure 7, a total of 16 pixels (4 pixels x 4 pixels) share one TDC circuit. This configuration makes it possible to reduce the area occupied by the TDC circuit on the second substrate. It also makes it possible to reduce signal timing variations within the block. For example, the TDC circuit to be placed on the second substrate is placed in the center of the block indicated by symbol 131, and the wiring from each pixel circuit is designed to be the same. This makes it possible to reduce signal timing variations due to differences in wiring layout.

[0104] Here, if a total of 16 pixels (4x4) are shared by a single TDC circuit, there are at least two possible methods.

[0105] The first method utilizes a 4x4 pixel array for imaging as a single distance-measuring pixel. Because the TDC circuit is large, it is difficult to place a separate TDC circuit for each pixel, for example, when many small pixels are arranged. Therefore, a method in which multiple pixels share one TDC circuit can be adopted. Especially in distance-measuring applications, it is not necessary to use all pixels, as in imaging photoelectric converters, and a method that aggregates and outputs signals from multiple pixels may suffice. In this case, a method in which multiple pixels share one TDC circuit is effective. Furthermore, in the case of avalanche photodiodes, there is a dead period between the incidence of one photon and the recharge. Even if the next photon occurs during this dead period in the same pixel, it cannot be detected as a signal. Therefore, configuring a 4x4 pixel array as a single distance-measuring pixel reduces count loss due to the dead period, compared to using a single pixel for each distance-measuring pixel. However, when this format is adopted, it is not possible to identify which pixel the signal originated from.

[0106] The second method involves inputting the address information of each pixel, along with the output signal from the photoelectric converter, into the TDC circuit for processing. With this method, as long as light does not incident on multiple pixels simultaneously, it is possible to identify which pixel the acquired light arrival time corresponds to.

[0107] (Connection relationship between the second and third boards) Figure 8 schematically shows the electrical connection relationship between the second substrate 2100 and the third substrate 3100 in a plan view. In Figure 8, the vertical scanning circuit section 202, the horizontal scanning circuit section 203, and the control pulse generation section 206, which were explained in Figure 3, are omitted.

[0108] The connection region 221 shown in Figure 8 corresponds to the joint 2040a that is connected to the joint 1040a shown in Figure 10. The circuit 241 is, for example, a TDC circuit, and one circuit is provided for each block 231. In the example in Figure 8, one circuit 241 is provided for each block 231 in order to process the signals output from 16 pixels. Multiple circuits 241 provided for each block row are connected by wiring 261. Each circuit 241 is provided for each block 231. Furthermore, the first circuit 241 corresponding to the first block 231 is arranged to overlap with the first block 231 in a plan view. By arranging them in this way, the physical distance between the multiple photoelectric conversion units belonging to the first block 231 and the first circuit 241 that processes the output signals from these multiple photoelectric conversion units becomes smaller, thereby suppressing signal propagation delay. Therefore, it is also possible to suppress variations in the timing of signal processing between the multiple pixels belonging to each block.

[0109] Furthermore, Figure 8 shows that a DFE242 is provided corresponding to each block row, and each DFE242 is connected to wiring 261. The output from the DFE242 is configured to be input to the third board 3100 via TSV wiring 252 (TSV wiring 5040 in Figure 10). Thus, in the second board 2100, the DFE242 is the final signal processing circuit and the circuit that outputs a signal to the third board 3100. Therefore, arranging the DFE242 on the side where the TSV wiring 252 (5040) connecting the second board 2100 and the third board 3100 is provided has the advantage of improving the efficiency of wiring routing. That is, in a plan view, when there is TSV wiring connecting the second board 2100 and the third board 3100 in a predetermined direction relative to the pixel area, the DFE242 is also provided in the same predetermined direction relative to the pixel area. Specifically, in Figure 8, the predetermined direction relative to the pixel area is downward.

[0110] Furthermore, in this embodiment, the DFE242 is provided on the second substrate 2100, but not on the third substrate 3100. Therefore, the DFE242 is provided between circuit 241 (TDC circuit), which is part of the pixel circuit, and the TSV wiring 252 (5040). When the pixel circuit and the TSV wiring 252 (5040) are connected, and the TDC circuit is provided in the subsequent stage, the capacitance added to the pixel circuit increases. This can cause signal propagation delay and lead to variations in signal processing. Therefore, by providing the DFE242 between the TDC circuit and the TSV wiring 252 (5040), the above-mentioned disadvantages are mitigated.

[0111] In Figure 8, the TSV wiring 251 (TSV wiring 5010 in Figure 10) on the second substrate 2100 is the wiring that supplies voltage VL to the APD103. Also, the TSV wiring 253 (TSV wiring 5020 in Figure 10) on the second substrate 2100 is the wiring that supplies the drive voltage to the second substrate 2100.

[0112] (Connection relationship between the third substrate and other components) Figure 9 schematically shows the electrical connection relationships between the third substrate 3100, the outside of the semiconductor device, the second substrate 2100, and the first substrate 1100 in a plan view.

[0113] Figure 9 shows the memory 301, control circuits 302 and 303, first signal processing unit 304, and second signal processing unit 305, as shown in Figure 4.

[0114] The upper part of Figure 9 shows TSV wiring 354 (TSV wiring 5030 in Figure 10) and TSV wiring 355 (TSV wiring 5020 in Figure 10). The lower part of Figure 9 shows TSV wiring 352 (TSV wiring 5030 in Figure 10), TSV wiring 355 (TSV wiring 5020 in Figure 10), and TSV wiring 354 (TSV wiring 5030 in Figure 10).

[0115] Returning to Figure 10, the junctions 1040a and 1040b of the first substrate have multiple junctions that are not electrically connected to the first semiconductor region 1011 of the first substrate 1100 or to the semiconductor region constituting the circuit of the second substrate 2100. These junctions are provided to strengthen the bond between the first substrate 1100 and the second substrate 2100. These junctions may be electrically floating, or they may be electrically connected to either the drive voltage or the ground voltage.

[0116] (Manufacturing method) Figures 11 to 13B are explanatory diagrams illustrating the manufacturing method of the photoelectric conversion device 1000 according to Embodiment 1.

[0117] Figure 11 shows the process of joining the first substrate 1100 and the second substrate 2100. Specifically, the wiring structure 1120 (first wiring structure) of the first substrate 1100 and the wiring structure 2120 (second wiring structure) of the second substrate 2100 are stacked so as to be provided between the first semiconductor layer 1010 and the second semiconductor layer 2010. In this process, the joint portion 1040 of the first substrate and the joint portion 2040 of the second substrate are joined to form a metal joint.

[0118] Figure 12 shows the process of stacking a first substrate 1100 and a second substrate 2100, and then stacking a third substrate 3100 on top of them. Specifically, the wiring structure 3020 (third wiring structure) of the third substrate is stacked so as to be provided between the second semiconductor layer 2010 and the third semiconductor layer 3010.

[0119] Here, before laminating the third substrate 3100, the second semiconductor layer 2010 of the second substrate 2100 is thinned by a thinning process. After the thinning process of the second semiconductor layer 2010, an insulating layer 2030 is provided. The insulating layer 2030 is, for example, a layer made of silicon oxide. Then, as shown in Figure 12, the third substrate 3100 is laminated onto the laminate of the first substrate 1100 and the second substrate 2100.

[0120] Figure 13A shows the wiring process for providing TSVs and the thinning process for the first substrate. Specifically, TSV wiring 5010 to 5050 are formed, and a support substrate 3050 for the third substrate is provided on the side (back side) of the third semiconductor layer 3010 of the third substrate 3100. Next, a thinning process is performed on the first semiconductor layer 1010 of the first substrate 1100, starting from the light incident side (back side). The support substrate 3050 is a necessary step in this thinning process of the first semiconductor layer 1010.

[0121] Figure 13B shows the wafer processing and mounting processes in the latter half of the process. Specifically, first, a pinning layer 1031 and a microlens 1032 are provided. Next, the support substrate 3050 for the third substrate is peeled off. This completes the wafer processing. Finally, in the mounting process, the package substrate 5120 is provided via the bumps 5130 and insulating adhesive regions 5110.

[0122] The thickness of the first substrate 1100 on which the pixels are provided is about 1 / 5 to 1 / 10 the thickness of the second substrate 2100 and the third substrate 3100. This is because the thickness of the first semiconductor layer 1110 is thinned to about 2 to 10 μm in the thinning process described above, depending on the wavelength of the light to be photoelectrically converted. The thickness of the second substrate 2100 and the third substrate 3100 is determined by the elements arranged on each substrate, but for example, if DRAM is provided as memory on the third substrate 3100, the third substrate 3100 will be constructed with a thickness of about 50 to 100 μm. The same applies when processing circuits other than memory are provided on the third substrate. Here, the number of wiring layers provided in the wiring structure 1120 of the first substrate 1100 is less than the number of wiring layers provided in the wiring structure of the substrate on which the memory or processing circuits are provided. The number of wiring layers provided in the wiring structure 1120 of the first substrate 1100 and the number of wiring layers provided in the wiring structure of the substrate on which memory and processing circuits are arranged are both approximately 5 to 10 layers. Within each wiring structure, wiring layers may have different main components. Main components include, for example, aluminum, copper, and tungsten. For example, one of six wiring layers may have an aluminum main component, while the remaining five layers may have copper main components. Furthermore, each wiring structure may have a greater number of wiring layers with different main components. For example, in the wiring structure 1120 of the first substrate 1100, the most abundant main component of each wiring layer may be copper, while in the wiring structure 2120 of the second substrate 2100, the most abundant main component of each wiring layer may be aluminum.

[0123] (Embodiment 2) Figure 14 shows the configuration of Embodiment 2. Embodiment 2 differs from Embodiment 1 in that it makes contact with the wiring structure 1120 of the first substrate.

[0124] In other words, in Embodiment 1, as shown in Figure 10, the TSV wiring 5010 was in contact with the wiring structure 2120 of the second substrate, whereas in Embodiment 2, the TSV wiring 5010 penetrates the wiring structure 2120 of the second substrate and is in contact with the wiring structure 1120 of the first substrate. Furthermore, the TSV wiring 5010 is supplied with voltage without going through the metal bonding provided between the wiring structure 1120 of the first substrate and the wiring structure 2120 of the second substrate.

[0125] Here, the voltage VL supplied to the TSV wiring 5010 is the voltage supplied to the fourth semiconductor region 1014, and is a high voltage. Furthermore, the signal processing unit 201 provided on the second substrate 2100 may be equipped with a circuit to which a fine process has been applied. Therefore, the voltage can be supplied directly to the fourth semiconductor region 1014 by the TSV wiring 5010 without going through the wiring provided in the wiring layer of the wiring structure 2120 of the second substrate. This reduces the possibility of damaging the circuit to which a fine process has been applied provided on the second substrate 2100.

[0126] (Embodiment 3) Figure 15 shows the configuration of Embodiment 3. Embodiment 3 differs from Embodiments 1 and 2 in that the electrode electrically connected to the outside is provided on the light incident side.

[0127] In other words, in embodiments 1 and 2, the electrode 5140 provided on the surface opposite to the light incident surface (first surface) (second surface) was the electrode that electrically connected to the outside. However, in embodiment 3, the electrodes 4210, 4220, and 4230 provided on the light incident side become the electrodes that electrically connect to the outside. These electrodes 4210 to 4230 are also called pad electrodes.

[0128] As described above, the voltage VL supplied to the fourth semiconductor region 1014 is high voltage, and the second substrate 2100 is provided with a circuit to which a fine process is applied. Therefore, as shown in Figure 15, if the voltage supplied from the electrode 4210 is supplied only to the first substrate 1100, it is possible to avoid applying high voltage to the circuit to which the fine process is applied, which is provided on the second substrate 2100.

[0129] Furthermore, in Figure 15, an electrode 4220 for supplying a drive voltage for the second substrate 2100 from an external source is provided in the wiring layer of the wiring structure 2120. The second substrate 2100 may contain circuits that require high-speed operation. Here, the first case is when the drive voltage is supplied to the wiring layer of the wiring structure 2120 of the second substrate via the wiring structure 1120 of the first substrate. The second case is when the voltage is supplied directly to the wiring structure 2120 of the second substrate. Compared to the first case, the wiring length from the electrode connecting to the outside to the circuit provided on the second substrate 2100 is shorter in the second case. If the wiring length is long, the operation of circuits that require high-speed operation may be slowed down due to signal propagation delay. Therefore, in this embodiment, an electrode 4220 for supplying a drive voltage for the second substrate 2100 from an external source is provided in the wiring layer of the wiring structure 2120.

[0130] Furthermore, in Figure 15, an electrode 4230 for supplying an external drive voltage for the third substrate 3100 is in contact with the wiring layer of the wiring structure 2120 of the second substrate. The electrode 4230 is electrically connected to the TSV wiring 5070 via the wiring layer of the wiring structure 2120 of the second substrate. The TSV wiring 5070 in Figure 15 corresponds to the TSV wiring 5030 in Figure 10. However, the TSV wiring 5070 in Figure 15 penetrates the semiconductor layer 2010 of the second substrate, the wiring structure 3120 of the third substrate, and the semiconductor layer 3010 of the third substrate, and is configured to be electrically connected to the TSV wiring 5030.

[0131] (Embodiment 4) Figure 16 shows the configuration of Embodiment 4. Embodiment 4 differs from Embodiment 3 in that an electrode that is electrically connected to the outside and supplies a driving voltage to the circuit of the third substrate 3100 is provided on the wiring structure 3120 of the third substrate.

[0132] The third substrate 3100 may also be equipped with circuits that require high-speed operation. Therefore, as shown in Figure 16, an electrode 4240 for supplying an external drive voltage for the third substrate 3100 can be provided in the wiring layer of the wiring structure 3120 of the third substrate. With this configuration, the wiring length from the electrode 4240 that supplies the external drive voltage to the circuits provided on the third substrate 3100 can be shortened, thereby reducing the possibility of slow operation of circuits that require high-speed operation.

[0133] When forming electrodes 4210, 4220, and 4240 shown in Figure 16, it is necessary to etch the silicon substrate or the interlayer insulating film, which is part of the wiring structure, to create pad openings. Here, since the wiring layers that the three electrodes contact are each of different heights, the opening process is required for each pad opening.

[0134] (Embodiment 5) Figure 17 shows an embodiment of Embodiment 5. Embodiment 5 differs from Embodiments 1 and 2 in that the electrode, which is electrically connected to the outside and supplies voltage to the fourth semiconductor region 1014 of the first substrate 1100, is drawn out from the light irradiation surface side.

[0135] In other words, in Embodiment 1 explained using Figure 10 and Embodiment 2 explained using Figure 14, all electrodes electrically connected to the outside were brought out from the side opposite to the light incident surface (first surface) (second surface). However, from the viewpoint of suppressing a decrease in reliability, it is preferable to configure the wiring for supplying high voltage to the first substrate 1100 to supply voltage without going through the second substrate 2100 or the third substrate 3100. For this reason, in Figure 17, electrodes 4210 are provided on the wiring layer of the wiring structure 1120 of the first substrate, so that high voltage is not supplied to the second substrate 2100 or the third substrate 3100.

[0136] (Embodiment 6) Figure 18 shows an embodiment of Embodiment 6. Embodiment 6 differs from Embodiment 1 in that the wiring structure of the second substrate and the wiring structure of the third substrate are metal bonding structures.

[0137] In other words, in Figure 10, one TSV wiring 5010 connected the electrode 5140 to the wiring layer of the wiring structure 2120 of the second substrate. In contrast, in Figure 18, a two-stage TSV wiring structure, consisting of two TSV wirings 5310 and 5320, is used to connect the electrode 5140 to the wiring structure 2120 of the second substrate. Furthermore, a metal bonding structure is provided between the TSV wirings 5310 and 5320, consisting of a connection between the junction 2050b of the second substrate and the junction 3040b of the third substrate.

[0138] Furthermore, the TSV wiring 5040 in Figure 10 is shown in Figure 18 as a two-tiered TSV wiring consisting of TSV wiring 5330 and 5340. In addition, a metal bonding structure is provided between TSV wiring 5330 and 5340.

[0139] Furthermore, the TSV wiring 5020 in Figure 10 is shown in Figure 18 as a two-tiered TSV wiring consisting of TSV wiring 5350 and 5360. In addition, a metal bonding structure is provided between TSV wiring 5350 and 5360.

[0140] With the configuration shown in Figure 18, TSV wiring that penetrates both the semiconductor layer 2010 of the second substrate and the semiconductor layer 3010 of the third substrate becomes unnecessary.

[0141] Furthermore, the pixel region is provided with a metal bonding structure consisting of a connection between the junction 2050a of the second substrate and the junction 3040a of the third substrate. This metal bonding structure does not necessarily have to constitute part of the circuitry provided on each substrate. This improves the bonding strength between the second substrate 2100 and the third substrate 3100.

[0142] (Embodiment 7) Figure 19 shows the configuration of Embodiment 7. Embodiment 7 differs from Embodiment 3 shown in Figure 15 in that the second substrate and the third substrate are electrically connected by a metal bonding structure. Furthermore, Embodiment 7 differs from Embodiment 6 shown in Figure 18 in that the electrodes connected to the outside are provided on the light incident surface (first surface) side.

[0143] As shown in Figure 19, since the junction 2050b of the second substrate and the junction 3040b of the third substrate are provided, the TSV wirings 5050 and 5040 shown in Figure 15 are functionally integrated into a single TSV wiring 5370 in Figure 19. In Figure 15, the TSV wiring 5040 penetrated both the semiconductor layer 2010 of the second substrate and the semiconductor layer 3010 of the third substrate, but according to the embodiment of Embodiment 7, such TSV wiring is unnecessary.

[0144] Furthermore, the TSV wirings 5030 and 5070 shown in Figure 15 are functionally integrated into a single TSV wiring 5380 in Figure 19. In Figure 15, the TSV wiring 5070 penetrated both the semiconductor layer 2010 of the second substrate and the semiconductor layer 3010 of the third substrate, but according to the embodiment of Embodiment 7, such TSV wiring becomes unnecessary.

[0145] Furthermore, the wiring that supplies the drive voltage to the circuit provided on the second substrate is also electrically connected to the wiring layer of the wiring structure 1120 of the first substrate via the junction 1040b of the first substrate and the junction 2040b of the second substrate. An electrode 4250 is provided on this wiring layer. The electrode 4250 is a pad portion that makes an electrical connection to the outside.

[0146] In addition, the wiring that supplies the drive voltage to the circuit provided on the third substrate is electrically connected to the wiring layer of the wiring structure 1120 of the first substrate via the junction 2050b of the second substrate and the junction 3040b of the third substrate. An electrode 4260 is provided on this wiring layer. The electrode 4260 is a pad portion that makes an electrical connection to the outside.

[0147] As described above, electrodes 4210, 4250, and 4260 are provided so as to be in contact with the same wiring layer of the wiring structure 1120 of the first substrate. Therefore, when forming the pad openings for these electrodes, the depth of the pad openings will be approximately the same. Consequently, the wiring process becomes easier compared to the example shown in Figure 15.

[0148] (Embodiment 8) Figure 20 shows the configuration of Embodiment 8. Embodiment 6 uses metal bonding to join the second substrate and the third substrate, whereas Embodiment 8 uses microbumps to join the second substrate and the third substrate.

[0149] As shown in Figure 20, the wiring structure 3120 of the third substrate is provided with a first via wiring 3021 and a first wiring layer wiring 3022 connected to it. It is also provided with a second via wiring 3023 connected to wiring 3022 and a second wiring layer wiring 3024 connected to wiring 3023. On the other hand, the wiring structure 2120 of the second substrate is provided with wiring 2060 connected to the TSV wiring 5340, and the wiring 2060 of the second substrate and the wiring 3024 of the third substrate are electrically connected via microbumps 2070. The microbumps 2070 are constructed by Cu bump bonding by solid-phase diffusion or microbump bonding by solder melting. Organic filler material is inserted into the gaps between the microbumps 2070.

[0150] (Embodiment 9) Figure 21 shows the configuration of Embodiment 9. Embodiment 1 uses TSV wiring to input the signal output from the second substrate to the third substrate, whereas Embodiment 9 uses metal bonding for this purpose.

[0151] As shown in FIG. 21, the output from the circuit provided on the second substrate 2100 is input to the circuit provided on the third substrate 3100 via the wiring 2080. A deep trench structure 2081, i.e., a DTI (Deep Trench Isolation) structure, which penetrates the semiconductor layer 2010 of the second substrate, is formed on the second substrate 2100. The trench structure 2081 is filled with an insulator 2082, avoiding an electrical connection between the wiring 2080 and the semiconductor layer 2010 of the second substrate.

[0152] In FIG. 21, it is assumed that a circuit corresponding to each pixel is provided on the second substrate 2100, and it shows that the output from the circuit corresponding to each pixel is input to the circuit of the third substrate. In this case, the wiring 2080 is provided corresponding to each pixel, and the wiring 2080 is input to the circuit of the third substrate 3100 via the joint 2050a of the second substrate, the joint 3040a of the third substrate, etc. The circuit of the third substrate 3100 is also provided corresponding to each pixel. That is, in the example of FIG. 18, the photoelectric conversion unit and the circuit of the second substrate 2100 to which a signal is input from the photoelectric conversion unit are electrically connected pixel by pixel via metal bonding. Also, the circuit of the second substrate 2100 that outputs a signal to the circuit of the third substrate 3100 and the circuit of the third substrate 3100 are electrically connected pixel by pixel via metal bonding.

[0153] In FIG. 21, the distance between adjacent wirings 2080 is indicated by L1. Here, when there are multiple distances between adjacent wirings 2080, the shortest distance is taken as L1. When the pitch between pixels is P, the relationship 0.8P < L1 < 1.2P is satisfied. Preferably, the relationship 0.9P < L1 < 1.1P is satisfied.

[0154] Here, the distance between the contact wirings 1021 connected to the first semiconductor region 1011 may be taken as the pitch P. That is, the distance between the first contact wiring connected to the first semiconductor region 1011 of the first pixel and the second contact wiring connected to the first semiconductor region 1011 of the second pixel adjacent to the first pixel may be taken as the pitch P.

[0155] In Figure 21, TSV wiring 5040 and 5050 are provided to electrically connect the second board 2100 and the third board 3100. In Figure 10 relating to Embodiment 1, TSV wiring 5040 and 5050 are wirings for inputting the signal output from the second board 2100 to the third board 3100. In this embodiment, since wiring 2080 is used as the wiring for inputting the signal output from the second board 2100 to the third board 3100, TSV wiring 5040 and 5050 do not need to be provided.

[0156] On the other hand, the circuits provided on the second substrate 2100 and the circuits provided on the third substrate 3100 may share power supply wiring or ground wiring that provides the drive voltage. In this case, the TSV wiring 5040 and 5050 shown in Figure 21 may be used to supply a common potential to the circuits provided on the second substrate 2100 and the third substrate 3100. Alternatively, metal bonding wiring having a junction 2050b of the second substrate and a junction 3040b of the third substrate may be used to supply a common potential to the circuits provided on the second substrate 2100 and the third substrate 3100.

[0157] Each circuit on the second substrate 2100, corresponding to each pixel, may be laid out so as to be translationally symmetric when viewed in a plan view. Alternatively, each circuit on the second substrate 2100, corresponding to each pixel, may be laid out so as to be line-symmetric (mirror-symmetric) when viewed in a plan view. When laid out so as to be mirror-symmetric, it is easy to share some functions and components between the first circuit on the second substrate 2100 corresponding to the first pixel and the second circuit on the second substrate 2100 corresponding to the second pixel, thereby reducing the required space. For example, the wells of the MOS transistors constituting the first and second circuits can be shared. This reduces the circuit area provided on the second substrate 2100. In particular, when providing the photoelectric conversion unit at a narrow pitch, it is possible to avoid the case where the area occupied by the circuits on the second substrate 2100 limits the provision of the photoelectric conversion unit at a narrow pitch.

[0158] Furthermore, each circuit on the third substrate 3100, which is provided for each pixel, may be laid out to be translationally symmetrical or to be lineally symmetrical (mirror symmetrical) when viewed in a planar view. In the latter case, it becomes possible to enjoy the advantages described above.

[0159] As described above, Figure 21 shows an example in which the circuit of the second board 2100 that outputs to the circuit of the third board 3100 and the circuit of the third board 3100 are provided for each pixel. However, even if the circuit of the second board 2100 that receives signals from the photoelectric conversion unit is provided for each pixel, the circuit that performs subsequent signal processing may be provided corresponding to multiple pixels. That is, one signal processing circuit of the second board 2100 is provided for each pixel block. In this case, the circuit of the second board 2100 that outputs signals to the circuit of the third board 3100 and the circuit of the third board 3100 are electrically connected via metal bonding not for each pixel, but for each pixel block. Specifically, the wiring 2080 is provided for each pixel block, not for each pixel. In this case, the number of metal bonds joining the first board 1100 and the second board 2100 is greater than the number of metal bonds joining the second board 2100 and the third board 3100.

[0160] (Embodiment 10) Figure 22 shows the configuration of Embodiment 10. The pixel structure of the photoelectric conversion unit in Embodiment 10 differs from Embodiment 1 in that the avalanche multiplication region is smaller.

[0161] In Figure 22, the width (horizontal length in the drawing) of the first semiconductor region 1011 of the first conductivity type is narrower than the width of the first semiconductor region 1011 in Figure 10. Also, although not shown, in a plan view, the area of ​​the first semiconductor region 1011 in Figure 19 is smaller than the area of ​​the first semiconductor region 1011 in Figure 10.

[0162] Furthermore, a sixth semiconductor region 1016 is provided in a position that overlaps with the first semiconductor region 1011 of the first conductivity type in a plan view. The sixth semiconductor region 1016 may be of the first conductivity type or the second conductivity type. The sixth semiconductor region 1016 is configured such that the potential for signal charges is lower than that of the second semiconductor region 1012. For example, if the sixth semiconductor region 1016 is of the first conductivity type, the impurity concentration of the sixth semiconductor region 1016 is lower than that of the first semiconductor region 1011.

[0163] By configuring such a potential structure, the charge generated in the third semiconductor region 1013 is more easily collected in the sixth semiconductor region 1016 than in the second semiconductor region 1012. The collected signal charge is multiplied in the avalanche multiplication region formed between the sixth semiconductor region 1016 and the first semiconductor region 1011.

[0164] Furthermore, seventh semiconductor regions 1017 are provided on both sides of the first semiconductor region 1011 of the first conductivity type. The conductivity type of the seventh semiconductor region 1017 may be either the first conductivity type or the second conductivity type. For example, if it is the first conductivity type, the impurity concentration of the seventh semiconductor region 1017 of the first conductivity type is lower than the impurity concentration of the first semiconductor region 1011. Also, if the seventh semiconductor region 1017 is the second conductivity type, the impurity concentration of the seventh semiconductor region 1017 is lower than the impurity concentration of the fourth semiconductor region 1014 of the second conductivity type.

[0165] By adopting this relationship of impurity concentrations, the possibility of an avalanche multiplication region being formed between the first semiconductor region 1011 and the seventh semiconductor region 1017 can be reduced.

[0166] In this embodiment, because of the above configuration, the charge generated in the third semiconductor region 1013 can be efficiently collected and avalanche multiplied, making it easier to improve the sensitivity of the photoelectric conversion unit. Furthermore, compared to Embodiment 1, the width or area of ​​the first semiconductor region 1011 is smaller, so the avalanche multiplication region can be made smaller, and thus the value of DCR (Dark Count Rate) can be reduced.

[0167] (Embodiment 11) Figures 23 to 25 show the configuration of Embodiment 11. Furthermore, Figures 1 to 6 and 10, described in Embodiment 1, also apply to the configuration of Embodiment 11. Embodiment 11 differs from Embodiment 1, in that a processing circuit is provided for each pixel block, in that a processing circuit is provided for each pixel sequence.

[0168] Figure 23 schematically shows the electrical connection relationship between the first substrate 1100 and the second substrate 2100 in a plan view. The difference from Figure 7 is that it does not show the concept of pixel blocks.

[0169] Figure 24 schematically shows the electrical connection relationship between the second substrate 2100 and the third substrate 3100 in a plan view. In Figure 8, the circuit 241 was provided corresponding to each block, but in Figure 21, the circuit 241 is provided corresponding to each pixel row. Also, in Figure 8, the circuit 21 was provided in the area overlapping with the pixel area, but in Figure 24, the circuit 21 is provided in the area not overlapping with the pixel area. That is, in Figure 24, the circuit 241 is provided in the peripheral area outside the pixel area. Here, the circuit 241 is, for example, a TDC circuit. With this configuration, heat propagation from multiple photoelectric conversion units and heat propagation from the TDC circuit do not interfere with each other, so heat propagation between the first substrate 1100 and the second substrate 2100 can be suppressed. This makes it possible to operate the photoelectric conversion device 100 stably.

[0170] The second substrate 2100 is provided with a pixel circuit region in which pixel circuits that process signals from the photoelectric conversion unit are arranged two-dimensionally. If the TDC circuit is to be placed in the pixel region, the area occupied by the pixel circuit is limited. In order to achieve high functionality of the pixel circuit, the area occupied by the pixel circuit also increases. Therefore, in order to achieve high functionality of the pixel circuit, the TDC circuit is placed in the peripheral region outside the pixel region, as in Embodiment 11. For example, if a ToF system is considered as the application, it is conceivable to provide an ambient light rejection circuit for each pixel. If the TDC circuit is placed in the peripheral region, it becomes possible to place the ambient light rejection circuit, which is a pixel circuit, in the pixel region of the second substrate 2100. This makes it possible to enhance the functionality of the pixel circuit.

[0171] Furthermore, in a plan view, it is preferable to arrange the circuit 241 (e.g., TDC circuit) such that the nearest pixel circuit to the circuit 241 is separated from the circuit 241 by 2 μm or more. In a plan view, the distance between the circuit 241 and the pixel region where the photoelectric conversion unit is located increases, and therefore the distance between the circuit 241 on the second substrate 2100 and the pixel region on the first substrate 1100 also increases. As a result, even if the pixel region on the first substrate 1100 generates heat, the thermal impact on the TDC circuit can be reduced. Conversely, even if the TDC circuit on the second substrate 2100 generates heat, the thermal impact on the photoelectric conversion unit in the pixel region of the first substrate 1100 can be reduced.

[0172] Figure 25 schematically shows the electrical connection relationship between the third substrate 3100, the outside of the semiconductor device, the second substrate 2100, and the first substrate 1100 in a plan view. The difference from Figure 9 is that the memory 301 is not provided on the third substrate 3100. Instead, in Figure 25, a third signal processing unit 309 is provided. That is, the signal output from the second substrate 2100 is processed by the third signal processing unit 309 without going through the memory. With this configuration, compared to Embodiment 1, the area for arranging the signal processing unit can be increased, making it possible to perform more computationally intensive signal processing. For example, it becomes possible to mount a trained model that performs computationally intensive calculations.

[0173] (Embodiment 12) Figures 26 to 29 show the configuration of Embodiment 12. Embodiment 12 differs from Embodiment 1 in that it feeds back the processing results of the signal processing unit provided on the third substrate to the control circuit unit on the second substrate, thereby achieving a high-precision or high-function photoelectric conversion device.

[0174] Figure 26 schematically shows the electrical connection relationship between the first substrate 1100 and the second substrate 2100 in a plan view. Reference numeral 131 indicates a unit (block) in which multiple pixels 101 share a predetermined circuit provided on the second substrate.

[0175] Figure 27 schematically shows the electrical connection relationship between the second substrate 2100 and the third substrate 3100 in a plan view. In Figure 27, the vertical scanning circuit section 202 and the horizontal scanning circuit section 203 (collectively referred to as the "scanning circuit section"), which were omitted in Figure 8 described in Embodiment 1, are shown. A control unit 243 is also provided for controlling the scanning circuit sections 202, 203, or other circuits. In Figure 27, an example is shown in which the control unit 243 controls the scanning circuit sections 202 and 203. In Figure 27, an example is shown in which control lines are provided from the scanning circuit sections 202 and 203 to the pixel circuit section for each block, but control lines may also be provided for each pixel.

[0176] The TSV wiring 254 (TSV wiring 5080 in Figure 29) is a wiring that transmits the processing results of the signal processing unit provided on the third board 3100 to the control unit 243 provided on the second board 2100. Specifically, as shown in Figure 29, the processing results of the signal processing unit on the third board 3100 are input to the control unit 243 via the TSV wiring 5090, wiring 3031, and TSV wiring 5080 (TSV wiring 254 in Figure 27).

[0177] The control unit 243 can perform various types of control.

[0178] For example, exposure can be controlled to have different exposure times for each pixel block. Specifically, within a pixel region, there may be pixel blocks that detect many photons per unit time (first pixel block) and pixel blocks that detect few photons (second pixel block). In this case, the control unit 243 can control the exposure time of the second pixel block to be longer than that of the first pixel block. This allows for an expansion of the dynamic range. For example, the control unit 243 can control the exposure time of each pixel block based on the count value of each pixel block acquired in the previous frame, which is the processing result of the signal processing unit of the third substrate 3100. The exposure time may be controlled by whether or not to apply a reverse bias to the photoelectric conversion unit in order to perform avalanche multiplication, or by whether or not to count pulses corresponding to photons with a counter.

[0179] Furthermore, when applying this photoelectric converter to a system that ensures safety and security (for example, a surveillance camera), there is a need to capture images at low resolution before an event occurs and at high resolution after an event occurs. This is because avalanche photodiodes consume a lot of power due to the high voltage applied to them, so capturing images at low resolution before an event occurs can reduce power consumption. Therefore, the signal processing unit of the third substrate 3100 can determine whether or not an event has occurred, and the control unit 243 can control the system from low-resolution mode to high-resolution mode according to the determination result. Specifically, for example, a low-resolution mode can be achieved by configuring the system to acquire photons by applying a reverse bias to only one of the four pixels in a 2x2 configuration. Then, when an event is detected, the control unit 243 can be controlled to acquire photons from all pixels in the 2x2 configuration. Whether or not an event has occurred may be determined using the second signal processing unit 305, which has a trained model created by machine learning. The events include the detection of suspicious persons and objects, the detection of more than a predetermined number of people or objects, and the prediction of collisions between moving objects. In addition, while power consumption was reduced by switching the photoelectric conversion unit as described above, power consumption could also be reduced by switching whether or not to use a counter for counting.

[0180] Furthermore, it is possible to acquire information only from the Region of Interest (ROI). For example, if there is a detected object of interest in only a part of the region, performing photoelectric conversion on the other regions would be a waste of power. Therefore, the control unit 243 controls the system to acquire information only from the region of interest. Specifically, the signal processing unit of the third substrate 3100 determines the region of interest where the detected object is located, and the control unit 243 controls the system to perform photoelectric conversion only in the region of interest and not in the regions outside the region of interest. This reduces power consumption. Alternatively, the control unit 243 may control the system so that photon counting is not performed by the counter in the region of interest, and photon counting is performed in the region of interest. In this case as well, power consumption can be reduced by stopping the counter that is not needed.

[0181] Figure 28 schematically shows the electrical connection relationship between the third substrate 3100, the outside of the semiconductor device, the second substrate 2100, and the first substrate 1100 in a plan view. The difference from Figure 9 described in Embodiment 1 is that TSV wiring 356 (TSV wiring 5090 in Figure 26) and TSV wiring 357 (TSV wiring 5080 in Figure 26) are shown. These TSV wirings are for transmitting the processing results of the signal processing unit provided on the third substrate 3100 to the control unit 243 provided on the second substrate 2100.

[0182] (Embodiment 13) Figures 30 to 42 show the configuration of Embodiment 13. Embodiment 13 differs from Embodiment 1 in that the circuit (for example, the TDC circuit) is provided on the third substrate. In Embodiment 13, the electrical connection relationship of the first substrate 1100 is the same as in Figure 26, so that will be used as a reference.

[0183] Figure 30 schematically shows the electrical connection relationship between the second board 2100 and the third board 3100 in a plan view. Control circuits 302 and 303 are omitted. A TSV wiring 254 is provided in the center of each block 231. The TSV wiring 254 (TSV wiring 5040 in Figure 32) is for inputting the output of the second board 2100 to the third board 3100.

[0184] Figure 31 schematically shows the electrical connection relationship between the second substrate 2100 and the third substrate 3100 in a plan view. The third substrate 3100 is provided with multiple signal processing blocks 331, each corresponding to one of the multiple pixel blocks 231 of the first substrate 1100 and the second substrate 2100.

[0185] Specifically, in Embodiment 13, a circuit 307 corresponding to the circuit 241 of Embodiment 1 is provided for each signal processing block. Circuit 307 is, for example, a TDC circuit. For example, if the circuit size of other circuits arranged on the second board 2100 becomes large and it is difficult to arrange the TDC circuit 307 on the second board 2100, it is also possible to provide the TDC circuit 307 on the third board 3100, as in this embodiment.

[0186] Furthermore, when the photoelectric converter 100 is used as a photoelectric converter for imaging, the counter circuit 213 can be provided on both the second substrate 2100 and the third substrate 3100. This is because, in an APD, each pixel has a counter, so the scale of the circuit constituting the counter becomes larger, and the area it occupies on the second substrate 2100 also becomes larger. In addition, in Embodiment 13, a DFE 308, which corresponds to the DFE 242 of Embodiment 1, is provided for each signal processing block 331.

[0187] Furthermore, in embodiment 13, a memory 301 is provided for each signal processing block.

[0188] In Figure 31, the output from the memory 301 provided in each signal processing block is input to the first signal processing unit 304, and the output from the first signal processing unit 304 is input to the second signal processing unit 305.

[0189] As described above, in Embodiment 13, each signal processing block is provided corresponding to each pixel block, and since signal processing can be performed in parallel by the circuit 307 (for example, the TDC circuit), high-speed signal processing becomes possible.

[0190] Furthermore, the first signal processing unit 304 and the second signal processing unit 305 may be provided within each signal processing block. Alternatively, the first signal processing unit 304 may be provided within each signal processing block, and the second signal processing unit 305 may be provided outside the area where the signal processing blocks are located, as shown in Figure 31.

[0191] (Embodiment 14) Figures 33 to 39 show the configuration of Embodiment 14. Components common to Embodiment 1 are given the same numbers and their descriptions are omitted. Embodiment 14 differs from Embodiment 1 in that it adds a fourth substrate 4100 in addition to the first substrate 1100, second substrate 2100, and third substrate 3100.

[0192] In the configuration shown in Figure 33, electrodes that are electrically connected to the outside and supply a drive voltage to the circuit of the fourth substrate 4100 are provided in the wiring structure 4120 of the fourth substrate. Electrodes that supply a drive voltage to the circuits of the first to third substrates are provided in the wiring structures of the first to third substrates, respectively. Specifically, electrode 4210 of the first substrate is provided in the wiring structure of the first substrate, electrode 4220 of the second substrate is provided in the wiring structure of the second substrate, electrode 4240 of the third substrate is provided in the wiring structure of the third substrate, and electrode 4270 of the fourth substrate is provided in the wiring structure of the fourth substrate.

[0193] Furthermore, the second board 2100 and the third board 3100, and the third board 3100 and the fourth board 4100 are electrically connected by TSV wiring. Specifically, the second board is connected to wiring 3031 of the wiring layer of the third board via bump 5040, and wiring 3031 is connected to the third board via bump 5050. The first board is connected to wiring 4031 of the wiring layer of the fourth board via bump 5060, and wiring 4031 is connected to the fourth board via bump 5100.

[0194] This configuration allows for a shorter wiring length from the electrodes supplying the drive voltage externally to the circuits on each substrate, thereby reducing the possibility of circuit operation being slowed due to signal propagation delay. Furthermore, it enables the supply of drive voltages from each electrode corresponding to the elements on each substrate.

[0195] In the configuration shown in Figure 34, electrodes are provided in the wiring structure of each board to supply a driving voltage to the circuit of each board, similar to Figure 33. However, it differs from Figure 33 in that the second board 2100 and the third board 3100, and the second board 2100 and the fourth board 4100 are connected by TSV wiring. Specifically, the third board is connected to the wiring 4031 of the wiring layer of the fourth board via bump 5150, and the wiring 4031 is connected to the fourth board via bump 5100.

[0196] In the configuration shown in Figure 35, electrodes are provided on each of the first substrate 1100, the third substrate 3100, and the fourth substrate 4100 to supply a drive voltage to the circuit of each substrate. The connection between the second substrate 2100 and the third substrate 3100, and between the third substrate 3100 and the fourth substrate 4100, is the same as in the configuration shown in Figure 34. Electrodes 4250 are provided on the first substrate 1100, and the first substrate 1100 and the second substrate 2100 are electrically connected by a joint 1040 on the first substrate and a joint 2040 on the second substrate.

[0197] In the configuration shown in Figure 36, electrodes are provided on the first substrate 1100 and the third substrate 3100 to supply drive voltage to the circuits of each substrate. The first substrate 1100 and the second substrate 2100 are electrically connected by a joint 1040 of the first substrate and a joint 2040 of the second substrate, and the third substrate 3100 and the fourth substrate 4100 are electrically connected by TSV wiring. Electrodes 4210 and 4250 are provided to contact the same wiring layer of the wiring structure 1120 of the first substrate. Similarly, electrodes 4240 and 4280 are provided to contact the same wiring layer of the wiring structure 3120 of the third substrate. Therefore, the depth of the pad openings formed when forming electrodes 4210 and 4250, or electrodes 4240 and 4270, will be approximately the same. Consequently, this configuration simplifies the wiring process.

[0198] In the configuration shown in Figure 37, the first substrate 1100 is provided with electrodes that supply a drive voltage to the circuit of the first substrate 1100. The first substrate 1100 and the second substrate 2100 are electrically connected by a joint between the junction 1040 of the first substrate and the junction 2040 of the second substrate. The second substrate 2100 and the third substrate 3100, and the second substrate 2100 and the fourth substrate 4100 are each electrically connected by TSV wiring.

[0199] In other words, electrodes 4210, 4250, 4260, and 4290 are each positioned to contact the same wiring layer of the wiring structure 1120 of the first substrate. Therefore, the depth of the pad openings formed when each electrode is formed is approximately the same. Furthermore, since it is not necessary to provide deep pad openings that penetrate from the first substrate 1100 to the wiring of the fourth substrate 4100, the wiring process becomes simpler.

[0200] In the configuration shown in Figure 38, TSV wiring is connected to each of the boards from the first to the fourth board. The wiring of the first board 1100 and the wiring 5031 of the wiring layer of the fourth board are connected via bump 5250, and the wiring of the second board 2100 and the wiring 5032 are connected via bump 5240. The wiring of the third board 3100 and the wiring 5033 are connected via bump 5230, and the fourth board 4100 and the wiring 5034 are connected via bump 5220. Since all external connection terminals can be provided on the surface side of the photoelectric converter, the area required for terminals around the pixel area is reduced, and a reduction in the area of ​​the photoelectric converter is expected.

[0201] (Embodiment 15) Figure 39 shows a cross-sectional view of the photoelectric conversion device according to Embodiment 15. Components common to Embodiment 1 are given the same numbers, and their descriptions are omitted. Embodiment 15 mainly modifies the structure of the pad electrode 4290 compared to the configuration of Embodiment 1.

[0202] The wiring structure 1120 includes a junction 1040 between the first wiring layer M1, the second wiring layer M2, the third wiring layer M3, the fourth wiring layer M4, and the first substrate. The wiring structure 2120 includes a connection 2040 between the first wiring layer M1, the second wiring layer M2, and the second substrate. Each wiring layer is a so-called copper wiring. Each wiring layer may have a mesh-like structure in plan view, for example. That is, wiring aligned in a certain direction in plan view and wiring intersecting that wiring constitute a mesh-like wiring layer.

[0203] In wiring structures 1120 and 2120, the first wiring layer includes a conductor pattern mainly composed of copper. The conductor pattern of the first wiring layer is a single damascene structure. Contacts are provided for electrical connection between the first wiring layer and the semiconductor layer 1110. The contacts are conductor patterns mainly composed of tungsten. The second and third wiring layers include conductor patterns mainly composed of copper. The conductor patterns of the second and third wiring layers are dual damascene structures and include parts that function as wiring and parts that function as vias. The fourth wiring layer is similar to the second and third wiring layers.

[0204] The pad electrode 4290 is a conductive pattern mainly composed of aluminum. The pad electrode 4290 is not a wiring structure, but is positioned in an opening in the semiconductor layer 1110. Here, the pad electrode 4290 is shown with an exposed surface between the second surface P2 and the first surface P1, but the exposed surface of the pad electrode may be located on the second surface P2.

[0205] A brief explanation of the method for forming this structure is provided. Pad openings are formed in the semiconductor layer 1110 so that a portion of the wiring layer M1 of the wiring structure 1120 is exposed. Then, an insulator 40-101 is formed to cover the second surface P2 of the semiconductor layer 1110 and the pad openings. Openings that will become vias for the pad electrodes 4290 are formed in the insulator 40-101. After forming the conductive film that will become the pad electrodes 4290, unnecessary portions of the conductive film are removed to achieve the desired pattern. Furthermore, an opening is formed in the insulator 40-102 so that the pad electrodes 4290 are exposed. This configuration can be formed in this manner.

[0206] Furthermore, through electrodes 40-104 may be provided from the second surface P2 side. The through electrodes 40-104 are made of a conductor mainly composed of copper, and may have a barrier metal between the semiconductor layer 1110 and the conductor.

[0207] A conductor 40-103 is placed on the through-electrode 40-104. The conductor 40-103 may be provided in common with other through-electrodes and may have the function of reducing the diffusion of the conductor of the through-electrode 40-104.

[0208] The materials and structures of each wiring layer in wiring structures 1120 and 2120 are not limited to those exemplified; for example, a conductor layer may be further provided between the wiring layer and the semiconductor layer. Furthermore, the contacts may have a stacked contact structure with two layers stacked.

[0209] (Embodiment 16) Figure 40 shows a cross-sectional view of the photoelectric conversion device according to Embodiment 16. Components common to Embodiment 1 are given the same numbers, and their descriptions are omitted. Embodiment 15 mainly modifies the structure of the pad electrode 4290 compared to the configuration of Embodiment 1.

[0210] The wiring structure 1120 includes a junction 1040 between the first wiring layer M1, the second wiring layer M2, the third wiring layer M3, the fourth wiring layer M4, and the first substrate. The wiring structure 2120 includes a connection 2040 between the first wiring layer M1, the second wiring layer M2, and the second substrate. Each wiring layer is a so-called copper wiring.

[0211] In wiring structures 1120 and 2120, the first wiring layer includes a conductor pattern mainly composed of copper. The conductor pattern of the first wiring layer is a single damascene structure. Contacts are provided for electrical connection between the first wiring layer and the semiconductor layer 1120. The contacts are conductor patterns mainly composed of tungsten. The second and third wiring layers include conductor patterns mainly composed of copper. The conductor patterns of the second and third wiring layers are dual damascene structures and include parts that function as wiring and parts that function as vias. The fourth wiring layer is similar to the second and third wiring layers.

[0212] The pad electrode 4300 is a conductive pattern mainly composed of aluminum. The pad electrode 4300 is provided across the second and third wiring layers of the wiring structure 1120. For example, it includes portions that function as vias connecting the first and second wiring layers and portions that function as wiring in the third wiring layer. The pad electrode 4300 is located, for example, between the second surface P1 and the fifth surface P5. The pad electrode 4300 can be provided between the second surface P2 and the fourth surface P4, or between the second surface P2 and the fifth surface P5.

[0213] The pad electrode 4300 has a first surface and a second surface opposite to the first surface. The first surface is partially exposed by an opening in the semiconductor layer. The exposed portion of the pad electrode 4300 can function as a connection portion to an external terminal, a so-called pad portion. The pad electrode 4300 is connected to multiple copper-based conductors at its second surface.

[0214] In a configuration different from this embodiment, the pad electrode 4300 may have an electrical connection on the unexposed portion of its first surface. For example, the pad electrode 4300 may have vias made of a conductor mainly composed of aluminum, and may be electrically connected through these vias to a conductor mainly composed of copper located on the first surface. Alternatively, the pad electrode 4300 may be connected to the first wiring layer of the wiring structure 1120 by a conductor mainly composed of tungsten on its first surface.

[0215] The pad electrode 4300 can be formed, for example, by first forming an insulator covering the third wiring layer, then removing a portion of the insulator, forming a film mainly composed of aluminum that will become the pad electrode 4300, and then patterning it. By forming the pad electrode 4300 after forming the copper wiring, it is possible to form a pad electrode 4300 with a thick film thickness while maintaining the flatness of the fine copper wiring.

[0216] In this embodiment, the pad electrode 4300 is shown as being included in the wiring structure 1120, but it may also be included in the wiring structure 2120. Furthermore, the position where the pad electrode is provided may be in either the wiring structure 1120 or 2120, and is not limited. The materials and structures of each wiring layer in the wiring structures 1120 and 2120 are not limited to those exemplified, and for example, there may be an additional conductor layer between the first wiring layer and the semiconductor layer. Also, there may be a stacked contact structure in which two contact layers are stacked.

[0217] The pad electrodes described in the embodiments so far are connected to the outside of the semiconductor device and are used to output signals generated within the semiconductor device to the outside, or to receive voltages supplied from the outside to drive the circuits of the semiconductor device. Since external noise such as static electricity and surge voltages are also input through the pad electrodes, a protection circuit may be placed near the pad electrodes to protect the internal circuit. The protection circuit is composed of, for example, a diode, a gate-grounded MOS, an RC trigger MOS, or a combination of these elements. The protection circuit may be placed in the area that overlaps with the pad electrodes in a plan view, or it may be placed on each substrate in accordance with the voltages that drive the elements on each of the stacked substrates and the arrangement of the pads.

[0218] (Embodiment 17) Figure 41 shows a cross-sectional view of the photoelectric converter according to Embodiment 17. Components common to Embodiment 1 are given the same numbers, and their descriptions are omitted. Embodiment 17 mainly changes the arrangement of pixels compared to the configuration of Embodiment 1.

[0219] In the embodiments described so far, TSV wiring is provided in a region that overlaps with the peripheral region 13 located outside the pixel region 12 in a plan view. However, the TSV wiring may also be provided in a region that overlaps with the pixel region 12 in a plan view. In the photoelectric conversion device according to this embodiment, since at least three semiconductor substrates are stacked, even in regions that overlap with the TSV wiring in a plan view, the influence of the voltage input and output via the TSV wiring on the pixels is reduced, and the area can be utilized efficiently.

[0220] Furthermore, pixels placed in the area overlapping with the TSV wiring in a plan view are not limited to effective pixels that output signals based on photoelectric conversion. For example, they may be OB pixels (Optical Black pixels) whose incident side is covered with a light-shielding film to prevent light from entering, or dummy pixels that are not connected to the output line and do not output signals. Dummy pixels are, for example, pixels placed between effective pixels and dummy pixels to prevent oblique light from entering the OB pixels. Since the impact on image quality is minimal even if such pixels are affected by the voltage input and output via the TSV wiring, dummy pixels can be placed in the area overlapping with the TSV wiring in a plan view to efficiently utilize the area.

[0221] The region overlapping with the TSV wiring in a plan view is not limited to photoelectric conversion elements such as the pixels described above, but may also be semiconductor elements such as transistors. By forming elements such as transistors in the semiconductor region 1110, the flatness of the substrate can be improved. The elements provided in the region overlapping with the TSV wiring in a plan view may also be protective elements having the function of the protection circuit described above.

[0222] (Embodiment 18) Figure 42 is a block diagram showing the configuration of the photoelectric conversion system 11200 according to this embodiment. The photoelectric conversion system 11200 of this embodiment includes a photoelectric conversion device 11204. Here, the photoelectric conversion device 11204 can be any of the photoelectric conversion devices described in the above embodiments. The photoelectric conversion system 11200 can be used, for example, as an imaging system. Specific examples of imaging systems include digital still cameras, digital camcorders, and surveillance cameras. In Figure 42, an example of a digital still camera is shown as the photoelectric conversion system 11200.

[0223] The photoelectric conversion system 11200 shown in Figure 42 includes a photoelectric converter 11204 and a lens 11202 that forms an optical image of the subject onto the photoelectric converter 11204. The photoelectric conversion system 11200 also includes an aperture 11203 for varying the amount of light passing through the lens 11202 and a barrier 11201 for protecting the lens 11202. The lens 11202 and aperture 11203 form an optical system that focuses light onto the photoelectric converter 11204.

[0224] The photoelectric conversion system 11200 includes a signal processing unit 11205 that processes the output signal output from the photoelectric conversion device 11204. The signal processing unit 11205 performs signal processing operations that perform various corrections and compressions on the input signal as needed before outputting it. The photoelectric conversion system 11200 further includes a buffer memory unit 11206 for temporarily storing image data, and an external interface unit (external I / F unit) 11209 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system 11200 includes a recording medium 11211 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 11210 for recording or reading from the recording medium 11211. The recording medium 11211 may be built into the photoelectric conversion system 11200 or may be detachable. In addition, communication between the recording medium control I / F unit 11210 and the recording medium 11211, and communication from the external I / F unit 11209 may be performed wirelessly.

[0225] Furthermore, the photoelectric conversion system 11200 includes an overall control and calculation unit 11208 that performs various calculations and controls the entire digital still camera, and a timing generation unit 11207 that outputs various timing signals to the photoelectric conversion device 11204 and the signal processing unit 11205. Here, the timing signals and the like may be input from an external source, and the photoelectric conversion system 11200 only needs to include at least the photoelectric conversion device 11204 and the signal processing unit 11205 that processes the output signals output from the photoelectric conversion device 11204. The overall control and calculation unit 11208 and the timing generation unit 11207 may be configured to perform some or all of the control functions of the photoelectric conversion device 11204.

[0226] The photoelectric converter 11204 outputs an image signal to the signal processing unit 11205. The signal processing unit 11205 performs predetermined signal processing on the image signal output from the photoelectric converter 11204 and outputs image data. The signal processing unit 11205 also generates an image using the image signal. The signal processing unit 11205 may also perform distance measurement calculations on the signal output from the photoelectric converter 11204. The signal processing unit 11205 and the timing generation unit 11207 may be mounted on the photoelectric converter. In other words, the signal processing unit 11205 and the timing generation unit 11207 may be provided on the substrate on which the pixels are arranged, or they may be provided on a separate substrate. By configuring an imaging system using the photoelectric converters of each embodiment described above, an imaging system capable of acquiring higher quality images can be realized.

[0227] (Embodiment 19) Figure 43 is a block diagram showing an example configuration of a distance image sensor, which is an electronic device utilizing the photoelectric conversion device described in the above embodiment.

[0228] As shown in Figure 43, the distance image sensor 12401 is configured to include an optical system 12407, a photoelectric converter 12408, an image processing circuit 12404, a monitor 12405, and a memory 12406. The distance image sensor 12401 receives light (modulated light or pulsed light) that is projected from a light source device 12409 toward the subject and reflected from the surface of the subject, thereby acquiring a distance image corresponding to the distance to the subject.

[0229] The optical system 12407 is composed of one or more lenses and guides the image light (incident light) from the subject to the photoelectric converter 12408, where it forms an image on the light-receiving surface (sensor part) of the photoelectric converter 12408.

[0230] The photoelectric converter 12408 is one of the photoelectric converters from each of the embodiments described above, and a distance signal indicating the distance obtained from the received light signal output from the photoelectric converter 12408 is supplied to the image processing circuit 12404.

[0231] The image processing circuit 12404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric converter 12408. The distance image (image data) obtained through this image processing is then supplied to the monitor 12405 for display or supplied to the memory 406 for storage (recording).

[0232] With the distance image sensor 12401 configured in this way, by applying the photoelectric conversion device described above, the characteristics of the pixels are improved, and for example, more accurate distance images can be acquired.

[0233] (Embodiment 20) The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be applied to an endoscopic surgical system.

[0234] Figure 44 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0235] Figure 44 illustrates a surgeon (physician) 13131 performing surgery on a patient 13132 on a patient bed 13133 using an endoscopic surgical system 13003. As shown in the figure, the endoscopic surgical system 13003 consists of an endoscope 13100, surgical instruments 13110, and a cart 13134 equipped with various devices for endoscopic surgery.

[0236] The endoscope 13100 consists of a barrel 13101, the tip of which is inserted into the body cavity of the patient 13132 for a predetermined length, and a camera head 13102 connected to the proximal end of the barrel 13101. In the illustrated example, the endoscope 13100 is shown as a so-called rigid endoscope having a rigid barrel 13101, but the endoscope 13100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0237] An opening into which an objective lens is fitted is provided at the tip of the endoscope tube 13101. A light source device 13203 is connected to the endoscope 13100, and the light generated by the light source device 13203 is guided to the tip of the endoscope tube by a light guide extending inside the endoscope tube 13101. This light is shone through the objective lens towards the object to be observed inside the body cavity of the patient 13132. The endoscope 13100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0238] The camera head 13102 contains an optical system and a photoelectric converter. Reflected light from the object being observed (observation light) is focused by the optical system into the photoelectric converter. The photoelectric converter converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The photoelectric converter can be any of the photoelectric converters described in the embodiments described above. The image signal is transmitted as RAW data to the camera control unit (CCU) 13135.

[0239] The CCU13135 consists of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 13100 and the display device 13136. Furthermore, the CCU13135 receives an image signal from the camera head 13102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display the image based on that image signal.

[0240] The display device 13136 displays an image based on an image signal that has been processed by the CCU 13135, under control from the CCU 13135.

[0241] The light source device 13203 consists of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 13100 when photographing the surgical area, etc.

[0242] The input device 13137 is an input interface for the endoscopic surgical system 13003. The user can input various types of information and instructions to the endoscopic surgical system 13003 via the input device 13137.

[0243] The treatment instrument control device 13138 controls the drive of the energy treatment instrument 13112 for purposes such as tissue cauterization, incision, or blood vessel sealing.

[0244] The light source device 13203, which supplies illumination light to the endoscope 13100 when photographing the surgical area, can be composed of, for example, an LED, a laser light source, or a combination thereof. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 13203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 13102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0245] Furthermore, the light source device 13203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 13102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0246] Furthermore, the light source device 13203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, the wavelength dependence of light absorption in body tissue is utilized. Specifically, by irradiating with narrowband light compared to the irradiation light used during normal observation (i.e., white light), predetermined tissues such as blood vessels on the surface of mucosa can be imaged with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light can be irradiated onto body tissue and fluorescence from the body tissue can be observed, or a reagent such as indocyanine green (ICG) can be injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent can be irradiated onto the body tissue to obtain a fluorescence image. The light source device 13203 may be configured to supply narrowband light and / or excitation light corresponding to such special light observation.

[0247] (Embodiment 21) The photoelectric conversion system and mobile unit of this embodiment will be described using Figures 45A, 45B, 46A, and 46B. Figures 45A and 45B are schematic diagrams showing an example configuration of the photoelectric conversion system and mobile unit according to this embodiment. In this embodiment, an example of an in-vehicle camera is shown as the photoelectric conversion system.

[0248] Figs. 45A and 45B show an example of a vehicle system and a photoelectric conversion system for imaging mounted thereon. The photoelectric conversion system 14301 includes a photoelectric conversion device 14302, an image preprocessing unit 14315, an integrated circuit 14303, and an optical system 14314. The optical system 14314 forms an optical image of a subject on the photoelectric conversion device 14302. The photoelectric conversion device 14302 converts the optical image of the subject formed by the optical system 14314 into an electric signal. The photoelectric conversion device 14302 is any of the photoelectric conversion devices of the above-described embodiments. The image preprocessing unit 14315 performs predetermined signal processing on the signal output from the photoelectric conversion device 14302. The function of the image preprocessing unit 14315 may be incorporated in the photoelectric conversion device 14302. At least two sets of the optical system 14314, the photoelectric conversion device 14302, and the image preprocessing unit 14315 are provided in the photoelectric conversion system 14301, and the output from each set of the image preprocessing unit 14315 is input to the integrated circuit 14303.

[0249] The integrated circuit 14303 is an integrated circuit for an imaging system application and includes an image processing unit 14304 including a memory 14305, an optical distance measurement unit 14306, a distance measurement calculation unit 14307, an object recognition unit 14308, and an abnormality detection unit 14309. The image processing unit 14304 performs image processing such as development processing and defect correction on the output signal of the image preprocessing unit 14315. The memory 14305 stores the primary storage of the captured image and the defect positions of the captured pixels. The optical distance measurement unit 14306 performs focusing and distance measurement of the subject. The distance measurement calculation unit 14307 calculates distance measurement information from a plurality of image data acquired by the plurality of photoelectric conversion devices 14302. The object recognition unit 14308 recognizes subjects such as vehicles, roads, signs, and people. When the abnormality detection unit 14309 detects an abnormality in the photoelectric conversion device 14302, it reports the abnormality to the main control unit 14313.

[0250] The integrated circuit 14303 may be implemented by dedicatedly designed hardware, software modules, or combinations thereof. It may also be implemented by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), etc., or combinations thereof.

[0251] The main control unit 14313 comprehensively controls the operations of the photoelectric conversion system 14301, vehicle sensors 14310, control unit 14320, etc. It is also possible to adopt a method where the photoelectric conversion system 14301, vehicle sensors 14310, and control unit 14320 do not have the main control unit 14313 but each has a communication interface and communicates control signals via a communication network (e.g., CAN standard).

[0252] The integrated circuit 14303 has a function of receiving a control signal from the main control unit 14313 or transmitting a control signal and set value to the photoelectric conversion device 14302 by its own control unit.

[0253] The photoelectric conversion system 14301 is connected to the vehicle sensors 14310 and can detect the running state of the host vehicle such as vehicle speed, yaw rate, steering angle, etc., as well as the state of the external environment of the host vehicle and other vehicles / obstacles. The vehicle sensors 14310 are also means for acquiring distance information to an object. In addition, the photoelectric conversion system 14301 is connected to the driving assistance control unit 1311 that performs various driving assistances such as automatic steering, adaptive cruise control, and collision prevention functions. Particularly, regarding the collision determination function, based on the detection results of the photoelectric conversion system 14301 and vehicle sensors 14310, the collision with other vehicles / obstacles is estimated and the presence or absence of a collision is determined. Thereby, avoidance control when a collision is estimated and activation of safety devices at the time of a collision are performed.

[0254] Furthermore, the photoelectric conversion system 14301 is also connected to a warning device 14312 that issues a warning to the driver based on the judgment result of the collision judgment unit. For example, if the collision judgment unit determines that there is a high probability of collision, the main control unit 14313 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 14312 warns the user by sounding an alarm, displaying warning information on a display screen such as the car navigation system or instrument panel, or vibrating the seat belt or steering wheel.

[0255] In this embodiment, the photoelectric conversion system 14301 captures images of the area around the vehicle, for example, the front or rear. Figure 45B shows an example of the arrangement of the photoelectric conversion system 14301 when it captures images of the area in front of the vehicle.

[0256] The two photoelectric converters 14302 are positioned in front of the vehicle 14300. Specifically, the center line of the vehicle 14300 with respect to its direction of movement or external shape (e.g., vehicle width) is considered as the axis of symmetry, and the two photoelectric converters 1302 are positioned symmetrically with respect to that axis of symmetry. This configuration is preferable for acquiring distance information between the vehicle 14300 and the object being photographed and for determining the possibility of collision. Furthermore, it is preferable that the photoelectric converters 14302 are positioned so as not to obstruct the driver's field of view when the driver is viewing the situation outside the vehicle 14300 from the driver's seat. The warning device 14312 is preferably positioned so as to be easily visible to the driver.

[0257] Furthermore, although this embodiment describes control to avoid collisions with other vehicles, it can also be applied to control that automatically follows other vehicles or control that automatically drives without deviating from the lane. Moreover, the photoelectric conversion system 14301 can be applied not only to vehicles such as automobiles, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0258] The photoelectric conversion device of the present invention may further be configured to acquire various types of information, such as distance information.

[0259] (Embodiment 22) Figures 46A and 46B illustrate a pair of glasses 16600 (smart glasses) according to one application example. The glasses 16600 have a photoelectric converter 16602. The photoelectric converter 16602 is the photoelectric converter described in each of the embodiments described above. In addition, a display device including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 16601. There may be one or more photoelectric converters 16602. Furthermore, multiple types of photoelectric converters may be used in combination. The arrangement position of the photoelectric converter 16602 is not limited to that shown in Figure 43(a).

[0260] The eyeglasses 16600 further include a control device 16603. The control device 16603 functions as a power source that supplies power to the photoelectric converter 16602 and the display device. The control device 16603 also controls the operation of the photoelectric converter 16602 and the display device. The lens 16601 has an optical system formed therein for focusing light onto the photoelectric converter 16602.

[0261] Figure 46B illustrates a pair of glasses 16610 (smart glasses) relating to one application example. The glasses 16610 have a control device 16612, which is equipped with a photoelectric converter equivalent to a photoelectric converter 16602 and a display device. The lens 16611 has an optical system formed therein for projecting light emitted from the photoelectric converter in the control device 16612 and from the display device, and an image is projected onto the lens 16611. The control device 16612 functions as a power supply that provides power to the photoelectric converter and the display device, and also controls the operation of the photoelectric converter and the display device. The control device may have a gaze detection unit that detects the wearer's gaze. Gaze detection may use infrared light. The infrared light emitter emits infrared light towards the eyeball of the user who is gazing at the displayed image. An imaging unit having a light-receiving element detects the reflected light from the eyeball of the emitted infrared light, thereby obtaining an image of the eyeball. By having a reduction mechanism that reduces the amount of light transmitted from the infrared light-emitting part to the display part in a planar view, the degradation of image quality is reduced.

[0262] The user's gaze towards a displayed image is detected from an image of the eyeball obtained by imaging with infrared light. Any known method can be applied to gaze detection using an image of the eyeball. As an example, a gaze detection method based on the Purkinje image obtained by the reflection of the irradiated light from the cornea can be used.

[0263] More specifically, gaze detection processing is performed based on the pupil-corneal reflection method. Using the pupil-corneal reflection method, a gaze vector representing the orientation (rotation angle) of the eyeball is calculated based on the pupil image and Purkinje image contained in the captured image of the eyeball, thereby detecting the user's gaze.

[0264] The display device of this embodiment includes a photoelectric converter having a light-receiving element, and may control the display image of the display device based on the user's gaze information from the photoelectric converter.

[0265] Specifically, the display device determines a first field of view that the user is fixated on, and a second field of view other than the first field of view, based on gaze information. The first and second field of view may be determined by the control device of the display device, or they may be determined by an external control device and received by the display device. Within the display area of ​​the display device, the display resolution of the first field of view may be controlled to be higher than the display resolution of the second field of view. In other words, the resolution of the second field of view may be lower than that of the first field of view.

[0266] Furthermore, the display area has a first display area and a second display area different from the first display area, and a higher priority area may be determined from the first and second display areas based on gaze information. The first and second view areas may be determined by the control device of the display device, or they may be determined by an external control device and received. The resolution of the higher priority area may be controlled to be higher than the resolution of the areas other than the higher priority area. In other words, the resolution of areas with relatively lower priority may be set lower.

[0267] AI may be used to determine the first field of view area and high-priority areas. The AI ​​may be a model configured to estimate the angle of gaze and the distance to the target object at the end of the line of sight from the image of the eye, using the image of the eye and the direction the eye was actually looking in that image as training data. The AI ​​program may be installed in the display device, the photoelectric converter, or an external device. If installed in an external device, it will be transmitted to the display device via communication.

[0268] When display control is based on visual detection, this method is preferably applicable to smart glasses that further include a photoelectric converter for capturing images of the surrounding environment. The smart glasses can display the captured external information in real time.

[0269] <Other Embodiments> Although the above embodiments have been described, the present invention is not limited to these embodiments, and various changes and modifications are possible. Also, the embodiments are mutually applicable. That is, a part of one embodiment can be replaced with a part of another embodiment, or a part of one embodiment can be added to a part of another embodiment. Also, it is possible to delete a part of a certain embodiment.

[0270] The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the following claims are appended to disclose the scope of the present invention.

Explanation of Reference Numerals

[0271] 1040 Joint of the first substrate 1100 First substrate 1110 First semiconductor layer 1120 First wiring structure 2040 Joint of the second substrate 2100 Second substrate 2110 Second semiconductor layer 2120 Second wiring structure 3100 Third substrate 3110 Third semiconductor layer 3120 Third wiring structure 5010, 5020, 5030, 5040, 5050 TSV wiring

Claims

1. A first semiconductor layer having multiple photoelectric conversion units and a first substrate having a first wiring structure, A second substrate having a second semiconductor layer and a second wiring structure, each of which is provided with a plurality of pixel circuits corresponding to each of the plurality of photoelectric conversion units, The third substrate has a signal processing circuit that processes output signals from the plurality of pixel circuits and a signal processing circuit that processes output signals from the plurality of pixel circuits, Each of the aforementioned photoelectric conversion units has an avalanche photodiode. The first substrate and the second substrate are stacked such that the first wiring structure and the second wiring structure are provided between the first semiconductor layer and the second semiconductor layer. The second substrate and the third substrate are stacked such that the third wiring structure is provided between the second semiconductor layer and the third semiconductor layer. A photoelectric conversion device characterized by comprising: a first through-wiring that penetrates the third semiconductor layer; a first bump electrically connected to the first through-wiring and disposed on the surface of the third semiconductor layer opposite to the side on which the third wiring structure is provided; and a semiconductor element that overlaps the first through-wiring and the first bump in a plan view.

2. The photoelectric conversion device according to claim 1, characterized in that a voltage is supplied to the first semiconductor layer via the first bump and the first through wiring.

3. The second semiconductor layer has a second through-wiring that penetrates it, The photoelectric conversion device according to claim 1 or 2, characterized in that the second through-wiring is wiring that electrically connects the wiring of the second wiring structure and the wiring of the third wiring structure.

4. The photoelectric conversion device according to claim 3, characterized in that the second through-wiring is wiring that penetrates the third semiconductor layer.

5. The photoelectric conversion device according to any one of claims 3 or 4, characterized in that the second through-wiring is formed from the surface of the third semiconductor layer opposite to the side on which the third wiring structure is provided, toward the third wiring structure.

6. The photoelectric converter according to any one of claims 3 to 5, characterized in that the second through-wiring is wiring that inputs the output signals from the plurality of pixel circuits of the second substrate to the signal processing circuit of the third substrate.

7. The photoelectric converter according to any one of claims 3 to 6, characterized in that the second through-wiring is wiring that supplies drive voltages for a plurality of pixel circuits on the second substrate and drive voltages for the signal processing circuits on the third substrate.

8. The photoelectric conversion device according to any one of claims 3 to 7, characterized in that the voltage supplied to the first through-wiring is different from the voltage supplied to the second through-wiring.

9. The photoelectric conversion device according to any one of claims 3 to 8, characterized in that it has a second bump which is electrically connected to the second through-wiring and is located on the surface of the third semiconductor layer opposite to the side on which the third wiring structure is provided.

10. The third semiconductor layer and the second semiconductor layer have a third through-wiring that penetrates them, The photoelectric conversion device according to any one of claims 1 to 9, characterized in that the third through-wiring is wiring that supplies voltage to the wiring of the second wiring structure.

11. Having a fourth through-wiring that penetrates the second semiconductor layer, The fourth through-wiring is wiring that supplies voltage to the wiring of the third wiring structure, The photoelectric conversion device according to claim 10, characterized in that the third through-wiring and the fourth through-wiring are not electrically connected.

12. A pixel region provided with a plurality of pixels having a plurality of photoelectric conversion units, and a peripheral region provided between the pixel region and the tip end of the photoelectric conversion device, The photoelectric conversion device according to any one of claims 3 to 9, characterized in that the first through-wiring is positioned to overlap the peripheral region in a plan view, and the second through-wiring is positioned to overlap the pixel region in a plan view.

13. A pixel region provided with a plurality of pixels having a plurality of photoelectric conversion units, and a peripheral region provided between the pixel region and the tip end of the photoelectric conversion device, The photoelectric conversion device according to any one of claims 3 to 9, characterized in that the first through-wiring and the second through-wiring are arranged in a position that overlaps with the peripheral region in a plan view.

14. The photoelectric conversion device according to claim 13, characterized in that the pixel region is arranged between the first through wiring and the second through wiring in a plan view.

15. The pixel region is provided with a plurality of pixels having the plurality of photoelectric conversion units, The first wiring structure has a plurality of first joints, The second wiring structure has a plurality of second joints, Each of the plurality of first joints and each of the plurality of second joints are joined to form a plurality of metal joints, The photoelectric conversion device according to any one of claims 1 to 11, characterized in that, in a plan view, each of the plurality of metal bonding portions arranged in the pixel region is provided in correspondence with each of the plurality of photoelectric conversion portions.

16. The device has a pixel region provided with a plurality of pixels having a plurality of photoelectric conversion units, and a peripheral region provided between the pixel region and the tip end of the photoelectric conversion device. The first wiring structure has a plurality of first joints, The second wiring structure has a plurality of second joints, Each of the plurality of first joints and each of the plurality of second joints are joined to form a plurality of metal joints, The photoelectric conversion device according to any one of claims 1 to 11, characterized in that the plurality of metal joints are provided in the peripheral region.

17. The pixel region is provided with a plurality of pixels having the plurality of photoelectric conversion units, The second wiring structure has a plurality of third joints, The third wiring structure has a plurality of fourth joints, The photoelectric conversion device according to any one of claims 1 to 11, characterized in that each of the plurality of third joints and each of the plurality of fourth joints are joined to form a plurality of metal joints.

18. At least one of the plurality of third junctions is electrically connected to the wiring of the first wiring structure via a third through-wiring that penetrates the second semiconductor layer. The photoelectric conversion device according to claim 17, characterized in that an insulator is provided between the third through-wiring and the second semiconductor layer.

19. The photoelectric conversion device according to any one of claims 1 to 11, characterized in that the number of first connections connecting the wiring of the first wiring structure and the wiring of the second wiring structure via the bonding surface of the first substrate and the second substrate is greater than the number of second connections connecting the wiring of the second wiring structure and the wiring of the third wiring structure via the bonding surface of the second substrate and the third substrate.

20. The pixel region has the plurality of photoelectric conversion units provided, The photoelectric conversion device according to claim 19, characterized in that the number of first connections in the pixel region is greater than the number of second connections.

21. The photoelectric conversion device according to any one of claims 1 to 20, characterized in that it has a time measurement circuit, the time measurement circuit is provided on the second substrate, and the time measurement circuit is shared by the plurality of photoelectric conversion units.

22. The photoelectric conversion device according to claim 21, characterized in that, in a plan view, the time measurement circuit shared by the plurality of photoelectric conversion units and at least a portion of the plurality of photoelectric conversion units that share the time measurement circuit are arranged in an overlapping manner.

23. The photoelectric conversion device according to any one of claims 1 to 22, characterized in that the semiconductor element is a photoelectric conversion element.

24. The photoelectric conversion device according to any one of claims 1 to 22, characterized in that the semiconductor element is a protective element.

25. A photoelectric conversion device according to any one of claims 1 to 24, A photoelectric conversion system characterized by having a signal processing unit that processes the signal output by the aforementioned photoelectric conversion device.

26. A photoelectric conversion device according to any one of claims 1 to 24, A mobile body having distance information acquisition means for acquiring distance information to an object from distance measurement information based on a signal from the aforementioned photoelectric converter, A mobile body further comprising control means for controlling the mobile body based on the distance information.

Images