MOS / MIS combined capacitor assembly

Abstract

A combined metal-oxide-semiconductor (MOS) and metal-insulator-semiconductor (MIS) capacitor assembly is provided. The capacitor assembly includes a substrate including a semiconductor material, an oxide layer formed on a surface of the substrate, and an insulator layer formed on at least a portion of the oxide layer. The capacitor assembly further includes first and second conductive terminals and a third terminal connected to the substrate. The oxide layer is connected in series between the substrate and the first conductive layer to form a first capacitor between the first terminal and the third terminal. The insulator layer is connected in series between the substrate and the second conductive layer to form a second capacitor between the second terminal and the third terminal.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 63 / 274,102, filed on November 1, 2021, which is hereby incorporated by reference in its entirety.

[0002] The subject matter of the present invention generally relates to a combined metal - oxide - semiconductor (MOS) and metal - insulator - semiconductor (MIS) capacitor.

Background Art

[0003] Semiconductor - based capacitors can offer various benefits such as temperature stability, generally high breakdown voltages, and low leakage currents. Thus, semiconductor - based capacitors may be desirable to use in a wide variety of applications, particularly those in which reliability is desired or required when subject to significant mechanical and / or environmental stress.

[0004] However, existing semiconductor-based capacitors are generally surface-mounted and occupy valuable surface area when mounted on substrates such as printed circuit boards. For example, some existing semiconductor-based capacitors are typically "flip-chip" mounted, having two terminals on a single surface of the chip. In "flip-chip" mounted capacitors, the terminals are generally coplanar, and therefore both terminals occupy space in the length and width directions to couple to the component such as the circuit board, which can increase the surface area occupied on the electronic component. This mounting configuration can be undesirable because the connection between the two coplanar terminals is required to form the capacitor, increasing the surface area that the capacitor can occupy. Furthermore, existing semiconductor-based capacitors may have limited capacitance values ​​that can be provided by individual chips.

[0005] As a result, there is a need for semiconductor-based capacitors that can offer greater versatility to enable the formation of dynamic capacitor layers within a limited area. [Overview of the Initiative] [Means for solving the problem]

[0006] The objectives and advantages of the present invention are partially described in the following description, may become apparent from the description, or may be learned through the practice of the present invention.

[0007] The present invention relates to a capacitor assembly. The capacitor assembly includes a substrate containing a semiconductor material, an oxide layer formed on the surface of the substrate, an insulating layer formed on at least a portion of the oxide layer, a first conductive layer formed on at least a portion of the oxide layer, a second conductive layer formed on at least a portion of the insulating layer, a first terminal connected to the first conductive layer, a second terminal connected to the second conductive layer, and a third terminal connected to the substrate. The oxide layer is connected in series between the substrate and the first conductive layer to form a first capacitor between the first terminal and the third terminal. The insulating layer is connected in series between the substrate and the second conductive layer to form a second capacitor between the second terminal and the third terminal.

[0008] In one particular embodiment of the capacitor assembly, the insulating layer may be formed from a dielectric material different from that of the oxide layer.

[0009] In another embodiment, the insulating layer may include a nitride layer. Furthermore, the insulating layer may include silicon nitride or silicon oxynitride.

[0010] In additional embodiments, the first and second terminals each have a length in the X direction, and the ratio of the length of the first terminal to the length of the second terminal may be about 1:1. Furthermore, the first and second terminals each have a width in the Y direction perpendicular to the X direction, and the ratio of the width of the first terminal to the width of the second terminal may be about 1:1.

[0011] In further embodiments, the third terminal may be connected to the substrate at a location spaced apart from the substrate surface in the Z direction.

[0012] In another embodiment, the first terminal may be spaced apart from the second terminal in the X and / or Y directions.

[0013] In yet another embodiment, the insulating layer can cover a first portion of the oxide layer, which is separate from a second portion of the oxide layer that lacks the insulating layer.

[0014] In additional embodiments, the first terminal may include a conductive material that is in direct contact with the oxide layer.

[0015] In further embodiments, the first terminal may include a conductive material that is in direct contact with the insulating layer.

[0016] In another embodiment, the semiconductor material of the substrate may include silicon.

[0017] In additional embodiments, the oxide layer may include silicon dioxide.

[0018] In another embodiment, the first terminal and the second terminal may have the same shape and size, the first capacitor may have a first capacitance value, the second capacitor may have a second capacitance value, and the first capacitance value and the second capacitance value do not have to be equal.

[0019] In further embodiments, the capacitor assembly may include additional terminals formed on the oxide or insulating layer. Furthermore, the additional terminals may be spaced apart from both the first and second terminals.

[0020] The present invention further relates to a method for forming a capacitor assembly. The method includes the steps of: forming an oxide layer on the surface of a substrate containing a semiconductor material; forming an insulating layer on at least a portion of the oxide layer; depositing a first conductive layer on at least a portion of the oxide layer; depositing a second conductive layer on at least a portion of the insulating layer; depositing a first terminal on the first conductive layer; and depositing a second terminal on the second conductive layer.

[0021] In one particular embodiment, the step of forming the insulator layer can include forming the insulator layer within a first portion of the surface of the oxide layer that is separate from a second portion of the oxide layer that includes the first terminal, and the step of depositing the first terminal can include depositing the first terminal within the second portion of the oxide layer. Further, the step of forming the insulator layer can include etching the insulator layer within the first portion of the oxide layer. Moreover, the step of forming the insulator layer can include masking the second portion of the oxide layer and forming the insulator layer over the first portion of the oxide layer.

[0022] In another embodiment, the method can further include depositing an additional terminal over at least a portion of the oxide layer or the insulator layer, and the additional terminal can be spaced apart from the first terminal and the second terminal.

[0023] These and other features, aspects, and advantages of the present invention will be better understood when the following description and the appended claims are considered. The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.

[0024] A complete and operable disclosure of the present invention, including the best mode thereof, directed to one of ordinary skill in the art, is set forth herein and reference is made to the accompanying drawings.

Brief Description of the Drawings

[0025] [Figure 1] A perspective view of a combined MIS / MOS capacitor assembly according to one particular embodiment of the present invention [Figure 2] A top view of the capacitor assembly of FIG. 1. [Figure 3] A cross-sectional view of the capacitor assembly of FIG. 1 taken along line 3-3 shown in FIG. 2. [Figure 4]It is a circuit diagram of the capacitor assembly of FIG. 1. [Figure 5] It is a top view of the capacitor assembly according to another embodiment of the present invention. [Figure 6] It is a circuit diagram of the capacitor assembly of FIG. 5.

Embodiments for Carrying Out the Invention

[0026] Next, reference to embodiments of the present invention will be made in detail, and one or more examples thereof are illustrated in the drawings. Each example is provided as an illustration of the present invention, not as a limitation of the present invention. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope or spirit of the present invention. For example, features illustrated or described as part of one embodiment can be used with another embodiment and can lead to further embodiments. Accordingly, the present invention is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.

[0027] As used herein, the terms "about," "substantially," or "generally" when used to modify a value indicate that the value can be within the disclosed embodiments even if increased or decreased by up to 5%. Further, when multiple ranges are provided, any combination of the minimum and maximum values described in those multiple ranges is contemplated by the present invention. For example, if ranges of "about 20% to about 80%" and "about 30% to about 70%" are described, ranges of "about 20% to about 70%" or "about 30% to about 80%" are also contemplated by the present invention.

[0028] In general, the present invention relates to capacitor assemblies comprising combined metal-oxide-semiconductor (MOS) capacitors and metal-insulator-semiconductor (MIS) capacitors. A combined MOS / MIS capacitor assembly can enable a single chip to have capacitors of different values ​​on the same chip while maintaining a feasible bond pad size.

[0029] MOS / MIS combined capacitor assemblies may include substrates containing semiconductor materials such as silicon, gallium arsenide, germanium, silicon carbide, strontium titanate, and / or mixtures thereof. The substrates may be doped with one or more suitable dopants such as boron, arsenic, phosphorus, gallium, aluminum, indium, and antimony.

[0030] The substrate may have a first end and a second end spaced apart from the first end in the longitudinal direction which is perpendicular to the transverse direction, and both the transverse and longitudinal directions are perpendicular to the vertical Z direction. The substrate may have a top surface and a bottom surface opposite the top surface in the Z direction.

[0031] The surface of the substrate may generally be smooth. For example, the surface of the substrate may be free of holes, trenches, etc. The oxide layer may have a generally uniform thickness on the surface of the oxide layer. For example, the thickness of the oxide layer may vary by less than 20%, less than 10% in some embodiments, and less than 5% in some embodiments across the oxide layer. As used herein, the terms “generally” and “generally smooth” or “generally equal” do not necessarily mean that the characteristics are strictly or perfectly smooth or equal, and small differences may be tolerable when each layer is uniformly connected to adjacent layers in a capacitor assembly and / or when mounted on a substrate such as a circuit board.

[0032] As used herein, the first layer "formed on" the second layer may refer to a first layer positioned on the second layer with respect to the thickness direction (i.e., the z-direction) of the monolithic substrate. The first layer may be in direct contact with the second layer. However, an intermediate layer may be formed between the first and second layers so that they do not come into direct contact with each other.

[0033] A MOS / MIS combined capacitor assembly may include an oxide layer formed on the surface of a substrate, for example, on the top surface of the substrate. The oxide layer may be or include an oxide of silicon oxide (SiO2) and / or other exemplary semiconductor materials described herein. The oxide layer may be grown in situ on the substrate. Lithography (e.g., photolithography) techniques may be used to define the shape of the oxide layer, if desired. For example, portions of the oxide layer may be removed by etching so that the oxide layer is shaped as required.

[0034] A combined MOS / MIS capacitor may include at least an insulating layer formed from a dielectric material on at least a portion of an oxide layer. The insulating layer may be or include, but is not limited to, silicon nitride and / or silicon oxynitride (SiON), other electrical insulating materials described herein. The insulating layer may be formed on a first portion of the oxide layer, separate from a second portion of the oxide layer that does not have an insulating layer. Lithography (e.g., photolithography) techniques may be used to define the shape of the insulating layer, if desired. For example, portions of the insulating layer may be removed by etching so that the insulating layer is shaped as required and to expose at least a portion of the oxide layer beneath the insulating layer.

[0035] The reliability of a capacitor can be improved by providing an insulating layer formed on top of an oxide layer. In particular, any potential defects in the oxide layer and / or the insulating layer, such as pores, are less likely to be aligned in the Z direction. For example, the insulating layer can cover or fill any defects, holes, or imperfections in the surface of the oxide layer. As a result, forming an insulating layer on top of at least a portion of the oxide layer can reduce the likelihood of the capacitor short-circuiting. Thus, as described above, the capacitance value of the capacitor can be increased by providing an insulating layer formed on top of the oxide layer. For example, the capacitance value can be increased by up to 1.5 times when the insulator is formed on top of the oxide layer.

[0036] A MOS / MIS combination capacitor may include a first conductive layer formed on at least a portion of an oxide layer. The first conductive layer may be contained within the outer periphery of the oxide layer. The first conductive layer may not have direct contact and / or direct electrical connection with the substrate, nor with the insulating layer. The conductive layer may be or may contain a metal, such as aluminum, copper, gold, silver, nickel, or a mixture thereof.

[0037] A MOS / MIS combination capacitor may include a second conductive layer formed on at least a portion of the insulating layer. The second conductive layer may be contained within the outer periphery of the insulating layer. The second conductive layer may not have direct contact and / or direct electrical connection with the substrate, nor with the oxide layer. The conductive layer may be or contain a metal, such as aluminum, copper, gold, silver, nickel, or a mixture thereof.

[0038] One or more protective layers may be formed on the surface of the substrate. When the capacitor is surface-mounted, the terminals may be exposed through the protective layer for electrical connection. Exemplary materials for the protective layer include benzocyclobutene (BCB), polyimide, silicon oxynitride, Al2O3, SiO2, Si3N4, epoxy, glass, or other suitable materials.

[0039] The capacitor assembly of the present invention may be formed as a thin-film capacitor assembly, in other words, having one or more thin-film layers. For example, a conductive layer, an oxide layer, and an insulating layer may each be formed as a thin-film layer. The thin-film components may be formed from a variety of suitable materials. The thin-film capacitor may include one or more conductive layers. The conductive layers may include a variety of suitable conductive materials. Exemplary conductive materials include copper, nickel, gold, tin, lead, palladium, silver, and alloys thereof. However, any conductive metal or non-metallic material suitable for thin-film fabrication may be used.

[0040] Various thin-film techniques can be used to form thin-film layers, such as conductive layers, insulating layers, and terminals. Examples of such techniques that may be employed include chemical deposition (e.g., chemical vapor deposition), physical deposition (e.g., sputtering), or any other suitable deposition technique for forming thin-film elements. Additional examples include any suitable patterning technique (e.g., photolithography), etching, and any other suitable subtractive technique for forming thin-film elements.

[0041] The thin film layer can have a thickness within a range. For example, the thin film layer can have a thickness ranging from about 0.0375 micrometers (microns) to about 40 microns, in some embodiments from about 0.1 microns to about 30 microns, in some embodiments from about 0.2 microns to about 20 microns, and in some embodiments from about 0.4 microns to about 10 microns.

[0042] Thin film components can be precisely formed using a variety of suitable subtractive, semi-additive, or fully additive processes. For example, physical vapor deposition and / or chemical deposition may be used. For example, in some embodiments, thin film components can be formed using sputtering, a certain type of physical vapor deposition. However, a variety of other suitable processes may be used, including, for example, plasma-enhanced chemical vapor deposition (PECVD), electroless plating, and electroplating. Lithography masks and etching may be used to produce the desired shape of the thin film component. A variety of suitable etching techniques may be used, including dry etching and / or wet etching using plasma of reactive or non-reactive gases (e.g., argon, nitrogen, oxygen, chlorine, boron trichloride).

[0043] A MOS / MIS combination capacitor may include a first terminal connected to a first conductive layer. A second terminal may be connected to a second conductive layer. As used herein, “connected to” may refer to components that are in direct physical contact. “Connected to” may also refer to items that are physically connected by one or more intermediate conductive layers such that the items are in direct electrical contact (e.g., without a resistive or dielectric layer between them). The first terminal may be formed on the first conductive layer. The second terminal may be formed on the second conductive layer. For example, the first and second terminals may be coupled to their respective first and second conductive layers and, for example, in direct contact with their respective first and second conductive layers. The first and second terminals may be contained within the outer periphery of their respective first and second conductive layers.

[0044] Each of the first and second terminals may be exposed along the surface of the substrate. Each of the first and second terminals may be configured to provide a wire bond terminal.

[0045] A MIS / MOS combined capacitor assembly may have a third terminal connected to the opposite surface of the substrate in the Z direction, for example, the surface of a substrate on which an oxide layer is formed. The third terminal may be connected to ground or may function as ground on the back surface of the substrate. Both the first and second terminals may be spaced apart from the third terminal of the substrate in the Z direction. The third terminal may be formed by the bare surface of the substrate. Additionally or alternatively, the third terminal may include a third conductive layer formed on the opposite surface of the substrate in the Z direction, from the surface of the substrate on which the oxide layer is formed.

[0046] The capacitor assembly may be connected or arranged such that the insulating layer covers less than all of the surface of the oxide layer. For example, the insulating layer and the first terminal may be spaced apart from the second terminal in the X direction. The edges of the insulating layer may be aligned with the Y direction which is perpendicular to the X direction. Optionally, the edges of the oxide layer may be spaced apart from the edges of the substrate in the X and / or Y directions, and the edges of the insulating layer may be spaced apart from the edges of the substrate in the X and / or Y directions.

[0047] The first terminal may be connected to the oxide layer at a location spaced apart from the insulating layer along the surface of the substrate. For example, the first terminal may be positioned between the edge of the insulating layer and the edge of the substrate. The edge of the insulating layer may be spaced apart from the first terminal by a distance longer than about 2 microns, longer than about 5 microns in some embodiments, longer than about 10 microns in some embodiments, and longer than about 15 microns in some embodiments.

[0048] The insulating layer may cover a first portion of the oxide layer, separate from a second portion of the oxide layer that lacks the insulating layer. The first terminal may be connected to the oxide layer within the second portion of the oxide layer. The first terminal may include a conductive material that is in direct contact with the oxide layer.

[0049] The substrate may have a pair of end faces perpendicular to the surface of the monolithic substrate. The pair of end faces may include terminals, or may not have terminations. As a further example, a first terminal, a second terminal, or both may be spaced apart from the pair of opposing edge faces on the surface of the monolithic substrate by their respective distances. The distance may be 10 microns or more, 15 microns or more in some embodiments, 20 microns or more in some embodiments, 40 microns or more in some embodiments, and 50 microns or more in some embodiments.

[0050] A first capacitor C1 may be formed between the first terminal and the third terminal. A second capacitor C2 may be formed between the second terminal and the third terminal. Due to the presence of an insulating layer beneath the second terminal, the first capacitor C1 and the second capacitor C2 may have different capacitance values. On the other hand, depending on the area of ​​the capacitor chip described above, as well as additional factors including the dielectric constant and properties of the material used to form each capacitor, each capacitor can maintain a capacitance value in the range between about 0.1 pF and about 1800 pF, such as from about 1 pF to about 1500 pF, for example, from about 10 pF to about 1000 pF.

[0051] While the embodiments of the capacitor assembly described above include only a first terminal formed on an oxide layer and a second terminal formed on an insulating layer, the present invention intends to use any number of terminals to form any number of n capacitors, where n is greater than or equal to 2. For example, to achieve a desired capacitance for a capacitor assembly, two or more terminals may be formed on the oxide layer, and two or more terminals may be formed on the insulating layer.

[0052] A method for forming a capacitor assembly may include the steps of: forming an oxide layer on the surface of a substrate containing a semiconductor material; forming an insulating layer on at least a portion of the oxide layer; depositing a first conductive layer on at least a portion of the oxide layer; depositing a second conductive layer on at least a portion of the insulating layer; depositing a first terminal on the first conductive layer; and depositing a second terminal on the second conductive layer.

[0053] Specific features of the capacitor assembly of the present invention can be better understood by referring to Figures 1 to 6.

[0054] Figure 1 is a perspective view of a capacitor assembly 100 according to an aspect of the present disclosure. The capacitor assembly 100 may include a substrate 102 containing a semiconductor material, such as silicon. The capacitor assembly 100 may include an oxide layer 104 formed on the surface 106 of the substrate 102. The capacitor assembly 100 may include a first conductive layer 108 formed on at least a portion of the oxide layer 104. The first conductive layer 108 may be contained within the outer periphery 110 of the oxide layer 104. The first conductive layer 108 may not have direct contact with and / or direct electrical connection to the substrate 102.

[0055] The capacitor assembly may further include an insulating layer 112, such as silicon nitride or silicon oxynitride, formed on at least a portion of the oxide layer 104. The capacitor assembly 100 may include a second conductive layer 114 formed on at least a portion of the insulating layer 112. The second conductive layer 114 may be contained within the outer periphery 116 of the insulating layer 112. The second conductive layer 114 may not have direct contact and / or direct electrical connection with the substrate 102, nor with the oxide layer 104.

[0056] A first terminal 116 may be connected to a first conductive layer 108. A second terminal 118 may be connected to a second conductive layer 114. Each of the first terminal 116 and the second terminal 118 may be exposed along the surface 106 of the substrate 102. The first terminal 116 may be coplane with the insulating layer 112. For example, each of the first terminal 116 and the insulating layer 112 may be formed exclusively on the oxide layer 104.

[0057] The first terminal 116 may be spaced apart from the second terminal 118 in the X direction 10 and / or the Y direction 20. The edge 156 of the insulating layer 112 may be aligned with the Y direction 20 which is perpendicular to the X direction 10. Additionally, the edge 160 of the insulating layer 112 may be aligned with the X direction 10 which is perpendicular to the Y direction 20.

[0058] The first terminal 116 may be connected to the oxide layer 104 at a location spaced apart from the insulating layer 112 along the surface 106 of the substrate 102. For example, the first terminal 116 may be positioned between the edge 156 of the insulating layer 112 and the edge 122 of the substrate 102. The edge 156 of the insulating layer 112 may be spaced a distance of 158 from the first terminal 116. In some embodiments, the distance 158 may be longer than about 2 microns.

[0059] The substrate 102 may be a monolithic substrate including the surface 106 described above. The surface 106 may be the top surface of the substrate 102. The substrate 102 may include a first side surface 120 and a second side surface 122, each extending parallel to the X direction 10. The substrate 102 may include a first edge 124 and a second edge 126, each extending parallel to the Y direction 20. The top surface 106 may extend between the first side surface 120 and the second side surface 122 in the X direction 10, and between the first edge 124 and the second edge 126 in the Y direction 20. The substrate 102 may further include a bottom surface 128, in other words, a back surface, extending parallel to the top surface 106 in the vertical Z direction. The bottom surface 128 may extend between the first side surface 120 and the second side surface 122 in the X direction 10, and between the first edge 124 and the second edge 126 in the Y direction 20.

[0060] The capacitor assembly 100 may include a third terminal 130 on the bottom surface 130 of the substrate 102. The third terminal 130 may be formed by the bare material of the bottom surface 130 of the semiconductor substrate 102. As an addition or alternative, the third terminal 130 may be formed from a layer 132 of conductive material formed on the bottom surface 128 of the substrate 102 opposite the top surface 106 in the Z direction. The third terminal 130 may be connected to earth or may function as earth on the back surface of the substrate.

[0061] The oxide layer 104 may be formed exclusively on the upper surface 106 of the substrate 102. For example, the oxide layer 104 may be formed within a portion 134 of the surface 106. The portion 134 may extend across the entire upper surface 106, in other words, from the first side surface 120 to the second side surface 122, from the first edge 124 to the second edge 126, or across any portion thereof. The oxide layer 104 may have a length 140 in the X direction 10 and a width 142 in the Y direction 20.

[0062] The insulating layer 112 may be formed on a first portion 136 of the oxide layer 104. The first portion 136 may be separate from a second portion 138 of the oxide layer 104 that does not have the insulating layer 112. The insulating layer 112 may have a length 144 in the X direction 10 and a width 146 in the Y direction 20. The length 144 and / or width 146 of the insulating layer 112 may be less than the respective lengths 140 and / or widths 142 of the oxide layer 104. In other words, only one of the lengths 144 or widths 146 of the insulating layer 112 may be equal to the respective lengths 140 or widths 142 of the oxide layer 104. In the example of the capacitor assembly 100 shown in Figures 1 and 2, the length 144 of the insulator layer 112 in the X direction 10 is less than the length of the oxide layer 104, and the width 146 of the insulator layer 112 is less than or approximately equal to the width 142 of the oxide layer 104. However, it should be understood that in other aspects of the invention, the lengths 144 and 140 may be approximately equal when the width 146 of the insulator layer 112 in the Y direction is less than the width 142 of the oxide layer 104 in the Y direction. In further aspects of the invention, both the length 144 and width 146 of the insulator layer 112 may be less than the length 140 and width 142 of the oxide layer 104. The dimensions of the length 140 and width 142 of the insulator layer 112 relative to the oxide layer 104 may be sufficient to allow a second portion 138 of the oxide layer 104 to contain the first terminal 116 thereon.

[0063] As shown in Figures 1 and 2, the first conductive layer 108 and the first terminal 116 may be formed within a second portion 138 of the oxide layer 104. The first terminal 116 and the second terminal 118 may be separated from each other in the X direction 10 and / or the Y direction 20. The first terminal 116 may have a length of 148 in the X direction and a width of 150 in the Y direction. The second conductive layer 114 and the second terminal 118 may be formed on top of the insulating layer 112. The second terminal 118 may have a length of 152 in the X direction and a width of 154 in the Y direction.

[0064] In some aspects of the present invention, the first terminal 116 and the second terminal 118 may have the same shape and size. In other words, the length 148 may be substantially equal to the length 152, and the width 150 may be substantially equal to the width 154. In other words, the ratio of length 148 to length 152 may be about 1:1, and the ratio of width 150 to width 154 may be about 1:1. In such a configuration, the capacitor assembly 100 may include a first capacitor formed between the first terminal 116 and the third terminal 130, and a second capacitor formed between the second terminal 118 and the third terminal 130, where the first capacitor and the second capacitor have different capacitance values. The first capacitor and the second capacitor have different capacitance values ​​due to the presence of an insulating layer 112 in the second capacitor.

[0065] Furthermore, the first terminal 116 and the second terminal 118 may have different dimensions as desired. In other words, the length 148 may be different from the length 152, and / or the width 150 may be different from the width 154. Such a configuration may be intended to allow the first capacitor formed between the first terminal 116 and the third terminal 130 and the second capacitor formed between the second terminal 118 and the third terminal 130 to be selected more precisely based on the desired capacitance value of the capacitor assembly 100.

[0066] Figure 4 illustrates the circuit diagram of the capacitor assembly 100 shown in Figures 1 to 3. The circuit diagram shows a first capacitor C1 connected to the first terminal 116 and a second capacitor C2 connected to the second terminal 118. Both the first capacitor C1 and the second capacitor C2 are connected to the third terminal 130, in other words, to the same ground port.

[0067] Figure 5 illustrates a capacitor assembly 200 of another embodiment of the present invention. The capacitor assembly 200 may include a substrate 202 containing a semiconductor material, such as silicon. The capacitor assembly 200 may include an oxide layer 204 formed on the surface of the substrate 202. The capacitor assembly 200 may include a conductive layer (not shown) formed on at least a portion of the oxide layer 204. The conductive layer may be contained within the outer periphery of the oxide layer 204. The conductive layer may not have direct contact with the substrate 202 and / or direct electrical connection. One or more terminals may be connected to the conductive layer. For example, as shown, a first terminal 206, a second terminal 208, a third terminal 210, and a fourth terminal 212 may be formed on the oxide layer 204 connected to the conductive layer (not shown). As illustrated in Figure 5, terminals 206, 208, 210, and 212 may have various dimensions in the X direction 10 and / or Y direction 20.

[0068] The capacitor assembly 200 may further include an insulating layer 214, such as silicon nitride or silicon oxynitride, formed on at least a portion of the oxide layer 204. The capacitor assembly 200 may also include a conductive layer (not shown) formed on at least a portion of the insulating layer 214 and contained within the outer periphery of the insulating layer 214. The conductive layer formed on the insulating layer 214 may not have direct contact and / or direct electrical connection with the substrate 202, nor with the oxide layer 204. One or more terminals may be connected to the conductive layer formed on the insulating layer 214. For example, a fifth terminal 216 may be connected to the conductive layer formed on the insulating layer 214.

[0069] Each of terminals 206, 208, 210, 212, and 216 may be exposed along the surface of the substrate 202. Terminals 206, 208, 210, and 212 may be coplane with the insulating layer 214. For example, each of terminals 206, 208, 210, and 212 and the insulating layer 214 may be formed exclusively on the oxide layer 204.

[0070] The first terminal 116 may be spaced apart from the second terminal 118 in the X direction 10 and / or the Y direction 20. The edge 156 of the insulating layer 112 may be aligned with the Y direction 20 which is perpendicular to the X direction 10. Additionally, the edge 160 of the insulating layer 112 may be aligned with the X direction 10 which is perpendicular to the Y direction 20.

[0071] Figure 6 illustrates the circuit diagram of the capacitor assembly 200 of Figure 5. As shown in Figure 6, the first capacitor C1 is coupled to a fifth terminal 216 formed on the insulating layer 214. The second capacitor C2 is coupled to the first terminal 206, the third capacitor C3 is coupled to the second terminal 208, the fourth capacitor C4 is coupled to the third terminal 210, and the fifth capacitor C5 is coupled to the fourth terminal 212. Each of the capacitors C1, C2, C3, C4, and C5 is coupled to a common ground terminal formed by, for example, the substrate 202. As shown in Figure 6, each of the capacitors C1, C2, C3, C4, and C5 may have different capacitance values, for example, determined by the area of ​​the capacitor and the dielectric material, respectively. As illustrated in Figure 5, the various dimensions of terminals 206, 208, 210, and 212, and therefore the area, can result in different capacitance values ​​for each respective capacitor. The capacitance values ​​shown in Figure 6 are just one example of the various capacitance values ​​intended by the capacitor assembly of the present invention, and represent only a non-limiting embodiment of the present invention.

[0072] This specification uses examples to disclose the invention, including in the best mode, and to enable a person skilled in the art to practice the invention, including by fabricating and using any device or system and by carrying out any incorporated method. The patentable scope of the invention is defined by the claims and may include other examples that a person skilled in the art can recall. Such other examples are intended to be within the claims if they include structural elements that are no different from the language of the claims, or if they include equivalent structural elements that have only minor differences from the language of the claims. [Explanation of Symbols]

[0073] 3 wires 10X direction 20 Y direction 100 Capacitor Assembly 102 circuit boards 104 Oxide layer 106 Surface / Top surface 108 First conductive layer 110 Outer circumference 112 Insulator layer 114 Conductive layer 116 First terminal 118 Second terminal 120 First Aspect 122 Second Aspect 124 First edge 126 Second edge 128 Base 130 Third terminal 132 layers 134 parts 136 Part 1 138 Part 2 140 Length 142 width 144 Length 146 width 148 Length 150 width 152 Length 154 width 156 Edge 158 distance 160 Edge 200 Capacitor Assembly 202 circuit boards 204 Oxide layer 206 First terminal 208 Second terminal 210 Third terminal 212 Fourth terminal 214 Insulator layer 216 Fifth terminal C1 First capacitor C2 Second capacitor C3 Third capacitor C4, the fourth capacitor C5, the fifth capacitor

Claims

1. A substrate containing semiconductor material, An oxide layer formed on the surface of the substrate, An insulating layer formed on at least a portion of the oxide layer, A first conductive layer formed on at least a portion of the oxide layer, A second conductive layer formed on at least a portion of the insulating layer, The first terminal connected to the first conductive layer, The second terminal connected to the second conductive layer, The third terminal connected to the aforementioned substrate and Equipped with, The oxide layer is connected in series between the substrate and the first conductive layer in order to form a first capacitor between the first terminal and the third terminal. The insulating layer is connected in series between the substrate and the second conductive layer in order to form a second capacitor between the second terminal and the third terminal. Capacitor assembly.

2. The capacitor assembly according to claim 1, wherein the insulating layer is formed from a dielectric material different from the oxide layer.

3. The capacitor assembly according to claim 1, wherein the insulating layer comprises a nitride layer.

4. The capacitor assembly according to claim 3, wherein the insulating layer comprises silicon nitride or silicon oxynitride.

5. The capacitor assembly according to claim 1, wherein the first terminal and the second terminal each have a length in the X direction, and further, the ratio of the length of the first terminal to the length of the second terminal is approximately 1:

1.

6. The capacitor assembly according to claim 5, wherein the first terminal and the second terminal each have a width in the Y direction perpendicular to the X direction, and further, the ratio of the width of the first terminal to the width of the second terminal is approximately 1:

1.

7. The capacitor assembly according to claim 1, wherein the third terminal is connected to the substrate at a location spaced apart from the surface of the substrate in the Z direction.

8. The capacitor assembly according to claim 1, wherein the first terminal is spaced apart from the second terminal in the X direction and / or Y direction.

9. The capacitor assembly according to claim 1, wherein the insulating layer covers a first portion of the oxide layer, and is separate from a second portion of the oxide layer that lacks the insulating layer.

10. The capacitor assembly according to claim 1, wherein the first terminal includes a conductive material that directly contacts the oxide layer.

11. The capacitor assembly according to claim 1, wherein the first terminal includes a conductive material that directly contacts the insulating layer.

12. The capacitor assembly according to claim 1, wherein the semiconductor material of the substrate includes silicon.

13. The capacitor assembly according to claim 1, wherein the oxide layer comprises silicon oxide.

14. The first terminal and the second terminal have the same shape and size. The first capacitor has a first capacitance value, and the second capacitor has a second capacitance value. The first capacity value and the second capacity value are not equal. The capacitor assembly according to claim 1.

15. The capacitor assembly according to claim 1, further comprising additional terminals formed on the oxide layer or the insulating layer.

16. The capacitor assembly according to claim 15, wherein the additional terminal is spaced apart from both the first terminal and the second terminal.

17. The steps include forming an oxide layer on the surface of a substrate containing a semiconductor material, The steps include forming an insulating layer on at least a portion of the oxide layer, The steps include depositing a first conductive layer on at least a portion of the oxide layer, The steps include depositing a second conductive layer on at least a portion of the insulating layer, The steps include depositing a first terminal on the first conductive layer, The steps include depositing a second terminal on the second conductive layer and A method for forming a capacitor assembly, including the following:

18. The step of forming the insulating layer includes forming the insulating layer within a first portion of the surface of the oxide layer, which is separate from the second portion of the oxide layer that includes the first terminal. The step of depositing the first terminal includes the step of depositing the first terminal within the second portion of the oxide layer, The method according to claim 17.

19. The method according to claim 18, wherein the step of forming the insulating layer includes the step of etching the insulating layer within the first portion of the oxide layer.

20. The method according to claim 18, wherein the step of forming the insulating layer includes the steps of masking the second portion of the oxide layer and forming the insulating layer on the first portion of the oxide layer.

21. The further step includes depositing additional terminals on at least a portion of the oxide layer or the insulating layer, The additional terminal is spaced apart from the first terminal and the second terminal. The method according to claim 17.

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