Semiconductor device and method for manufacturing a semiconductor device

Abstract

According to an embodiment of the present invention, a method for manufacturing a semiconductor device may include growing a stack layer by alternately stacking a sacrificial layer and a channel region on a substrate, forming a sacrificial poly gate on the stack layer, forming an inner spacer and a side spacer on a side of the sacrificial layer and a side of the sacrificial poly gate, and performing a heat treatment on the inner spacer or the side spacer in a chamber set to a predetermined process pressure and a predetermined process temperature.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] A semiconductor device is a component mainly used in electronic circuits and similar devices that utilize the electrical conduction characteristics of semiconductors. Semiconductors can be classified into memory semiconductors and non-memory semiconductors. Memory semiconductors can be further classified into volatile memories such as DRAM and SRAM, and non-volatile memories such as Mask ROM, EP ROM, EEP ROM, and flash memory. [[ID=!3]]

[0003] New processes for miniaturization of semiconductor devices and semiconductor devices having new structures based on such processes have been developed. A typical example is the Gate-All-Around (GAA) process. According to the GAA process, since the gate and the channel come into contact on four sides, the flow of current can be precisely controlled, and the limitations of existing semiconductor devices can be overcome.

[0004] In recent years, a new structure called MBCFET (Multi-Bridge Channel Field Effect Transistor) has been disclosed to solve the drawbacks of the Gate-All-Around structure. According to the MBCFET structure, since the channel region is formed in a nanosheet shape, the substantial area where the gate and the channel contact increases, and thereby the amount of current flowing between the gate and the channel also increases.

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to improve the film quality performance of an inner spacer or a side spacer included in a semiconductor device including nanosheets.

[0006] The purposes of this specification are not limited to those mentioned above. Other purposes and advantages of this specification not mentioned can be better understood from the examples described below. Furthermore, the purposes and advantages of this specification can be achieved by the components and combinations thereof described in the claims. [Means for solving the problem]

[0007] In one embodiment, a method for manufacturing a semiconductor device may include the steps of: growing a stacked layer by alternately stacking a sacrificial layer and a channel region on a substrate; forming a sacrificial polygate on the stacked layer; forming an inner spacer and a side spacer on the side surface of the sacrificial layer and the side surface of the sacrificial polygate; and performing heat treatment on the inner spacer or the side spacer in a chamber set to a predetermined process pressure and a predetermined process temperature.

[0008] A semiconductor device according to one embodiment includes a substrate, a channel region comprising a number of nanosheets stacked on the substrate, a gate electrode disposed in contact with at least one surface of the channel region, a source region and a drain region disposed on both sides of the channel region, a side spacer disposed on the side surface of the gate electrode, and an inner spacer disposed on the side surface of the gate electrode, wherein an oxide film layer can be formed on the outer surface of the side spacer or the inner spacer by heat treatment performed in a chamber set to a predetermined process pressure and a predetermined process temperature. [Effects of the Invention]

[0009] The semiconductor device manufacturing method according to the embodiment can improve the film quality performance of the inner spacer or side spacer of the semiconductor device. Specifically, the thickness of the inner spacer or side spacer becomes uniform, improving stability, which can improve the insulating properties of the inner spacer or side spacer. As a result, the parasitic capacitance between the gate electrode and the source and drain regions is reduced, which can improve the electrical characteristics and reliability of the semiconductor device. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view showing the structure of a semiconductor device according to one embodiment. [Figure 2a] This figure shows the manufacturing process of a semiconductor device according to one embodiment. [Figure 2b] This figure shows the manufacturing process of a semiconductor device according to one embodiment. [Figure 2c] This figure shows the manufacturing process of a semiconductor device according to one embodiment. [Figure 2d] This figure shows the manufacturing process of a semiconductor device according to one embodiment. [Figure 2e] This figure shows the manufacturing process of a semiconductor device according to one embodiment. [Figure 2f] This figure shows the manufacturing process of a semiconductor device according to one embodiment. [Figure 2g] This figure shows the manufacturing process of a semiconductor device according to one embodiment. [Figure 3] This is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 4a] This figure shows the manufacturing process of a semiconductor device according to another embodiment. [Figure 4b] This figure shows the manufacturing process of a semiconductor device according to another embodiment. [Figure 4c] This figure shows the manufacturing process of a semiconductor device according to another embodiment. [Figure 4d] This figure shows the manufacturing process of a semiconductor device according to another embodiment. [Figure 4e] This figure shows the manufacturing process of a semiconductor device according to another embodiment. [Figure 5] It is a flowchart showing a method for manufacturing a semiconductor device according to another embodiment. [Figure 6] It is a graph showing leakage current values measured when a voltage is applied to a semiconductor device manufactured according to the prior art and a semiconductor device manufactured according to an embodiment of the present specification.

Embodiments for Carrying Out the Invention

[0011] The above-described objects, features, and advantages will be described in detail below with reference to the accompanying drawings, whereby those having ordinary knowledge in the technical field to which this specification pertains can easily implement the embodiments of this specification. In explaining this specification, when it is determined that a specific description of the known technology related to this specification obscures the gist of this specification, the detailed description will be omitted. Hereinafter, preferred embodiments according to this specification will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or similar components.

[0012] The "nanosheet" in this specification means a conductive structure having a cross-section substantially perpendicular to the direction in which current flows through the nanosheet. Also, one of the Cartesian cross-sectional dimensions in the nanosheet is significantly smaller compared to the other dimensions. For example, the nanosheet may include a conductive structure having a cross-sectional area where one of the Cartesian cross-sectional dimensions reaches several nm to about 20 nm and the other Cartesian cross-sectional dimensions reach about 15 nm to about 70 nm.

[0013] FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment.

[0014] Referring to FIG. 1, a semiconductor device 10 according to an embodiment may include substrates 110, 120, a source region 210, a drain region 220, a gate electrode 370, channel regions 150, 160, a side spacer 180, and an inner spacer 190. It should be noted that in the translation of item , there seems to be an incorrect numbering in the original text. I translated it as it is, but it might need to be double-checked in the original context. Also, for the sake of consistency in the translation style, I added a single quote mark in the translation of item as it is a more common way to translate "

Embodiments for Carrying Out the Invention

[0015] The base substrate layer 110 may be a single crystal substrate. The base substrate layer 110 can include a single crystal semiconductor layer on at least one surface. The single crystal semiconductor layer may be made of any one of Si, Ge, SiGe, GeSn, InSb, GaAs, GaP, InAlAs, InGaAs, GaSbP, GaAsSb, and InP, but is not limited thereto.

[0016] The buffer substrate layer 120 can be formed by epitaxial growth on the base substrate layer 110. The buffer substrate layer 120 can be formed by doping the base substrate layer 110 with impurities of a material different from that of the base substrate layer 110.

[0017] The buffer substrate layer 120 may have a lattice constant different from that of the base substrate layer 110 in order to minimize lattice stress. In some embodiments, the lattice constant and crystal structure of the buffer substrate layer 120 may be substantially the same as those of the base substrate layer 110.

[0018] The lattice constant of the buffer substrate layer 120 may be different for each layer position. For example, the lattice constant of the buffer substrate layer 120 may increase from the lower layer position to the higher layer position.

[0019] The source region 210 and the drain region 220 may be respectively disposed at both ends of the channel regions 150, 160.

[0020] The gate electrodes 340, 370 can control the flow of current passing through the channel regions 150, 160. The gate electrodes 340, 370 may be disposed between the source region 210 and the drain region 220. The gate electrodes 340, 370 may be arranged to surround the upper surface, lower surface, and side surfaces of the channel regions 150, 160, that is, to contact the upper surface, lower surface, and side surfaces of the base nanosheet 150 and the nanosheet 160 respectively.

[0021] The base gate insulating film 130 can prevent parasitic bonding between the gate electrodes 340 and 370 and the substrates 110 and 120. The base gate insulating film 130 can prevent the formation of undesirable conductive channels in the substrates 110 and 120 when the semiconductor element 10 is conductive. In Figure 1, the base gate insulating film 130 may be positioned below the gate electrode 340, which is located at the bottom. In some embodiments, the base gate insulating film 130 can be omitted.

[0022] The channel regions 150,160 may include a base nanosheet 150 positioned on the bottom surface and at least one nanosheet 160 stacked on top of the base nanosheet 150. In one embodiment, the channel regions 150,160 may be stacked alongside the gate electrodes 340,370, spaced apart from each other in the vertical direction. The channel regions 150,160 may be positioned between the source region 210 and the drain region 220. The number of nanosheets 160 included in the channel regions 150,160 may vary depending on the embodiment.

[0023] The channel regions 150 and 160 can also be defined as conductive structures having a cross-section perpendicular to the direction of current flow. The base nanosheets 150 and 160 may consist of materials doped with conductive impurities. For example, the base nanosheets 150 and 160 may contain Si and group 3-4 semiconductor materials such as SiGe, Ge, and InGaAs.

[0024] The base nanosheet 150 and nanosheet 160 may be spaced apart from each other in the vertical direction. The base nanosheet 150 and nanosheet 160 may be plate-shaped, and their horizontal length may be relatively larger than their vertical thickness.

[0025] The inner spacer 190 can reduce the parasitic capacitance between the gate electrode 340 and the source region 210 and drain region 220.

[0026] The inner spacer 190 may be positioned on the side of the gate electrode 340. This allows the source region 210 and the drain region 220 to be separated from the gate electrode 340. The inner spacer 190 may be in contact with the channel regions 150 and 160.

[0027] An oxide film layer 191 may be formed on the outer surface of the inner spacer 190. In one embodiment, by heat treatment of the outer surface of the inner spacer 190, the outer surface of the inner spacer 190 is oxidized, and an oxide film layer 191 can be formed. The oxide film layer 191 can improve the film quality performance of the inner spacer 190. The formation of the oxide film layer 191 can reduce defects in the inner spacer 190 and improve the quality of the inner spacer 190.

[0028] The side spacer 180 can be formed to surround part or all of the side surface of the gate electrode 370. The side spacer 180 can separate the source region 210 and the drain region 220 from the gate electrode 370. In one embodiment, the side spacer 180 can be heat-treated to form an oxide film layer on its outer surface. The oxide film layer can improve the film quality performance of the side spacer 180. The formation of the oxide film layer can reduce defects in the side spacer 180 and improve the quality of the side spacer 180.

[0029] Figures 2a to 2g show the manufacturing process of a semiconductor device according to one embodiment. Figure 3 is a flowchart showing the manufacturing method of a semiconductor device according to one embodiment.

[0030] Referring to Figure 3, the method for manufacturing a semiconductor device according to one embodiment may include a stack layer growth stage (a1), a sacrificial polygate and side spacer formation stage (b1), a side recess formation stage (c1), an inner spacer formation stage (d1), and an oxide film layer formation stage (e1). Furthermore, the method for manufacturing a semiconductor device according to one embodiment may further include a source region and drain region growth stage (f1) and an interface film formation stage (g1).

[0031] Referring to Figure 2a, in the growth stage of the stack layer (a1), a base gate insulating film 130 may first be stacked on the substrates 110 and 120. Depending on the embodiment, the stacking of the base gate insulating film 130 may be omitted. Next, stack layers, i.e., sacrificial layers 140 and channel regions 150 and 160, may be alternately stacked on the base gate insulating film 130. The sacrificial layers 140 and channel regions 150 and 160 can be formed epitaxially.

[0032] In one embodiment, the sacrificial layer 140 may contain SiGe, and the channel regions 150 and 160 may contain Si.

[0033] Referring to Figure 2b, in the formation stage of the sacrificial polygate and side spacers (b1), the sacrificial polygate 170 and side spacers 180 can be formed on top of the stack layer, i.e., the sacrificial layer 140 and the channel regions 150, 160, respectively.

[0034] The sacrificial polygate 170 may contain silicon, for example, Poly-Si. The side spacer 180 may contain a dielectric material, for example, silicon nitride. The side spacer 180 may contain a low dielectric material (or low-k material).

[0035] Referring to Figure 2c, in the side recess formation stage (c1), a portion of the sacrificial layer 140 and the base gate insulating film 130 is selectively removed to form the side recess. In the side recess formation stage (c1), a portion of the sacrificial layer 140 and the base gate insulating film 130 can be removed by wet etching or dry etching, and can be removed by selective etching.

[0036] The sacrificial layer 140 and the base gate insulating film 130 may have a relatively high selective etching ratio with respect to the channel regions 150 and 160. Therefore, when the sacrificial layer 140 and the base gate insulating film 130 are removed, the channel regions 150 and 160 may not be removed.

[0037] If the process of stacking the base gate insulating film 130 is omitted during the growth stage of the stack layer (a1), then only a portion of the sacrificial layer 140 can be selectively removed during the side recess formation stage (c1).

[0038] Referring to Figure 2d, in the inner spacer formation stage (d1), the inner spacer 190 can be formed in the side recess formed in the side recess formation stage (c1). In one embodiment, the inner spacer 190 can be formed by atomic layer deposition (ALD). The inner spacer 190 may contain a low dielectric material (or low-k material).

[0039] Referring to Figure 2e, during the oxide film layer formation stage (e1), heat treatment can be performed on the inner spacer 190.

[0040] More specifically, in the oxide film layer formation stage (e1), the inner spacer 190 can be heat-treated in a chamber set to a predetermined process pressure and a predetermined process temperature. In one embodiment, the predetermined process pressure can be determined to be between 2 atmospheres and 100 atmospheres. In one embodiment, the predetermined process temperature can be determined to be between 200°C and 600°C.

[0041] When heat treatment is performed during the oxide film layer formation stage (e1), an atmospheric gas can be supplied into the chamber. In one embodiment, the atmospheric gas may be O2 or H2O. In one embodiment, the concentration of the atmospheric gas in the chamber may be 100%.

[0042] In one embodiment, the heat treatment performed in the oxide film layer formation stage (e1) can be carried out in a wet, dry, or supercritical environment.

[0043] Referring to Figure 2f, in the growth stage (f1) of the source and drain regions, the source region 210 and drain region 220 can be formed on both sides of the stack layer, i.e., the sacrificial layer 140 and the channel regions 150, 160, respectively. In addition, in the growth stage (f1) of the source and drain regions, the sacrificial layer 140 and the sacrificial polygate 170 can be removed by selective etching, respectively.

[0044] Referring to Figure 2g, in the interfacial film formation stage (g1), gate electrodes 340 and 370 containing metal components can be formed in the regions where the sacrificial layer 140 and sacrificial polygate 170 have been removed, respectively. An interfacial film containing oxides can be formed on the outer surfaces of the gate electrodes 340 and 370.

[0045] Depending on the embodiment, the sacrificial layer 140 and the sacrificial polygate 170 may be removed, and the gate electrodes 340 and 370 may be formed before the source region 210 and the drain region 220 are formed.

[0046] Figures 4a to 4e show the manufacturing process of semiconductor devices according to other embodiments. Figure 5 is a flowchart showing a semiconductor device manufacturing method according to another embodiment.

[0047] Referring to Figure 5, the method for manufacturing a semiconductor device according to other embodiments may include a stack layer growth stage (a2), a sacrificial polygate formation stage (b2), a mask formation stage (c2), a recess formation stage (d2), a spacer material layer formation stage (e2), a side spacer and inner spacer formation stage (f2), and an oxide film layer formation stage (g2). Furthermore, the method for manufacturing a semiconductor device according to other embodiments may further include a source region and drain region growth stage (h2) and an interface film formation stage (i2).

[0048] Referring to Figure 4a, in the growth stage of the stack layer (a2), a base gate insulating film 130 may first be stacked on the substrates 110 and 120. Depending on the embodiment, the stacking of the base gate insulating film 130 may be omitted. Next, stack layers, i.e., sacrificial layers 140 and channel regions 150 and 160, may be alternately stacked on the base gate insulating film 130. The sacrificial layers 140 and channel regions 150 and 160 can be formed epitaxially.

[0049] In one embodiment, the sacrificial layer 140 may contain SiGe, and the channel regions 150 and 160 may contain Si.

[0050] Referring to Figure 4a, in the sacrificial polygate formation stage (b2), sacrificial polygates 170 can be formed on top of the stack layers, i.e., the sacrificial layer 140 and the channel regions 150, 160. The sacrificial polygates 170 can be formed spaced apart from each other. The sacrificial polygates 170 may contain silicon, for example, Poly-Si.

[0051] Referring to Figure 4a, in the mask formation stage (c2), the mask 171 can be formed on top of the sacrificial polygate 170.

[0052] Referring to Figure 4b, in the recess formation stage (d2), a recess can be formed by selectively removing a portion of the sacrificial layer 140 and the base gate insulating film 130. In the recess formation stage (d2), a portion of the sacrificial layer 140 and the base gate insulating film 130 can be removed by wet etching or dry etching, and can be removed by selective etching.

[0053] The sacrificial layer 140 and the base gate insulating film 130 may have a relatively high selective etching ratio with respect to the channel regions 150 and 160. Therefore, when the sacrificial layer 140 and the base gate insulating film 130 are removed, the channel regions 150 and 160 may not be removed.

[0054] If the stacking process of the base gate insulating film 130 is omitted during the growth stage of the stack layer (a2), then only a portion of the sacrificial layer 140 can be selectively removed during the recess formation stage (d2).

[0055] Referring to Figure 4c, in the spacer material layer formation step (e2), the spacer material layer 280 can be formed on the recess formed in the recess formation step (d2) and on the side surface of the sacrificial polygate 170. The sacrificial polygate 170 in the spacer material layer formation step (e2) can be used as a support structure and a mask. In one embodiment, the spacer material layer 280 can be formed by atomic layer deposition (ALD). The spacer material layer 280 may contain a low dielectric material (or low-k material).

[0056] Referring to Figure 4d, in the formation stage (f2) of the side spacers and inner spacers, the side spacers 180 and inner spacers 190 can be formed by etching a portion of the channel regions 150 and 160 and a portion of the spacer material layer 280. In the formation stage (f2) of the side spacers and inner spacers, the side spacers 180 and inner spacers 190 can be formed simultaneously.

[0057] Referring to Figure 4e, heat treatment can be performed on the inner spacer 190 during the oxide film layer formation stage (g2).

[0058] More specifically, in the oxide film layer formation stage (g2), the inner spacer 190 can be heat-treated in a chamber set to a predetermined process pressure and predetermined process temperature. In one embodiment, the predetermined process pressure can be determined to be between 2 atmospheres and 100 atmospheres. In one embodiment, the predetermined process temperature can be determined to be between 200°C and 600°C.

[0059] When heat treatment is performed during the oxide film layer formation stage (g2), an atmospheric gas can be supplied into the chamber. In one embodiment, the atmospheric gas may be O2 or H2O. In one embodiment, the concentration of the atmospheric gas in the chamber may be 100%.

[0060] In one embodiment, the heat treatment performed in the oxide film layer formation stage (g2) can be carried out in a wet, dry, or supercritical environment.

[0061] In some embodiments, heat treatment can be performed on the side spacer 180 during the oxide film layer formation stage (g2). This allows for the formation of an oxide film layer on the outer surface of the side spacer 180.

[0062] Although not shown, during the growth phase (h2) of the source and drain regions, the source region 210 and drain region 220 can be formed on both sides of the stack layer, i.e., the sacrificial layer 140 and the channel regions 150, 160, respectively. Furthermore, during the growth phase (h2) of the source and drain regions, the sacrificial layer 140 and the sacrificial polygate 170 can be removed by selective etching, respectively.

[0063] Although not shown, in the interfacial film formation stage (i2), gate electrodes 340 and 370 containing metal components can be formed in the regions where the sacrificial layer 140 and sacrificial polygate 170 have been removed, respectively. An interfacial film containing an oxide can be formed on the outer surfaces of the gate electrodes 340 and 370.

[0064] Depending on the embodiment, the sacrificial layer 140 and the sacrificial polygate 170 may be removed, and the gate electrodes 340 and 370 may be formed before the source region 210 and the drain region 220 are formed.

[0065] Figure 6 is a graph showing the leakage current values ​​measured when a voltage is applied to a semiconductor device manufactured according to the prior art and a semiconductor device manufactured according to the embodiments described herein.

[0066] In Figure 6, M0 represents a semiconductor device manufactured according to the prior art, and M1 to M3 represent semiconductor devices manufactured according to one embodiment of this specification.

[0067] M0 is a semiconductor device manufactured according to a process similar to that of one embodiment of this specification, but without heat treatment of the inner spacer.

[0068] M1 is a semiconductor device manufactured according to a process similar to that of one embodiment herein, in which the inner spacer is heat-treated in a chamber with a process temperature set to 400°C and a process pressure set to 2 atmospheres.

[0069] M2 is a semiconductor device manufactured according to a process similar to that of one embodiment herein, in which the inner spacer is heat-treated in a chamber with a process temperature set to 400°C and a process pressure set to 5 atmospheres.

[0070] M3 is a semiconductor device manufactured according to a process similar to that of one embodiment herein, in which the inner spacer is heat-treated in a chamber with a process temperature set to 400°C and a process pressure set to 10 atmospheres.

[0071] As shown in Figure 6, the leakage current of semiconductor elements (M1, M2, M3) with heat treatment applied to the inner spacer according to one embodiment is smaller than that of semiconductor element (M0) without heat treatment applied to the inner spacer. In particular, it is confirmed that the leakage current of semiconductor elements (M1, M2, M3) with heat treatment applied to the inner spacer according to one embodiment is maintained at 3.5 mA or less. Therefore, heat treatment applied to the inner spacer can improve the electrical characteristics of semiconductor elements.

[0072] As described above, this specification has been explained with reference to the illustrative drawings, but this specification is not limited to the embodiments and drawings disclosed herein, and various modifications can be made by a person of the ordinary skill. Furthermore, even if the effects of the configurations described herein are not explicitly stated and explained in the embodiments described herein, the effects that can be predicted by such configurations should also be recognized.

Claims

1. The process involves alternately stacking sacrificial layers and channel regions on a substrate to grow a stacked layer, The steps include forming a sacrificial polygate on the stack layer, The steps include forming inner spacers and side spacers on the sides of the sacrificial layer and the sides of the sacrificial polygate, After the formation of the inner spacer and the side spacer is completed, the inner spacer or the side spacer is subjected to heat treatment in a chamber set to a predetermined process pressure and a predetermined process temperature. including, A method for manufacturing semiconductor devices.

2. The predetermined process pressure is It is determined within a range of 2 to 100 atmospheres. A method for manufacturing a semiconductor device according to claim 1.

3. The predetermined process temperature is Determined between 200°C and 600°C. A method for manufacturing a semiconductor device according to claim 1.

4. An atmospheric gas is supplied to the chamber. The aforementioned atmospheric gas is O ２ or H ２ It is O. A method for manufacturing a semiconductor device according to claim 1.

5. The concentration of the aforementioned atmospheric gas is 100%. A method for manufacturing a semiconductor device according to claim 4.

6. The aforementioned heat treatment is The process is carried out in a wet, dry, or supercritical environment. A method for manufacturing a semiconductor device according to claim 1.

7. The step of forming the inner spacer and side spacer is, The step includes forming the side spacers on the stack layer, A method for manufacturing a semiconductor device according to claim 1.

8. The step of forming the inner spacer and side spacer is, The step of removing a portion of the aforementioned sacrificial layer to form a side recess, The steps include forming an inner spacer in the side recess, including, A method for manufacturing a semiconductor device according to claim 1.

9. The step of forming the inner spacer and side spacer is, The step of removing a portion of the aforementioned sacrificial layer to form a recess, The steps include forming a spacer material layer on the recess and the side surface of the sacrificial polygate, The steps include removing a portion of the channel region and a portion of the spacer material layer to form the inner spacer and the side spacer, including, A method for manufacturing a semiconductor device according to claim 1.

10. The steps include forming a source region and a drain region, The steps include removing the sacrificial layer and the sacrificial polygate, The step of forming the gate electrode, This also includes, A method for manufacturing a semiconductor device according to claim 1.

11. The steps include removing the sacrificial layer and the sacrificial polygate, The step of forming the gate electrode, The steps include forming a source region and a drain region, This also includes, A method for manufacturing a semiconductor device according to claim 1.

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