Drivers, electro-optical devices, and electronic equipment

Abstract

To provide a driver and the like that can achieve both an amplification factor and frequency response characteristics of an operational amplifier that drives a signal supply line of an electro-optical panel.SOLUTION: A driver 100 includes a first driving circuit 60 and a second driving circuit 70. The second driving circuit 70 includes an operational amplifier 71 formed by a transistor with a withstand voltage lower than a withstand voltage of a transistor forming the first driving circuit 60, an output capacitor CQ arranged between an output node NAMQ of the operational amplifier 71 and a signal supply line, and a first feedback capacitor Cfa arranged between an inverted input node NAN of the operational amplifier 71 and the signal supply line. The second driving circuit 70 includes capacitors CB1-CBm for first to m-th voltage output connected at one ends with the inverted input node NAN of the operational amplifier 71, and first to m-th voltage output circuits DB1-DBm outputting a voltage based on gradation data to the other ends of the capacitors CB1-CBm for first to m-th voltage output.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a driver, an electro-optical device, an electronic device, and the like.

Background Art

[0002] Patent Document 1 discloses a driver that includes a capacitance drive circuit and an amplifier circuit and drives an electro-optical panel. After the capacitance drive for driving the electro-optical panel by the capacitance drive circuit is started, the amplifier circuit performs voltage drive to output a data voltage corresponding to gradation data to a data voltage output terminal. Thereby, since the voltage drop of the data line after the source line switch of the electro-optical panel changes from off to on is compensated by the amplifier circuit, a decrease in the accuracy of the data voltage in capacitance drive is suppressed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Depending on the type of liquid crystal panel, a high voltage is required for driving it. Therefore, an operational amplifier composed of high breakdown voltage transistors is used in a drive circuit for driving such a liquid crystal panel. However, since high breakdown voltage transistors have low mobility, there is a problem that it is difficult to achieve both the amplification factor and the frequency response characteristics of the operational amplifier. For example, in order to increase the drive speed with high resolution or the like, it is necessary to increase the frequency response characteristics of the operational amplifier. However, if the frequency response characteristics are increased while maintaining the amplification factor of the operational amplifier, the power consumption of the operational amplifier will increase.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a driver comprising: a first drive circuit that supplies data signals to a signal supply line of an electro-optical panel based on grayscale data; an operational amplifier composed of transistors having a voltage rating lower than the voltage rating of the transistors constituting the first drive circuit; an output capacitor disposed between the output node of the operational amplifier and the signal supply line; a first feedback capacitor disposed between the inverting input node of the operational amplifier and the signal supply line; first to m voltage output capacitors (where m is an integer of 2 or more) with one end connected to the inverting input node of the operational amplifier; and first to m voltage output circuits that output voltages based on the grayscale data to the other end of the first to m voltage output capacitors, and a second drive circuit electrically connected to the signal supply line.

[0006] Other aspects of this disclosure relate to an electro-optical apparatus including the driver and the electro-optical panel.

[0007] Another aspect of this disclosure is an electronic device characterized by including the above-described driver. [Brief explanation of the drawing]

[0008] [Figure 1] An example of an electro-optical device configuration. [Figure 2] First detailed configuration example of the driver. [Figure 3] A diagram illustrating the relationship between grayscale data and data voltage. [Figure 4] A first detailed configuration example of the first drive circuit. [Figure 5] A first detailed configuration example of the second drive circuit. [Figure 6] The first waveform example illustrates the operation of the first and second drive circuits. [Figure 7] A second waveform example illustrating the operation of the first and second drive circuits. [Figure 8] A third waveform example illustrating the operation of the first and second drive circuits. [Figure 9] Second detailed configuration example of the driver. [Figure 10]A diagram for explaining the relationship among gradation data, setting data, and data voltage. [Figure 11] A second detailed configuration example of the first driving circuit. [Figure 12] A fourth waveform example for explaining the operations of the first driving circuit and the second driving circuit. [Figure 13] A second detailed configuration example of the second driving circuit. [Figure 14] The relationship between gradation data and the output voltage of the data line driving circuit. [Figure 15] A second detailed configuration example of the second driving circuit. [Figure 16] A fifth waveform example for explaining the operations of the first driving circuit and the second driving circuit. [Figure 17] A sixth waveform example for explaining the operations of the first driving circuit and the second driving circuit. [Figure 18] A configuration example of an electronic device.

Modes for Carrying Out the Invention

[0009] Hereinafter, preferred embodiments of the present disclosure will be described in detail. Note that the embodiments described below do not unduly limit the content described in the claims, and not all of the configurations described in these embodiments are essential constituent elements.

[0010] 1. Electro-optical device FIG. 1 shows a configuration example of an electro-optical device. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200. Hereinafter, the electro-optical device 400 using the phase development driving method will be described as an example, but the present disclosure is not limited thereto. For example, the electro-optical device 400 may be a demultiplex driving method.

[0011] The driver 100 drives the electro-optical panel 200 by outputting a data signal to the signal supply line of the electro-optical panel 200. Note that the voltage written into one pixel at a time is referred to as a data voltage. When a plurality of pixels are driven in time series, the data voltage for each pixel is output to the signal supply line as a time series signal, and this signal to the signal supply line is referred to as a data signal.

[0012] The scanning line driving circuit for driving the scanning lines of the electro-optical panel 200 may be included in the driver 100 or may be provided outside the driver 100. The driver 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. The driver 100 includes a control circuit 40 and first to k data line driving circuits DD1 to DDk. k is an integer of 2 or more. Hereinafter, the case of k = 8 will be described as an example.

[0013] The control circuit 40 outputs corresponding gradation data to each of the data line driving circuits of the data line driving circuits DD1 to DD8. Further, the control circuit 40 outputs a control signal ENBX for controlling the data line switch to the electro-optical panel 200.

[0014] The data line driving circuits DD1 to DD8 convert the gradation data into data voltages and output the data voltages as output voltages VQ1 to VQ8 to the signal supply lines SPL1 to SPL8 of the electro-optical panel 200. The output voltages VQ1 to VQ8 change according to the time-series gradation data, and the signals by the changing output voltages VQ1 to VQ8 correspond to the data signals described above.

[0015] The electro-optical panel 200 includes first to eighth signal supply lines SPL1 to SPL8, first to 1280th data line switches SWEP1 to SWEP1280, and first to 1280th data lines DL1 to DL1280. The number of data lines may be k × t. t is an integer of 2 or more. Here, WXGA is taken as an example and t = 160.

[0016] One ends of the data line switches SWEP((j - 1)×k + 1) to SWEP(j×k) among the data line switches SWEP1 to SWEP1280 are connected to the signal supply lines SPL1 to SPL8. j is an integer of 160 or less. For example, when j = 1, the data line switches are SWEP1 to SWEP8.

[0017] Each of the data line switches SWEP1 to SWEP1280 is composed of, for example, a TFT and is controlled based on the control signal ENBX. TFT stands for Thin Film Transistor. For example, the electro-optic panel 200 includes a switch control circuit (not shown), which controls the data line switches SWEP1 to SWEP1280 to turn on or off based on the control signal ENBX.

[0018] The data line drive circuits DD1 to DD8 perform 160 drives during the horizontal scanning period, and in the j-th drive, data line switches SWEP((j-1)×k+1) to SWEP(j×k) are turned on, while the other data line switches are turned off. As a result, data lines DL((j-1)×k+1) to DL(j×k) are driven in the j-th drive. Focusing on data line drive circuit DD1, during the horizontal scanning period, data line switches SWEP1, SWEP2, ..., SWEP1273 are turned on sequentially, and data line drive circuit DD1 drives data lines DL1, DL2, ..., DL1273 sequentially.

[0019] 2. First Embodiment Figure 2 shows a first detailed configuration example of the driver. The driver 100 includes a data line drive circuit 110 and a control circuit 40. The data line drive circuit 110 corresponds to any one of the data line drive circuits DD1 to DD8 in Figure 1.

[0020] The data line drive circuit 110 includes a first drive circuit 60, a second drive circuit 70, a variable capacitance circuit 30, and a detection circuit 50. The control circuit 40 includes a processing circuit 42, an interface circuit 44, and a register circuit 48.

[0021] The interface circuit 44 performs interface processing between the driver 100 and the display controller 300 that controls the driver 100. The interface circuit 44 outputs the grayscale data GD[9:0] received from the display controller 300 to the processing circuit 42. The number of bits of the received grayscale data may be arbitrary. The interface circuit 44 is an image interface circuit such as an LVDS system, a parallel RGB system, or a DisplayPort system. LVDS stands for Low Voltage Differential Signaling.

[0022] The processing circuit 42 determines the setting data CSW[4:0] for the capacitance value of the variable capacitance circuit 30 during initialization processing when power is applied to the driver 100, and stores the setting data CSW[4:0] in the register circuit 48. During normal operation when driving the electro-optical panel 200, the processing circuit 42 sets the capacitance value of the variable capacitance circuit 30 using the setting data CSW[4:0] read from the register circuit 48. The processing circuit 42 also outputs the gradation data DTH[10:0] to the first drive circuit 60 and the gradation data DTL[10:0] to the second drive circuit 70 based on the gradation data GD[9:0]. The processing circuit 42 also outputs the polarity inversion signal FR to the second drive circuit 70. Depending on the configuration of the second drive circuit 70, the input of the polarity inversion signal FR to the second drive circuit 70 may be omitted.

[0023] Output node NVQ is connected to the data voltage output terminal TVQ, and the voltage of this output node NVQ is defined as the output voltage VQ. The load capacitance of the data voltage output terminal TVQ is defined as the electro-optic panel side capacitance CP.

[0024] The first drive circuit 60 supplies charge corresponding to the grayscale data DTH[10:0] to the output node NVQ by charge redistribution using a capacitor. This charge is then distributed to the variable capacitance circuit 30 and the electro-optic panel side capacitance CP, so that the output voltage VQ becomes the data voltage corresponding to the grayscale data DTH[10:0]. The first drive circuit 60 is composed of circuit elements with a high voltage resistance process that can drive the electro-optic panel 200. For example, if the electro-optic panel 200 is a high-temperature polysilicon type liquid crystal panel, the power supply voltage of the first drive circuit 60 is about 15V to 20V, and the first drive circuit 60 is composed of circuit elements with a voltage resistance higher than that power supply voltage.

[0025] If there is an error in the charge output by the first drive circuit 60, or if charge conservation at the output node NVQ is slightly not maintained, an error will occur between the output voltage VQ due to the charge output by the first drive circuit 60 and the target voltage corresponding to the grayscale data DTH[10:0]. The second drive circuit 70 corrects the output voltage VQ to the target voltage using feedback control with an operational amplifier. At this time, because the error between the output voltage VQ and the target voltage is small, the second drive circuit 70 only needs to output a small amount of charge. Taking advantage of this, the operational amplifier is constructed with circuit elements from a low-voltage process while DC blocking is performed between the operational amplifier and the output node NVQ with a capacitor. As an example, the voltage withstand capability of a low-voltage process is about 1 / 3 to 1 / 10 of the voltage withstand capability of a high-voltage process. The second drive circuit 70 operates at a power supply voltage lower than the voltage withstand capability of the low-voltage process.

[0026] This document describes a method for determining the capacitance value of the variable capacitance circuit 30 and an example configuration of the variable capacitance circuit 30 and the detection circuit 50.

[0027] The detection circuit 50 compares a given detection voltage with the output voltage VQ and outputs the result as a detection signal DET. The detection circuit 50 is, for example, a comparator.

[0028] The processing circuit 42 outputs gradation data DTH[10:0] corresponding to a given data voltage to the capacitor drive circuit 20. At this time, the given detection voltage is set to the same voltage as the given data voltage, which is the expected value of the output voltage VQ. The processing circuit 42 sequentially changes the capacitance value of the variable capacitance circuit 30 by sequentially changing the value of the setting data CSW[4:0]. The processing circuit 42 determines the capacitance value of the variable capacitance circuit 30 based on the detection signal DET at each capacitance value. That is, the processing circuit 42 determines the capacitance value at which the output voltage VQ becomes the given detection voltage based on the detection signal DET, and stores the setting data CSW[4:0] of that capacitance value in the register circuit 48.

[0029] The variable capacitance circuit 30 includes first to fifth adjustment capacitors and first to fifth adjustment switches. One end of the first adjustment switch is connected to the output node NVQ, and the other end is connected to one end of the first adjustment capacitor. The other end of the first adjustment capacitor is connected to the ground node. The same applies to the second to fifth adjustment capacitors and the second to fifth adjustment switches. The capacitance values ​​of the first to fifth adjustment capacitors are binary weighted. The first adjustment switch is controlled on or off by CSW[0]. Similarly, the second to fifth adjustment switches are controlled on or off by CSW[1] to CSW[4].

[0030] The details of the first drive circuit 60, the second drive circuit 70, the variable capacitance circuit 30, and the detection circuit 50 will be described below.

[0031] Figure 3 illustrates the relationship between grayscale data and data voltage.

[0032] The processing circuit 42 converts the input gradation data GD[9:0] into gradation data DTH[10:0] and DTL[10:0]. Specifically, when driven by negative polarity, the processing circuit 42 converts GD[9:0] with gradation values ​​from 0 to 1023 into DTH[10:0] and DTL[10:0] with gradation values ​​from 1023 to 0, and when driven by positive polarity, it converts GD[9:0] with gradation values ​​from 0 to 1023 into DTH[10:0] and DTL[10:0] with gradation values ​​from 1024 to 2047.

[0033] VSH=0V is the low-potential power supply voltage of the first drive circuit 60. VDH=15V is the high-potential power supply voltage of the first drive circuit 60. The common voltage supplied to the counter electrode of the electro-optic panel 200 is VC=7.5V. The data voltage supplied to the pixels is 7.5V to 2.5V in negative polarity drive and 7.5V to 12.5V in positive polarity drive.

[0034] Figure 4 shows a first detailed configuration example of the first drive circuit. In the following, the same sign as the capacitor's symbol will be used to represent its capacitance value. For example, the capacitance value of capacitor C1 will be denoted as C1.

[0035] The capacitor circuit 10 includes the first to the nth capacitors C1 to Cn. The capacitor drive circuit 20 includes the first to the nth drive circuits DR1 to DRn. The following example describes the case where n=11, but n can be any integer greater than or equal to 2. n should be set to the same number of bits as the grayscale data DTH[10:0].

[0036] One end of capacitor Ci is connected to the output node NVQ, and the other end is connected to the capacitor drive node NDRi. i is an integer between 1 and n=11. Capacitors C1 to C10 have binary weighted capacitance values. Specifically, the capacitance value of capacitor Ci is 2 (i-1) ×C1

[0037] The processing circuit 42 outputs the i-th bit DTH[i-1] of the grayscale data DTH[10:0] to the input node of the drive circuit DRi. The drive circuit DRi outputs a first voltage level to the capacitor drive node NDRi when bit DTH[i-1] is at the first logic level, and outputs a second voltage level to the capacitor drive node NDRi when bit DTH[i-1] is at the second logic level. For example, the first logic level is "0", the second logic level is "1", the first voltage level is the low-potential side power supply voltage VSH, and the second voltage level is the high-potential side power supply voltage VDH. The drive circuit DRi is composed of high-voltage process transistors and operates with power supply voltages VDH and VSH. The drive circuit DRi is composed of, for example, a level shifter that level shifts the input logic level to the output voltage level of the drive circuit DRi, and a buffer circuit that buffers the output of the level shifter.

[0038] The drive circuits DR1 to DR11 drive capacitors C1 to C11, causing charge redistribution between capacitors C1 to C11, the variable capacitance circuit 30, and the electro-optic panel side capacitance CP. As a result, a data voltage is output to the output node NVQ.

[0039] The electro-optical panel capacitance CP is the sum of the capacitances visible from the data voltage output terminal TVQ. For example, the electro-optical panel capacitance CP is the sum of the parasitic capacitance of the printed circuit board, which is the board capacitance CP1, and the parasitic capacitance within the electro-optical panel 200, which is the panel capacitance CP2. The printed circuit board is the board on which the driver 100 is mounted and which is connected to the electro-optical panel 200.

[0040] Let's assume that the sum of the capacitance values ​​of capacitors C1 to C11 is Ctot = C1 + C2 + ... + C11, and the capacitance value of the variable capacitance circuit 30 is CF. For example, CF is set so that Ctot / (CF+CP)=2. In this case, at the maximum gradation value of DTH[10:0] 2047, VQ = 15V × {Ctot / (Ctot+CF+CP)} + 2.5V = 10V + 2.5V = 12.5V. At the minimum gradation value of DTH[10:0] 0, VQ = 0V × {Ctot / (Ctot+CF+CP)} + 2.5V = 0V + 2.5V = 2.5V. This achieves the same data voltage as in the example in Figure 3.

[0041] Figure 5 shows a first detailed configuration example of the second drive circuit. The second drive circuit 70 includes an operational amplifier 71, an output capacitor CQ, a first feedback capacitor Cfa, a second feedback capacitor Cfb, an initialization switch SWR, capacitors CB1 to CBm+1 for the first to m+1 voltage outputs, and first to m+1 voltage output circuits DB1 to DBm+1. Here, an example with m=10 is described, but m can be any integer greater than or equal to 2. In the first embodiment, m+1 should be set to the same number of bits as the grayscale data DTL[10:0].

[0042] The operational amplifier 71 is composed of low-voltage process transistors and operates with a high-voltage side power supply voltage VDL and a low-voltage side power supply voltage VSL. In the following, VDL = 1.8V and VSL = 0V, but it is not limited to these values; VDL can be any voltage lower than the breakdown voltage of the low-voltage process. Specifically, the source-drain distance of the transistors constituting the first drive circuit 60 is longer than the source-drain distance of the transistors constituting the second drive circuit 70, which includes the operational amplifier 71. Alternatively, the thickness of the gate insulating film of the transistors constituting the first drive circuit 60 is thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit 70, which includes the operational amplifier 71. However, the above is just one example of a configuration that uses transistor breakdown voltages differently; it is sufficient that the transistors in each drive circuit are configured such that the breakdown voltage of the transistors constituting the second drive circuit 70 is lower than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0043] One end of output capacitor CQ is connected to the output node NAMQ of the operational amplifier 71, and the other end is connected to the output node NVQ of the data line drive circuit 110. One end of first feedback capacitor Cfa is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to the output node NVQ of the data line drive circuit 110. One end of second feedback capacitor Cfb is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to the node of the low-potential side power supply voltage VSL. The other end of second feedback capacitor Cfb only needs to be connected to a predetermined potential node to which a constant potential is supplied.

[0044] One end of the voltage output capacitor CBp is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to the output node of the voltage output circuit DBp. p is an integer greater than or equal to 1 and less than or equal to m+1=11. The voltage output capacitors CB1 to CB11 have binary weighted capacitance values. Specifically, the capacitance value of the voltage output capacitor CBp is 2 (p-1) ×CB1

[0045] The voltage output circuit DBp outputs a first voltage level when the bit signal XDTL[p-1], which is the logic inversion signal of the bit signal DTL[p-1], is at the first logic level, and outputs a second voltage level when the bit signal XDTL[p-1] is at the second logic level. For example, the first logic level is "0", the second logic level is "1", the first voltage level is the low-potential side power supply voltage VSH, and the second voltage level is the high-potential side power supply voltage VDH. The voltage output circuit DBp is composed of low-voltage process transistors and operates with power supply voltages VDL and VSL. The voltage output circuit DBp is a buffer circuit that buffers the input signal and outputs it.

[0046] One end of the initialization switch SWR is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to node NVREF, which is supplied with a reference voltage VREF. The non-inverting input node of the operational amplifier 71 is connected to node NVREF, which is supplied with a reference voltage VREF. The reference voltage VREF is a voltage higher than VSL and lower than VDL. Here, VREF = 0.9V. The reference voltage VREF is supplied to node NVREF from, for example, a voltage generation circuit (not shown) included in driver 100. The initialization switch SWR is an analog switch, for example, an N-type transistor, a P-type transistor, or a transfer gate combining them.

[0047] The initialization switch SWR is off when driving pixels. At this time, the operational amplifier 71 performs feedback control so that the voltage VFB of the inverting input node NAN of the operational amplifier 71 becomes a reference voltage VREF = 0.9V due to a virtual short. As a result, the bit signals XDTL

[10] ~XDTL[0] become 0 or 1 according to the grayscale data DTL[10:0], and the data voltage corresponding to the grayscale data DTL[10:0] is output to the output node NVQ.

[0048] The capacitance values ​​of each capacitor are explained below. In the following, the total capacitance of CB1 to CB11 will be denoted as CB = CB1 + CB2 + ... + CB11.

[0049] In the example in Figure 3, the range of the output voltage VQ is 10V. In this case, when XDTL

[10] to XDTL[0] all change from 1 to 0, that is, when the output voltages of the voltage output circuits DB1 to DB11 all change from VDL=1.8V to VSL=0V, the output voltage VQ should change by 10V, so CB / Cfa = 10V / 1.8V = 50 / 9.

[0050] Conversely, when the first drive circuit 60 changes the voltage of the output node NVQ by 10V, the voltage change fed back to the inverting input node NAN of the operational amplifier 71 via the first feedback capacitor Cfa is denoted as Vfa. As will be described later, it is sufficient if Vfa ≤ 1.8V, but here we assume Vfa = 1V. In this case, it is sufficient that 10V is divided in a 9:1 ratio by Cfa and Cfb + CB, so (Cfb + CB) / Cfa = 9.

[0051] Furthermore, the voltage change at the inverting input node NAN due to the change in XDTL

[10] ~XDTL[0] is a maximum of 1.8V, so it is sufficient if Vfa ≤ 1.8V. If Vfa ≤ 1.8V, the voltage change at the inverting input node NAN due to the change in XDTL

[10] ~XDTL[0] can be balanced with the voltage change at the inverting input node NAN when the first drive circuit 60 changes the voltage of the output node NVQ. In other words, as long as the voltage changes are ideally balanced, the voltage at the inverting input node NAN will be maintained at VFB = 0.9V even if the operational amplifier 71 does not output charge, and only if there is an error in the balance will the operational amplifier 71 need to output charge to correct that error.

[0052] The capacitance value of the output capacitor CQ can be arbitrary, as long as it is set so that the output voltage AMQ of the operational amplifier 71 is within the range of VSL to VDL. For example, the capacitance value of the output capacitor CQ is set to approximately 1 to 10 times the sum of the capacitor circuit 10, the variable capacitance circuit 30, and the electro-optic panel side capacitance CP. As an example, if the capacitance value of the output capacitor CQ is 4 times the above sum, in order to compensate for an error of 0.1V in the output voltage VQ, the output voltage AMQ of the operational amplifier 71 only needs to change by 0.1V × (5 / 4) = 0.125V.

[0053] Figure 6 shows a first waveform example illustrating the operation of the first and second drive circuits. Assume that the gradation values ​​of the gradation data DTH[10:0] and DTL[10:0] change to 1024, 1535, and 1024. The target voltage corresponding to a gradation value of 1535 is 10.0V.

[0054] Assuming that the second drive circuit 70 is absent and the system is driven only by the first drive circuit 60, when the grayscale value changes from 1024 to 1535, the output voltage VQ changes from 7.5V to 9.9V. The difference from the target voltage of 10.0V is 0.1V. The operation of the second drive circuit 70 in this case will be explained below.

[0055] Assuming that the output voltage VQ increases from 7.5V to the target voltage of 10V due to the first drive circuit 60, the voltage VFB at the inverting input node NAN of the operational amplifier 71 will attempt to change from 0.9V to 0.9V + (10V - 7.5V) / 10 = 1.15V. The increase is 0.25V. At this time, the voltage output capacitors CB1~CB11 and voltage output circuits DB1~DB11 of the second drive circuit 70 operate to lower the voltage VFB at the inverting input node NAN by 0.25V. As a result, the change in voltage VFB due to the first drive circuit 60 and the change in voltage VFB due to the second drive circuit 70 cancel each other out, and the voltage VFB remains unchanged at 0.9V.

[0056] However, when the output voltage VQ is increased from 7.5V to 9.9V by the first drive circuit 60, the voltage VFB attempts to change from 0.9V to 0.9V + (9.9V - 7.5V) / 10 = 1.14V. The increase is 0.24V. Then, due to the difference with the decrease of 0.25V by the second drive circuit 70, the voltage VFB = 0.9V + (0.24V - 0.25V) = 0.89V. The operational amplifier 71 changes the output voltage AMQ from 0.9V to 0.9V + (10.0V - 9.9V) × (5 / 4) = 1.025V in order to make VFB = 0.9V. As a result, the output voltage VQ becomes the target voltage of 10.0V and the voltage VFB = 0.9V. Thus, the operational amplifier 71 supplies only the charge corresponding to an error of 0.1V relative to the target voltage of 10V to the output node NVQ via the output capacitor CQ.

[0057] Figure 7 shows a second waveform example illustrating the operation of the first and second drive circuits. Figure 7 shows a waveform example of the horizontal scanning period during the positive polarity drive period of polarity reversal drive. Here, an example is shown in which grayscale values ​​of 0, 127, ..., 1023 are sequentially written to nine pixels, but the number of pixels driven during the horizontal scanning period and the grayscale values ​​written to each pixel can be arbitrary.

[0058] The rising edge of the horizontal synchronization signal HSYNC is used as the start timing for the horizontal scanning period. After the horizontal scanning period has started, the processing circuit 42 outputs DTH[9:0]=DTL[9:0]=0 and changes DTH

[10] =DTL

[10] from 0 to 1. Here, 0 is shown as a low level and 1 as a high level. This corresponds to DTH[10:0]=DTL[10:0]=1024, so the output voltage VQ=7.5V.

[0059] Next, the initialization switch SWR switches from off to on, and then from on to off. Here, off is represented by a low level, and on by a high level. When the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = 0.9V. The period during which the voltage VFB is initialized is called the initialization period. In Figure 8, the period during which the initialization switch SWR is on corresponds to the initialization period.

[0060] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTH[9:0]=DTL[9:0] with grayscale values ​​0, 127, ..., 1023. As a result, the output voltage VQ changes sequentially from 7.5V to 12.5V. Note that the grayscale values ​​shown here are merely examples of grayscale values ​​that make the voltage range easy to understand, and as mentioned above, the grayscale values ​​written to each pixel can be arbitrary.

[0061] Figure 8 is a third waveform example illustrating the operation of the first and second drive circuits. Figure 8 shows an example waveform of the horizontal scanning period during the negative polarity drive period of polarity reversal drive.

[0062] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=DTL[9:0]=0 and changes DTH

[10] =DTL

[10] from 0 to 1. This corresponds to DTH[10:0]=DTL[10:0]=1024, so the output voltage VQ=7.5V.

[0063] Next, the initialization switch SWR switches from off to on, and then from on to off. When the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = 0.9V.

[0064] Next, the processing circuit 42 changes DTH

[10] =DTL

[10] from 1 to 0. As a result, DTH[10:0]=DTL[10:0]=0, so the output voltage VQ changes from 7.5V to 2.5V.

[0065] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTH[9:0]=DTL[9:0] with grayscale values ​​0, 127, ..., 1023. As a result, the output voltage VQ changes sequentially from 2.5V to 7.5V. Note that the grayscale values ​​shown here are merely examples of grayscale values ​​that make the voltage range easy to understand, and the grayscale values ​​written to each pixel can be arbitrary.

[0066] In the above, DTH[10:0] = DTL[10:0] was assumed, but DTH[10:0] ≠ DTL[10:0] is also possible. For example, DTH[10:0] ≠ DTL[10:0] may occur when correction data is added to the grayscale data DTH[10:0]. The correction data is, for example, data that corrects for excess or deficit charge. The excess or deficit charge is the difference between the charge output by the first drive circuit 60 in the grayscale data DTH[10:0] without the addition of correction data, and the charge required to make the output voltage VQ the target voltage. The correction data is this excess or deficit charge converted into grayscale values. By adding the correction data to the grayscale data DTH[10:0], the error between the output voltage VQ due to the charge output by the first drive circuit 60 and the target voltage corresponding to the grayscale data DTH[10:0] can be reduced. When such correction is performed, if an error still occurs between the output voltage VQ and the target voltage even after the correction, the second drive circuit 70 corrects that error by feedback control using the operational amplifier 71.

[0067] In the above embodiment, the driver 100 includes a first drive circuit 60 that supplies data signals to the signal supply line of the electro-optic panel 200 based on grayscale data, and a second drive circuit 70 electrically connected to the signal supply line. The second drive circuit 70 includes an operational amplifier 71, an output capacitor CQ, a first feedback capacitor Cfa, first to m-th voltage output capacitors CB1 to CBm, and first to m-th voltage output circuits DB1 to DBm. In the first embodiment, CB1 to CB10 correspond to CB1 to CBm, provided that m ≥ 2. The operational amplifier 71 is composed of transistors with a voltage rating lower than the voltage rating of the transistors constituting the first drive circuit 60. The output capacitor CQ is provided between the output node NAMQ of the operational amplifier 71 and the signal supply line. The first feedback capacitor Cfa is provided between the inverting input node NAN of the operational amplifier 71 and the signal supply line. One end of the first to m-th voltage output capacitors CB1 to CBm is connected to the inverting input node NAN of the operational amplifier 71. The first to m-th voltage output circuits DB1 to DBm output voltages based on grayscale data to the other end of the first to m-th voltage output capacitors CB1 to CBm.

[0068] According to this embodiment, the output node NAMQ of the operational amplifier 71 and the signal supply line are coupled by the output capacitor CQ, and the inverting input node NAN of the operational amplifier 71 and the signal supply line are coupled by the first feedback capacitor Cfa. As a result, the operational amplifier 71 and the signal supply line are DC disconnected, so the operational amplifier 71 can be constructed using transistors with a voltage rating lower than the voltage rating of the transistors constituting the first drive circuit 60.

[0069] Furthermore, by configuring the operational amplifier 71 with transistors having a lower voltage rating than the transistors constituting the first drive circuit 60, the operational amplifier 71 can be constructed with high-mobility transistors. This makes it possible to achieve both high amplification and high frequency response characteristics in the operational amplifier. For example, in order to increase the drive speed due to high resolution, it is necessary to increase the frequency response characteristics of the operational amplifier. However, it is possible to increase the frequency response characteristics while maintaining the amplification of the operational amplifier, and thus reduce the power consumption of the operational amplifier.

[0070] An electrical connection is defined as a connection that allows electrical signals to be transmitted, and is a connection that enables the transmission of information via electrical signals. An electrical connection may also be a connection mediated by active elements, etc.

[0071] In this embodiment, a reference voltage VREF is input to the non-inverting input node of the operational amplifier 71.

[0072] According to this embodiment, a reference voltage VREF is input to the non-inverting input node of the operational amplifier 71, and the first to m-th voltage output circuits DB1 to DBm output voltages based on grayscale data to the other ends of the first to m-th voltage output capacitors CB1 to CBm, thereby enabling the second drive circuit 70 to output a voltage corresponding to the grayscale data. That is, the second drive circuit 70 functions as a D / A conversion circuit that performs D / A conversion on the grayscale data.

[0073] In this embodiment, the second drive circuit 70 also includes a second feedback capacitor Cfb provided between the inverting input node NAN of the operational amplifier 71 and a predetermined potential node.

[0074] According to this embodiment, the voltage of the signal supply line is divided by the first feedback capacitor Cfa and the second feedback capacitor Cfb and fed back to the inverting input node NAN of the operational amplifier 71. As a result, a voltage change of 1V, which is smaller than the voltage change of 10V in the signal supply line, is fed back to the inverting input node NAN of the operational amplifier 71, so that the operational amplifier 71 can be constructed with transistors that have a lower voltage rating than the voltage rating of the transistors constituting the first drive circuit 60.

[0075] In this embodiment, the second drive circuit 70 includes a capacitor CBm+1 for the m+1th voltage output, one end of which is electrically connected to the inverting input node NAN of the operational amplifier 71, and a voltage output circuit DBm+1 for the m+1th voltage output, which outputs a voltage based on grayscale data, at the other end of the capacitor CBm+1. In the first embodiment, CB11 corresponds to CBm+1.

[0076] According to this embodiment, the first to m+1 voltage output circuits DB1 to DBm+1 output voltages based on gradation data to the other ends of the first to m+1 voltage output capacitors CB1 to CBm+1, enabling the second drive circuit 70 to output voltages corresponding to the gradation data. As explained in Figure 3, by extending the m=10-bit gradation data by 1 bit to create m+1=11-bit gradation data by combining negative and positive polarity, the second drive circuit 70 can output negative and positive gradation voltages.

[0077] Furthermore, in this embodiment, the total capacitance of the second feedback capacitor Cfb and the first to m+1 voltage output capacitors CB1 to CBm+1 is greater than the capacitance of the first feedback capacitor Cfa. For example, in the first embodiment, when CB = CB1 + CB2 + ... + CB11, (Cfb + CB) / Cfa = 9.

[0078] The gain at which the voltage change at the output node NVQ is fed back to the inverting input node NAN of the operational amplifier 71 is Cfa / (Cfa+Cfb+CB). According to this embodiment, since the feedback gain is less than 1 / 2, the voltage range fed back to the inverting input node NAN of the operational amplifier 71 is less than 1 / 2 of the voltage range of the signal supply line. As a result, the operational amplifier 71 can be constructed using transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0079] In this embodiment, the source-drain distance of the transistors constituting the first drive circuit 60 is longer than the source-drain distance of the transistors constituting the second drive circuit 70. Alternatively, the thickness of the gate insulating film of the transistors constituting the first drive circuit 60 is thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit 70.

[0080] According to this embodiment, the transistors constituting the second drive circuit 70, which includes the operational amplifier 71, can be composed of transistors with a lower breakdown voltage than the transistors constituting the first drive circuit 60.

[0081] In this embodiment, the first to m-th voltage output circuits DB1 to DBm are composed of transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0082] As described above, in this embodiment, the voltage change fed back to the inverting input node NAN of the operational amplifier 71 is Vfa = 1V ≤ 1.8V = VDL. This allows the first to m-th voltage output circuits DB1 to DBm to be constructed with low-voltage transistors. By using low-voltage transistors, it is possible to achieve faster pixel driving and a smaller driver area.

[0083] The m+1 voltage output circuit DBm+1 may be composed of a transistor with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60, or it may be composed of a transistor with the same breakdown voltage as the transistors constituting the first drive circuit 60, as will be described later in the third embodiment.

[0084] In this embodiment, the driver 100 also includes an initialization switch SWR. The initialization switch SWR is turned on during the initialization period and supplies a reference voltage VREF to the inverting input node NAN of the operational amplifier 71.

[0085] According to this embodiment, the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF during the initialization period, and then maintained at the reference voltage VREF by a virtual short. As a result, if the output voltage VQ output by the first drive circuit 60 deviates from the target voltage, the voltage of the inverting input node NAN of the operational amplifier 71 deviates from the reference voltage VREF, and the operational amplifier 71 corrects this deviation so that the output voltage VQ becomes the target voltage.

[0086] In this embodiment, the first drive circuit 60 includes a capacitor drive circuit 20 and a capacitor circuit 10. The capacitor drive circuit 20 outputs the first to nth capacitor drive voltages corresponding to the grayscale data DTH[10:0] to the first to nth capacitor drive nodes NDR1 to NDRn, where n is an integer of 2 or more. The capacitor circuit 10 has a signal supply line and first to nth capacitors C1 to Cn provided between the signal supply line and the first to nth capacitor drive nodes NDR1 to NDRn.

[0087] According to this embodiment, the capacitor drive circuit 20 outputs a first to nth capacitor drive voltage corresponding to the grayscale data DTH[10:0], causing the first to nth capacitors C1 to Cn to output a charge corresponding to the grayscale data DTH[10:0] to the signal supply line. As a result, a voltage corresponding to the grayscale data DTH[10:0] is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit 70 can correct this error by feedback control.

[0088] 3. Second Embodiment Figure 9 shows a second detailed configuration example of the driver. In this configuration example, the data line drive circuit 110 includes a first drive circuit 60 and a second drive circuit 70. The processing circuit 42 outputs setting data DP[9:0] and DN[9:0] which set the drive capability of the first drive circuit 60 based on the grayscale data GD[9:0]. Since the configuration and operation of the second drive circuit 70 are the same as in the first embodiment, the configuration and operation of the first drive circuit 60 will be mainly described below.

[0089] Figure 10 illustrates the relationship between grayscale data, setting data, and data voltage. The relationship between grayscale data GD[9:0], grayscale data DTH[10:0], and data voltage is the same as in Figure 3.

[0090] Assume that one pixel is driven with a grayscale value DTH1, the next pixel is driven with a grayscale value DTH2, and DTH2-DTH1>0. In this case, the processing circuit 42 outputs DP[9:0]=|DTH2-DTH1| and DN[9:0]=0. Assume that one pixel is driven with a grayscale value DTH3, the next pixel is driven with a grayscale value DTH4, and DTH4-DTH3<0. In this case, the processing circuit 42 outputs DP[9:0]=0 and DN[9:0]=|DTH4-DTH3|. Figure 10 shows an example of positive polarity driving, but the same applies to negative polarity driving.

[0091] Furthermore, since DTH

[10] is canceled when the difference is taken, it is also possible to directly calculate DP[9:0] and DN[9:0] from the grayscale data GD[9:0] without going through DTH[10:0].

[0092] Figure 11 shows a second detailed configuration example of the first drive circuit. In this configuration example, the first drive circuit 60 includes a first drive transistor group TRG1 and a second drive transistor group TRG2.

[0093] The first drive transistor group TRG1 includes P-type transistors TP1 to TP10 connected in parallel between the node of the high-potential side power supply voltage VDH and the output node NVQ. The gate of P-type transistor TP1 is input to the bit signal XDP[0]. Similarly, the gates of P-type transistors TP2 to TP10 are input to the bit signals XDP[1] to XDP[9]. XDP[9:0] is the data obtained by logically inverting each bit of DP[9:0]. The drive capability of P-type transistors TP1 to TP10 is binary weighted. That is, the drive capability of P-type transistor TPi is twice the drive capability of P-type transistor TP1. (i-1) It is double. The driving capability is adjusted by, for example, the gate width of the transistor or the number of unit transistors connected in parallel.

[0094] The second group of drive transistors, TRG2, includes N-type transistors TN1 to TN10 connected in parallel between the output node NVQ and the low-potential power supply voltage VSH. The gate of N-type transistor TN1 is input to the bit signal DN[0]. Similarly, the gates of N-type transistors TN2 to TN10 are input to the bit signals DN[1] to DN[9]. The drive capability of N-type transistors TN1 to TN10 is binary weighted. That is, the drive capability of N-type transistor TNi is twice the drive capability of N-type transistor TN1. (i-1) It is double.

[0095] For example, let Itp1 be the current that flows when a P-type transistor TP1 is ON, and let ton be the ON period for driving one pixel. The charge that the P-type transistor TP1 supplies to the output node NVQ is Itp1 × ton, and the change in output voltage VQ due to that charge is (Itp1 × ton) / CP. Itp1 is set so that this voltage change is 1 LSB, that is, the driving capability of the P-type transistor TP1 is set.

[0096] Figure 12 is a fourth waveform example illustrating the operation of the first and second drive circuits. Figure 12 shows an example waveform of the horizontal scanning period during the positive polarity drive period.

[0097] After the horizontal scanning period begins, the processing circuit 42 outputs DTL[9:0]=DP[9:0]=DN[9:0]=0 and changes DTL

[10] from 0 to 1. This corresponds to DTL[10:0]=1024, so the output voltage VQ=7.5V.

[0098] Next, the initialization switch SWR switches from off to on, and then from on to off. When the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = 0.9V.

[0099] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTL[9:0] with grayscale values ​​of 0, 127, ..., 1023, and also sequentially outputs DP[9:0]=0, 127, 128, ..., 128. As a result, the output voltage VQ changes sequentially from 7.5V to 12.5V. Note that Figure 12 shows an example where DP[9:0]>0 and DN[9:0]=0, but when the grayscale value of DTL[9:0] decreases, DP[9:0]=0 and DN[9:0]>0. Note that the grayscale values ​​shown here are just examples that make the voltage range easy to understand, and the grayscale values ​​written to each pixel can be arbitrary.

[0100] The waveform diagram for the negative polarity drive period is omitted. During the negative polarity drive period, the waveforms of SWR, DTL[9:0], DP[9:0], and DN[9:0] are the same as in Figure 12. The waveforms of DTL

[10] and VQ are the same as in Figure 8.

[0101] In the above embodiment, the driver 100 includes a control circuit 40 that controls the first drive circuit 60. The first drive circuit 60 includes a first drive transistor group TRG1 provided between a node to which a high-potential-side power supply voltage VDH is supplied and a signal supply line, and a second drive transistor group TRG2 provided between a node to which a low-potential-side power supply voltage VSH is supplied and a signal supply line. The control circuit 40 controls each transistor of the first drive transistor group TRG1 or each transistor of the second drive transistor group TRG2 to be turned on or off based on the grayscale data GD[9:0].

[0102] According to this embodiment, based on the grayscale data GD[9:0], the transistor that is turned on from the first drive transistor group TRG1 or the second drive transistor group TRG2 outputs a charge corresponding to the grayscale data GD[9:0] to the signal supply line. As a result, a voltage corresponding to the grayscale data GD[9:0] is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit 70 can correct this error by feedback control.

[0103] 4. Third Embodiment In the third embodiment, the configuration and operation of the first drive circuit 60 are the same as in the first or second embodiment. The following will mainly describe the differences in the configuration and operation of the second drive circuit 70 compared to the first embodiment.

[0104] Figure 13 shows a second detailed configuration example of the second drive circuit. In this configuration example, the processing circuit 42 outputs grayscale data DTM[9:0] based on grayscale data GD[9:0]. The voltage output circuits DB10, DB9, ..., DB1 are input to the bit signals XDTM[9], XDTM[8], ..., XDTM[0], which are the logical inversion signals of the bit signals DTM[9], DTM[8], ..., DTM[0]. The processing circuit 42 also outputs a polarity inversion signal FR indicating the drive polarity. The voltage output circuit DB11 is input to the signal XFR, which is the logical inversion signal of the polarity inversion signal FR.

[0105] Figure 14 shows the relationship between the grayscale data and the output voltage of the data line drive circuit. In positive polarity drive, the processing circuit 42 sets DTM[9:0]=GD[9:0], and the second drive circuit 70 outputs an output voltage VQ=7.5V~15V for DTM[9:0]=0~1023. In negative polarity drive, the processing circuit 42 sets DTM[9:0]=XGD[9:0], and the second drive circuit 70 outputs an output voltage VQ=2.5V~7.5V for DTM[9:0]=0~1023.

[0106] In this configuration example, when the first drive circuit 60 changes the voltage of the output node NVQ by 5V, the voltage change fed back to the inverting input node NAN of the operational amplifier 71 via the first feedback capacitor Cfa is Vfa = 1V. In this case, it is sufficient that 10V is divided in a 4:1 ratio by Cfa and Cfb + CB, so (Cfb + CB) / Cfa = 4. As mentioned above, it is sufficient that Vfa ≤ 1.8V. Also, in this configuration example, it is sufficient that the voltage output capacitor CB11 and the voltage output circuit DB11 produce a voltage shift equivalent to Vfa = 1V / 2 = 0.5V, so the capacitance value of the voltage output capacitor CB11 is CB11 = CB10.

[0107] Figure 15 shows a second detailed configuration example of the second drive circuit. In this configuration example, the second drive circuit 70 further includes level shifters LSB11 and LSB10. Here, an example is shown in which level shifters are provided before the voltage output circuits DB11 and DB10, but it is not limited to this. For example, a level shifter may be provided only before the voltage output circuit DB11, or a level shifter may be provided before any number of voltage output circuits from DB10 to DB1, starting from the upper end.

[0108] The level shifter LSB11 shifts the signal XFR to the high-voltage process power supply voltages VDH and VSH. That is, when the signal XFR is low level, i.e., VSL=0V, the level shifter LSB11 outputs a signal with VSH=0V, and the voltage output circuit DB11 outputs a VSH=0V signal to the other end of the voltage output capacitor CB11. When the signal XFR is high level, i.e., VDL=1.8V, the level shifter LSB11 outputs a signal with VDH=15V, and the voltage output circuit DB11 outputs a VDH=15V signal to the other end of the voltage output capacitor CB11.

[0109] The level shifter LSB10 level-shifts the bit signal XDTM[9] to the high-voltage process power supply voltages VDH and VSH. That is, when the signal XDTM[9] is at a low level, i.e., VSL=0V, the level shifter LSB10 outputs a signal with VSH=0V, and the voltage output circuit DB10 outputs a signal with VSH=0V to the other end of the voltage output capacitor CB10. When the signal XDTM[9] is at a high level, i.e., VDL=1.8V, the level shifter LSB10 outputs a signal with VDH=15V, and the voltage output circuit DB10 outputs a signal with VDH=15V to the other end of the voltage output capacitor CB10.

[0110] Since the voltage amplitude output by voltage output circuits DB11 and DB10 becomes 15V, the capacitance values ​​of voltage output capacitors CB11 and CB10 can be reduced to 1.8V / 15V = 3 / 25 times compared to the second detailed configuration example.

[0111] Figure 16 is a fifth waveform example illustrating the operation of the first and second drive circuits. Figure 16 shows an example waveform of the horizontal scanning period during the positive polarity drive period.

[0112] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=0 and DTM[9:0]=512, and changes DTH

[10] from 0 to 1. At this time, the output voltage VQ=7.5V.

[0113] Next, the processing circuit 42 changes the signal XFR from a low level to a high level, and then switches the initialization switch SWR from off to on, and then from on to off. When the signal XFR is at a high level and the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = 0.9V. Next, the processing circuit 42 changes the signal XFR from a high level to a low level, for example, changing DTM[9:0] from 512 to 0. As XFR changes from a high level to a low level and XDTM[9] changes from a low level to a high level, and as mentioned above CB11 = CB10, the charges are canceled and the output voltage VQ of the second drive circuit 70 does not change. Note that in Figure 16, the period from when the initialization switch SWR is turned from off to on until the signal XFR changes from a high level to a low level corresponds to the initialization period.

[0114] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTH[9:0]=DTM[9:0] with grayscale values ​​0, 127, ..., 1023. As a result, the output voltage VQ changes sequentially from 7.5V to 12.5V. Note that the grayscale values ​​shown here are merely examples of grayscale values ​​that make the voltage range easy to understand, and the grayscale values ​​written to each pixel can be arbitrary.

[0115] In the third embodiment, the feedback gain from the output voltage VQ to the voltage VFB of the inverting input node NAN of the operational amplifier 71 is 1 / 5. That is, a change of 5V in the output voltage VQ is fed back to the inverting input node NAN of the operational amplifier 71 as a voltage change of Vfa = 1V. This Vfa = 1V is canceled by the charge input and output of the voltage output capacitors CB1 to CB10. On the other hand, in the first embodiment, the feedback gain is 1 / 10, so a change of 5V in the output voltage VQ is fed back as a voltage change of Vfa = 0.5V. This Vfa = 0.5V is similarly canceled by the charge input and output of the voltage output capacitors CB1 to CB10. From these observations, it can be said that the third embodiment substantially performs D / A conversion of 10 bits of data to a voltage range of 1V, while the first embodiment substantially performs D / A conversion of 10 bits of data to a voltage range of 0.5V. Therefore, the voltage step per LSB is larger in the third embodiment, which improves the accuracy of the D / A conversion.

[0116] Figure 17 is a sixth waveform example illustrating the operation of the first and second drive circuits. Figure 17 shows an example waveform of the horizontal scanning period during the negative polarity drive period.

[0117] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=0 and DTM[9:0]=512, and changes DTH

[10] from 0 to 1. At this time, the output voltage VQ=7.5V.

[0118] Next, the processing circuit 42 changes the signal XFR from a high level to a low level, then switches the initialization switch SWR from off to on, and then from on to off. When the signal XFR is at a low level and the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = 0.9V. Next, the processing circuit 42 changes the signal XFR from a low level to a high level, changing DTH

[10] from 1 to 0, for example, to make DTH[9:0] = DTM[9:0] 1023. At this time, since the output voltage of the first drive circuit 60 and the output voltage of the second drive circuit 70 do not change, the voltage VQ of the output node NVQ does not change.

[0119] Next, writing to the pixels begins. The processing circuit 42 sets DTH

[10] from 1 to 0, and then sequentially outputs DTH[9:0]=DTM[9:0] with gradation values ​​of 1023, 895, ..., 0. As a result, the output voltage VQ changes sequentially from 7.5V to 2.5V. Note that the gradation values ​​shown here are merely examples that make the voltage range easy to understand, and the gradation values ​​written to each pixel can be arbitrary.

[0120] Furthermore, the ability to improve the accuracy of D / A conversion compared to the first embodiment is the same as in the case of positive polarity drive described above.

[0121] In the embodiments described above, the second drive circuit 70 includes a capacitor CBm+1 for the m+1th voltage output, one end of which is electrically connected to the inverting input node NAN of the operational amplifier 71, and a voltage output circuit DBm+1 for the m+1th voltage output, which outputs a voltage based on the polarity inversion signal FR, at the other end of the capacitor CBm+1. In the third embodiment, CB11 corresponds to CBm+1. Furthermore, since the logic inverted signal of the polarity inversion signal FR is input to CB11, CB11 outputs a voltage based on the polarity inversion signal FR.

[0122] According to this embodiment, the m+1 voltage output circuit DBm+1 outputs a voltage based on the polarity inversion signal FR, causing the m+1 voltage output capacitor CBm+1 to output a charge based on the polarity inversion signal FR to the inverting input node NAN of the operational amplifier 71. As a result, as described above, the feedback gain from the output node NVQ to the inverting input node NAN of the operational amplifier 71 can be made smaller than in the first embodiment, which enables improvements in the accuracy of the D / A conversion of the second drive circuit 70.

[0123] Furthermore, in this embodiment, the total capacitance of the second feedback capacitor Cfb and the first to m+1 voltage output capacitors CB1 to CBm+1 is greater than the capacitance of the first feedback capacitor Cfa. For example, in the first embodiment, when CB = CB1 + CB2 + ... + CB11, (Cfb + CB) / Cfa = 4.

[0124] The gain at which the voltage change at the output node NVQ is fed back to the inverting input node NAN of the operational amplifier 71 is Cfa / (Cfa+Cfb+CB). According to this embodiment, since the feedback gain is less than 1 / 2, the voltage range fed back to the inverting input node NAN of the operational amplifier 71 is less than 1 / 2 of the voltage range of the signal supply line. As a result, the operational amplifier 71 can be constructed using transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0125] 5. Electronic equipment Figure 18 shows an example of the configuration of an electronic device including the driver of this embodiment. Various electronic devices equipped with a display device can be envisioned as the electronic device of this embodiment. For example, the electronic device may be a projector, television system, information processing device, portable information terminal, car navigation system, or portable game terminal.

[0126] The electronic device 500 includes an electro-optical device 400, a display controller 300, a processing unit 310, a storage unit 320, a user interface unit 330, and a data interface unit 340. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200.

[0127] The electro-optic panel 200 is, for example, a matrix-type liquid crystal display panel. Alternatively, the electro-optic panel 200 may be an EL display panel using self-luminescent elements. EL stands for Electro-Luminescence. The user interface unit 330 is an interface unit that accepts various operations from the user. For example, it consists of buttons, a mouse, a keyboard, or a touch panel attached to the electro-optic panel 200. The data interface unit 340 is an interface unit that performs input and output of image data or control data. For example, it is a wired communication interface such as USB, or a wireless communication interface such as wireless LAN. The storage unit 320 stores the image data input from the data interface unit 340. Alternatively, the storage unit 320 functions as the working memory of the processing unit 310 or the display controller 300. The processing unit 310 performs control processing of various parts of the electronic device and various data processing. The processing unit 310 is, for example, a processor such as a CPU or a microcomputer. The display controller 300 performs control processing of the driver 100. For example, the display controller 300 converts the image data transferred from the data interface unit 340 or the storage unit 320 into a format that the driver 100 can accept, and outputs the converted image data to the driver 100. The driver 100 drives the electro-optical panel 200 based on the image data transferred from the display controller 300.

[0128] The driver of this embodiment described above includes a first drive circuit that supplies data signals to the signal supply line of an electro-optical panel based on grayscale data, and a second drive circuit electrically connected to the signal supply line. The second drive circuit includes an operational amplifier composed of transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit, and an output capacitor placed between the output node of the operational amplifier and the signal supply line. The second drive circuit also includes a first feedback capacitor placed between the inverting input node of the operational amplifier and the signal supply line, and first to m voltage output capacitors, one end of which is connected to the inverting input node of the operational amplifier, where m is an integer of 2 or more. The second drive circuit also includes first to m voltage output circuits that output voltages based on grayscale data to the other end of the first to m voltage output capacitors.

[0129] According to this embodiment, the output capacitor and the first feedback capacitor result in a DC disconnection between the operational amplifier and the signal supply line. This allows the operational amplifier to be constructed using transistors with a lower voltage rating than the transistors constituting the first drive circuit. Furthermore, by constructing the operational amplifier with low-voltage transistors, the operational amplifier can be constructed with high-mobility transistors. This makes it possible to achieve both high amplification and high frequency response characteristics in the operational amplifier. In addition, it becomes possible to reduce the power consumption of the operational amplifier.

[0130] In this embodiment, a reference voltage may also be input to the non-inverting input node of the operational amplifier.

[0131] According to this embodiment, a reference voltage is input to the non-inverting input node of the operational amplifier, and the first to m-th voltage output circuits output voltages based on grayscale data to the other ends of the first to m-th voltage output capacitors, thereby enabling the second drive circuit to output a voltage corresponding to the grayscale data. In other words, the second drive circuit functions as a D / A conversion circuit that performs D / A conversion on the grayscale data.

[0132] In this embodiment, the second drive circuit may also include a second feedback capacitor positioned between the inverting input node and a predetermined potential node of the operational amplifier.

[0133] According to this embodiment, the voltage of the signal supply line is divided by the first and second feedback capacitors and fed back to the inverting input node of the operational amplifier. As a result, a voltage change smaller than the voltage change of the signal supply line is fed back to the inverting input node of the operational amplifier, so the operational amplifier can be constructed using transistors with a voltage rating lower than the voltage rating of the transistors constituting the first drive circuit.

[0134] In this embodiment, the second drive circuit may also include a capacitor for the m+1 voltage output, one end of which is electrically connected to the inverting input node of the operational amplifier, and a voltage output circuit for the m+1 voltage output, which outputs a voltage based on grayscale data to the other end of the capacitor for the m+1 voltage output.

[0135] According to this embodiment, the first to m+1 voltage output circuits output voltages based on gradation data to the other ends of the first to m+1 voltage output capacitors, enabling the second drive circuit to output voltages corresponding to the gradation data. By extending the m-bit gradation data by one bit to create m+1-bit gradation data that combines negative and positive polarity, the second drive circuit can output negative and positive gradation voltages.

[0136] In this embodiment, the total capacitance of the second feedback capacitor and the first to m+1 voltage output capacitors may be greater than the capacitance of the first feedback capacitor.

[0137] According to this embodiment, the gain at which the voltage change at the output node of the first drive circuit is fed back to the inverting input node of the operational amplifier is less than 1 / 2. As a result, the voltage range fed back to the inverting input node of the operational amplifier is less than 1 / 2 of the voltage range of the signal supply line. This allows the operational amplifier to be constructed using transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit.

[0138] In this embodiment, the driver may also include a capacitor for the m+1 voltage output, one end of which is electrically connected to the inverting input node of the operational amplifier, and a circuit for the m+1 voltage output, which outputs a voltage based on a polarity inversion signal, at the other end of the capacitor for the m+1 voltage output.

[0139] According to this embodiment, the m+1 voltage output circuit outputs a voltage based on the polarity inversion signal, causing a charge based on the polarity inversion signal to be output from the m+1 voltage output capacitor to the inverting input node of the operational amplifier. This makes it possible to reduce the feedback gain from the output node of the first drive circuit to the inverting input node of the operational amplifier, thereby improving the accuracy of the D / A conversion of the second drive circuit.

[0140] In this embodiment, the source-drain distance of the transistors constituting the first drive circuit may be longer than the source-drain distance of the transistors constituting the second drive circuit. Alternatively, the thickness of the gate insulating film of the transistors constituting the first drive circuit may be thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit.

[0141] According to this embodiment, the transistors constituting the second drive circuit, which includes an operational amplifier, can be configured with transistors having a lower breakdown voltage than the transistors constituting the first drive circuit.

[0142] In this embodiment, the first to m-th voltage output circuits may be composed of transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit.

[0143] In this embodiment, the voltage change fed back to the inverting input node of the operational amplifier is less than or equal to the power supply voltage of the operational amplifier. This allows the first to mth voltage output circuits to be constructed with low-voltage transistors. By using low-voltage transistors, it is possible to achieve faster pixel driving and a smaller driver area.

[0144] In this embodiment, the driver may also include an initialization switch. The initialization switch may be turned on during the initialization period and supply a reference voltage to the inverting input node of the operational amplifier.

[0145] According to this embodiment, the inverting input node of the operational amplifier is initialized to a reference voltage during the initialization period, and then maintained at the reference voltage by a virtual short circuit. As a result, if the output voltage output by the first drive circuit deviates from the target voltage, the voltage at the inverting input node of the operational amplifier deviates from the reference voltage, and the operational amplifier corrects this deviation so that the output voltage becomes the target voltage.

[0146] In this embodiment, the first drive circuit may also include a capacitor drive circuit that outputs first to nth capacitor drive voltages corresponding to grayscale data to first to nth capacitor drive nodes, and a capacitor circuit having first to nth capacitors arranged between a signal supply line and the first to nth capacitor drive nodes, where n is an integer of 2 or more.

[0147] According to this embodiment, the capacitor drive circuit outputs a first to nth capacitor drive voltage corresponding to the grayscale data, causing the first to nth capacitors to output a charge corresponding to the grayscale data to the signal supply line. As a result, a voltage corresponding to the grayscale data is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit can correct this error by feedback control.

[0148] In this embodiment, the driver may also include a control circuit for controlling the first drive circuit. The first drive circuit may include a group of first drive transistors arranged between a node to which a high-potential power supply voltage is supplied and a signal supply line, and a group of second drive transistors arranged between a node to which a low-potential power supply voltage is supplied and a signal supply line. The control circuit may control each transistor of the first drive transistor group or each transistor of the second drive transistor group to be turned on or off based on grayscale data.

[0149] According to this embodiment, based on the grayscale data, the transistors that are turned on from the first group of drive transistors or the second group of drive transistors output a charge corresponding to the grayscale data to the signal supply line. As a result, a voltage corresponding to the grayscale data is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit can correct this error by feedback control.

[0150] Furthermore, the electro-optical device of this embodiment includes a driver as described in any of the above and an electro-optical panel.

[0151] Furthermore, the electronic device of this embodiment includes a driver as described in any of the above.

[0152] Although this embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novelty and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, any term that appears at least once in the specification or drawings together with a broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. In addition, the configuration and operation of control circuits, data line drive circuits, drivers, electro-optic panels, electro-optic devices, and electronic equipment are not limited to those described in this embodiment, and various modifications are possible. [Explanation of symbols]

[0153] 10...Capacitor circuit, 20...Capacitor drive circuit, 30...Variable capacitance circuit, 40...Control circuit, 42...Processing circuit, 44...Interface circuit, 48...Register circuit, 50...Detection circuit, 60...First drive circuit, 70...Second drive circuit, 71...Operational amplifier, 100...Driver, 110...Data line drive circuit, 200...Electro-optic panel, 300...Display controller, 310...Processing unit, 320...Storage unit, 330...User interface unit, 340...Data interface unit, 400...Electro-optic device, 500...Electronic equipment, C1~C11...Capacitors, CB1~CB11...Voltage output capacitors, CQ ...Output capacitor, Cfa...First feedback capacitor, Cfb...Second feedback capacitor, DB1~DB11...Voltage output circuit, DR1~DR11...Drive circuit, DTH[10:0], DTL[10:0]...Gradation data, FR...Polarity inversion signal, GD[9:0]...Gradation data, LSB10, LSB11...Level shifter, NAN...Operational amplifier inverting input node, NDR1~NDR10...Capacitor drive node, SPL1~SPL8...Signal supply line, SWR...Initialization switch, TRG1...First drive transistor group, TRG2...Second drive transistor group, VFB...Voltage, VREF...Reference voltage

Claims

1. A first drive circuit that supplies data signals to the signal supply lines of an electro-optical panel based on grayscale data, A second drive circuit is electrically connected to the signal supply line and includes an operational amplifier composed of transistors having a voltage rating lower than the voltage rating of the transistors constituting the first drive circuit, an output capacitor disposed between the output node of the operational amplifier and the signal supply line, a first feedback capacitor disposed between the inverting input node of the operational amplifier and the signal supply line, first to m voltage output capacitors (where m is an integer of 2 or more) with one end electrically connected to the inverting input node of the operational amplifier, and first to m voltage output circuits that output voltages based on the grayscale data at the other end of the first to m voltage output capacitors. A driver characterized by including [this].

2. In the driver described in claim 1, A driver characterized in that a reference voltage is input to the non-inverting input node of the operational amplifier.

3. In the driver described in claim 1, The second drive circuit is, A driver characterized by including a second feedback capacitor positioned between the inverting input node and a predetermined potential node of the operational amplifier.

4. In the driver described in claim 3, The second drive circuit is, A capacitor for the m+1 voltage output, one end of which is electrically connected to the inverting input node of the operational amplifier, The other end of the m+1 voltage output capacitor is connected to an m+1 voltage output circuit that outputs a voltage based on the grayscale data, A driver characterized by including [this].

5. In the driver described in claim 4, The total capacitance of the second feedback capacitor and the first to m+1 voltage output capacitors is A driver characterized by having a capacitance greater than that of the first feedback capacitor.

6. In the driver described in claim 3, A capacitor for the m+1 voltage output, one end of which is electrically connected to the inverting input node of the operational amplifier, The other end of the aforementioned m+1 voltage output capacitor is connected to an m+1 voltage output circuit that outputs a voltage based on a polarity reversal signal, A driver characterized by including [this].

7. In the driver described in claim 6, The total capacitance of the second feedback capacitor and the first to m+1 voltage output capacitors is A driver characterized by having a capacitance greater than that of the first feedback capacitor.

8. In the driver described in claim 1, A driver characterized in that the source-drain distance of the transistors constituting the first drive circuit is longer than the source-drain distance of the transistors constituting the second drive circuit, or the thickness of the gate insulating film of the transistors constituting the first drive circuit is thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit.

9. In a driver according to any one of claims 1 to 8, The first to m voltage output circuits are, A driver characterized by being composed of transistors with a voltage rating lower than that of the transistors constituting the first drive circuit.

10. In a driver according to any one of claims 1 to 8, A driver characterized by including an initialization switch that turns on during the initialization period and supplies a reference voltage to the inverting input node of the operational amplifier.

11. In a driver according to any one of claims 1 to 8, The first drive circuit is, A capacitor drive circuit that outputs first to nth capacitor drive voltages (where n is an integer of 2 or more) corresponding to the grayscale data to the first to nth capacitor drive nodes, A capacitor circuit having first to n capacitors arranged between the signal supply line and the first to n capacitor drive node, A driver characterized by including [this].

12. In a driver according to any one of claims 1 to 8, Includes a control circuit for controlling the first drive circuit, The first drive circuit is, A first group of drive transistors is arranged between the node to which the high-potential power supply voltage is supplied and the signal supply line, A second group of drive transistors is arranged between the node to which the low-potential power supply voltage is supplied and the signal supply line, Includes, The aforementioned control circuit is A driver characterized by controlling each transistor in the first drive transistor group or each transistor in the second drive transistor group to be turned on or off based on the aforementioned grayscale data.

13. A driver according to any one of claims 1 to 8, The aforementioned electro-optical panel, An electro-optical apparatus characterized by including [a certain component].

14. An electronic device characterized by including a driver as described in any one of claims 1 to 8.

Images