Electronic components, coil components, and methods for manufacturing electronic components

Abstract

To prevent deviation in lamination or misalignment of wiring layers without deteriorating electrical characteristics, in an electronic component that includes a second insulating layer laminated on a principal surface of a first insulating layer in which a circuit pattern is buried.SOLUTION: An electronic component comprises: a first insulating layer with a principal surface; a circuit pattern buried in the first insulating layer, extending along a plane parallel to the principal surface; and a second insulating layer laminated on the principal surface. A cross section of the first insulating layer orthogonal to the principal surface is such an inverted trapezoid that a length of a lower side at an opposite side to the principal surface is shorter than a length of an upper side at the principal surface side.SELECTED DRAWING: Figure 2

Description

Technical Field

[0002] , , , ,

[0001] The present invention relates to electronic components, coil components, and a method for manufacturing electronic components.

Background Art

[0002] Conventionally, coil components having coils plated and grown on a substrate are known. <00000!0>In Patent Document 1, for the purpose of improving the insulation of a coil, a plurality of resin walls having openings on a substrate are provided as insulating walls, and the coil is plated and grown so that a winding portion extends between the insulating walls. A method for manufacturing a coil component is disclosed. Further, Patent Document 2 discloses a coil component in which the insulating wall on the substrate as described above is formed in a tapered shape whose width at the upper end is narrower than the width at the lower end, and the strength of the winding portion is improved.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] All of the above conventional coil components only have one layer of winding portions on one or both of the main surfaces of the substrate, and do not disclose forming a plurality of layers of winding portions on one main surface to constitute a coil.

[0005] When attempting to construct two or more winding layers on a single main surface of a substrate, it is necessary to precisely align the insulating wall of the upper winding layer with respect to the lower winding layer. However, when the insulating wall of the upper layer is formed by photolithography, depending on the accuracy of the exposure alignment, misalignment between layers (stack misalignment) may occur, potentially resulting in a "missed step" condition where a portion of the upper winding layer falls onto the substrate beyond the upper surface area of ​​the lower winding layer.

[0006] One way to prevent such slippage is to configure each layer such that the lower surface of the upper winding section is contained within the range of the upper winding section of the lower winding section; in other words, in a cross-sectional view of the winding section, the width of the cross-sectional shape of the upper winding section is narrower than the width of the cross-sectional shape of the lower winding section.

[0007] However, in order to achieve the above configuration, it may be necessary to make the width of the lower layer greater than the width of the upper layer by making the thickness of the insulating wall in the lower winding thicker than that of the upper winding, or by reducing the number of turns in the upper winding compared to the lower winding, or by making the coil conductor thinner (for example, narrower). As a result, a decrease in electrical characteristics such as a decrease in the inductance value of the coil component and an increase in electrical resistance may occur.

[0008] When stacking layered wiring layers, such as the winding section described above, in which circuit patterns are embedded in an insulating layer, the aforementioned misalignment and slippage that can occur, as well as the reduction in the thickness of the insulating wall in the upper layer and the reduction in the number of conductors that may result from trying to prevent these issues, are undesirable not only for coil components but also for electronic components in general.

[0009] The object of the present invention is to prevent misalignment or displacement of wiring layers without impairing electrical characteristics in an electronic component including a second insulating layer laminated on the main surface of a first insulating layer in which a circuit pattern is embedded. [Means for solving the problem]

[0010] One aspect of the present invention provides an insulating layer comprising a first insulating layer having a main surface and a second insulating layer laminated on the main surface, wherein each insulating layer has a circuit pattern embedded therein and extending along a plane parallel to the main surface. and, Circuit pattern An absolute interval extending within the mutual interval Including an edge wall, the insulating wall is integrally formed with the insulating layer using the same photosensitive resin as the insulating layer, and the cross-section of the first insulating layer perpendicular to the main surface is such that the length of the lower side opposite to the main surface is shorter than the length of the upper side on the main surface side. The two opposing sides connecting the end of the upper side and the end of the lower side form a straight line. It is an electronic component that is shaped like an inverted trapezoid. Another aspect of the present invention comprises the steps of forming a circuit pattern extending along a plane, forming a first insulating layer having a main surface parallel to the plane that covers the circuit pattern, and laminating a second insulating layer on the main surface, wherein in the step of forming the first insulating layer, a photosensitive resin is placed so as to cover the circuit pattern, and the photosensitive resin is exposed and developed by irradiating the surface of the photosensitive resin with light from a projection exposure apparatus set to off-focus, thereby forming a cross-section of the first insulating layer perpendicular to the main surface such that the length of the lower side opposite to the main surface is shorter than the length of the upper side on the main surface side. The two opposing sides connecting the end of the upper side and the end of the lower side form a straight line. Formed in a trapezoidal shape, the circuit pattern An absolute interval extending within the mutual interval This is a method for manufacturing electronic components, wherein the edge wall is formed from the same exposure-developed photosensitive resin as the first insulating layer. [Effects of the Invention]

[0011] According to the present invention, in an electronic component including a second insulating layer laminated on the main surface of a first insulating layer in which a circuit pattern is embedded, it is possible to prevent misalignment or slippage of the wiring layers without impairing their electrical characteristics. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic diagram showing the internal structure of a coil component according to the first embodiment of the present invention. [Figure 2] Figure 1 is a detailed view of the laminated coil component shown. [Figure 3]It is a diagram showing the manufacturing process of the laminate shown in FIG. 2. [Figure 4] It is a diagram showing the manufacturing process following FIG. 3 of the laminate shown in FIG. 2. [Figure 5] It is a diagram showing the configuration of the coil component according to the second embodiment. [Figure 6] It is a partial detailed view of the laminate of the coil component shown in FIG. 5. [Figure 7] It is a diagram for explaining the dimension definition of the laminate shown in FIG. 6. [Figure 8] It is a diagram showing the manufacturing process of the laminate shown in FIG. 7. [Figure 9] It is a diagram showing the manufacturing process following FIG. 8 of the laminate shown in FIG. 7. [Figure 10] It is a diagram showing the configuration of the coil component according to the third embodiment. [Figure 11] It is a partial detailed view of the laminate of the coil component shown in FIG. 10. [Figure 12] It is a diagram showing the manufacturing process of the laminate shown in FIG. 11. [Figure 13] It is a diagram showing the manufacturing process following FIG. 12 of the laminate shown in FIG. 11. [Figure 14] It is a diagram showing the configuration of the coil component according to the fourth embodiment. [Figure 15] It is a partial detailed view of the laminate of the coil component shown in FIG. 14. [Figure 16] It is a diagram showing an example of the process of embedding the laminate shown in FIG. 15 in a magnetic layer. [Figure 17] It is a diagram showing a modified example of the laminate shown in FIG. 15.

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a coil component will be described as an example of an electronic component including a laminate in which insulating layers are laminated. Note that the drawings may partly include schematic diagrams. Also, the dimensions and ratios in the schematic diagrams may differ from the actual values.

[0014] [First Embodiment] First, let me describe the first embodiment. Figure 1 is a schematic diagram showing the internal structure of a coil component 1 according to the first embodiment of the present invention. The coil component 1 comprises a first insulating layer 21a having a main surface La, a circuit pattern 22 embedded in the first insulating layer 21a and extending along a plane parallel to the main surface La of the first insulating layer 21a, and a second insulating layer 21b laminated on the main surface La of the first insulating layer 21a. In the coil component 1, a wiring layer 15a in which the circuit pattern 22 is embedded in the first insulating layer 21a and a wiring layer 15b in which the circuit pattern 22 is embedded in the second insulating layer 21b are stacked to form a laminate 10. The wiring layers 15a and 15b have a ring shape when viewed from above in the figure, and a portion of the circuit pattern 22 is connected to each other inside the laminate 10 to form a coil. The circuit patterns 22 of the two stacked wiring layers 15a and 15b each extend in the same direction. In Figure 1, the direction of extension of the circuit pattern 22 is the direction normal to the plane of the paper. Accordingly, Figure 1 shows a cross-section of the coil component 1 along a plane perpendicular to the extending direction of the circuit pattern 22. Hereinafter, the first insulating layer 21a and the second insulating layer 21b will be collectively referred to as insulating layer 21, and the wiring layer 15a and the wiring layer 15b will be collectively referred to as wiring layer 15.

[0015] Figure 2 is a detailed view of the laminate 10 in section A of Figure 1, showing a cross-section of the first insulating layer 21a perpendicular to the main surface La of the first insulating layer 21a. This cross-section is a cross-section of the laminate 10 along a plane perpendicular to the extending direction of the circuit pattern 22. Hereinafter, the cross-section of the laminate 10 along a plane perpendicular to the extending direction of the circuit pattern 22 will also be referred to as the laminate cross-section. Note that the laminate cross-section is a cross-section that includes the central portion of the coil component 1. The laminate 10 includes two wiring layers 15 in which a circuit pattern 22 is embedded in an insulating layer 21, and these wiring layers 15 are stacked in one direction on top of the bottom cover layer 3.

[0016] Furthermore, in the laminate 10, the main surface of each layer of the wiring layer 15 may contain irregularities within its surface, and may also contain distortion in a cross-sectional view including the lamination direction.

[0017] As shown in Figure 2, in this embodiment, in particular, the cross-sectional shape of the first insulating layer 21a in the cross-section of the laminate 10 formed on the lower cover layer 3 is an inverted trapezoid, where the length L1 of the lower side 24b on the opposite side of the main surface La is shorter than the length L2 of the upper side 24a on the main surface La side. The upper second insulating layer 21b shown is constructed similarly. Here, the two opposing sides connecting the end of the upper side 24a and the end of the lower side 24b are referred to as the side sides 24c.

[0018] With the above configuration, the coil component 1 ensures a margin of (L1-L2) for the placement of the upper wiring layer 15b on the upper surface of the lower wiring layer 15a. Therefore, it is possible to effectively prevent misalignment or misstepping of the upper wiring layer 15b relative to the lower wiring layer 15a during the manufacturing process of the coil component 1.

[0019] Furthermore, in coil component 1, instead of making the size of the upper wiring layer smaller than the lower wiring layer and stacking the wiring layers in a pyramidal shape, each of the wiring layers 15 can be formed with the same cross-sectional shape and size, as shown in Figure 2. That is, the cross-section of the second insulating layer 21b along the cross-section of the laminate is an inverted trapezoid in which the length of the lower side L1 on the side of the first insulating layer 21a is shorter than the length L2 on the upper side opposite to the first insulating layer 21a. For this reason, in coil component 1, it is not necessary to increase the amount of insulating layer 21 between the circuit patterns 22 of the lower wiring layer 15a compared to the upper wiring layer 15b, or to reduce the number of circuit patterns 22 of the upper wiring layer 15b or narrow the width of the circuit patterns 22 compared to the lower wiring layer 15a. Furthermore, in the coil component 1, since the cross-section of the insulating layer 21 (and therefore the cross-section of the wiring layer 15) is inverted trapezoidal, the volume of the magnetic layer 2 in which the laminate 10 is embedded can be increased compared to a conventional configuration in which the cross-section of the wiring layer is a rectangle with a width of L2, for example, thus improving the inductance value of the coil component 1.

[0020] In other words, the coil component 1 can prevent misalignment or slippage of the wiring layers 15 when forming the laminate 10 without impairing electrical characteristics such as inductance value and electrical resistance. As a result, the coil component 1 can stably achieve good characteristics with a high manufacturing yield.

[0021] For example, the width w of the circuit pattern 22 is 5 μm or more and 100 μm or less, the thickness t1 of the circuit pattern 22 is 5 μm or more and 100 μm or less, and the spacing g between the circuit patterns 22 is 5 μm or more and 30 μm or less. Also, for example, the thickness t2 of the insulating layer 21 on the upper part of the circuit pattern 22 is 5 μm or more and 40 μm or less, and the thickness t3 of the insulating layer 21 is 10 μm or more and 140 μm or less.

[0022] Furthermore, for one or both of the two trapezoidal sides 24c formed by the cross-section of the first insulating layer 21a, it is preferable that the first distance L3 measured along the upper side 24a from the part of the circuit pattern 22 closest to the side 24c (for example, the first side on the right side in the figure) (i.e., the circuit pattern 22 at the rightmost end in the figure) to the upper end of the side 24c, and the second distance L4 measured along the lower side 24b from the part of the circuit pattern 22 closest to the side 24c to the lower end of the side 24c, be set within a range that satisfies the following equations (1) and (2). 5μm ≤ L4 ≤ 20μm (1) 1.1 ≤ L3 / L4 ≤ 1.5 (2)

[0023] In Figure 2, L3 and L4 are defined at the right end of the upper wiring layer 15, but it is more preferable that L3 and L4 can be similarly defined at the left end as well, and that the conditions shown in equations (1) and (2) apply. The same applies to the upper wiring layer 15b.

[0024] In equation (1), if the length L4 of the bottom edge is less than 5 μm, the adhesion between the wiring layer 15 and the adjacent layer below it may be weak, potentially reducing the insulation performance. Furthermore, if the length L4 of the bottom edge is greater than 20 μm, a significant decrease in the inductance value may be observed due to a reduction in the volume of the magnetic layer 2 covering the laminate 10.

[0025] Furthermore, if L4 in equation (1) has a lower limit of 5 μm, the value of L3 corresponding to the lower limit of 1.1 in equation (2) is 5.5 μm, and the tolerance for the arrangement of the upper wiring layer 15 relative to the lower wiring layer 15 is 0.5 μm (= L3 - L4) in one direction, left or right. This tolerance is a value that assumes the alignment accuracy of a typical mask aligner used in the photolithography process when forming the wiring layer 15. Therefore, if the alignment accuracy of the mask aligner used is greater than 0.5 μm, the lower limit in equation (2) can be adjusted accordingly.

[0026] In the above, if there is a step or unevenness on the upper surface of the first insulating layer 21a, the length L2 of the upper edge 24a of the cross-section of the first insulating layer 21a may be measured as the maximum width of the portion of interest in a planar projection view of the first insulating layer 21a viewed from above. Similarly, the length L4 may also be measured in the planar projection view. Furthermore, if L1, L2, L3, and L4 vary along the extending direction of the circuit pattern 22, they may be the average values ​​over a predetermined distance (e.g., 1 mm) or more along the extending direction of the circuit pattern 22, including the portion of interest. The same applies to the measurement of dimensions in the second insulating layer 21b and other embodiments described later.

[0027] The laminate 10 of the coil component 1 can be manufactured as follows. Figures 3 and 4 show the manufacturing process of the laminate 10. In Figure 3, first, a resin is applied to a flat substrate 40 to form a lower cover layer 3 (S100), and then a seed layer 41 is formed on the flat surface of the lower cover layer 3 (S102). The substrate 40 is, for example, a flat ceramic plate. The seed layer 41 is a power supply film made of copper metal for plating growth by SAP (Semi Additive Process), and can be formed using sputtering or electroless plating.

[0028] Next, a resist 42 is applied to the seed layer 41, and openings 43 for forming a circuit pattern 22 are created by patterning using photolithography (S104). Subsequently, copper metal is plated and grown within the openings 43 by electroplating to form the circuit pattern 22 (S106), and the resist 42 is removed (S108).

[0029] Referring to Figure 4, the seed layer 41 is then removed by etching (S110). Here, steps S102 to S110 correspond to the process of forming a circuit pattern 22 that extends along a plane in this disclosure.

[0030] Next, under a vacuum heating environment, an insulating dry film 44, which is a photosensitive resin that will become the insulating layer 21, is pressed against the substrate 40, covering the circuit pattern 22 so that the insulating dry film 44 fills the gaps in the circuit pattern 22 (S112). The insulating dry film 44 is a so-called photosensitive permanent film or permanent resist, and in this embodiment, it is a negative type.

[0031] Next, by patterning using photolithography, the portion of the insulating dry film 44 that covers the circuit pattern 22 is removed, leaving the rest (S114). As a result, a first insulating layer 21a having a main surface La parallel to the surface of the lower cover layer 3 is formed from the insulating dry film 44, which is a photosensitive resin that has been exposed and developed. Here, steps S112 and S114 correspond to the process in this disclosure of forming a first insulating layer 21a that covers the circuit pattern 22 and has a main surface La parallel to the plane on which the circuit pattern 22 is formed.

[0032] In the photolithography process in step S114, the projection exposure apparatus is specifically set to be off-focus relative to the surface of the insulating dry film 44. In this embodiment, the focus of the projection exposure apparatus is set away from the surface of the insulating dry film 44 (i.e., shifted upward from the surface). As a result, the insulating dry film 44 remaining on the lower cover layer 3 after development will have an inverted trapezoidal cross-section, as shown in Figure 4. If the insulating dry film 44 is a positive type, a similar inverted trapezoidal cross-section can be formed by shifting the focus position of the projection exposure apparatus inward from the insulating dry film 44 (i.e., shifted downward from the surface).

[0033] Generally, in photolithography, the focus position of the exposure machine is usually set precisely on the surface of a photosensitive resin such as a resist, from the viewpoint of performing high-precision patterning. In contrast, in this embodiment, the focus position of the projection exposure device is intentionally set to be off-focus relative to the surface of the insulating dry film 44, so that the insulating dry film 44 having an inverted trapezoidal cross-section remains on the lower cover layer 3 as the first insulating layer 21a after subsequent exposure and development.

[0034] This results in a cross-section of the first insulating layer 21a perpendicular to the main surface La being formed into an inverted trapezoidal shape, where the length of the lower side opposite to the main surface La is shorter than the length of the upper side on the main surface La side.

[0035] Next, the process from steps S102 to S114 described above is repeated on the upper surface of the wiring layer 15a formed above, thereby stacking the second insulating layer 21b of the second wiring layer 15b on the main surface La of the first insulating layer 21a to form the laminate 10 (S116). Here, when forming the second wiring layer 15b, the cross-sections of the two insulating layers 21 on the lower cover layer 3 are formed in an inverted trapezoid shape, where the length of the lower side is shorter than the length of the upper side. As described above, this prevents the second (upper) wiring layer 15b from shifting or slipping off the first (lower) wiring layer 15a.

[0036] [Second Embodiment] Next, a second embodiment of the present invention will be described. Figure 5 shows the configuration of the coil component 4 according to the second embodiment. In Figure 5, the same components as those in the coil component 1 shown in Figure 1 are indicated by the same reference numerals as in Figure 1, and the explanation of Figure 1 described above will be used with reference. The coil component 4 has the same configuration as the coil component 1, but differs in that it has a laminate 50 instead of a laminate 10. The laminate 50, like the laminate 10, is configured in a ring shape when viewed from above in the figure.

[0037] Figure 6 is a detailed view of the laminate 50 in section B of Figure 5, and corresponds to Figure 2, which shows the structure of the laminate 10. In Figure 6, the same components as those in the laminate 10 shown in Figure 2 are indicated using the same reference numerals as in Figure 2, and the explanation of Figure 2 described above is used with reference.

[0038] The laminate 50 shown in Figure 6 has two wiring layers 55a and 55b stacked on top of the bottom cover layer 3. The wiring layer 55a has a first insulating layer 51a with a main surface Lb and a circuit pattern 52 embedded in the first insulating layer 51a. The wiring layer 55b has a second insulating layer 51b stacked on the main surface Lb of the first insulating layer 51a and a circuit pattern 52 embedded in the second insulating layer 51b. The first insulating layer 51a, like the first insulating layer 21a, has an inverted trapezoidal cross-section, where the length of the bottom side 56b is shorter than the length of the top side 56a (L2).

[0039] The first insulating layer 51a has an insulating wall 53a that sandwiches the circuit pattern 52 along the direction of the lower side 56b of its inverted trapezoidal cross-section, and an upper wall 54a that covers the circuit pattern 52. In particular, all insulating walls 53a have an inverted tapered shape in which their cross-section decreases in width along the direction toward the lower cover layer 3, that is, from the upper side 56a to the lower side 56b. The circuit pattern 52 is located between the inverted tapered insulating walls 53a, and its cross-sectional shape is a trapezoidal shape in which its width increases along the direction toward the lower cover layer 3. The second insulating layer 51b has an insulating wall 53b corresponding to the insulating wall 53a and an upper wall 54b corresponding to the upper wall 54a, and has the same shape as the first insulating layer 51a. Hereinafter, the wiring layer 55a and the wiring layer 55b will be collectively referred to as the wiring layer 55, and the first insulating layer 51a and the second insulating layer 51b will be collectively referred to as the insulating layer 51. Furthermore, insulating wall 53a and insulating wall 53b shall be collectively referred to as insulating wall 53, and upper wall 54a and upper wall 54b shall be collectively referred to as upper wall 54.

[0040] An insulating layer 51 having the shape described above can be formed in the manufacturing process by simultaneously forming all of the insulating walls 53 into an inverse tapered shape by setting the projection exposure apparatus to off-focus as described above, and then plating and growing the circuit pattern 52 between these insulating walls 53. In this way, in the laminate 50, the insulating walls 53 of the insulating layer 51 can be formed in advance before the formation of the circuit pattern 52, thereby ensuring high adhesion between the insulating walls 53 and the components below them (in the case of the first insulating layer 51a, the lower cover layer 3 below it, and in the case of the second insulating layer 51b, the first insulating layer 51a below it), and improving the insulation between the circuit patterns 52.

[0041] As shown in Figure 7, for the wiring layer 55, similar to the wiring layer 15 shown in Figure 2, the thickness t1 of the circuit pattern 52, the spacing g between the circuit patterns 52, the thickness t2 of the insulating layer 51 above the circuit pattern 52, and the thickness t3 of the insulating layer 51 can be defined. Also, similar to the insulating layer 21 shown in Figure 2, for one or both sides of the inverted trapezoidal side 56c formed by the cross-section of the insulating layer 51, a first distance L3 can be defined from the circuit pattern 52 closest to the side 56c to the upper end of the side 56c measured along the upper side 56a, and a second distance L4 can be defined to the lower end of the side 56c measured along the lower side 56b. Specific examples and preferred conditions for these dimensions are the same as for the insulating layer 21 described above.

[0042] The laminate 50 can be manufactured as follows. Figures 8 and 9 show the manufacturing process of the laminate 50. In Figures 8 and 9, the same components as in Figures 3 and 4 are indicated using the same reference numerals as in Figures 3 and 4, and the explanations for Figures 3 and 4 described above are used accordingly.

[0043] In Figure 8, first, a resin is applied to a flat substrate 40 to form a lower cover layer 3 (S200), and then a seed layer 41, which is a copper metal layer for plating growth, is formed on the flat surface of the lower cover layer 3 (S202).

[0044] Next, the seed layer 41 is patterned by photolithography to form a seed pattern 45 (S204). Subsequently, similar to steps S112 and S114 in Figure 4 described above, an insulating dry film, which is a photosensitive resin, is pressed onto the seed pattern 45 to make it adhere, and then this insulating dry film is patterned by photolithography. This forms insulating walls 53a extending along the seed pattern 45 at positions on the surface of the lower cover layer 3 that sandwich the seed pattern 45 (S206).

[0045] Here, in step S206, similar to step S114 in Figure 4 described above, the projection exposure apparatus is set to off-focus during the photolithography process. As a result, the cross-sections of all insulating walls 53a are formed in an inverse tapered shape, with the width decreasing from the side of the main surface Lb where the second insulating layer 51b will be laminated in a later process toward the opposite side. Next, copper metal is plated and grown between adjacent insulating walls 53a by electroplating to form a circuit pattern 52 having a trapezoidal cross-section (S208).

[0046] Referring to Figure 9, the insulating dry film 44 is then pressed to adhere to the insulating wall 53a and the circuit pattern 52 (S210). After that, the unnecessary portion of the insulating dry film 44 is removed by photolithography to form the upper wall 54a, and the first wiring layer 55a is formed on the lower cover layer 3 (S212). This forms the upper wall 54a, which covers the insulating wall 53a and the circuit pattern 52, and has a main surface Lb parallel to the plane formed by the surface of the lower cover layer 3. The inversely tapered insulating wall 53a and the upper wall 54a constitute the first insulating layer 51a, which has an inverse trapezoidal shape in which the length of the lower side opposite to the main surface Lb is shorter than the length of the upper side on the main surface Lb side.

[0047] Next, the above-described steps S202 to S212 are repeated on the upper surface of the formed wiring layer 55 to form a wiring layer 55b on top of the formed wiring layer 55a, thereby forming a laminate 50 (S214).

[0048] In the process shown in Figures 8 and 9, step S206 corresponds to the process of forming a plurality of insulating walls arranged in one direction within a plane, and step 208 corresponds to the process of forming a circuit pattern extending along the plane between the plurality of insulating walls. Steps S210 and S212 correspond to the process of forming an upper wall having a main surface parallel to the plane that covers the insulating walls and the circuit pattern, and step S214 corresponds to the process of laminating a second insulating layer on the main surface.

[0049] [Third Embodiment] Next, a third embodiment of the present invention will be described. Figure 10 shows the configuration of a coil component 5 according to a third embodiment of the present invention. In Figure 10, the same components as those in the coil component 1 shown in Figure 1 are indicated by the same reference numerals as in Figure 1, and the explanation of Figure 1 described above will be used with reference. The coil component 5 has the same configuration as the coil component 1, but differs in that it has a laminate 60 instead of a laminate 10. The laminate 60, like the laminate 10, is configured in a ring shape when viewed from above in the figure.

[0050] Figure 11 is a detailed view of the laminate 60 in section C of Figure 10, and corresponds to Figure 2, which shows the structure of the laminate 10. In Figure 11, the same components as in Figure 2 are indicated using the same reference numerals as in Figure 2, and the explanation of Figure 2 described above is used with reference.

[0051] The laminate 60 shown in Figure 11 has a similar configuration to the laminate 10 shown in Figure 2, but differs in that it has two wiring layers 65a and 65b stacked on the bottom cover layer 3 instead of the wiring layers 15a and 15b. The wiring layer 65a has a similar configuration to the wiring layer 15a, but has a first insulating layer 61a instead of the first insulating layer 21a. The first insulating layer 61a has a similar configuration to the first insulating layer 21a, but its cross-sectional shape is different from that of the first insulating layer 21a. Specifically, the cross-sectional shape of the first insulating layer 61a is a roughly trapezoidal shape in which the length L2 of the upper side 66a on the main surface Lc side of the first insulating layer 61a is shorter than the length L1 of the lower side 66b, and the two side sides 66c each form an arched curve that is concave inward toward the interior of the first insulating layer 61a.

[0052] The wiring layer 65b has the same configuration as the wiring layer 15b, but instead of the second insulating layer 21b, it includes a second insulating layer 61b having the same configuration as the first insulating layer 61a described above. Hereinafter, the first insulating layer 61a and the second insulating layer 61b will be collectively referred to as insulating layer 61, and the wiring layer 65a and the wiring layer 65b will be collectively referred to as wiring layer 65.

[0053] With the above-described configuration, in the coil component 5 using the laminate 60, additional space is secured in the recessed portion formed by the side edge of the insulating layer 61 for the magnetic layer 2 to fit into. Therefore, compared to the case where an insulating layer 21 without recesses is used as shown in Figure 2, the volume of the magnetic layer 2 can be increased, and the inductance value of the coil component 5 can be improved.

[0054] In this embodiment, the two sides of the inverted trapezoidal shape formed by the cross-section of the insulating layer 61 in the laminate 60 are curved, but they may also be composed of broken lines that form a recess toward the interior of the insulating layer 61. In this case as well, the inductance value of the coil component 5 can be improved by the magnetic layer 2 fitting into the recessed shape of the broken line sides.

[0055] The laminate 60 can be manufactured as follows. Figures 12 and 13 show the manufacturing process of the laminate 60. In Figures 12 and 13, the same components as in Figures 3 and 4 are indicated using the same reference numerals as in Figures 3 and 4, and the explanations for Figures 3 and 4 described above are used accordingly.

[0056] The steps S300 to S308 shown in Figure 12, and the steps S310 and S312 shown in Figure 13, are the same as the steps S100 to S108 shown in Figure 3, and the steps S110 and S112 shown in Figure 4, respectively. Therefore, the explanations for Figures 3 and 4 described above will be applied here.

[0057] In step S314 of Figure 13, similar to step S114 described above, the projection exposure apparatus is set to off-focus, and patterning is performed using photolithography to remove the portion of the insulating dry film 44 that covers the circuit pattern 22. However, in step S314, the exposure amount in photolithography is set to be less than the exposure amount in step S114. This creates an overdeveloped state in the development process following the exposure process in photolithography, forming a concave shape on the side portion of the patterned insulating dry film 44. As a result, the first wiring layer 65 is formed on the lower cover layer 3.

[0058] Next, by repeating the steps from S302 to S314 on the upper surface of the formed wiring layer 65, a second wiring layer 65 is formed on the main surface Lc of the first insulating layer 61a of the formed wiring layer 65, and the laminate 60 is formed (S316).

[0059] [Fourth Embodiment] Next, a fourth embodiment of the present invention will be described. Figure 14 shows the configuration of a coil component 6 according to a fourth embodiment of the present invention. In Figure 14, the same components as those in the coil component 1 shown in Figure 1 are indicated by the same reference numerals as in Figure 1, and the explanation of Figure 1 described above will be used with reference. The coil component 6 has the same configuration as the coil component 1, but differs in that it has a laminate 70 instead of a laminate 10. The laminate 70, like the laminate 10, is configured in a ring shape when viewed from above in the figure.

[0060] Figure 15 is a detailed view of the laminate 70 in section D of Figure 14, and corresponds to Figure 2, which shows the configuration of the laminate 10. In Figure 15, the same components as those in the laminate 10 shown in Figure 2 are indicated using the same reference numerals as in Figure 2, and the explanation of Figure 2 described above is used with reference.

[0061] The laminate 70 shown in Figure 15 has a similar structure to the laminate 10 shown in Figure 2, but further includes a third insulating layer 71 laminated as the uppermost layer above the second insulating layer 21b, which is furthest from the bottom cover layer 3. The third insulating layer 71 and the circuit pattern 72 embedded in the third insulating layer 71 constitute a wiring layer 75. The third insulating layer 71 has a similar structure to the insulating layer 21, but its cross-sectional shape is different from that of the insulating layer 21. That is, the cross-section of the third insulating layer 71 along the cross-section of the first insulating layer 21a is a rectangle in which the length L5 of the upper side 75a on the opposite side from the second insulating layer 21b is the same as the length L6 of the lower side 75b on the second insulating layer 21b side.

[0062] In the laminate 70 having the above configuration, the cross-sectional shape of the third insulating layer 71 of the uppermost wiring layer 75 is rectangular, rather than an inverted trapezoidal shape like the wiring layer 15, which facilitates embedding the coil component 6 into the magnetic layer 2 during the manufacturing process.

[0063] Figure 16 shows an example of the process of embedding the laminate 70 in the magnetic layer 2 during the manufacturing of the coil component 6. The laminate 70 is embedded inside the magnetic layer 2 composed of magnetic pellets 2a and 2b by, for example, inserting it into the opening of a magnetic pellet 2a with an E-shaped cross-section, and then pressing and melting an I-shaped magnetic pellet 2b from the top in the direction of the white arrow in the figure. The process of embedding the laminate 70 in the magnetic layer 2 is not limited to the above. For example, a sheet containing magnetic powder in resin may be placed on top of the laminate 70, sandwiching it from both above and below, and the sheet may be heated and pressed to embed the laminate 70 inside the magnetic layer 2 composed of the sheet.

[0064] In this case, since the cross-section of the third insulating layer 71 of the wiring layer 75, which is the uppermost layer of the laminate 70, is rectangular rather than trapezoidal, the magnetic pellet 2b, which is pressurized and melted from above as shown in the figure, easily forms a flow along the outer surface of the laminate 70 and can easily flow into the gap between the magnetic pellet 2a and the laminate 70 within the opening of the magnetic pellet 2a. For this reason, in the coil component 6 using the laminate 70, voids (bubble-like spaces) are less likely to occur between the laminate 70 and the magnetic layer 2, and manufacturing variations in inductance values ​​are less likely to occur.

[0065] Furthermore, when using the laminate 70, as shown in Figure 15, by making the length L5 of the upper edge 75a and the length L6 of the lower edge 75b of the third insulating layer 71 of the uppermost wiring layer 75 shorter than the length L2 of the upper edge of the insulating layer 21 of the wiring layer 15 below it, the volume of the magnetic layer 2 can be increased compared to a configuration in which all wiring layers are wiring layer 15, and the inductance value of the coil component 6 can be further improved.

[0066] Furthermore, the cross-section of the uppermost wiring layer of the laminate 70 is not limited to a rectangle; it may also be trapezoidal. Figure 17 shows the configuration of a modified laminate 80, which is a variation of the laminate 70, and corresponds to Figure 15, which shows the configuration of the laminate 70. The laminate 80 can be used in place of the laminate 70 for the coil component 6. In Figure 17, components that are the same as those of the laminate 70 shown in Figure 15 are indicated using the same reference numerals as in Figure 15, and the explanation of Figure 15 described above will be used with reference.

[0067] The laminate 80 shown in Figure 17 has a similar structure to the laminate 70, but differs in that it has a wiring layer 85 in its uppermost layer instead of the wiring layer 75. The wiring layer 85 has a similar structure to the wiring layer 75, but differs in that it has a third insulating layer 81 instead of the third insulating layer 71. The third insulating layer 81 has a similar structure to the third insulating layer 71, but its cross-sectional shape is a trapezoid in which the length L7 of the upper side 85a is shorter than the length L8 of the lower side 85b.

[0068] When the laminate 80 having the above configuration is embedded in the magnetic layer 2 by the process shown in Figure 16, for example, the pressurized and molten magnetic pellets 2b can easily slide down the trapezoidal cross-section of the uppermost wiring layer 85. Therefore, compared to the laminate 70, the laminate 80 is even easier to embed in the magnetic layer 2 when manufacturing coil components, and the generation of voids in the magnetic layer 2 can be further suppressed.

[0069] [Other embodiments] In the embodiments described above, the laminates 10, 50, 60, 70, and 80 each have two wiring layers 15, 55, or 65, but they may also have three or more layers.

[0070] Furthermore, although coil components 1, 4, 5, and 6 were shown as examples of electronic components having a laminate in the embodiments described above, the electronic components to which the present invention can be implemented may be any electronic components other than coil components that include a laminate having a cross-sectional structure similar to laminates 10, 50, 60, 70, or 80 in part. The plan view of such a laminate is not limited to a ring shape, and can have any shape depending on the circuit design of the electronic component.

[0071] Furthermore, in the first embodiment described above, the laminate cross-section, that is, the cross-section of the first insulating layer 21a that includes the central portion of the coil component and is perpendicular to the main surface La of the first insulating layer 21a, was not particularly limited, but it is sufficient that the cross-sectional shape of the first insulating layer 21a be an inverted trapezoid in at least one laminate cross-section. In the cross-section of the first insulating layer 21a perpendicular to the laminate cross-section, the cross-section of the first insulating layer 21a may be a rectangle where the length of the upper side 24a is the same as the length of the lower side 24b, or a trapezoid where the length of the upper side 24a is shorter than the length of the lower side 24b. However, it is more preferable that the cross-sectional shape of the first insulating layer 21a be an inverted trapezoid in any angle of the laminate cross-section perpendicular to the main surface La of the first insulating layer 21a that includes the central portion of the coil component. The same applies to other embodiments.

[0072] Furthermore, although the circuit patterns 22 and 52 constitute the coil portion in the embodiment described above, the configuration of the circuit patterns 22 and 52 is not limited to this. The circuit patterns 22 and 52 may be spiral, circular in shape with less than one turn, linear, or meander, etc.

[0073] Furthermore, the characteristic configurations shown in the embodiments and modified examples described above can be combined and used in any electronic component. For example, an electronic component may comprise any combination of any number of laminates having the same configuration as the laminates 10, 50, 60, 70, and 80 described above. Alternatively, an electronic component may comprise a laminate comprising any number of wiring layers having the same configuration as the wiring layers 15, 55, 65, 75, and 85 described above, in any combination.

[0074] Furthermore, all embodiments and modifications described above are illustrative of one aspect of the present invention and can be arbitrarily modified and applied without departing from the spirit of the invention.

[0075] Furthermore, unless otherwise specified, the horizontal and vertical directions, various numerical values, shapes, and materials in the embodiments described above include a range that produces the same effects as those directions, numerical values, shapes, and materials (the so-called equivalence range).

[0076] [Configurations supported by the above embodiment] The embodiments and modifications described above support the following configurations.

[0077] (Configuration 1) An electronic component comprising: a first insulating layer having a main surface; a circuit pattern embedded in the first insulating layer and extending along a plane parallel to the main surface; and a second insulating layer laminated on the main surface, wherein the cross-section of the first insulating layer perpendicular to the main surface is an inverted trapezoid, with the length of the lower side opposite to the main surface being shorter than the length of the upper side on the main surface side. In the electronic component of configuration 1, the first insulating layer is formed in an inverted trapezoidal shape, which prevents the second insulating layer stacked on top of it from shifting or being stepped on.

[0078] (Configuration 2) The electronic component according to Configuration 1, wherein the cross-section of the second insulating layer along the cross-section of the first insulating layer is an inverted trapezoid in which the length of the lower side on the first insulating layer side is shorter than the length of the upper side on the side opposite to the first insulating layer side. In the electronic component of configuration 2, each of the stacked insulating layers can be configured to have the same cross-section as the others. Therefore, it is not necessary to narrow the width of the insulating layer on top to avoid misalignment or slippage of the insulating layers, and consequently, there are no constraints such as narrowing the width of the circuit pattern on top. For this reason, the electronic component of configuration 2 can prevent misalignment or slippage of the wiring layers without impairing their electrical characteristics.

[0079] (Configuration 3) The electronic component according to Configuration 1 or 2, wherein the two opposing sides of the inverted trapezoidal cross-section of the first insulating layer, connecting the end of the upper side and the end of the lower side, form a curved or broken line that is recessed toward the interior of the first insulating layer. According to the electronic component of configuration 3, when the laminate is embedded in an electrical material such as a magnetic material, additional space can be secured for the electrical material to enter in the recess formed on the side of the insulating layer, thereby improving the electrical properties of the electronic component.

[0080] (Configuration 4) The electronic component according to any one of Configurations 1 to 3, wherein the first insulating layer includes insulating walls that sandwich the circuit pattern along the direction of the lower side of the inverted trapezoidal cross-section of the first insulating layer, and the cross-section of the insulating wall in the cross-section of the first insulating layer has an inverted tapered shape in which the width decreases along the direction from the upper side to the lower side. According to the electronic component of configuration 4, for example, in the manufacturing process, before the formation of the circuit pattern, all of the multiple insulating walls can be formed into an inverted tapered shape at once by setting the projection exposure apparatus to off-focus, so that the cross-section of the final insulating layer is inverted trapezoidal. Thus, according to the electronic component of configuration 3, insulating walls can be formed before the formation of the circuit pattern, so the insulation between circuit patterns can be improved.

[0081] (Configuration 5) With respect to a first side which is one of two opposing side faces that connect the end of the upper side and the end of the lower side of the inverted trapezoidal cross-section of the first insulating layer, the ratio of the second distance to the first distance between the first side, measured along the upper side from the portion of the circuit pattern closest to the first side to the upper end of the first side, and the ratio of the second distance to the first distance between the second distance and the lower end of the first side, measured along the lower side from the portion of the circuit pattern closest to the first side to the lower end of the first side, is 1.1 or more and less than 1.5, and the second distance is 5 μm or more and 20 μm or less, as described in any configuration 1 to 4. According to the electronic component of configuration 5, a laminate can be formed without misalignment or misstepping between wiring layers using a mask aligner with the general alignment accuracy used in photolithography processes.

[0082] (Configuration 6) An electronic component according to any one of Configurations 1 to 5, further comprising a third insulating layer laminated on top of the second insulating layer, wherein the cross-section of the third insulating layer along the cross-section of the first insulating layer is a rectangle in which the length of the upper side opposite to the second insulating layer is the same as the length of the lower side on the second insulating layer side, or a trapezoid in which the length of the upper side is shorter than the length of the lower side. According to the electronic component of configuration 6, when embedding a laminate in an electrical material such as a magnetic material, the flow of the electrical material on the outer surface of the laminate is facilitated, making it easy to achieve a good embedded state without voids.

[0083] (Configuration 7) The circuit pattern is a coil component which is an electronic component described in any of Configurations 1 to 5 that constitutes a coil. The coil component of configuration 7 prevents misalignment and slippage of wiring layers without compromising electrical characteristics such as inductance and electrical resistance, thereby stably achieving good characteristics with a high manufacturing yield.

[0084] (Configuration 8) A method for manufacturing an electronic component, comprising the steps of: forming a circuit pattern extending along a plane; forming a first insulating layer having a main surface parallel to the plane that covers the circuit pattern; and laminating a second insulating layer on the main surface, wherein in the step of forming the first insulating layer, a photosensitive resin is placed so as to cover the circuit pattern, and the photosensitive resin is exposed and developed by irradiating the surface of the photosensitive resin with light from a projection exposure apparatus set to off-focus, thereby forming a cross section of the first insulating layer perpendicular to the main surface in an inverted trapezoidal shape in which the length of the lower side opposite to the main surface is shorter than the length of the upper side on the main surface side. According to the manufacturing method of the electronic component of configuration 8, the electronic component described in configuration 1 can be easily manufactured.

[0085] (Configuration 9) A method for manufacturing an electronic component, comprising the steps of: forming a plurality of insulating walls arranged in one direction within a plane; forming a circuit pattern extending along the plane between the plurality of insulating walls; forming an upper wall having a main surface parallel to the plane that covers the insulating walls and the circuit pattern; and laminating a second insulating layer on the main surface, wherein in the step of forming the insulating walls, a photosensitive resin is placed so as to cover the plane, and the photosensitive resin is exposed and developed by irradiation light from a projection exposure apparatus set to off-focus on the surface of the photosensitive resin, thereby forming a cross section of the insulating wall perpendicular to the plane in an inverse tapered shape in which the width decreases from the side on which the second insulating layer is laminated toward the opposite side, and the insulating walls and the upper wall constitute a first insulating layer in an inverse trapezoidal shape in which the length of the lower side opposite to the main surface is shorter than the length of the upper side on the main surface side. According to the manufacturing method of the electronic component of configuration 9, the electronic component described in configuration 4 can be easily manufactured. [Explanation of symbols]

[0086] 1, 4, 5, 6…Coil components, 2…Magnetic layer, 2a, 2b…Magnetic pellets, 3…Bottom cover layer, 10, 50, 60, 70, 80…Laminate, 15, 15a, 15b, 55, 55a, 55b, 65, 65a, 65b, 75, 85…Wiring layers, 21, 51, 61…Insulating layers, 21a, 51a, 61a…First insulating layer, 21b, 51b, 61b…Second insulating layer, 71, 81…Third insulating layer Layers: 24a, 56a, 66a, 75a, 85a... top edge, 24b, 56b, 66b, 75b, 85b... bottom edge, 24c, 56c, 66c... side edge, 22, 52... circuit pattern, 40... substrate, 41... seed layer, 42... resist, 43... opening, 44... insulating dry film, 53, 53a, 53b... insulating wall, 54, 54a, 54b... top wall, La, Lb, Lc... main surface.

Claims

1. The insulating layer comprises a first insulating layer having a main surface, It includes a second insulating layer laminated on the main surface, Each of the aforementioned insulating layers is A circuit pattern embedded in the insulating layer and extending along a plane parallel to the main surface, The circuit patterns include insulating walls extending within the intervals between them, and the insulating walls are formed integrally with the insulating layer using the same photosensitive resin as the insulating layer. The cross-section of the first insulating layer perpendicular to the main surface is such that the length of the lower side opposite to the main surface is shorter than the length of the upper side on the main surface side, and the two opposing sides connecting the end of the upper side and the end of the lower side form a straight line, forming an inverted trapezoid. Electronic components.

2. The cross-section of the second insulating layer, along the cross-section of the first insulating layer, is such that the length of the lower side on the side of the first insulating layer is shorter than the length of the upper side on the side opposite to the first insulating layer, and the two opposing sides connecting the end of the upper side and the end of the lower side form a straight line, forming an inverted trapezoid. The electronic component according to claim 1.

3. The first insulating layer includes insulating walls that sandwich the circuit pattern along the direction of the lower edge of the inverted trapezoid formed by the cross-section of the first insulating layer, The cross-section of the insulating wall in the cross-section of the first insulating layer has an inverse tapered shape in which the width decreases along the direction from the upper side to the lower side. The electronic component according to claim 1.

4. With respect to a first side, which is one of two opposing side edges connecting the end of the upper edge and the end of the lower edge of the inverted trapezoidal cross-section of the first insulating layer, the ratio of the first distance to the second distance is 1.1 or more and less than 1.5, and the second distance is 5 μm or more and 20 μm or less. The electronic component according to claim 1.

5. It further comprises a third insulating layer laminated on top of the second insulating layer, The cross-section of the third insulating layer along the cross-section of the first insulating layer is a rectangle in which the length of the upper side opposite to the second insulating layer is the same as the length of the lower side on the second insulating layer side, or a trapezoid in which the length of the upper side is shorter than the length of the lower side. The electronic component according to claim 1.

6. The circuit pattern constitutes a coil, A coil component which is an electronic component according to any one of claims 1 to 5.

7. A process of forming a circuit pattern that extends along a plane, A step of forming a first insulating layer having a main surface parallel to the plane that covers the circuit pattern, The process involves laminating a second insulating layer onto the aforementioned main surface, Equipped with, In the step of forming the first insulating layer, a photosensitive resin is placed so as to cover the circuit pattern, and the surface of the photosensitive resin is exposed and developed by irradiating it with light from a projection exposure apparatus set to off-focus, thereby forming a cross-section of the first insulating layer perpendicular to the main surface in an inverted trapezoidal shape, where the length of the lower side opposite to the main surface is shorter than the length of the upper side on the main surface side, and the two opposing sides connecting the end of the upper side and the end of the lower side form a straight line, and insulating walls extending within the intervals between the circuit patterns are formed from the same exposed and developed photosensitive resin as the first insulating layer. Manufacturing methods for electronic components.

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