Modular multilevel cascade converter and its control method

Abstract

To prevent such a problem that a predetermined volts alternating current required for system interconnection cannot be output from an SST when operation is continued in the case where a part of cells fails.SOLUTION: A plurality of cells each including an AC-DC converter ACDC, a primary-side DC capacitor C1, an insulated DC-DC converter DCDC, and a secondary-side DC capacitor C2 are provided per phase. A plurality of DC systems to which a plurality of secondary side DC capacitors C2 are connected in parallel are provided, and voltages of the plurality of DC systems are supplied to a load or a power source. When a cell fails, the control unit of the AC / DC converter ACDC increases the output voltage on the AC system side of the cell connected to the same DC system as the failed cell, and decreases the output voltage on the AC system side of the cell connected to the other DC system. The third harmonic is superimposed on the AC output voltage of the cell connected to the same DC system as the failed cell, and the third harmonic in the opposite direction is superimposed on the AC output voltage of the cell connected to the DC system different from the failed cell.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a modular multilevel cascade converter (MMCC) of a single star bridge cell (SSBC) connected to a three-phase AC power system, wherein a bidirectional isolated DC / DC converter (isolated DC-DC converter) or the like is connected to the DC side of the full bridge cell (AC-DC converter) that constitutes the converter, enabling the output of multiple DC systems. [Background technology]

[0002] A prime example of this configuration is a solid-state transformer (SST). Figure 1 shows an SST consisting of four cells (m) per phase, combining an MMCC-SSBC (Multi-Metal Circuit-Simulated Cell-Simulated Cell-Simulated Cell-Simulated Cell-Simulated Cell-DC Converter) configured by cascading AC-DC converters (ACDC) and a dual active bridge (DAB) type isolated DC converter (DCDC). Each cell consists of an AC-DC converter (ACDC), an isolated DC converter (DCDC), and capacitors C1 and C2.

[0003] High-voltage AC power can be converted to DC power using cells connected in series, then the DC power can be converted back to high-frequency AC power, and finally converted back to DC power by isolation and rectification using a transformer. Power exchange in the reverse direction is also possible. Because SST uses a high-frequency transformer, it can be made smaller than conventional commercial frequency transformers.

[0004] By connecting the output terminals of six isolated DC converters (DCDC:3m / x=6) in parallel, it is possible to output two isolated DC systems with the same capacitance. By connecting multiple of these DC systems in series, a high DC voltage can also be obtained.

[0005] In situations where high reliability is required, such as when critical loads are connected to a DC system, it is necessary to implement a fault tolerance function that allows operation to continue even if some of the cells constituting the SST fail.

[0006] If a failure occurs within a cell, such as an open circuit or short circuit due to a severed wire, or an open circuit or short circuit in some switching devices, the output terminal on the three-phase AC system side can be short-circuited by the remaining healthy switching devices or a separately provided mechanical switch, while the output terminal on the DC system side can be opened, preventing the failure from spreading to other cells.

[0007] However, the subsequent problem is balancing the voltage of the DC capacitors connected to the AC system side of the remaining cells (primary DC voltage) and the voltages of each stage connected in series at the output. Furthermore, if the proportion of faulty cells to the total number of cells increases, there is a higher risk that the MMCC-SSBC will not be able to output the AC voltage necessary for grid connection.

[0008] Patent Document 6 discloses a control method for maintaining the primary DC voltage inside the cell and the voltage of the output DC system uniformly in the SST shown in Figure 1. The control method in Patent Document 6 consists of the following feedback control.

[0009] (1) Primary DC voltage average value control The AC output current of the MMCC-SSBC is adjusted so that if the average value of the primary DC voltage is lower than the command value, active power is input from the AC system; if it is higher, active power is output to the AC system.

[0010] (2) Primary DC voltage phase balance control The AC output voltage of the AC / DC converter (ACDC) for a cell is adjusted by comparing the primary DC voltage of a cell connected to a certain phase of the AC system with the average value of the primary DC voltages of all cells connected to the same phase. If the primary DC voltage of a cell is high and power is flowing in from the AC system, the AC voltage is reduced to suppress charging. If the power is flowing out into the AC system in the opposite direction, the AC voltage is increased to promote discharge.

[0011] (3) Individual balance control of primary DC voltage The current of an isolated DC converter (DCDC) is controlled so that the primary DC voltage of all cells connected to a given DC system is equal. Cells with a high primary DC voltage receive more power from the AC system to the DC system via the DCDC, while cells with a low primary DC voltage receive less power from the AC system to the DC system via the DCDC.

[0012] (4) Individual control of secondary DC voltage The power supply of the isolated DC-DC converters (DC-DC converters) in all cells connected to the relevant DC system is adjusted so that the voltage of the DC capacitor located on the DC system side of the high-frequency transformer within the cell, i.e., the DC system voltage (secondary DC voltage), equals the command value.

[0013] Patent documents 1, 2, and 3 disclose a method for continuing operation when a cell constituting a converter fails, by short-circuiting the terminals by turning on a switch connected to one of the input / output terminals of the cell, thereby preventing the effects of the failure from spreading to other cells.

[0014] Furthermore, Patent Document 1 assumes that either AC or DC power is input and DC power is output, and the output cells are connected in series (the input side can be either parallel or series). If some cells fail, the DC capacitor voltage on the series-connected output side of the cells can be increased, thereby obtaining an output voltage with the same amplitude as before the failure from the converter.

[0015] Patent Document 2 describes a technology applied to a configuration in which both the input and output terminals of a cell are connected in series, assuming the interconversion of two AC power sources. If some cells fail, the switch on the faulty side of the input and output terminals of the affected cell is short-circuited, and the other terminal is controlled to maintain a constant DC capacitor voltage inside the cell, thereby obtaining an output voltage with the same amplitude as before the failure from the converter.

[0016] Furthermore, Patent Document 2 shows the waveform before failure in Figure 5 and the waveform after failure in Figure 6. The AC output voltage (Vo2~Vo4) of the non-faulty cells shows an increase in pulse width. In other words, it can be interpreted that the non-faulty cells prioritize increasing the amplitude even if the distortion of the AC output voltage worsens, while the faulty cells eliminate the distortion, thereby making the AC output voltage of the converter equal before and after the failure.

[0017] Patent Document 3 describes a technology applied to the mutual conversion of two DC power sources, where cells are connected in parallel and series within the unit constituting the converter. If some cells fail, the voltage of the DC capacitor on the parallel-connected side remains unchanged, while the voltage of the DC capacitor on the series-connected side is increased. Patent Document 3 ensures that the voltage of the DC system on the series-connected side does not change before and after the failure. Furthermore, the input and output powers remain equal, enabling stable and continuous operation.

[0018] Non-patent document 1, and patent documents 4 and 5 disclose a technique that reduces the peak of the voltage command value by superimposing a third harmonic on the output phase voltage command value, thereby enabling the output of an AC voltage with a larger amplitude, while ensuring that the superimposed third harmonic does not affect the line voltage.

[0019] Patent documents 7 and 8 disclose a technique for superimposing a zero-sequence voltage of the fundamental wave so that the amplitude of the AC voltage output by the SST can be maintained even if some cells fail. [Prior art documents] [Patent Documents]

[0020] [Patent Document 1] Patent No. 6476318 [Patent Document 2] Patent No. 6725758 [Patent Document 3] Patent No. 6976426 [Patent Document 4] Japanese Patent Application Publication No. 3-107373 [Patent Document 5] Japanese Patent Publication No. 2022-107230 [Patent Document 6] Patent application No. 2023-191251 [Patent Document 7] Patent application No. 2023-215645 [Patent Document 8] Patent application No. 2023-215646 [Non-patent literature]

[0021] [Non-Patent Document 1] "Sensorless Vector Control of AC Drive Systems," Research Committee on the Standardization of Sensorless Vector Control, Institute of Electrical Engineers of Japan, Ohmsha, pp. 54 (2016) [Overview of the project] [Problems that the invention aims to solve]

[0022] To ensure stable operation of the SST, it is necessary to improve the stability of the primary DC voltage within the cell and the voltage balance of the output DC system, even in the event of power imbalances in each DC system, sudden load changes, or cell failures. As a method to achieve this, a feedforward adjustment of the AC output voltage of the cell's AC-DC converter (ACDC) can be considered, as described in Patent Document 6 (2) Primary DC voltage phase balance control.

[0023] Furthermore, the following methods can be considered to maintain an equal DC voltage in each DC system. Other cells connected to a DC system containing a faulty cell will have a higher AC output voltage than the remaining cells. The amplitude ratio of the AC output voltage is set as follows: other cells in the DC system with the faulty cell: remaining cells = 3m:3m-x (=6:5).

[0024] As a result, the power supplied from the AC system to each DC system can be made equal, and both the primary voltage inside the cell and the DC voltage of each secondary DC system are balanced.

[0025] However, the above methods require increasing the AC output voltage of the cell's AC-DC converter (ACDC). However, the maximum amplitude of the cell's AC output voltage is limited by the primary DC voltage. Therefore, there is a limit to how much the cell's AC output voltage can be increased. It is also possible to maintain an equal DC voltage across each DC system by lowering the AC output voltage of cells connected to a DC system without faulty cells, and this is not limited by the primary DC voltage. However, if the AC output voltage of the entire MMCC-SSBC decreases due to a cell failure, and the AC output voltage of even more cells must be lowered, there is a high risk that the MMCC-SSBC will not be able to output the AC voltage necessary for grid connection.

[0026] One possible solution is to lower the AC system voltage by injecting reactive power into the AC system, thereby reducing the AC voltage required for grid connection. However, changing the AC system voltage would affect other devices connected to the same system. If a reactive power compensation device is connected nearby, not only would it be impossible to lower the AC voltage, but unnecessary reactive power exchange would occur between the system and the compensation device, resulting in losses.

[0027] By setting a high primary DC voltage beforehand, the AC output voltage of the cell's AC-DC converter (ACDC) can be freely increased. However, this requires a corresponding cell voltage rating design, necessitating the selection of high-voltage components, which increases cost and size. Furthermore, switching losses also increase steadily. Methods such as those described in Patent Documents 1 and 3, which increase the cell's primary DC voltage only when some cells fail, can also be considered. However, even then, cell voltage rating design is required, and switching losses during failure are unavoidable.

[0028] To apply the technology described in Patent Document 2, it is necessary to maintain a constant primary DC voltage using a full-bridge inverter of the faulty cell. Therefore, if a failure occurs in the full-bridge inverter, the technology described in Patent Document 2 cannot be applied.

[0029] Furthermore, Patent Document 2 increases the AC output voltage (increases the pulse width) of all cells that do not fail. Considering the case of Figure 1, in order to maintain equal power in DC system 21 and DC system 22, the AC output voltage of cells V11 to W12 should be increased, but the AC output voltage of cells U21 to W22 should not be increased. In this respect as well, the technology of Patent Document 2 cannot be applied as is.

[0030] Non-patent document 1, patent document 4, and patent document 5 can also be applied to MMCC-SSBCs. However, there is a problem in that the neutral point of an MMCC-SSBC is superimposed with third harmonics. When the potential of the neutral point fluctuates, common-mode current flows out via stray capacitance, which may lead to false detection of ground faults or adverse effects on other devices connected to the same AC system. In particular, SSTs are intended to be directly connected to high-voltage AC systems of 6.6kV or higher without a transformer, so even if the stray capacitance is small, a large common-mode current will flow. Among these, the method in patent document 4 superimposes many harmonics of the ninth order and above, so the common-mode current becomes even larger, increasing the risk of problems.

[0031] In Patent Documents 7 and 8, the superimposed zero-sequence voltage is the fundamental wave. Therefore, compared to Non-Patent Document 1 and Patent Documents 4 and 5, the common-mode current flowing out from stray capacitance is reduced to one-third, thus mitigating the impact. However, Patent Documents 7 and 8 assume that all cells are connected in parallel on the DC system side. They do not mention maintaining voltage balance when connected in series.

[0032] As described above, when operation continues in the event of a failure in part of the cells, the challenge is to prevent problems such as the SST being unable to output the required AC voltage for grid connection, being unable to supply power according to the command value, outputting a distorted current on the AC side, and the need to apply a gate block due to overcurrent, which would cause the device to shut down. [Means for solving the problem]

[0033] The present invention was devised in view of the above-mentioned conventional problems, and in one aspect thereof, each phase has m (m: an integer of 2 or more) cells comprising: an AC-DC converter connected to an AC system; a primary DC capacitor connected to the DC side of the AC-DC converter; an isolated DC-DC converter with one DC side connected to the primary DC capacitor; and a secondary DC capacitor connected to the other DC side of the isolated DC-DC converter, and there are x (x: an integer of 2 or more) DC systems in which a plurality of the secondary DC capacitors are connected in parallel, and the voltage of the plurality of DC systems is used as a load or power supply. A modular multilevel cascade converter for supplying power to a power supply, wherein the control unit of the AC / DC converter, when a cell fails, increases the output voltage on the AC side of the cell connected to the same DC system as the failed cell, decreases the output voltage on the AC side of the cell connected to other DC systems, superimposes a third harmonic on the AC output voltage of the cell connected to the same DC system as the failed cell, and superimposes a reverse third harmonic on the AC output voltage of the cell connected to a different DC system than the failed cell.

[0034] Furthermore, in one embodiment, the control unit of the AC / DC converter includes a second multiplier that multiplies the phase voltage command value of the AC / DC converter by 3m / (3m-x+1) for cells connected to the same DC system as the failed cell when one cell fails, (3m-x) / (3m-x+1) for cells connected to a different DC system than the failed cell when one cell fails, and 1 if there are no failed cells. The second multiplier multiplies the phase voltage command value of the AC / DC converter by 3m / (3m+1-x) for cells connected to the same DC system as the failed cell, and -3(mx) / ((x-1)(3m+1-x)) for cells connected to the same phase and a different DC system as the failed cell. The AC-DC converter is characterized by comprising: a third multiplier that multiplies the third harmonic by -3m / (x-1)(3m+1-x) for cells connected to a different phase and a different DC system from the cell, and by 0 if there are no faulty cells; a first adder that adds the output of the third multiplier to the output of the second multiplier; a primary DC voltage phase balance control unit that outputs a primary DC voltage phase balance control value based on the phase average value of the primary DC voltage of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage phase balance control value from the output of the first adder to output a cell voltage command value, and generates a gate signal for the AC-DC converter based on the cell voltage command value.

[0035] Furthermore, in one embodiment, the control unit of the AC-DC converter is characterized by comprising: a dq inverse converter that converts a voltage command value on a rotating coordinate system to a voltage command value on a fixed coordinate system; a switch for each phase that outputs (3m-x+1) / (3m-x-2) as a coefficient for the phase to which the faulty cell is connected, and 1 for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase; an arithmetic unit that outputs a zero-sequence voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-sequence voltage to the voltage command value on the fixed coordinate system; and a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary DC voltages of all cells and outputs it as the voltage command value for each phase.

[0036] Furthermore, in one embodiment, if two cells connected to the same phase and the same DC system fail, the control unit of the AC / DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system to a voltage command value on a fixed coordinate system, switches for each phase that output (3m-2x+2) / (3m-2x-4) as a coefficient for the phase to which the failed cell is connected, and 1 for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switches for each phase, and the output of the fourth multiplier and the relationship A calculator that outputs a zero-sequence voltage based on a number; a third adder that adds the zero-sequence voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary DC voltage of all cells and outputs it as the phase voltage command value; a cell connected to the same DC system as the faulty cell that outputs 3m / (3m+2-2x), a cell connected to a different DC system than the faulty cell that outputs (3m-2x) / (3m+2-2x), and the AC-DC conversion A second multiplier that multiplies the voltage command value of each phase of the device by a second multiplier, a third multiplier that multiplies the third harmonic by 3m / (3m+2-2x) for cells connected to the same DC system as the faulty cell, -3(m-2x) / ((x-1)(3m+2-2x)) for cells connected to a different DC system on the same phase as the faulty cell, and -3m / (x-1)(3m+2-2x) for cells connected to a different DC system on a different phase than the faulty cell, and the second multiplier The AC-DC converter comprises a first adder that adds the output of a third multiplier to the output of a multiplier; a primary DC voltage phase balance control unit that outputs a primary DC voltage phase balance control value based on the phase average value of the primary DC voltages of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage phase balance control value from the output of the first adder to output a cell voltage command value, wherein the gate signal of the AC-DC converter is generated based on the cell voltage command value.

[0037] Furthermore, in one embodiment, if two cells connected to the same DC system but on different phases fail, the control unit of the AC / DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system to a voltage command value on a fixed coordinate system, switches for each phase that output (3m-2x+2) / (3m-2x-1) as a coefficient for the phase to which the failed cell is connected, and 1 for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switches for each phase, and the output of the fourth multiplier and the A calculator that outputs a zero-sequence voltage based on a coefficient; a third adder that adds the zero-sequence voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary DC voltage of all cells and outputs it as the phase voltage command value; a cell connected to the same DC system as the faulty cell outputs 3m / (3m+2-2x), a cell connected to a different DC system than the faulty cell outputs (3m-2x) / (3m+2-2x), and the AC / DC converter outputs A second multiplier multiplies the voltage command value of each phase of the converter by 3m / (3m+2-2x) for cells connected to the same DC system as the faulty cell, -3(mx) / ((x-1)(3m+2-2x)) for cells connected to a different DC system on the same phase as the faulty cell, and -3m / (x-1)(3m+2-2x) for cells connected to a different DC system on a different phase than the faulty cell, multiplying the third harmonic by the second multiplier multiplier multiplier multiplies the third harmonic by 3m / (3m+2-2x) for cells connected to a different DC system on the same phase as the faulty cell, and -3m / (x-1)(3m+2-2x) for cells connected to a different DC system on a different phase than the faulty cell, and the second multiplier multiplier multiplies the third harmonic by 3m / (3m+2-2x) The AC-DC converter comprises a first adder that adds the output of the third multiplier to the output of the converter; a primary DC voltage phase balance control unit that outputs a primary DC voltage phase balance control value based on the primary DC voltage phase average value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage phase balance control value from the output of the first adder to output the cell voltage command value, and generates a gate signal for the AC-DC converter based on the cell voltage command value.

[0038] Furthermore, in one embodiment, if two cells connected to the same phase but different DC systems fail, the control unit of the AC / DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system to a voltage command value on a fixed coordinate system, switches for each phase that output (3m-x+2) / (3m-x-4) as a coefficient for the phase to which the failed cells are connected, and 1 for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switches for each phase, and the output of the fourth multiplier and the coefficient A calculator that outputs a zero-sequence voltage based on the above; a third adder that adds the zero-sequence voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary DC voltage of all cells and outputs it as the phase voltage command value; a cell connected to the same DC system as the faulty cell outputs 3m / (3m+2-x), a cell connected to a different DC system than the faulty cell outputs (3m-x) / (3m+2-x), and the AC / DC converter outputs A second multiplier that multiplies each of the phase voltage command values, a third multiplier that multiplies the third harmonic by 3m / (3m+2-x) for cells connected to the same DC system as the faulty cell, -6(mx) / ((x-2)(3m+2-x)) for cells connected to a different DC system on the same phase as the faulty cell, and -6m / (x-2)(3m+2-x) for cells connected to a different DC system on a different phase than the faulty cell, and the second multiplier The AC-DC converter is characterized by comprising: a first adder that adds the output of the third multiplier to the output; a primary DC voltage phase balance control unit that outputs a primary DC voltage phase balance control value based on the phase average value of the primary DC voltage of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage phase balance control value from the output of the first adder to output the cell voltage command value, and generates a gate signal for the AC-DC converter based on the cell voltage command value.

[0039] Furthermore, in one embodiment, if two cells connected to different phases and different DC systems fail, the control unit of the AC / DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system to a voltage command value on a fixed coordinate system, switches for each phase that output (3m-x+2) / (3m-x-1) as a coefficient for the phase to which the failed cell is connected, and 1 for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switches for each phase, and the output of the fourth multiplier and the A calculator that outputs a zero-sequence voltage based on a coefficient; a third adder that adds the zero-sequence voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary DC voltage of all cells and outputs it as the phase voltage command value; a cell connected to the same DC system as the faulty cell outputs 3m / (3m+2-x), a cell connected to a different DC system than the faulty cell outputs (3m-x) / (3m+2-x), and the AC / DC converter outputs A second multiplier that multiplies each of the phase voltage command values, a third multiplier that multiplies the third harmonic by 3m / (3m+2-x) for cells connected to the same DC system as the faulty cell, -3(2m-x) / ((x-2)(3m+2-x)) for cells connected to a different DC system on the same phase as the faulty cell, and -6m / (x-2)(3m+2-x) for cells connected to a different DC system on a different phase than the faulty cell, and the second multiplier The AC-DC converter is characterized by comprising: a first adder that adds the output of the third multiplier to the output of the AC converter; a primary DC voltage phase balance control unit that outputs a primary DC voltage phase balance control value based on the phase average value of the primary DC voltage of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage phase balance control value from the output of the first adder to output the cell voltage command value, wherein the gate signal of the AC-DC converter is generated based on the cell voltage command value. [Effects of the Invention]

[0040] According to the present invention, when operation is continued in the event of a failure in part of the cell, it is possible to prevent problems such as the inability to output the predetermined AC voltage required for grid connection from the SST, the inability to provide power according to the command value, the output of a distorted current on the AC side, and the need to apply a gate block due to overcurrent, which would cause the device to shut down. [Brief explanation of the drawing]

[0041] [Figure 1] A diagram showing an example of the main circuit configuration of the modular multilevel cascade converter of Embodiment 1. [Figure 2] This diagram shows the main circuit configuration when cell U11 malfunctions, short-circuiting the AC side and opening the DC side. [Figure 3] A block diagram showing the control unit of the AC-DC converter according to Embodiment 1. [Figure 4] A block diagram showing the voltage command value calculation unit of Embodiment 2. [Figure 5] This figure shows the output voltage waveform of the AC-DC converter when Embodiment 2 is applied. [Modes for carrying out the invention]

[0042] Embodiments 1 to 3 of the modular multilevel cascade converter according to the present invention will be described in detail below with reference to Figures 1 to 5.

[0043] [Embodiment 1] Here, m (an integer greater than or equal to 2) is the number of cells per phase, and x (an integer greater than or equal to 2) is the number of DC systems that output power. In Figure 1, m=4 and x=2.

[0044] Fig. 1 shows the main circuit configuration of a modular multilevel cascade converter (SST) that generates a plurality of DC systems. As shown in Fig. 1, an AC-DC converter ACDC connected to a high-voltage AC system via reactors Lu, Lv, and Lw, a primary-side DC capacitor C1 connected to the DC side of the AC-DC converter ACDC, an isolated DC-DC converter DCDC with one DC side connected to the primary-side DC capacitor C1, and a secondary-side DC capacitor C2 connected to the other DC side of the isolated DC-DC converter DCDC. The AC-DC converter ACDC and the isolated DC-DC converter DCDC may be appropriately selected from those known in the art and used. Since the AC-DC converter ACDC and the isolated DC-DC converter DCDC are well-known, detailed descriptions thereof are omitted here.

[0045] Here, the AC-DC converter ACDC, the primary-side DC capacitor C1, the isolated DC-DC converter DCDC, and the secondary-side DC capacitor C2 are taken as one cell. In Fig. 1, it has cells U11 to U22 for the U phase, cells V11 to V22 for the V phase, and cells W11 to W22 for the W phase. The AC sides of the cells in each phase are connected in series. Cells U11 to W12 are connected in parallel to form a DC system 21, and the DC sides of cells U21 to W22 are connected in parallel to form a DC system 22. The DC system 21 and the DC system 22 are connected in series. dc21 , dc21 , dc22 , DC21 , , DC22 , DC21 , , DC22 ,

[0046] , ACU11 , dc22 , ACW22 , dc22 , dc21 ~V ACW22 represents the AC output voltage of each cell, and V DC21 , V DC22 represents the detected value of the DC system voltage, and I DC21 , I DC22 represents the detected value of the DC system current.

[0046] In the first embodiment, the secondary-side DC capacitor C2 is connected in parallel to form one DC system V dc21 or DC system V dc22 . Also, the DC system V dc21 , or, V dc22 , or V dc21 +V dc22 is supplied to a load or a power source. Each cell (AC-DC converter ACDC, isolated DC-DC converter DCDC) includes a switching element. By the on-off operation of the switching element, the voltage and current of each cell can be controlled.

[0047] In this embodiment 1, the aforementioned (3) primary side DC voltage individual balance control and (4) secondary side DC voltage individual control are applied as is. Modifications have been made to (1) primary side DC voltage average value control and (2) primary side DC voltage phase balance control.

[0048] Here, we will explain (1) to (4).

[0049] (1) Primary DC voltage average value control calculates the sum of the primary DC voltages of all cells and uses this as the total primary DC voltage for all cells. The average primary DC voltage for all cells is calculated from the product of the total primary DC voltage for all cells and the reciprocal of the total number of cells. The deviation between the command value for the average primary DC voltage and the average primary DC voltage for all cells is amplified, and the d-axis current command value i d_ref Output as follows.

[0050] Furthermore, the AC system voltage V is controlled by a PLL (Phase Locked Loop). u ,V v ,V w Based on this, the phase ωt is output. In the dq converter, the three-phase system current value i u i v i w Based on the phase ωt, a dq transformation is performed to obtain the d-axis current detection value id and the q-axis current detection value i on a rotating coordinate system synchronized with the power system. q Outputs.

[0051] The system current control unit controls the d-axis current command value I d_ref From the d-axis current detection value I d Subtract and amplify to obtain the d-axis voltage command value V d_ref It outputs as follows. Also, the q-axis current command value I q_ref The q-axis current detection value Iq is subtracted and amplified to obtain the q-axis voltage command value V. q_ref Output as follows.

[0052] (2) The primary DC voltage phase balance control unit calculates the sum of the primary DC voltages within each phase and uses this as the primary DC voltage phase total. The unit then calculates the primary DC voltage phase average value for each phase from the product of the primary DC voltage phase total value and the reciprocal of the number of cells within the phase. The unit amplifies the deviation between the primary DC voltage phase average value for each phase and the primary DC voltage of each cell within the phase, multiplies it by the sign of the system current value for each phase, and outputs it as the primary DC voltage phase balance control value. This value is used to calculate the cell voltage command value as described later.

[0053] (3) The primary DC voltage individual balance control unit calculates the sum of the primary DC voltages of the cells connected to each DC system, and calculates the average primary DC voltage of the DC system for the cells connected to each DC system by multiplying this by the reciprocal of the number of cells connected to each DC system. The unit then calculates the deviation between the average primary DC voltage of the DC system and the primary DC voltage of each cell within the phase, removes the system frequency double component superimposed on the deviation as necessary, amplifies the result by an amplifier, multiplies it by the turns ratio of the transformer of the AC / DC converter and the transformer of the isolated DC / DC converter, and outputs it as the primary DC voltage individual balance control value.

[0054] (4) The secondary DC voltage individual control unit amplifies the difference between the secondary DC voltage command value and the secondary DC voltage of each DC system, calculates the product of this difference and the reciprocal of the number of cells connected to the DC system, and outputs it as the secondary DC voltage individual control value. The isolated DC-DC converter (DCDC) of each cell adds the corresponding primary DC voltage individual balance control value and the secondary DC voltage individual control value to obtain a current command value, and performs power exchange based on this command.

[0055] Figure 3 shows a block diagram of the control unit of the AC-DC converter ACDC of this embodiment 1. In this embodiment 1, when a cell fails, the output voltage on the AC side of cells connected to the same DC system as the failed cell is increased, and the output voltage on the AC side of cells connected to other DC systems is decreased. Then, a third harmonic is superimposed on the AC output voltage of cells connected to the same DC system as the failed cell, and a third harmonic in the opposite direction is superimposed on the AC output voltage of cells connected to a different DC system than the failed cell.

[0056] Specifically, the dq inverse converter 1 uses the d-axis voltage command value V d_ref q-axis voltage command value V q_ref The phase ωt is input, and the voltage command value on the rotating coordinate system synchronized with the system is converted to a voltage command value on the fixed coordinate system. d-axis voltage command value V d_ref q-axis voltage command value V q_ref The phase ωt is the value calculated in (1). The first multiplier 2 is the reciprocal of the average value of the primary DC voltages of all cells, 1 / V, from the output of the dq inverse converter 1. dc1_ave The product of the following is calculated. The output of the first multiplier 2 is the phase voltage command value V u_ref , V v_ref , V w_ref Let's assume that.

[0057] A fixed value of 3m / (3m+1-x) is entered as a coefficient to increase the output voltage on the AC side of the cell. In Figure 1, since m=4 and x=2, 3m / (3m+1-x)=12 / 11. A fixed value of (3m-x) / (3m+1-x) is entered as a coefficient to decrease the output voltage on the AC side of the cell. Applying this to Figure 1, (3m-x) / (3m+1-x)=10 / 11.

[0058] Switch SW1 outputs 3m / (3m+1-x) if a cell connected to DC system 21 fails, and (3m-x) / (3m+1-x) otherwise. Switch SW2 outputs (3m-x) / (3m+1-x) if a cell connected to DC system 21 fails, and 3m / (3m+1-x) otherwise.

[0059] Switch SW3 outputs the output of switch SW1 if a faulty cell exists, and 1 otherwise. Switch SW3 outputs 1 if there are no faulty cells, 3m / (3m+1-x) if a cell connected to DC system 21 has failed, and (3m-x) / (3m+1-x) if a cell connected to DC system 22 has failed.

[0060] Switch SW4 outputs the output of switch SW2 if a faulty cell exists, and 1 otherwise. Switch SW4 outputs 1 if there are no faulty cells, (3m-x) / (3m+1-x) if a cell connected to DC system 21 fails, and 3m / (3m+1-x) if a cell connected to DC system 22 fails.

[0061] The second multiplier 3 processes each phase voltage command value V u_ref , V v_ref , V w_ref The outputs of switches SW3 and SW4 are multiplied by this. The number of second multipliers 3 is 3x, and there are 6 when applied to Figure 1. For example, in the case of a 3-stage series connection of DC systems, if there is no fault cell, it is 1; if there is a fault cell in DC system 23, it is 3m / (3m+1-x); and if there is a fault cell in another stage, it is (3m-x) / (3m+1-x), and the phase voltage command value V u_ref , V v_ref , V w_ref Three additional second multipliers 3 are added to calculate the product of the two values.

[0062] 3rd harmonic V 03 This value was obtained from Non-Patent Document 1, Patent Documents 4 and 5, etc. Switch SW5 outputs 0 if there is no faulty cell, and the third harmonic V if there is a faulty cell. 03 Outputs.

[0063] The third harmonic V is superimposed on the AC output voltage of a cell connected to the same phase but a different DC system as the faulty cell. 03 A fixed value of -3(mx) / ((x-1)(3m+1-x)) is input as the coefficient that determines the amplitude. In the example in Figure 1, this is -6 / 11. The third harmonic V is superimposed on the AC output voltage of a cell connected to a different phase and a different DC system than the faulty cell. 03 A fixed value of -3m / ((x-1)(3m+1-x)) is entered as the coefficient that determines the amplitude. In the example in Figure 1, this is -12 / 11.

[0064] Switch SW6 outputs -3(mx) / ((x-1)(3m+1-x)) if the faulty cell is in the U phase, and -3m / ((x-1)(3m+1-x)) otherwise. Switch SW7 outputs -3(mx) / ((x-1)(3m+1-x)) if the faulty cell is in the V phase, and -3m / ((x-1)(3m+1-x)) otherwise. Switch SW8 outputs -3(mx) / ((x-1)(3m+1-x)) if the faulty cell is in the W phase, and -3m / ((x-1)(3m+1-x)) otherwise.

[0065] The third harmonic V is superimposed on the AC output voltage of cells connected to the same DC system as the faulty cell. 03 A fixed value of 3m / (3m+1-x) is entered as the coefficient that determines the amplitude. In the example in Figure 1 where m=4 and x=2, this value is 12 / 11.

[0066] Switch SW9 outputs 3m / (3m+1-x) if the faulty cell is in DC system 21, otherwise it outputs the output of switch SW6. Switch SW10 outputs 3m / (3m+1-x) if the faulty cell is in DC system 22, otherwise it outputs the output of switch SW6. Switch SW11 outputs 3m / (3m+1-x) if the faulty cell is in DC system 21, otherwise it outputs the output of switch SW7. Switch SW12 outputs 3m / (3m+1-x) if the faulty cell is in DC system 22, otherwise it outputs the output of switch SW7. Switch SW13 outputs 3m / (3m+1-x) if the faulty cell is in DC system 21, otherwise it outputs the output of switch SW8. Switch SW14 outputs 3m / (3m+1-x) if the faulty cell is in DC system 22, otherwise it outputs the output of switch SW8.

[0067] The third multiplier 5 calculates the product of the output of switch SW5 and the outputs of switches SW9 to SW14. Specifically, the third multiplier 5 multiplies the third harmonic by 3m / (3m+1-x) for cells connected to the same DC system as the faulty cell, -3(mx) / ((x-1)(3m+1-x)) for cells connected to a different DC system but on the same phase as the faulty cell, -3m / (x-1)(3m+1-x) for cells connected to a different DC system but on a different phase than the faulty cell, and 0 if there are no faulty cells.

[0068] The first adder 6 outputs the output of the third multiplier 5 with the command value V for each phase voltage. u_ref , V v_ref , V w_ref The product of switches SW3 and SW4 (output of the second multiplier 3) is added. Then, the first subtractor 4 subtracts the primary DC voltage phase balance control value obtained in (2) from the output of the first adder 6 to calculate the command value for each cell voltage. Based on these command values ​​for each cell voltage, the gate signal of the AC / DC converter ACDC is generated by PWM modulation.

[0069] In Patent Document 6 (2) Primary DC Voltage Phase Balance Control, feedforward adjustment is performed on the AC output voltage of the cell's AC-DC converter (ACDC). The problem with this method is that if some of the cells constituting the SST fail, it is not possible to output a voltage sufficient to connect to the AC system. The reason why the amplitude of the AC voltage output by the cell cannot be increased is that it is limited by the primary DC voltage within the cell, and in order to maintain the voltage balance of each stage of the DC system, the amplitude of the AC voltage of cells connected to a DC system without faulty cells must be smaller than the AC voltage of cells connected to a DC system with faulty cells.

[0070] This embodiment 1 applies the third harmonic superposition described in Non-Patent Document 1, Patent Documents 5 and 6 to the AC output voltage of the AC-DC converter (ACDC) of a cell connected to a DC system with a faulty cell, thereby increasing the AC output voltage of the AC-DC converter without increasing the primary side DC voltage average value control. Furthermore, since the amplitude of the AC voltage needs to be reduced in cells connected to a DC system without a faulty cell, there is a margin in the limit of the AC voltage amplitude. Therefore, by superimposing a third harmonic in the opposite direction to that of the cell connected to the DC system with the faulty cell, the third harmonics cancel each other out, preventing the third harmonic superposition to the neutral point of the MMCC-SSBC.

[0071] Let's explain the amplitude of the superimposed third harmonic. Consider the case where one cell connected to both the U phase and the DC system 21 fails. Non-patent document 1 states that in order to minimize the voltage peak after superposition, it is sufficient to superimpose a third harmonic with an amplitude of 1 / 6 of the voltage amplitude before superposition. Figure 3 shows the third harmonic V 03 This assumes that the third harmonic has the corresponding amplitude. Alternatively, the command value V for each phase voltage u_ref , V v_ref , V w_ref Applying Patent Documents 4 and 5, the third harmonic V 03 You may also request this.

[0072] When a failure occurs, the remaining cells connected to DC system 21 need to increase the AC output voltage of the AC-DC converter ACDC by a factor of 3m / (3m+1-x). A third harmonic superposition is applied to these cells. The amplitude of the third harmonic needs to be multiplied by 3m / (3m+1-x) in accordance with the increase in the AC output voltage of the AC-DC converter ACDC.

[0073] In the remaining cells, the superimposed third harmonic needs to be canceled out. Focusing on the U phase, the cells superimposed with a third harmonic multiplied by 3m / (3m+1-x) are in the m / x-1 range, there is one faulty cell, and the remaining cells are in the mm / x range. In order to cancel out the third harmonic in these remaining cells, the amplitude of the third harmonic that should be superimposed on the remaining cells must be -3(mx) / ((x-1)(3m+1-x)).

[0074] In the V and W phases, cells superimposed with a 3rd harmonic multiplied by 3m / (3m+1-x) are in the m / x range, while the remaining cells are in the mm / x range. The amplitude of the 3rd harmonic to be superimposed on the remaining cells is -3m / ((x-1)(3m+1-x)).

[0075] Taking m=4 and x=2 in Figure 1 as an example, the remaining cells connected to the DC system 21 will produce a third harmonic V 03 This is multiplied by 12 / 11 and superimposed. This corresponds to one U-phase cell, and the remaining two U-phase cells produce the third harmonic V 03 If we multiply by -6 / 11 and superimpose it, the third harmonic in the U phase becomes zero. In the V phase and W phase, the third harmonic V 03 Two cells are superimposed by multiplying by 12 / 11. The remaining two cells produce the third harmonic V. 03 By multiplying it by -12 / 11 and superimposing it, the third harmonic V is produced. 03 It can be negated.

[0076] Applying third-harmonic superposition can increase the fundamental wave component of the output voltage amplitude by approximately 2 / √3 ≈ 1.15 times. In contrast, to make the output voltage of a phase in a faulty cell equivalent to that before the failure, the AC output voltage of the AC / DC converter (ACDC) needs to be increased by (3m-x+1) / (3m-x-2) times.

[0077] In this embodiment 1, if m > 7.8 at x = 2, the AC output voltage of the AC-DC converter (ACDC) that needs to be increased will be within 1.15 times. In the example of m = 4 in Figure 1, the AC output voltage of the AC-DC converter (ACDC) needs to be increased to 11 / 8 = 1.375, which exceeds 1.15 times. In such cases, it is necessary to design the primary side DC voltage average value control to be higher in advance. However, even in the example of m = 4 in Figure 1, applying this embodiment 1 can reduce the increase in the primary side DC voltage within the cell from 1.375 times to 1.2 times.

[0078] This embodiment 1 solves the problem in a modular multilevel cascade converter (SST) that has its output terminals connected in series to output a higher DC voltage, where the AC voltage output by the SST drops when some of the cells fail. This makes it possible to suppress phenomena such as inability to transfer the predetermined power, outputting a distorted current on the AC side, and the occurrence of overcurrent.

[0079] Furthermore, with this embodiment 1, if one cell fails, cells connected in parallel to the same DC system as the failed cell can increase their AC voltage output by up to 1.15 times. This makes it possible to maintain both the balance of the output DC voltage and the AC system connection without increasing the DC capacitor voltage inside the cell. It is also advantageous in terms of cost and size because there is no need to strengthen the voltage withstand design of the cell or change to components that can handle high voltage. Increased switching losses can also be avoided.

[0080] [Embodiment 2] Figure 4 shows the phase voltage command values ​​V in this embodiment 2. u_ref , V v_ref , V w_ref The block diagram of the arithmetic unit is shown below.

[0081] AC system voltage detection value V u , V v , V w Enter the value. Enter the fixed value (3m-x+1) / (3m-x-2). Assuming application to Figure 1, the number of cells per phase is m=4 and the number of DC systems is x=2, so (3m-x+1) / (3m-x-2)=11 / 8.

[0082] Switch SW15 calculates (3m-x+1) / (3m-x-2) if the cell connected to the U phase fails, and 1 otherwise, using the coefficient N / n. u The output is as follows: Switch SW16 outputs (3m-x+1) / (3m-x-2) if the cell connected to the V phase has failed, and 1 otherwise, with coefficient N / n. vThe output is as follows: Switch SW17 outputs (3m-x+1) / (3m-x-2) if the cell connected to the W phase fails, and 1 otherwise, with coefficient N / n. w Output as follows.

[0083] The numerator N of the coefficient is the number of cells in each phase, and N = m. The notation for N follows that of Patent Documents 7 and 8. The denominator of the coefficient is n. u , n v , n w This represents the number of cells operating without failure in each phase.

[0084] The fourth multiplier 7 processes the detected AC system voltage V u and coefficient N / n u AC system voltage detection value V v and coefficient N / n v AC system voltage detection value V w and coefficient N / n w Find the product of the two.

[0085] The arithmetic unit 8 receives the output V of the fourth multiplier 7. u N / n u , V v N / n v , V w N / n w coefficient N / n u N / n v N / n w Input the zero-sequence voltage V based on Patent Document 7. 0q sinωt, V 0d Output cosωt.

[0086] Here, we will explain the method for calculating the zero-sequence voltage described in Patent Document 7, which is implemented inside the arithmetic unit 8.

[0087] The correction voltage command value generation unit outputs a phase ωt synchronized with the AC voltage of the system. The first dq converter converts a value obtained by multiplying a phase voltage detection signal or a voltage command value, or a phase voltage detection signal or a voltage command value by a coefficient obtained by dividing the number of cell units of each phase by the number of cell units operating without failure in each phase, into a value on a rotating coordinate synchronized with the system frequency. The second dq converter converts a value obtained by multiplying a phase voltage detection signal or a voltage command value, or a phase voltage detection signal or a voltage command value by a coefficient obtained by dividing the number of cell units of each phase by the number of cell units operating without failure in each phase, into a value on a rotating coordinate rotating in the opposite direction to the system frequency. The arithmetic unit extracts the DC component from the output of the first dq converter to obtain the positive-phase d-axis component V 1d , the positive-phase q-axis component V 1q , and from the output of the second dq converter, extracts the DC component to obtain the negative-phase d-axis component V<0️⃣0️⃣0️⃣0️⃣0️⃣8️⃣9️⃣>, the negative-phase q-axis component V 2q . Based on these, the zero-phase voltage d-axis component and the zero-phase voltage q-axis component that equalize the AC-side output voltage of each cell are calculated by any of the following equations (1) to (3). The zero-phase voltage d-axis component V 0d is multiplied by cosωt. The zero-phase voltage q-axis component V 0q is multiplied by sinωt.

[0088] <000️⃣0️⃣0️⃣0️⃣0️⃣4️⃣6️⃣4️⃣>

Equation

[0089]

Equation

[0090]

Equation

[0091] Next, the method for calculating the zero-phase voltage when Patent Document 8 is implemented in the arithmetic unit 8 will be described.

[0092] The correction voltage command value generation unit calculates the amplitude of the correction voltage command value for each phase. The amplitude is, for example, the effective value of the voltage command value, the value obtained by extracting the amplitude of the fundamental wave component of the voltage command value, or the peak value per cycle of the voltage command value. Multiply the obtained amplitude by a coefficient based on the number of failed cells. Amplify the deviation between the three-phase average value of the multiplied correction voltage command value amplitude and the multiplied correction voltage command value amplitude, and multiply by a sine wave in the same phase as the voltage command value. Add the values after multiplication for the three phases and output as the zero-phase voltage.

[0093] The zero-phase voltage V output from the arithmetic unit 8 0q sinωt, V 0d cosωt is added by the second adder 9. The third adder 10 adds the zero-phase voltage V 0q sinωt + V 0d cosωt to the output of the dq inverter 1 and outputs the correction voltage command value for each phase. <000049l>

[0094] The correction voltage command value for each phase is input to the first multiplier ②, and is also input to the arithmetic unit 12 again, and the zero-phase voltage V 0q sinωt, V 0d cosωt is calculated again by feedback control based on Patent Document 8 (when calculating based on Patent Document 7, it is not necessary to input the correction voltage command value for each phase to the arithmetic unit 8).

[0095] <000049lo>The first multiplier 2 multiplies the output of the third adder 10 by the reciprocal 1 / V of the average value of the DC voltage on the primary side of all cells dc1_ave to obtain the phase voltage command values V u_ref V v_ref V w_ref

[0096] Embodiment 2 combines Patent Documents 7 and 8 with Embodiment 1.

[0097] In Patent Documents 7 and 8, the coefficient N / n is applied to the AC voltage of the phase including the failed cell u N / n v N / n w ​By applying this, the voltage amplitude is made to appear larger in proportion to the number of faulty cells, and the zero-sequence voltage that makes the voltage amplitudes equal is calculated and superimposed. However, this can only be applied if the amplitude of the AC output voltage of the AC / DC converter (ACDC) of each cell is equal.

[0098] In Embodiment 1, the AC output voltage of the AC-DC converter ACDC is multiplied by fixed values ​​3m / (3m+1-x) and (3m-x) / (3m+1-x), so the amplitudes of the AC output voltages of the AC-DC converter ACDC are not equal. Therefore, in order to apply Patent Documents 7 and 8, the coefficient N / n u N / n v N / n w Adjustments are needed.

[0099] Here, we define the output voltage of the AC-DC converter (ACDC) for all cells before cell failure as 1, and consider the case where cells connected to both the U-phase and the DC system 21 fail. The remaining 3m / x-1 cells connected to the DC system 21 will have an AC output voltage of 3m / (3m+1-x) based on Embodiment 1. The other cells connected to the DC systems 22~2x will have an AC output voltage of (3m-x) / (3m+1-x) based on the AC-DC converter (ACDC).

[0100] Looking at the U phase, there are m / x-1 cells where the AC output voltage of the AC-DC converter (ACDC) is 3m / (3m+1-x), mm / x cells where it is (3m-x) / (3m+1-x), and 1 cell which has failed and is 0. The sum of the U phase AC output voltages of the AC-DC converter (ACDC) is m(3m-x-2) / (3m-x+1). Before the failure, there were m cells outputting 1, so the sum of the U phase AC output voltages of the AC-DC converter (ACDC) changes by a factor of (3m-x-2) / (3m-x+1).

[0101] For the V and W phases, cells where the AC output voltage of the AC / DC converter (ACDC) becomes 3m / (3m+1-x) due to a failure are in the m / x range, while cells where it becomes (3m-x) / (3m+1-x) are in the mm / x range, similar to the U phase. The sum of the AC output voltages of the V and W phases of the AC / DC converter (ACDC) is m and does not change before and after the failure. Therefore, the coefficient is N / n.u This should be set to (3m-x+1) / (3m-x-2), which is the reciprocal of the change in the sum of the U-phase AC output voltages of the AC / DC converter.

[0102] Let's re-examine the case where cells connected to both the U-phase and the DC system 21 fail, using the configuration m=4, x=2 shown in Figure 1. In Embodiment 1, the output voltage of the AC / DC converters ACDC of the five cells connected to the DC system 21 becomes 12 / 11 times. The output voltage of the AC / DC converters ACDC of the six cells connected to the DC system 22 becomes 10 / 11 times. In the U-phase, there is one cell whose output voltage has become 12 / 11 times and two cells whose output voltage has become 10 / 11 times. The total output voltage changes from 4 to 32 / 11, decreasing to 8 / 11 times. Rather than simply decreasing from 4 cells to 3 cells resulting in a 3 / 4 time decrease, the decrease in the total output voltage is larger because there are more cells whose AC / DC converter ACDC output voltage has decreased. In the V-phase and W-phase, there are two cells whose output voltage has become 12 / 11 times and two cells whose output voltage has become 10 / 11 times, so the total output voltage remains 4. From the above, V u By multiplying it by a coefficient of 11 / 8, the U-phase voltage amplitude can be made to appear larger.

[0103] Figure 5 shows the AC output voltage waveform of the U-phase AC-DC converter (ACDC) when this embodiment 2 is applied. Initially, all cells are outputting the AC voltage of the AC-DC converter (ACDC) normally. For example, the amplitude of the AC voltage is the primary side DC voltage (V dc1u11 ~V dc1u22 It is set at 0.9 times the value of ().

[0104] After two cycles, cell U11 fails and short-circuits the AC output terminal, so V ACU11 V becomes zero. ACU12 The amplitude is multiplied by 12 / 11, V ACU21 , V ACU22 It is multiplied by 10 / 11.

[0105] Furthermore, by applying Patent Documents 7 and 8, zero-sequence voltages are superimposed, and the AC voltage becomes three-phase balanced. In this case, the AC voltage of the AC-DC converters (ACDC) of all cells is multiplied by approximately 1.09. As a result, V ACU12This causes the amplitude to exceed the primary DC voltage, resulting in overmodulation. In reality, it is not possible to output such a voltage, leading to distortion and overcurrent.

[0106] The case after 4 cycles is when this embodiment 2 is applied. The fundamental wave component of the AC voltage of each AC-DC converter (ACDC) remains unchanged. ACU12 The third harmonic is added, reducing the peak, keeping the amplitude within the primary DC voltage, and thus avoiding overmodulation. The superimposed third harmonic is reversed and bisected to V ACU21 , V ACU22 It superimposes on V. ACU21 , V ACU22 Although the distortion peaks increase in a triangular wave pattern, overmodulation can be avoided because the amplitude decreases and there is a margin of error before application. ACU12 , V ACU21 , V ACU22 The distortions cancel each other out, preventing the superposition of third harmonics on the neutral point.

[0107] However, for the V phase, V ACV11 , V ACV12 Both amplitudes are multiplied by 12 / 11 × 1.09, and a third harmonic must be superimposed on both. This is shared and canceled out by two cells, V21 and V22, so V is more difficult than U. ACV21 , V ACV22 A second third harmonic is superimposed, increasing the risk of overmodulation. The same applies to the W phase. Here, we explained using m=4 as an example, but in configurations with a large m, the number of cells that can share the workload by canceling out the third harmonic increases, thus preventing overmodulation.

[0108] This second embodiment allows the AC output voltages of AC-DC converters (ACDC) of cells connected to the same DC system to be equalized in the event of a single cell failure. This prevents situations such as excessive DC voltage being applied to other cells in the phase with a faulty cell, causing a chain reaction of failures; insufficient AC output voltage in the phase with a faulty cell, making it impossible to maintain grid connection and resulting in overcurrents; and voltage and current distortion. Furthermore, similar to Patent Documents 7 and 8, it also provides the effect of equalizing the AC output voltages of cells even when an imbalance occurs in the AC voltage, or when an unbalanced AC voltage is intentionally output.

[0109] [Embodiment 3] Table 1 shows the formulas for calculating the fixed values ​​used in this embodiment 3. Depending on the number and location of faulty cells, the fixed values ​​used in embodiments 1 and 2 should be changed to the values ​​obtained in Table 1.

[0110] [Table 1]

[0111] This third embodiment describes the case where two cell failures are addressed. In Table 1, the voltage command value fault stage is the value input to the upper side of switch SW1 and the lower side of switch SW2. The voltage command value healthy stage is the value input to the lower side of switch SW1 and the upper side of switch SW2. The coefficient N / n fault phase is the value input to the upper side of switch SW15, the middle of switch SW16, and the lower side of switch SW17. The third harmonic fault stage is the value input to the upper sides of switches SW9, SW11, and SW13, and the lower sides of switches SW10, SW12, and SW14. The third harmonic healthy stage fault phase is the value input to the upper side of switch SW6, the middle of switch SW7, and the lower side of switch SW8. The third harmonic healthy stage healthy phase is the value input to the middle and lower side of switch SW6, the upper and lower sides of switch SW7, and the upper and middle sides of switch SW8.

[0112] (1) When two faulty cells are connected to the same phase and the same DC system (stage) Consider the case where two faulty cells are connected to the U-phase DC system 21. Excluding the faulty cells, the cells in DC system 21 are 3m / x-2 units, and the AC output voltage is increased by 3m / (3m+2-2x). The cells in DC systems 22~2x total 3m-3m / x units, and the AC output voltage is decreased by (3m-2x) / (3m+2-2x).

[0113] In the U phase, cells connected to DC system 21 have a density of m / x-2 units, excluding faulty cells, while cells connected to other DC systems have a density of mm / x units. In the V and W phases, cells connected to DC system 21 have a density of m / x units, while cells connected to other DC systems have a density of mm / x units.

[0114] The AC output voltage of the U phase decreases by a factor of {(3m / (3m+2-2x))·(m / x-2)+((3m-2x) / (3m+2-2x))·(mm / x)} / m = (3m-2x-4) / (3m-2x+2) due to the fault. The AC output voltage of the V and W phases remains unchanged at {(3m / (3m+2-2x))·m / x+((3m-2x) / (3m+2-2x))(mm / x)} / m = 1.

[0115] Therefore, the coefficient N / n u The value is set to (3m-2x+2) / (3m-2x-4). Since the third harmonic superposition is performed to lower the peak value of the cell with increased AC output voltage, the amplitude of the third harmonic superimposed on the DC system 21 cell is set to 3m / (3m+2-2x).

[0116] The cell in which this third harmonic is superimposed on the U phase is in the m / x-2 range. Since this is canceled out by the remaining cells in the mm / x range, the amplitude of the third harmonic that should be superimposed on the remaining cells is -3m / (3m+2-2x)·(m / x-2) / (mm / x)=-3(m-2x) / ((x-1)(3m+2-2x)). The cell in which this third harmonic is superimposed on the V phase and W phase is in the m / x range. Since this is canceled out by the remaining cells in the mm / x range, the amplitude of the third harmonic that should be superimposed on the remaining cells is -3m / (3m+2-2x)·(m / x) / (mm / x)=-3m / ((x-1)(3m+2-2x)).

[0117] (2) When two faulty cells are connected to different phases but the same DC system (stage) Consider the case where there is one faulty cell each in the U-phase and V-phase, and both are connected to DC system 21. The cells in DC system 21, excluding the faulty cell, are 3m / x-2, and the AC output voltage is increased by 3m / (3m+2-2x). The cells in DC systems 22~2x are a total of 3m-3m / x, and the AC output voltage is decreased by (3m-2x) / (3m+2-2x).

[0118] In the U and V phases, cells connected to DC system 21 have a density of m / x-1 units each, excluding faulty cells, while cells connected to other DC systems have a density of mm / x units each. In the W phase, cells connected to DC system 21 have a density of m / x units, while cells connected to other DC systems have a density of mm / x units.

[0119] The AC output voltage of the U-phase and V-phase decreases by a factor of {(3m / (3m+2-2x))·(m / x-1)+((3m-2x) / (3m+2-2x))·(mm / x)} / m=(3m-2x-1) / (3m-2x+2) due to the fault. The AC output voltage of the W-phase remains unchanged at {(3m / (3m+2-2x))·m / x+((3m-2x) / (3m+2-2x))(mm / x)} / m=1 before and after the fault.

[0120] Therefore, the coefficient N / n u N / n v The value is set to (3m-2x+2) / (3m-2x-1). Since the third harmonic superposition is performed to lower the peak value of the cell with increased AC output voltage, the amplitude of the superimposed third harmonic is set to 3m / (3m+2-2x) times.

[0121] The cell in which this third harmonic is superimposed on the U and V phases is in the m / x-1 range. Since this is canceled out by the remaining cells in the mm / x range, the amplitude of the third harmonic that should be superimposed on the remaining cells is -3m / (3m+2-2x)·(m / x-1) / (mm / x)=-3(mx) / ((x-1)(3m+2-2x)). The cell in which this third harmonic is superimposed on the W phase is in the m / x range. Since this is canceled out by the remaining cells in the mm / x range, the amplitude of the third harmonic that should be superimposed on the remaining cells is -3m / (3m+2-2x)·(m / x) / (mm / x)=-3m / ((x-1)(3m+2-2x)).

[0122] (3) When two faulty cells are connected to the same phase but different DC systems (stages) Consider the case where there are two faulty cells in the U phase, one each connected to DC system 21 and DC system 22. The cells in DC system 21 and DC system 22, excluding the faulty cells, are each 3m / x-1 units, and the AC output voltage is increased by 3m / (3m+2-x). The cells in DC systems 23~2x total 3m-6m / x units, and the AC output voltage is decreased by (3m-x) / (3m+2-x).

[0123] In the U phase, the cells connected to DC systems 21 and 22 total 2m / x-2 units, excluding faulty cells, while the cells connected to other DC systems are m-2m / x units. In the V and W phases, the cells connected to DC systems 21 and 22 total 2m / x units, while the cells connected to other DC systems are m-2m / x units.

[0124] The AC output voltage of the U phase decreases by a factor of {(3m / (3m+2-x))·(2m / x-2)+((3m-x) / (3m+2-x))·(m-2m / x)} / m = (3m-x-4) / (3m-x+2) due to the fault. The AC output voltage of the V and W phases remains unchanged at {(3m / (3m+2-x))·2m / x+((3m-x) / (3m+2-x))(m-2m / x)} / m = 1.

[0125] Therefore, the coefficient N / n uThe value is set to (3m-x+2) / (3m-x-4). Since the third harmonic superposition is performed to lower the peak value of the cell with increased AC output voltage, the amplitude of the superimposed third harmonic is set to 3m / (3m+2-x).

[0126] The cell in the U phase with this third harmonic superimposed is in the range of 2m / x-2. Since this is canceled out by the remaining cell in the range of m-2m / x, the amplitude of the third harmonic to be superimposed on the remaining cell is -3m / (3m+2-x)·(2m / x-2) / (m-2m / x)=-6(mx) / ((x-2)(3m+2-x)). The cell in the V phase and W phase with this third harmonic superimposed is in the range of 2m / x. Since this is canceled out by the remaining cell in the range of m-2m / x, the amplitude of the third harmonic to be superimposed on the remaining cell is -3m / (3m+2-x)·(2m / x) / (m-2m / x)=-6m / ((x-2)(3m+2-x)).

[0127] (4) When two faulty cells are connected to different phases and different DC systems (stages) Consider the case where there is one faulty cell each in the U-phase and V-phase, connected to DC system 21 and DC system 22, respectively. The cells in DC system 21 and DC system 22, excluding the faulty cell, each have 3m / x-1 units, and the AC output voltage is increased by 3m / (3m+2-x). The cells in DC systems 23 to 2x have a total of 3m-6m / x units, and the AC output voltage is decreased by (3m-x) / (3m+2-x).

[0128] In the U and V phases, the total number of cells connected to DC systems 21 and 22 is 2m / x-1 units per phase, excluding faulty cells, while the total number of cells connected to other DC systems is m-2m / x units each. In the W phase, the total number of cells connected to DC systems 21 and 22 is 2m / x units, while the total number of cells connected to other DC systems is m-2m / x units.

[0129] The AC output voltage of the U-phase and V-phase decreases by a factor of {(3m / (3m+2-x))·(2m / x-1)+((3m-x) / (3m+2-x))·(m-2m / x)} / m=(3m-x-1) / (3m-x+2) due to the fault. The AC output voltage of the W-phase remains unchanged at {(3m / (3m+2-x))·2m / x+((3m-x) / (3m+2-x))(m-2m / x)} / m=1 before and after the fault.

[0130] Therefore, the coefficient N / n u N / n v The value is set to (3m-x+2) / (3m-x-1). Since the third harmonic superposition is performed to lower the peak value of the cell with increased AC output voltage, the amplitude of the superimposed third harmonic is set to 3m / (3m+2-x).

[0131] The cell with this third harmonic superimposed on the U and V phases is in the range of 2m / x-1. Since this is canceled out by the remaining cell in the range of m-2m / x, the amplitude of the third harmonic to be superimposed on the remaining cell is -3m / (3m+2-x)·(2m / x-1) / (m-2m / x) = -3(2m-x) / ((x-2)(3m+2-x)). The cell with this third harmonic superimposed on the W phase is in the range of 2m / x. Since this is canceled out by the remaining cell in the range of m-2m / x, the amplitude of the third harmonic to be superimposed on the remaining cell is -3m / (3m+2-x)·(2m / x) / (m-2m / x) = -6m / ((x-2)(3m+2-x)).

[0132] Table 1 summarizes the above. From Table 1, the number and location of faulty cells correspond to the phase voltage command values ​​V u_ref , V v_ref , V w_ref The fixed value to be multiplied, coefficient N / n u N / n v N / n w By referring to and applying the values ​​to be set and the amplitude of the superimposed third harmonic, operation can continue even if up to two units fail.

[0133] If m is sufficiently large and even with only one cell failure, if the modular multilevel cascade converter (SST) can output the AC voltage necessary for grid connection, it is conceivable that the third harmonic will not be superimposed. In this case, Embodiment 3 would be applied when the number of failed cells reaches two. Alternatively, if there is only one failed cell, the third harmonic V 03 The amplitude of the superimposed third harmonic can be reduced by multiplying it by a coefficient of 2 / 3 to superimpose a third harmonic with an amplitude of 1 / 9 of the voltage amplitude before superimposition.

[0134] Extending the above, it is possible to handle cases where three or more cells fail. However, as the number of failed cells increases, the case distinctions become more complex, and there is a high risk that the AC output voltage of cells connected to the same DC system as the failed cell will have to be increased by more than 1.15 times. In this case, it becomes necessary to increase the primary DC voltage of the cell in advance. However, even when increasing the primary DC voltage of the cell, applying this embodiment 3 can limit the increase to √3 / 2 ≈ 0.866 times.

[0135] This third embodiment makes it possible to obtain the effects of Embodiments 1 and 2 even when two cells fail.

[0136] Although the present invention has been described in detail only with respect to the specific examples described above, it will be obvious to those skilled in the art that a wide variety of modifications and alterations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and alterations fall within the scope of the claims. [Explanation of symbols]

[0137] 1…dq inverse converter, 2…first multiplier, 3…second multiplier, 4…first subtractor, 5…third multiplier, 6…first adder, 7…fourth multiplier, 8…arithmetic unit, 9…second adder, 10…third adder, SW1~SW17…switches, ACDC…AC / DC converter, C1…primary DC capacitor, DCDC…isolated DC converter, C2…secondary DC capacitor

Claims

1. A modular multilevel cascade converter having m (m: an integer of 2 or more) cells per phase, each cell comprising: an AC-DC converter connected to an AC system; a primary DC capacitor connected to the DC side of the AC-DC converter; an isolated DC-DC converter with one DC side connected to the primary DC capacitor; and a secondary DC capacitor connected to the other DC side of the isolated DC-DC converter; and having x (x: an integer of 2 or more) DC systems in which a plurality of the secondary DC capacitors are connected in parallel, and supplying the voltage of the plurality of DC systems to a load or power supply, The control unit of the AC-DC converter is When the aforementioned cell fails, The output voltage on the AC side of the cell connected to the same DC system as the faulty cell is increased, and the output voltage on the AC side of the cell connected to other DC systems is decreased. A modular multilevel cascade converter characterized by superimposing a third harmonic on the AC output voltage of a cell connected to the same DC system as the faulty cell, and superimposing a third harmonic in the opposite direction on the AC output voltage of a cell connected to a different DC system than the faulty cell.

2. The control unit of the AC-DC converter is A second multiplier multiplies the phase voltage command values ​​of the AC / DC converter by 3m / (3m-x+1) for cells connected to the same DC system as the failed cell when one cell fails, (3m-x) / (3m-x+1) for cells connected to a different DC system than the failed cell when one cell fails, and 1 if there are no failed cells. A third multiplier multiplies the third harmonic by 3m / (3m+1-x) for cells connected to the same DC system as the faulty cell, -3(m-x) / ((x-1)(3m+1-x)) for cells connected to a different DC system on the same phase as the faulty cell, -3m / (x-1)(3m+1-x) for cells connected to a different DC system on a different phase than the faulty cell, and 0 if there are no faulty cells. A first adder that adds the output of the third multiplier to the output of the second multiplier, A primary DC voltage phase balance control unit outputs a primary DC voltage phase balance control value based on the phase average value of the primary DC voltage of each phase and the primary DC voltage of each cell. A first subtractor that subtracts the primary DC voltage phase balance control value from the output of the first adder to output each cell voltage command value, The modular multilevel cascade converter according to claim 1, comprising a function that generates a gate signal for the AC / DC converter based on the respective cell voltage command values.

3. The control unit of the AC-DC converter is A dq inverse converter that converts a voltage command value on a rotating coordinate system to a voltage command value on a fixed coordinate system, A switch for each phase outputs (3m - x + 1) / (3m - x - 2) as the coefficient for the phase to which the faulty cell is connected, and 1 as the coefficient for the other phases. A fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, A calculator that outputs a zero-sequence voltage based on the output of the fourth multiplier and the coefficient, A third adder that adds the zero-sequence voltage to the voltage command value on the fixed coordinates, A first multiplier multiplies the output of the third adder by the reciprocal of the average value of the primary DC voltages of all cells and outputs it as the phase voltage command value, The modular multilevel cascade converter according to claim 2, characterized by comprising the following:

4. If two of the aforementioned cells, connected to the same phase and the same DC system, fail, The control unit of the AC-DC converter is A dq inverse converter that converts a voltage command value on a rotating coordinate system to a voltage command value on a fixed coordinate system, A switch for each phase outputs (3m - 2x + 2) / (3m - 2x - 4) as the coefficient for the phase to which the faulty cell is connected, and 1 for the other phases. A fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, A calculator that outputs a zero-sequence voltage based on the output of the fourth multiplier and the coefficient, A third adder that adds the zero-sequence voltage to the voltage command value on the fixed coordinates, A first multiplier multiplies the output of the third adder by the reciprocal of the average value of the primary DC voltages of all cells and outputs it as a command value for each phase voltage, A second multiplier multiplies the phase voltage command values ​​of the AC / DC converter by 3m / (3m+2-2x) for cells connected to the same DC system as the faulty cell, and by (3m-2x) / (3m+2-2x) for cells connected to a different DC system than the faulty cell. A third multiplier multiplies the third harmonic of the following: 3m / (3m+2-2x) for cells connected to the same DC system as the faulty cell, -3(m-2x) / ((x-1)(3m+2-2x)) for cells connected to a different DC system but on the same phase as the faulty cell, and -3m / (x-1)(3m+2-2x) for cells connected to a different DC system but on a different phase than the faulty cell. A first adder that adds the output of the third multiplier to the output of the second multiplier, A primary DC voltage phase balance control unit outputs a primary DC voltage phase balance control value based on the phase average value of the primary DC voltage of each phase and the primary DC voltage of each cell. A first subtractor that subtracts the primary DC voltage phase balance control value from the output of the first adder to output each cell voltage command value, The modular multilevel cascade converter according to claim 1, comprising a function that generates a gate signal for the AC / DC converter based on the respective cell voltage command values.

5. If two of the aforementioned cells, which are on different phases but connected to the same DC system, fail, The control unit of the AC-DC converter is A dq inverse converter that converts a voltage command value on a rotating coordinate system to a voltage command value on a fixed coordinate system, A switch for each phase outputs (3m - 2x + 2) / (3m - 2x - 1) as the coefficient for the phase to which the faulty cell is connected, and 1 for the other phases. A fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, A calculator that outputs a zero-sequence voltage based on the output of the fourth multiplier and the coefficient, A third adder that adds the zero-sequence voltage to the voltage command value on the fixed coordinates, A first multiplier multiplies the output of the third adder by the reciprocal of the average value of the primary DC voltages of all cells and outputs it as a command value for each phase voltage, A second multiplier multiplies the phase voltage command values ​​of the AC / DC converter by 3m / (3m+2-2x) for cells connected to the same DC system as the faulty cell, and by (3m-2x) / (3m+2-2x) for cells connected to a different DC system than the faulty cell. A third multiplier multiplies the third harmonic of the following: 3m / (3m+2-2x) for cells connected to the same DC system as the faulty cell, -3(m-x) / ((x-1)(3m+2-2x)) for cells connected to a different DC system but on the same phase as the faulty cell, and -3m / (x-1)(3m+2-2x) for cells connected to a different DC system but on a different phase than the faulty cell. A first adder that adds the output of the third multiplier to the output of the second multiplier, A primary DC voltage phase balance control unit outputs a primary DC voltage phase balance control value based on the phase average value of the primary DC voltage of each phase and the primary DC voltage of each cell. A first subtractor that subtracts the primary DC voltage phase balance control value from the output of the first adder to output each cell voltage command value, The modular multilevel cascade converter according to claim 1, comprising a function that generates a gate signal for the AC / DC converter based on the respective cell voltage command values.

6. If two cells connected to the same phase but different DC systems fail, The control unit of the AC-DC converter is A dq inverse converter that converts a voltage command value on a rotating coordinate system to a voltage command value on a fixed coordinate system, A switch for each phase outputs (3m - x + 2) / (3m - x - 4) as the coefficient for the phase to which the faulty cell is connected, and 1 for the other phases. A fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, A calculator that outputs a zero-sequence voltage based on the output of the fourth multiplier and the coefficient, A third adder that adds the zero-sequence voltage to the voltage command value on the fixed coordinates, A first multiplier multiplies the output of the third adder by the reciprocal of the average value of the primary DC voltages of all cells and outputs it as a command value for each phase voltage, A second multiplier multiplies the phase voltage command value of the AC / DC converter by 3m / (3m+2-x) for cells connected to the same DC system as the faulty cell, and by (3m-x) / (3m+2-x) for cells connected to a different DC system than the faulty cell. A third multiplier multiplies the third harmonic of the following: 3m / (3m+2-x) for cells connected to the same DC system as the faulty cell, -6(m-x) / ((x-2)(3m+2-x)) for cells connected to a different DC system on the same phase as the faulty cell, and -6m / (x-2)(3m+2-x) for cells connected to a different DC system on a different phase than the faulty cell. A first adder that adds the output of the third multiplier to the output of the second multiplier, A primary DC voltage phase balance control unit outputs a primary DC voltage phase balance control value based on the phase average value of the primary DC voltage of each phase and the primary DC voltage of each cell. A first subtractor that subtracts the primary DC voltage phase balance control value from the output of the first adder to output each cell voltage command value, The modular multilevel cascade converter according to claim 1, comprising a function that generates a gate signal for the AC / DC converter based on the respective cell voltage command values.

7. If two of the aforementioned cells, connected to different phases and different DC systems, fail, The control unit of the AC-DC converter is A dq inverse converter that converts a voltage command value on a rotating coordinate system to a voltage command value on a fixed coordinate system, A switch for each phase outputs (3m - x + 2) / (3m - x - 1) as the coefficient for the phase to which the faulty cell is connected, and 1 for the other phases. A fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, A calculator that outputs a zero-sequence voltage based on the output of the fourth multiplier and the coefficient, A third adder that adds the zero-sequence voltage to the voltage command value on the fixed coordinates, A first multiplier multiplies the output of the third adder by the reciprocal of the average value of the primary DC voltages of all cells and outputs it as a command value for each phase voltage, A second multiplier multiplies the phase voltage command value of the AC / DC converter by 3m / (3m+2-x) for cells connected to the same DC system as the faulty cell, and by (3m-x) / (3m+2-x) for cells connected to a different DC system than the faulty cell. A third multiplier multiplies the third harmonic of the following: 3m / (3m+2-x) for cells connected to the same DC system as the faulty cell, -3(2m-x) / ((x-2)(3m+2-x)) for cells connected to a different DC system but on the same phase as the faulty cell, and -6m / (x-2)(3m+2-x) for cells connected to a different DC system but on a different phase than the faulty cell. A first adder that adds the output of the third multiplier to the output of the second multiplier, A primary DC voltage phase balance control unit outputs a primary DC voltage phase balance control value based on the phase average value of the primary DC voltage of each phase and the primary DC voltage of each cell. A first subtractor that subtracts the primary DC voltage phase balance control value from the output of the first adder to output each cell voltage command value, The modular multilevel cascade converter according to claim 1, comprising a function that generates a gate signal for the AC / DC converter based on the respective cell voltage command values.

8. A control method for a modular multilevel cascade converter, comprising: a cell comprising: an AC-DC converter connected to an AC system; a primary DC capacitor connected to the DC side of the AC-DC converter; an isolated DC-DC converter with one DC side connected to the primary DC capacitor; and a secondary DC capacitor connected to the other DC side of the isolated DC-DC converter, with m (m: an integer of 2 or more) cells per phase; and x (x: an integer of 2 or more) DC systems in which a plurality of the secondary DC capacitors are connected in parallel, wherein the voltage of the plurality of DC systems is supplied to a load or power supply, When the aforementioned cell fails, The control unit of the AC-DC converter is The output voltage on the AC side of the cell connected to the same DC system as the faulty cell is increased, and the output voltage on the AC side of the cell connected to other DC systems is decreased. A control method for a modular multilevel cascade converter, characterized by superimposing a third harmonic on the AC output voltage of a cell connected to the same DC system as the faulty cell, and superimposing a third harmonic in the opposite direction on the AC output voltage of a cell connected to a different DC system than the faulty cell.

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