Semiconductor equipment

Abstract

To provide a semiconductor device that can suppress the deterioration in high-frequency characteristic.SOLUTION: A semiconductor device includes: a semiconductor chip 10 including a substrate 11, a transistor 60 provided on an upper surface of the substrate and including an input electrode to which a high-frequency signal is input, an output electrode from which the high-frequency signal is output, and a reference potential electrode to which a reference potential is supplied, and a metal pattern 20 provided on the upper surface of the substrate and electrically connected to the reference potential electrode; a first capacitor 30 provided on the metal pattern and including a first lower electrode electrically connected to the metal pattern, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer; and a first bonding wire 42 that electrically connects the first upper electrode and a first electrode corresponding to one of the input electrode and the output electrode.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] It is known to mount a semiconductor chip provided with transistors on a base and an impedance matching circuit element for impedance matching, and electrically connect the transistors and the impedance matching circuit element using bonding wires (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When heat generated in a transistor is released to a base through a substrate of a semiconductor chip, the thermal resistance of the substrate can be lowered by increasing the planar area of the substrate. However, when the area of the substrate is increased, the bonding wires connecting the transistor and the impedance matching circuit element become longer. As a result, it becomes difficult to perform impedance matching by the impedance matching circuit element, and the high-frequency characteristics may deteriorate.

[0005] This disclosure has been made in view of the above problems, and an object thereof is to suppress deterioration of high-frequency characteristics.

Means for Solving the Problems

[0006] One embodiment of the present disclosure is a semiconductor chip comprising: a substrate; a transistor provided on the upper surface of the substrate and having an input electrode into which a high-frequency signal is input, an output electrode into which a high-frequency signal is output, and a reference potential electrode to which a reference potential is supplied; a metal pattern provided on the upper surface of the substrate and electrically connected to the reference potential electrode; a first capacitor provided on the metal pattern and electrically connected to the metal pattern; a first dielectric layer provided on the first dielectric layer; and a first bonding wire electrically connecting the first upper electrode and a first electrode of either the input electrode or the output electrode. [Effects of the Invention]

[0007] According to this disclosure, the degradation of high-frequency characteristics can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a circuit diagram of the semiconductor device according to Example 1. [Figure 2] Figure 2 is a plan view of the semiconductor chip in Example 1. [Figure 3] Figure 3 is a cross-sectional view of AA in Figure 2. [Figure 4] Figure 4 is a plan view of the semiconductor device in Example 1. [Figure 5] Figure 5 is a cross-sectional view of AA in Figure 4. [Figure 6] Figure 6 is a cross-sectional view of BB in Figure 4. [Figure 7] Figure 7 is a plan view of the semiconductor device according to Comparative Example 1. [Figure 8] Figure 8 is a plan view of the semiconductor device according to Comparative Example 2. [Figure 9] Figure 9 is a plan view of the semiconductor chip in Example 2. [Figure 10] Figure 10 is a plan view of the semiconductor device in Example 2. [Figure 11]FIG. 11 is a cross-sectional view taken along the line A-A of FIG. 10. [Figure 12] FIG. 12 is a plan view of the semiconductor device in Example 3. [Figure 13] FIG. 13 is a cross-sectional view taken along the line A-A of FIG. 12. [Figure 14] FIG. 14 is a plan view of the semiconductor chip in Example 4. [Figure 15] FIG. 15 is a cross-sectional view taken along the line A-A of FIG. 14. [Figure 16A] FIG. 16A is a cross-sectional view showing a manufacturing method of the semiconductor chip in Example 4. [Figure 16B] FIG. 16B is a cross-sectional view showing a manufacturing method of the semiconductor chip in Example 4. [Figure 16C] FIG. 16C is a cross-sectional view showing a manufacturing method of the semiconductor chip in Example 4. [Figure 17] FIG. 17 is a plan view of the semiconductor device in Example 4. [Figure 18] FIG. 18 is a cross-sectional view taken along the line A-A of FIG. 17.

BEST MODE FOR CARRYING OUT THE INVENTION

[0009] [Details of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a substrate, a transistor provided on the upper surface of the substrate, having an input electrode to which a high-frequency signal is input, an output electrode from which a high-frequency signal is output, and a reference potential electrode to which a reference potential is supplied, a semiconductor chip provided on the upper surface of the substrate and having a metal pattern electrically connected to the reference potential electrode, a first lower electrode provided on the metal pattern and electrically connected to the metal pattern, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer. A first capacitor, and a first bonding wire that electrically connects the first upper electrode to a first electrode of either the input electrode or the output electrode. Thereby, deterioration of high-frequency characteristics can be suppressed. (2) In the above (1), the first lower electrode may be connected using a brazing material on the metal pattern. (3) In the above (1) or (2), the first dielectric layer may be a ceramic substrate or a semiconductor substrate. (4) In the above (1), the first lower electrode may be in contact with the metal pattern, and the first dielectric layer may be provided from a region on the upper surface of the metal pattern where the first lower electrode is not provided to between the first lower electrode and the first upper electrode. (5) In any one of the above (1) to (4), a second capacitor including a second lower electrode provided on the metal pattern and electrically connected to the metal pattern, a second dielectric layer provided on the second lower electrode, and a second upper electrode provided on the second dielectric layer, and a second bonding wire that electrically connects the second upper electrode and a second electrode other than the first electrode of the input electrode and the output electrode may be provided. (6) In any one of the above (1) to (5), a first signal terminal and a third bonding wire that electrically connects the first upper electrode and the first signal terminal may be provided. (7) In the above (5), a second signal terminal and 2nd signal terminal a fourth bonding wire that electrically connects the second upper electrode and may be provided. (8) In any one of the above (1) to (4), a conductive base on which the semiconductor chip is mounted and to which a reference potential is supplied, a second lower electrode provided on a region of the base other than the region where the semiconductor chip is mounted and electrically connected to the base, a second dielectric layer provided on the second lower electrode, and a second upper electrode provided on the second dielectric layer, and a second bonding wire that electrically connects the second upper electrode and a second electrode other than the first electrode of the input electrode and the output electrode may be provided. (9) In the above (5) or (8), the first electrode may be the input electrode, and the second bonding wire may be longer than the first bonding wire. (10) In any of (1) to (9) above, the semiconductor chip is mounted and a reference potential is supplied conductive The substrate is provided with a base, and the metal pattern and the reference potential electrode may be electrically connected to the base via via holes penetrating the substrate.

[0010] Specific examples of semiconductor devices according to embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to these examples, and all modifications within the meaning and scope of the claims are intended to be included.

[0011] [Example 1] Figure 1 is a circuit diagram of a semiconductor device according to Embodiment 1. As shown in Figure 1, the semiconductor device 100 includes a transistor 60, matching circuits 62 and 64. Transistor 60 is, for example, a FET (Field Effect Transistor) and includes a source S, a drain D, and a gate G. Matching circuit 62 is connected between the input terminal Tin and the gate G. In matching circuit 62, inductors L1 and L2 are connected in series between the input terminal Tin and the gate G. Capacitor C1 is shunt-connected to the node between inductors L1 and L2. Matching circuit 64 is connected between the output terminal Tout and the drain D. In matching circuit 64, inductors L3 and L4 are connected in series between the output terminal Tout and the drain D. Capacitor C2 is shunt-connected to the node between inductors L3 and L4.

[0012] Matching circuit 62 matches the impedance seen from input terminal Tin to matching circuit 62 with the impedance seen from matching circuit 62 to gate G. Matching circuit 64 matches the impedance seen from drain D to matching circuit 64 with the impedance seen from matching circuit 64 to output terminal Tout. The high-frequency signal input to input terminal Tin is amplified by transistor 60. The amplified high-frequency signal is output from the output terminal. The frequency of the high-frequency signal is, for example, 30 MHz to 300 GHz, and when semiconductor device 100 is used as a base station for mobile communications, the frequency of the high-frequency signal is, for example, 0.5 GHz to 10 GHz.

[0013] Figure 2 is a plan view of the semiconductor chip in Example 1. Figure 3 is a cross-sectional view AA of Figure 2. In Figure 2, the source electrode 14, drain electrode 16, gate electrode 18, and metal pattern 20 are shown using cross-hatching. The direction normal to the upper surface of the substrate 11 is the Z direction, the direction from the source electrode 14 to the drain electrode 16 is the X direction, and the extension direction of the drain electrode 16 is the Y direction.

[0014] As shown in Figures 2 and 3, the substrate 11 comprises a substrate 11a and a semiconductor layer 11b provided on the substrate 11a. An active region 12 is provided on the substrate 11. Regions other than the active region 12 are inactive regions in which the semiconductor layer 11b has been deactivated by ion implantation or the like. A source electrode 14, a drain electrode 16, a gate electrode 18, and a metal pattern 20 are provided on the upper surface of the substrate 11. The source electrode 14 and the gate electrode 18 are arranged alternately in the Y direction. The drain electrode 16 is provided in the + direction in the X direction of the source electrode 14 and the gate electrode 18. An active region 12 is provided between the source electrode 14 and the gate electrode 18 and the drain electrode 16. The active region 12 is provided with a plurality of source fingers, a plurality of drain fingers, and a plurality of gate fingers (not shown) extending in the X direction. The plurality of source fingers, a plurality of drain fingers, and a plurality of gate fingers are electrically connected and short-circuited to the source electrode 14, the drain electrode 16, and the gate electrode 18, respectively. The transistor 60 comprises an active region 12, a source electrode 14, a drain electrode 16, and a gate electrode 18. The source electrode 14, drain electrode 16, and gate electrode 18 correspond to the source S, drain D, and gate G, respectively.

[0015] A metal pattern 20 is provided in the negative direction in the X direction of the source electrode 14. The metal pattern 20 is electrically connected to and short-circuited with the source electrode 14. A metal layer 28 is provided on the lower surface of the substrate 11. A via hole 22 is provided so as to overlap with the metal pattern 20 when viewed from the Z direction. The via hole 22 penetrates the substrate 11. A metal layer 28a is provided on the inner surface of the via hole 22. Metal layers 28 and 28a are made of the same metal. The metal pattern 20 is electrically connected to and short-circuited with the metal layer 28 via the via hole 22.

[0016] If the semiconductor chip 10 is, for example, a nitride semiconductor chip, the substrate 11a is, for example, a silicon carbide (SiC) substrate, a diamond substrate, a silicon substrate, a gallium nitride (GaN) substrate, or a sapphire substrate. The semiconductor layer 11b includes, for example, a nitride semiconductor layer such as a GaN layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. If the transistor is a GaN HEMT (High Electron Mobility Transistor), the semiconductor layer 11b includes a GaN electron transport layer and an AlGaN barrier layer provided on the GaN electron transport layer. If the semiconductor device is, for example, a GaAs-based semiconductor device, the substrate 11a is, for example, a gallium arsenide (GaAs) substrate. The semiconductor layer 11b includes, for example, an arsenide semiconductor layer such as a GaAs layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer. The source electrode 14, drain electrode 16, gate electrode 18, metal pattern 20, and metal layers 28 and 28a include, for example, a gold layer.

[0017] Figure 4 is a plan view of the semiconductor device in Example 1. Figure 5 is a cross-sectional view AA of Figure 4. Figure 6 is a cross-sectional view BB of Figure 4. In Figure 4, the lid 54 is not shown. The source electrode 14, drain electrode 16, gate electrode 18, metal pattern 20, base 50, input pattern 45, and output pattern 46 are shown with cross-hatching. The direction normal to the upper surface of the base 50 is the Z direction, the direction from the input lead to the output lead is the X direction, and the direction intersecting the X and Z directions is the Y direction.

[0018] As shown in Figures 4 to 6, a semiconductor chip 10 and a capacitor 34 are mounted on a base 50. At least the upper surface of the base 50 is a conductive layer. An insulating frame 52 is mounted on the base 50 so as to surround the semiconductor chip 10 and the capacitor 34. The capacitor 34 comprises a dielectric layer 35 and upper electrodes 36 and lower electrodes 37 that sandwich the dielectric layer 35.

[0019] The base 50 and the metal layer 28 of the semiconductor chip 10 are joined by a conductive bonding layer 51. This electrically connects and short-circuits the base 50 and the metal layer 28. The base 50 and the lower electrode 37 of the capacitor 34 are joined by a conductive bonding layer 51. This electrically connects and short-circuits the base 50 and the lower electrode 37. The base 50 and the frame 52 are joined by a bonding layer 53.

[0020] A capacitor 30 is mounted on a metal pattern 20 of a semiconductor chip 10. The capacitor 30 comprises a dielectric layer 31 and upper and lower electrodes 32 and 33 that sandwich the dielectric layer 31. The metal pattern 20 and the lower electrode 33 are joined by a conductive junction layer 26. As a result, the metal pattern 20 and the lower electrode 33 are electrically connected and short-circuited.

[0021] In a plan view, an input pattern 45 and an output pattern 46, which are metal patterns, are provided at opposing positions on the frame 52. An input lead 47 and an output lead 48 are electrically connected to the input pattern 45 and the output pattern 46, respectively. A lid 54 is attached to the frame 52. The semiconductor chip 10 is sealed in a gas 56 such as air or an inert gas by the lid 54.

[0022] Bonding wire 41 electrically connects the input pattern 45 to the upper electrode 32 of the capacitor 30. Bonding wire 42 electrically connects the upper electrode 32 of the capacitor 30 to the gate electrode 18. Bonding wire 43 electrically connects the drain electrode 16 to the upper electrode 36 of the capacitor 34. Bonding wire 44 electrically connects the upper electrode 36 of the capacitor 34 to the output pattern 46.

[0023] Bonding wires 41 and 42 correspond to inductors L1 and L2 in Figure 1, respectively, and bonding wires 43 and 44 correspond to inductors L3 and L4 in Figure 1, respectively. Capacitors 30 and 34 correspond to capacitors C1 and C2 in Figure 1, respectively. A reference potential, such as ground potential, is supplied to the base 50, and the source electrode 14 receives the reference potential from the base 50 via the junction layer 51, metal layer 28, metal layer 28a, and metal pattern 20. The lower electrode 33 of capacitor 30 receives the reference potential from the base 50 via the junction layer 51, metal layer 28, metal layer 28a, metal pattern 20, and junction layer 26. The lower electrode 37 of capacitor 34 receives the reference potential from the base 50 via the junction layer 51.

[0024] The high-frequency signal is input to the gate electrode 18 via the input lead 47, input pattern 45, bonding wire 41, upper electrode 32, and bonding wire 42. The high-frequency signal amplified by transistor 60 is output to the output lead 48 via the drain electrode 16, bonding wire 43, upper electrode 36, bonding wire 44, and output pattern 46.

[0025] The base 50 is a metal layer, such as copper. The frame 52 is a ceramic insulator, such as alumina. The lid 54 is an insulator, such as ceramics, or a metal. The dielectric layers 31 and 35 are inorganic insulating layers, such as barium titanate, or semiconductor layers, such as silicon. The upper electrodes 32 and 36, the lower electrodes 33 and 37, the input pattern 45, and the output pattern 46 are metal layers, such as a gold layer. The bonding wires 41 to 44 are metal wires, such as gold wires. The input leads 47 and the output leads 48 are metal leads, such as Kovar.

[0026] The widths of the base 50 in the X and Y directions are, for example, 8 mm and 10 mm, respectively. The widths of the semiconductor chip 10 in the X and Y directions are, for example, 3.75 mm and 4.6 mm, respectively. The widths of the capacitors 30 and 34 in the X and Y directions are, for example, 0.9 mm and 3.5 mm, respectively. The widths of the input lead 47 and output lead 48 in the X and Y directions are, for example, 2.5 mm and 1.5 mm, respectively.

[0027] [Comparative Example 1] Figure 7 is a plan view of the semiconductor device according to Comparative Example 1. The base 50, input leads 47, and output leads 48 outside the frame 52 are not shown. As shown in Figure 7, in the semiconductor device 110 of Comparative Example 1, the capacitor 30 is not mounted on the semiconductor chip 10, but on the base 50. The semiconductor chip 10 is mounted on the capacitor 30 of the two capacitors 30 and 34. As a result, the bonding wire 42 is shorter than the bonding wire 43. This is because the gate input impedance of the FET is smaller than the drain output impedance, so when impedance matching occurs, the inductor L2 This is to make the inductance of [the component] smaller than the inductance of inductor L3.

[0028] To increase the output power of transistor 60, it is necessary to lower the thermal resistance of the substrate 11 and dissipate the heat generated in transistor 60 to the base 50. For example, when a silicon carbide substrate is used as substrate 11a, heat dissipation can be improved because silicon carbide has high thermal conductivity. To lower the thermal resistance of substrate 11, it is possible to increase the planar area of ​​the semiconductor chip 10.

[0029] [Comparative Example 2] Figure 8 is a plan view of the semiconductor device according to Comparative Example 2. The base 50, input leads 47, and output leads 48 outside the frame 52 are not shown. As shown in Figure 8, the semiconductor device 112 of Comparative Example 2 has a larger planar area of ​​the semiconductor chip 10 than Comparative Example 1. The transistor 60 is located near the center of the semiconductor chip 10 in the X direction. This is to reduce thermal resistance by conducting the heat of the transistor 60 symmetrically in the +X and -X directions. As a result, the distance between the capacitor 30 and the gate electrode 18 is increased. This makes the bonding wire 42 longer than in Comparative Example 1. The length of the bonding wire 42 is determined so that the matching circuit 62 functions. When the bonding wire 42 is longer, the inductance of the inductor L2 increases. This makes it difficult to match the input impedance of the input lead 47 with the input impedance of the gate electrode 18. Therefore, it may not be possible to obtain the desired high-frequency characteristics of the semiconductor device 112, and the high-frequency characteristics may deteriorate.

[0030] According to Example 1, the semiconductor chip 10 includes a transistor 60 provided on the upper surface of the substrate 11 and a metal pattern 20 electrically connected to a source electrode 14 provided on the upper surface of the substrate 11. The transistor 60 has a gate electrode 18 (input electrode) to which a high-frequency signal is input. High-frequency signal The device has a drain electrode 16 (output electrode) that outputs a current and a source electrode 14 (reference potential electrode) to which a reference potential is supplied. A capacitor 30 (first capacitor) is provided on the metal pattern 20. The capacitor 30 comprises a lower electrode 33 (first lower electrode) provided on the metal pattern 20 and electrically connected to the metal pattern 20, a dielectric layer 31 (first dielectric layer) provided on the lower electrode 33, and an upper electrode 32 (first upper electrode) provided on the dielectric layer 31.

[0031] As a result, a reference potential is supplied to the lower electrode 33 of the capacitor 30. Since the metal pattern 20 is provided on the substrate 11, the planar area of ​​the substrate 11 can be increased and the thermal resistance of the substrate 11 can be reduced. The bonding wire 42 (first bonding wire) electrically connects the upper electrode 32 and the gate electrode 18. As a result, a matching circuit 62 can be formed by the capacitor 30 and the bonding wire 42. Since the bonding wire 42 can be shortened, the matching circuit 62 can achieve the desired impedance matching. Therefore, the high-frequency characteristics of the semiconductor device 100 can be improved.

[0032] The lower electrode 33 of the capacitor 30 is joined to the metal pattern 20 using a brazing material. This allows the lower electrode 33 of the capacitor 30 to be set to a reference potential, and the capacitor 30 can be shunt-connected. The brazing material is, for example, solder made of tin, silver, copper, or gold, tin, or a metal paste such as silver paste.

[0033] The dielectric layer 31 of the capacitor 30 is a ceramic substrate. By using a material with a high relative permittivity (for example, a relative permittivity of 10 or more or 100 or more) as the material for the ceramic substrate, the capacitor 30 can be miniaturized. In addition, by using a material with low dielectric loss as the material for the ceramic substrate, losses can be reduced.

[0034] The dielectric layer 31 of the capacitor 30 may be a semiconductor substrate. The semiconductor substrate is, for example, a silicon substrate. By using a semiconductor substrate for the dielectric layer 31, passive elements other than the capacitor (e.g., resistors and inductors) can be integrated into the dielectric layer 31, resulting in an IPD (Integrated Preservative). Passive A device can be used. Thus, the capacitor 30 may be a capacitor provided on the IPD.

[0035] The bonding wire 41 (third bonding wire) electrically connects the upper electrode 32 of the capacitor 30 to the input pattern 45 (first signal terminal). This allows the bonding wires 41, 42 and the capacitor 30 to form a matching circuit 62. Note that the matching circuit 62 does not necessarily require an inductor L1.

[0036] The capacitor 34 (second capacitor) is provided on a region of the conductive base 50 other than the region on which the semiconductor chip 10 is mounted, and comprises a lower electrode 37 (second lower electrode) electrically connected to the base 50, a dielectric layer 35 (second dielectric layer) provided on the lower electrode 37, and an upper electrode 36 (second upper electrode) provided on the dielectric layer 35. The bonding wire 43 (second bonding wire) electrically connects the upper electrode 36 and the drain electrode 16. As a result, the capacitor 34 and the bonding wire 43 can form a matching circuit 64.

[0037] The bonding wire 44 (fourth bonding wire) electrically connects the upper electrode 36 of the capacitor 34 to the output pattern 46 (second signal terminal). This allows the bonding wires 43, 44 and the capacitor 34 to form a matching circuit 64. Note that the inductor L4 is not required to be provided in the matching circuit 64. The dielectric layer 35 of the capacitor 34 can be the same ceramic substrate or semiconductor substrate as the capacitor 30.

[0038] As shown in Figure 4, the length D2 of bonding wire 43 is longer than the length D1 of bonding wire 42. This allows the input impedance of the input lead 47 to be matched with the input impedance of the gate electrode 18, and the output impedance of the output lead 48 to be matched with the output impedance of the drain electrode 16. Note that lengths D1 and D2 are three-dimensional lengths, not planar lengths. Preferably, length D2 is 1.2 times or more, 1.5 times or more, and 10 times or less than length D1.

[0039] The metal pattern 20 and source electrode 14 are connected via via holes 22 that penetrate the substrate 11. conductive It is electrically connected to and short-circuited with the base 50. This allows a reference potential to be supplied to the metal pattern 20 and the source electrode 14.

[0040] In Figure 2, distance D3 is the distance in the X direction between the -X end of the gate electrode 18 and the -X side of the substrate 11, and distance D4 is the distance in the X direction between the +X end of the drain electrode 16 and the +X side of the substrate 11. From the viewpoint of conducting heat from the transistor 60 symmetrically in the +X and -X directions, distance D3 is preferably 0.5 times or more and 2 times or less than distance D4, and more preferably 2 / 3 times or more and 1.5 times or less.

[0041] [Example 2] Figure 9 is a plan view of the semiconductor chip in Embodiment 2. As shown in Figure 9, the semiconductor chip 10a has a metal pattern 20 which includes mounting areas 20a, 20b, and connection areas 20c and 20d. Mounting area 20a is provided between the transistor 60 and the -X side of the substrate 11, and mounting area 20b is provided between the transistor 60 and the +X side of the substrate 11. Connection area 20c is provided between the transistor 60 and the -Y side of the substrate 11. Connection area 20d is provided between the transistor 60 and the +Y side of the substrate 11. Connection areas 20c and 20d connect mounting areas 20a and 20b. As a result, mounting areas 20a and 20b are electrically short-circuited and at the same potential. Either connection area 20c or 20d may be omitted.

[0042] Figure 10 is a plan view of the semiconductor device in Example 2. Figure 11 is a cross-sectional view of AA in Figure 10. In Figure 10, the lid 54 is not shown.

[0043] As shown in Figures 10 and 11, in the semiconductor device 102 of Embodiment 2, the capacitor 30 is mounted on the mounting area 20a of the metal pattern 20. The capacitor 34 is mounted on the mounting area 20b of the metal pattern 20. The lower electrode 33 of the capacitor 30 is bonded to the mounting area 20a by a bonding layer 26, and the lower electrode 37 of the capacitor 34 is bonded to the mounting area 20b by a bonding layer 26. The bonding layer 26 is, for example, a brazing material. The bonding wire 43 electrically connects the drain electrode 16 and the upper electrode 36 of the capacitor 34, and the bonding wire 44 electrically connects the upper electrode 36 of the capacitor 34 and the output pattern 46. The other configurations are the same as in Embodiment 1 and will not be described.

[0044] According to Embodiment 2, the lower electrode 37 of the capacitor 34 is provided on the mounting area 20b of the metal pattern 20 and is electrically connected to the metal pattern 20. This supplies a reference potential to the lower electrode 37 of the capacitor 34. Since the mounting areas 20a and 20b of the metal pattern 20 are provided on the substrate 11, the planar area of ​​the substrate 11 can be increased and the thermal resistance of the substrate 11 can be reduced. The bonding wire 43 (second bonding wire) electrically connects the upper electrode 36 and the drain electrode 16. This allows the capacitor 34 and the bonding wire 43 to form a matching circuit 64.

[0045] The bonding wire 44 (fourth bonding wire) electrically connects the upper electrode 36 of the capacitor 34 to the output pattern 46 (second signal terminal). This allows the bonding wires 43, 44 and the capacitor 34 to form a matching circuit 64. Note that the matching circuit 64 does not necessarily need to have an inductor L4.

[0046] Example 1 describes an example in which capacitor 30 is mounted on the metal pattern 20 and capacitor 34 is not mounted on the semiconductor chip 10, while Example 2 describes an example in which capacitors 30 and 34 are mounted on the metal pattern 20. Capacitor 34 may be mounted on the metal pattern 20 and capacitor 30 may not be mounted on the semiconductor chip 10. Thus, the first electrode to which the first bonding wire is connected may be either the gate electrode or the drain electrode. The second electrode to which the second bonding wire is connected may be any second electrode other than the first electrode among the gate electrode and the drain electrode.

[0047] In the matching circuit 62 that matches the input impedance of the input electrode of transistor 60, the inductance of inductor L2 can often be small. Therefore, it is preferable that the first electrode to which the first bonding wire is connected is the input electrode.

[0048] [Example 3] Figure 12 is a plan view of the semiconductor device in Example 3. Figure 13 is a cross-sectional view AA of Figure 12. In Figure 12, the base 50 is shown through the sealing resin 55.

[0049] As shown in Figures 12 and 13, the semiconductor device 104 of Embodiment 3 does not have a frame 52 and a capacitor 34 on the base 50. The base 50, semiconductor chip 10, and capacitor 30 are sealed with a sealing resin 55. The sealing resin 55 is, for example, epoxy resin. A bonding wire 41 electrically connects the input lead 47, which is the first signal terminal, to the upper electrode 32 of the capacitor 30, and a bonding wire 43 electrically connects the drain electrode 16 to the output lead 48, which is the second signal terminal. The other configurations are the same as in Embodiment 1 and will not be described.

[0050] As in Example 3, the semiconductor chip 10 and capacitor 30 may be sealed with a sealing resin 55. Alternatively, the capacitor 34 may be omitted, and the drain electrode 16 and output lead 48 may be connected by a bonding wire 43. In this case, the bonding wire 43 forms part of the inductor L3 of the matching circuit 64, and the capacitor C2 and inductor L4 may be provided outside the semiconductor device 104. The semiconductor chip 10a of Example 2 may be used as the semiconductor chip 10 in Example 3. In this case, the capacitor 34 is built into the semiconductor device.

[0051] [Example 4] Figure 14 is a plan view of the semiconductor chip in Example 4. Figure 15 is a cross-sectional view of AA in Figure 14. As shown in Figures 14 and 15, in the semiconductor chip 10b, the lower electrode 33a is directly provided on the metal pattern 20, and the dielectric layer 31a is provided in a larger area than the lower electrode 33a in a plan view so as to cover the lower electrode 33a. The upper electrode 32a is provided on the dielectric layer 31a. The capacitor 30a comprises the lower electrode 33a, the dielectric layer 31a, and the upper electrode 32a. The lower electrode 33a and the upper electrode 32a are metal layers including, for example, a gold layer, and the dielectric layer 31a is, for example, a silicon nitride layer or a silicon oxide layer.

[0052] Figures 16A to 16C are cross-sectional views showing the manufacturing method of a semiconductor chip in Example 4. As shown in Figure 16A, a transistor 60 and a metal pattern 20 are formed on a substrate 11. As shown in Figure 16B, a lower electrode 33a is formed on the metal pattern 20. A dielectric layer 31a is formed on the substrate 11, covering the transistor 60, the metal pattern 20, and the lower electrode 33a, for example using the CVD (Chemical Vapor Deposition) method. An upper electrode 32a is formed on the dielectric layer 31a. As shown in Figure 16C, the dielectric layer 31a on the transistor 60 and other parts is removed, for example using the etching method. The lower surface of the substrate 11 is polished or ground to thin the substrate 11. Via holes 22 are formed through the substrate 11. Metal layers 28 and 28a are formed on the lower surface of the substrate 11 and on the inner surfaces of the via holes 22. The semiconductor chip 10b of Example 4 is thus formed.

[0053] Figure 17 is a plan view of the semiconductor device in Example 4. Figure 18 is a cross-sectional view AA of Figure 17. In Figure 17, the base 50 is shown through the sealing resin 55. As shown in Figures 17 and 18, the semiconductor device 106 of Example 4 has the semiconductor chip 10b shown in Figures 14 and 15 mounted on the base. The other configurations are the same as in Example 3 and will not be described.

[0054] As in Example 4, the capacitor 30a may be provided on the semiconductor chip 10b. That is, the lower electrode 33a (first lower electrode) is in contact with the metal pattern 20. The dielectric layer 31a (first dielectric layer) extends from the region on the upper surface of the metal pattern 20 where the lower electrode 33a is not provided to the lower electrode 33a and the upper electrode 32a ( 1st upper electrode ) may be provided between them. This makes it possible to reduce the step of mounting the capacitor 30 on the semiconductor chip 10b, as in Example 1.

[0055] As a package for encapsulating the semiconductor chip 10b, instead of using the encapsulating resin 55, a frame and lid, as in Example 1, may be used. Instead of the capacitor 34 having a ceramic substrate or semiconductor substrate as the dielectric layer 35, as in Example 2, a capacitor formed on the substrate 11 using a semiconductor process, such as capacitor 30a, may be provided on the semiconductor chip 10b.

[0056] In Examples 1 to 4, an FET was used as an example for transistor 60, but transistor 60 may be other than an FET, such as a bipolar transistor. When transistor 60 is an FET, and the input electrode is the gate electrode 18, the output electrode is the drain electrode 16, and the reference potential electrode is the source electrode 14, the inductance of the inductor L2 of the matching circuit 62 becomes smaller, and the bonding wire 42 is shortened. For this reason, capacitors 30 and 30a connected to the gate electrode 18 are provided on the metal pattern 20.

[0057] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims, not in the sense described above, and all modifications are intended to be in the sense and scope equivalent to the claims. [Explanation of Symbols]

[0058] 10, 10a, 10b semiconductor chips 11, 11a Substrate 11b Semiconductor layer 12 Active area 14 Source electrodes 16 Drain electrode 18 Guard gate 20 Metal Patterns 20a, 20b mounting area 20c, 20d connection area 22 Beer Hall 26, 51, 53 bonding layer 28, 28a metal layer 30, 30A, 34 capacitor 31, 31a, 35 Dielectric layer 32, 32a, 36 upper electrode 33, 33a, 37 bottom electrode 41, 42, 43, 44 Bonding wires 45 Input Patterns 46 output patterns 47 Input Leads 48 Output Leads 50 base 52 Frame 54 Lid 55 Sealing resin 56 Gases 60 transistors 62, 64 matching circuit 100, 102, 104, 106, 110, 112 Semiconductor equipment

Claims

1. A semiconductor chip comprising a substrate, a transistor provided on the upper surface of the substrate and having an input electrode into which a high-frequency signal is input, an output electrode into which a high-frequency signal is output, and a reference potential electrode to which a reference potential is supplied, and a metal pattern provided on the upper surface of the substrate and electrically connected to the reference potential electrode, A first capacitor comprising: a first lower electrode provided on the metal pattern and electrically connected to the metal pattern; a first dielectric layer provided on the first lower electrode; and a first upper electrode provided on the first dielectric layer. A first bonding wire electrically connects the first upper electrode and the first electrode of either the input electrode or the output electrode, A semiconductor device equipped with a semiconductor device.

2. The semiconductor device according to claim 1, wherein the first lower electrode is connected to the metal pattern using brazing material.

3. The semiconductor device according to claim 1 or claim 2, wherein the first dielectric layer is a ceramic substrate or a semiconductor substrate.

4. The semiconductor device according to claim 1, wherein the first lower electrode is in contact with the metal pattern, and the first dielectric layer is provided on the upper surface of the metal pattern from a region where the first lower electrode is not provided to the space between the first lower electrode and the first upper electrode.

5. A second capacitor comprising: a second lower electrode provided on the metal pattern and electrically connected to the metal pattern; a second dielectric layer provided on the second lower electrode; and a second upper electrode provided on the second dielectric layer; A second bonding wire electrically connects the second upper electrode and the input electrode and the second electrode other than the first electrode among the output electrodes, A semiconductor device according to any one of claims 1, 2, and 4, comprising:

6. First signal terminal and, A third bonding wire electrically connects the first upper electrode and the first signal terminal, A semiconductor device according to any one of claims 1, 2, and 4, comprising:

7. The second signal terminal and A fourth bonding wire electrically connects the second upper electrode and the second signal terminal, The semiconductor device according to claim 5, comprising:

8. The aforementioned semiconductor chip is mounted on a conductive base to which a reference potential is supplied, A second capacitor comprising: a second lower electrode provided on a region of the base other than the region on which the semiconductor chip is mounted and electrically connected to the base; a second dielectric layer provided on the second lower electrode; and a second upper electrode provided on the second dielectric layer; A second bonding wire electrically connects the second upper electrode and the input electrode and the second electrode other than the first electrode among the output electrodes, A semiconductor device according to any one of claims 1, 2, and 4, comprising:

9. The first electrode is the input electrode, The semiconductor device according to claim 5, wherein the second bonding wire is longer than the first bonding wire.

10. The aforementioned semiconductor chip is mounted on a conductive base to which a reference potential is supplied, The semiconductor device according to any one of claims 1, 2, and 4, wherein the metal pattern and the reference potential electrode are electrically connected to the base via via holes penetrating the substrate.

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