Display board, method for manufacturing the same, and display device.

Abstract

A display substrate and a display device are provided, in which each sub-pixel (300) of the display substrate (100) comprises a conductive light-shielding structure (122), a buffer layer (130) located on a side of the conductive light-shielding structure (122) facing away from a base substrate (110), a semiconductor layer (140) located on a side of the buffer layer (130) facing away from the conductive light-shielding structure (122), an interlayer insulating layer (170) located on a side of the semiconductor layer (140) facing away from the buffer layer (130), and a conductive layer (180) located on a side of the interlayer insulating layer (170) facing away from the semiconductor layer (140), the conductive layer having a conductive structure (181). The conductive light-shielding structure (122) includes a first body (1220) and a first recess (1224), the average thickness of the first recess (1224) in a direction perpendicular to the base substrate (110) is smaller than the thickness of the first body (1220) in a direction perpendicular to the base substrate (110), and the display substrate (100) further includes a first contact hole (251), the first contact hole (251) penetrates the interlayer insulating layer (170) and the buffer layer (130), and the conductive structure (181) is connected to the first recess (1224) through the first contact hole (251), thereby improving the electrical connection effect between the conductive structure and the conductive light-shielding structure.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202110039159.4 filed on January 13, 2021, and the entire content disclosed in the above Chinese patent application is incorporated herein by reference.

[0002] Embodiments of the present disclosure relate to a display substrate, a method for manufacturing the same, and a display device.

Background Art

[0003] With the continuous development of display technology, active matrix organic light-emitting diode display devices (AMOLEDs) have become the research hotspots and technology development directions of major manufacturers due to advantages such as a wide color gamut, high contrast, lightweight and thin design, self-emission, and a wide viewing angle.

[0004] Currently, active matrix organic light-emitting diode display devices (AMOLEDs) are widely applied to various electronic products, ranging from small electronic products such as smart bracelets, smart watches, smart phones, and tablet PCs to large electronic products such as notebook computers, desktop computers, and televisions. Therefore, the market demand for active matrix organic light-emitting diode display devices is also increasing.

Summary of the Invention

Means for Solving the Problems

[0005] Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device. The display substrate comprises a base substrate and a plurality of subpixels located on the base substrate, each of which comprises a conductive light-shielding structure located on the base substrate, a buffer layer located on the side of the conductive light-shielding structure away from the base substrate, a semiconductor layer located on the side of the buffer layer away from the conductive light-shielding structure, an interlayer insulating layer located on the side of the semiconductor layer away from the buffer layer, and a conductive layer located on the side of the interlayer insulating layer away from the semiconductor layer and comprising a conductive structure, the conductive light-shielding structure comprises a first body portion and a first recess, the display substrate further comprises a first contact hole, the first contact hole penetrates the interlayer insulating layer and the buffer layer, the conductive structure is electrically connected to the first recess via the first contact hole, the area of ​​the surface of the first recess adjacent to the conductive layer is larger than the orthographic area of ​​the first recess on the base substrate, and the average thickness of the first recess in the direction perpendicular to the base substrate is smaller than the average thickness of the first body portion in the direction perpendicular to the base substrate. As a result, by arranging the first recess in the conductive light-shielding structure, the display substrate can increase the contact area between the first drain and the conductive light-shielding structure, resulting in more sufficient contact, thereby reducing contact resistance and improving the electrical connection effect between the first drain and the conductive light-shielding structure.

[0006] At least one embodiment of the present disclosure provides a display substrate comprising a base substrate and a plurality of subpixels located on the base substrate, each of which comprises a conductive light-shielding structure located on the base substrate, a buffer layer located on the side of the conductive light-shielding structure away from the base substrate, a semiconductor layer located on the side of the buffer layer away from the conductive light-shielding structure, an interlayer insulating layer located on the side of the semiconductor layer away from the buffer layer, and a conductive layer located on the side of the interlayer insulating layer away from the semiconductor layer and comprising a conductive structure, wherein the conductive light-shielding structure comprises a first body portion and a first recess, the display substrate further comprises a first contact hole, the first contact hole penetrates the interlayer insulating layer and the buffer layer, the conductive structure is electrically connected to the first recess via the first contact hole, the area of ​​the surface of the first recess adjacent to the conductive layer is greater than the orthographic area of ​​the first recess on the base substrate, and the average thickness of the first recess in the direction perpendicular to the base substrate is less than the average thickness of the first body portion in the direction perpendicular to the base substrate.

[0007] For example, in a display substrate according to one embodiment of the present disclosure, the buffer layer comprises a first buffer portion, the side away from the base substrate is in contact with the conductive layer and the side closer to the base substrate is in contact with the conductive light-shielding structure, and a second buffer portion, the side away from the base substrate is in contact with the interlayer insulating layer and the side closer to the base substrate is in contact with the conductive light-shielding structure.

[0008] For example, in a display substrate according to one embodiment of the present disclosure, the first contact hole is provided with a side wall, the side wall comprises at least a first sub-side wall located in the interlayer insulating layer and a second sub-side wall located in the buffer layer, the angle between the first sub-side wall and the base substrate is a first gradient angle, the angle between the second sub-side wall and the base substrate is a second gradient angle, the first gradient angle is smaller than the second gradient angle, and the contact portion between the second sub-side wall and the first buffer portion is located between the first buffer portion and the second buffer portion.

[0009] For example, in a display substrate according to one embodiment of the present disclosure, the side wall of the first contact hole further comprises a third sub-side wall located in the first buffer portion, and the angle between the third sub-side wall and the base substrate is a third gradient angle, which is different from the first gradient angle, the second gradient angle, and the third gradient angle.

[0010] For example, in a display substrate according to one embodiment of the present disclosure, the ratio of the length of the first buffer portion to the average thickness of the first buffer portion along the radial direction of the first contact hole is greater than the ratio of the projected length of the first sub-sidewall on the base substrate to the average thickness of the interlayer insulating layer.

[0011] For example, in a display substrate according to one embodiment of the present disclosure, along the radial direction of the first contact hole, the ratio of the projected length of the first sub-sidewall on the base substrate to the average thickness of the interlayer insulating layer is greater than the ratio of the projected length of the second sub-sidewall on the base substrate to the average thickness of the buffer layer.

[0012] For example, in a display substrate according to one embodiment of the present disclosure, the second gradient angle is greater than the third gradient angle, and the first gradient angle is greater than the third gradient angle.

[0013] For example, in a display substrate according to one embodiment of the present disclosure, the size L of the first recess in the direction parallel to the base substrate in the orthographic projection on the base substrate satisfies the following formula.

number

[0014] For example, in a display substrate according to one embodiment of the present disclosure, the first recess includes a first edge portion in which the thickness in a direction perpendicular to the base substrate gradually decreases in the direction from the edge of the first recess toward the center of the first recess.

[0015] For example, in a display substrate according to one embodiment of the present disclosure, the first recess includes a first edge portion in which the fourth gradient angle of the surface adjacent to the conductive layer changes continuously in a direction perpendicular to the base substrate.

[0016] For example, in a display substrate according to one embodiment of the present disclosure, the surface of the first recess adjacent to the conductive structure is a continuous arc surface, or a combined surface formed by combining at least a portion of continuous arc surfaces and at least a portion of planes.

[0017] For example, in a display substrate according to one embodiment of the present disclosure, the first recess includes a first edge portion, and the fourth gradient angle α of the surface of the first edge portion adjacent to the conductive layer satisfies the following formula.

number

[0018] For example, in the display substrate according to one embodiment of the present disclosure, when k=2, the fourth gradient angle is in the range of 1-π / 18.

[0019] For example, in a display substrate according to one embodiment of the present disclosure, the first recess includes a first edge portion, and the fourth gradient angle α of the surface of the first edge portion adjacent to the conductive layer is smaller than the third gradient angle of the third sub-side wall, satisfying the following formula.

number

[0020] For example, a display substrate according to one embodiment of the present disclosure further comprises a planarization layer located on the side of the conductive layer away from the semiconductor layer and having an anode hole, and an extension located on the side of the planarization layer away from the semiconductor layer and comprising a light-emitting unit, a drive unit, and an extension connecting the light-emitting unit and the drive unit, wherein the drive unit is at least partially located within the anode hole, and in at least one of the subpixels, the orthographic projection of the first contact hole on the base substrate at least partially overlaps the orthographic projection of the drive unit on the base substrate, and the display substrate further comprises a power line located in the conductive layer and a sensing line located in the conductive layer, wherein the power line and the sensing line are in the first direction The subpixels are arranged in a direction and each extends in a second direction intersecting the first direction, and the plurality of subpixels comprises a first subpixel pair and a second subpixel pair, the first subpixel pair comprises two subpixels located on both sides of the power line, the second subpixel pair comprises two subpixels located on both sides of the sensing line, the first subpixel pair and the second subpixel pair are arranged alternately in the first direction, and in two of the subpixels of the second subpixel pair, the orthographic projection of the anode hole and the first recess on the base substrate has a first overlapping region, the area of ​​the first overlapping region is smaller than the area of ​​the orthographic projection of the first contact hole on the base substrate.

[0021] For example, in a display substrate according to one embodiment of the present disclosure, the anode further includes a recessed structure at the edge position of the anode hole, the recess direction of which is toward the conductive light-shielding structure.

[0022] For example, in a display substrate according to one embodiment of the present disclosure, the size of the first recess in the direction parallel to the base substrate in orthographic projection on the base substrate is in the range of 5 to 10 microns.

[0023] For example, in the display substrate according to an embodiment of the present disclosure, the orthographic projection of the first contact hole on the base substrate at least partially overlaps with the orthographic projection of the first recess on the base substrate.

[0024] For example, in the display substrate according to an embodiment of the present disclosure, each of the sub-pixels includes a pixel driving circuit, the pixel driving circuit includes a first thin film transistor, and the conductive structure is the first drain of the first thin film transistor.

[0025] For example, in the display substrate according to an embodiment of the present disclosure, the first thin film transistor is located in the semiconductor layer and further includes a first active layer including a first channel region, and a first source region and a first drain region located on both sides of the first channel region, and a first source located in the conductive layer, the display substrate further includes a first via hole and a second via hole, the first via hole and the second via hole are located in the interlayer insulating layer, the first source is connected to the first source region through the first via hole, and the first drain is connected to the first drain region through the second via hole.

[0026] For example, in the display substrate according to an embodiment of the present disclosure, the conductive light-shielding structure further includes a first insulating portion whose orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate and whose orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the first source region on the base substrate.

[0027] For example, in the display substrate according to an embodiment of the present disclosure, the first insulating portion includes a first hollow portion filled with the material of the buffer layer.

[0028] For example, in the display substrate according to an embodiment of the present disclosure, the first hollow portion includes a first hollow ring, and both the inner part and the outer part of the first hollow ring are made of the material of the conductive light-shielding structure.

[0029] For example, in a display substrate according to one embodiment of the present disclosure, the first insulating portion is an oxidized portion.

[0030] For example, a display substrate according to one embodiment of the present disclosure further comprises a gate insulating layer located between the semiconductor layer and the interlayer insulating layer, a gate layer located between the gate insulating layer and the interlayer insulating layer, a passivation layer located on the side of the conductive layer away from the base substrate, a color filter layer located on the side of the passivation layer away from the conductive layer and comprising at least three different colored optical filters, and an anode layer, wherein the planarization layer is located on the side of the color filter layer away from the passivation layer, the anode layer is located on the side of the planarization layer away from the color filter layer, and the anode is located in the anode layer.

[0031] For example, a display substrate according to one embodiment of the present disclosure further comprises a power connection line disposed in the same layer as the conductive light-shielding structure, the power connection line comprising a second main body and a plurality of power recesses, the average thickness of each power recess in the direction perpendicular to the base substrate is smaller than the average thickness of the second main body in the direction perpendicular to the base substrate, the area of ​​the surface of each power recess adjacent to the conductive layer is larger than the area of ​​the orthographic projection of the power recess on the base substrate, and the orthographic projection of at least one of the plurality of power recesses on the base substrate at least partially overlaps with the orthographic projection of the optical filter of the color filter layer on the base substrate.

[0032] For example, in a display substrate according to one embodiment of the present disclosure, the power supply recess is provided with a second edge portion in which the thickness in a direction perpendicular to the base substrate is continuously and gradually reduced in the direction from the edge of the power supply recess toward the center of the power supply recess.

[0033] For example, in a display substrate according to one embodiment of the present disclosure, the power supply recess includes a second edge portion in which the fifth gradient angle of the surface adjacent to the conductive layer changes continuously in a direction perpendicular to the base substrate.

[0034] For example, in a display substrate according to one embodiment of the present disclosure, the display substrate further comprises power contact holes, the power contact holes are located in the interlayer insulating layer and the buffer layer, and the orthographic projection of the power contact holes on the base substrate at least partially overlaps with the orthographic projection of the power recesses on the base substrate.

[0035] For example, in a display substrate according to one embodiment of the present disclosure, the buffer layer comprises a third buffer portion located within the power contact hole, with the side away from the base substrate in contact with the power connection line and the side closer to the base substrate in contact with the conductive light-shielding structure, and a fourth buffer portion located away from the center of the power recess of the third buffer portion, the side wall of the power contact hole comprises a fourth sub-side wall located in the interlayer insulating layer and a fifth sub-side wall located in the fourth buffer portion, the angle between the fourth sub-side wall and the base substrate is a sixth gradient angle, the angle between the fifth sub-side wall and the base substrate is a seventh gradient angle, the sixth gradient angle is smaller than the seventh gradient angle, and the contact portion between the fifth sub-side wall and the third buffer portion is located between the third buffer portion and the fourth buffer portion.

[0036] For example, in a display board according to one embodiment of the present disclosure, the side wall of the power supply contact hole further comprises a sixth sub-side wall located in the third buffer portion, and the angle between the sixth sub-side wall and the base board is an eighth gradient angle, which is different from the sixth gradient angle, the seventh gradient angle, and the eighth gradient angle.

[0037] For example, in a display substrate according to one embodiment of the present disclosure, the seventh gradient angle is smaller than the second gradient angle.

[0038] For example, in a display substrate according to one embodiment of the present disclosure, the eighth gradient angle is greater than the third gradient angle.

[0039] For example, a display substrate according to one embodiment of the present disclosure further comprises a sensing connection line disposed in the same layer as the conductive light-shielding structure, the sensing connection line comprising a third body portion and a plurality of sensing recesses, wherein the average thickness of each sensing recess in the direction perpendicular to the base substrate is smaller than the average thickness of the third body portion in the direction perpendicular to the base substrate, the area of ​​the surface of each sensing recess adjacent to the conductive layer is larger than the area of ​​the orthographic projection of the sensing recess on the base substrate, and the orthographic projection of at least one of the plurality of sensing recesses on the base substrate at least partially overlaps with the orthographic projection of the optical filter of the color filter layer on the base substrate.

[0040] For example, in a display substrate according to one embodiment of the present disclosure, the sensing recess is provided with a third edge portion in which the thickness in a direction perpendicular to the base substrate is continuously and gradually reduced in the direction from the edge of the sensing recess toward the center of the sensing recess.

[0041] For example, in a display substrate according to one embodiment of the present disclosure, the sensing recess includes a third edge portion in which the ninth gradient angle of the surface adjacent to the conductive layer changes continuously in a direction perpendicular to the base substrate.

[0042] For example, in a display substrate according to one embodiment of the present disclosure, the display substrate further comprises sensing contact holes, the sensing contact holes are located in the interlayer insulating layer and the buffer layer, and the orthographic projection of the sensing contact holes on the base substrate at least partially overlaps with the orthographic projection of the sensing recesses on the base substrate.

[0043] For example, in a display substrate according to one embodiment of the present disclosure, the buffer layer comprises a fifth buffer portion located within the sensing contact hole, with its side away from the base substrate in contact with the sensing connection line and its side closer to the base substrate in contact with the conductive light-shielding structure, and a sixth buffer portion located away from the center of the sensing recess of the fifth buffer portion, the side wall of the sensing contact hole comprises a seventh sub-side wall located in the interlayer insulating layer and an eighth sub-side wall located in the sixth buffer portion, the angle between the seventh sub-side wall and the base substrate is a tenth gradient angle, the angle between the eighth sub-side wall and the base substrate is an eleventh gradient angle, the tenth gradient angle is smaller than the eleventh gradient angle, and the contact portion between the eighth sub-side wall and the fifth buffer portion is located between the fifth buffer portion and the sixth buffer portion.

[0044] For example, in a display substrate according to one embodiment of the present disclosure, the buffer layer further comprises a ninth sub-sidewall located in the fifth buffer portion, and the angle between the ninth sub-sidewall and the base substrate is a twelfth gradient angle, which is different from the tenth gradient angle, the eleventh gradient angle, and the twelfth gradient angle.

[0045] For example, in a display substrate according to one embodiment of the present disclosure, the 11th gradient angle is smaller than the 2nd gradient angle.

[0046] For example, in a display substrate according to one embodiment of the present disclosure, the 12th gradient angle is greater than the 3rd gradient angle.

[0047] For example, in a display substrate according to one embodiment of the present disclosure, each subpixel includes a drive region and a light-emitting region, the conductive light-shielding structure is located in the drive region, the drive portion of the anode is located in the drive region, and the light-emitting portion of the anode is located in the light-emitting region.

[0048] For example, a display substrate according to one embodiment of the present disclosure further comprises a first gate line located in the gate layer and extending in a first direction, a second gate line located in the gate layer and extending in a first direction, and a data line located in the conductive layer and extending in a second direction, wherein the power line extends in a second direction, the sensing line extends in a second direction, and the plurality of subpixels are arranged in an array along the first and second directions to form a plurality of subpixel rows arranged in the second direction and a plurality of subpixel columns arranged in the first direction, wherein in each subpixel row, the first gate line is located between the drive region and the light-emitting region, the second gate line is located between two adjacent subpixel rows, the power line is located between two adjacent subpixel columns, the sensing line is located between two adjacent subpixel columns, and the data line is located between two adjacent subpixel columns.

[0049] For example, in a display substrate according to one embodiment of the present disclosure, each subpixel comprises a pixel driving circuit, the pixel driving circuit comprises a first thin-film transistor, the first thin-film transistor comprises a first gate, a first source, and a first drain, the conductive structure is the first drain of the first thin-film transistor, the pixel driving circuit further comprises a second thin-film transistor and a third thin-film transistor, the second thin-film transistor comprises a second gate, a second source, and a second drain, the third thin-film transistor comprises a third gate, a third source, and a third drain, the semiconductor layer further comprises a conductive block, and the first source of the first thin-film transistor is the conductive structure. The second thin-film transistor is connected to a source line, the second source is connected to the data line, the second gate is connected to the first gate line, and the second drain is connected to the first gate of the first thin-film transistor and the conductive block, respectively. The third thin-film transistor is connected to a second gate line, the third source is connected to the sensing line, and the third drain is connected to the first drain of the first thin-film transistor. The conductive light-shielding structure, the first drain connected to the conductive light-shielding structure, and the conductive block located between the conductive light-shielding structure and the first drain form a storage capacitor.

[0050] For example, in a display substrate according to one embodiment of the present disclosure, the first source of the first thin-film transistor is connected to the power line via a first connection part, the second source of the second thin-film transistor is connected to the data line via a second connection part, the first connection part is arranged on the same layer as the power line, and the second connection part is arranged on the same layer as the data line.

[0051] For example, in a display board according to one embodiment of the present disclosure, the direction from the first source to the first drain intersects the extension direction of the first connection portion, and the direction from the second source to the second drain intersects the extension direction of the second connection portion.

[0052] For example, in a display substrate according to one embodiment of the present disclosure, the plurality of subpixels comprises at least a first color subpixel, a second color subpixel, a third color subpixel, and a fourth color subpixel, and in each row of subpixels, the first color subpixel, the second color subpixel, the third color subpixel, and the fourth color subpixel are sequentially arranged along the first direction to form a subpixel group, and the power line is located between the second color subpixel and the third color subpixel in the subpixel group.

[0053] For example, in a display substrate according to one embodiment of the present disclosure, the display substrate further comprises power connection lines arranged in the same layer as the conductive light-shielding structure.

[0054] For example, in a display substrate according to one embodiment of the present disclosure, the display substrate further comprises a second contact hole, a third contact hole, and a fourth contact hole, wherein the second, third, and fourth contact holes are located in the interlayer insulating layer and the buffer layer, and in the subpixel group, the power line is connected to the power connection line via the second contact hole, the first source of the second color subpixel is connected to the same layer as the power line, the first source of the third color subpixel is connected to the same layer as the power line, the first source of the first color subpixel is connected to the power connection line via the third contact hole, and the first source of the fourth color subpixel is connected to the power connection line via the fourth contact hole.

[0055] For example, in a display board according to one embodiment of the present disclosure, the power connection line comprises a second main body, a second recess, a third recess, and a fourth recess, wherein the orthographic projection of the second recess on the base substrate at least partially overlaps with the orthographic projection of the second contact hole on the base substrate, the orthographic projection of the third recess on the base substrate at least partially overlaps with the orthographic projection of the third contact hole on the base substrate, the orthographic projection of the fourth recess on the base substrate at least partially overlaps with the orthographic projection of the fourth contact hole on the base substrate, the thickness of the second recess, the third recess, and the fourth recess in the direction perpendicular to the base substrate is all smaller than the thickness of the second main body in the direction perpendicular to the base substrate, the area of ​​the surface of the second recess adjacent to the power line is larger than the area of ​​the orthographic projection of the second recess on the base substrate, the area of ​​the surface of the third recess away from the base substrate is larger than the area of ​​the orthographic projection of the third recess on the base substrate, and the area of ​​the surface of the fourth recess away from the base substrate is larger than the area of ​​the orthographic projection of the fourth recess on the base substrate.

[0056] For example, in a display substrate according to one embodiment of the present disclosure, the orthographic projection of at least one of the second recess, the third recess, and the fourth recess on the base substrate at least partially overlaps with the orthographic projection of the optical filter of the color filter layer on the base substrate.

[0057] For example, in a display substrate according to one embodiment of the present disclosure, the second color subpixel is provided with a first color filter, the third color subpixel is provided with a second color filter, and the fourth color subpixel is provided with a third color filter, and in the subpixel group, the orthographic projection of at least one of the first color filter and the second color filter on the base substrate at least partially overlaps with the orthographic projection of the second recess on the base substrate, and the orthographic projection of the third color filter on the base substrate at least partially overlaps with the orthographic projection of the fourth recess on the base substrate.

[0058] For example, in a display substrate according to one embodiment of the present disclosure, the sensing line is located between two adjacent sub-pixel groups in the first direction, the two adjacent sub-pixel groups in the first direction comprise a first sub-pixel group and a second sub-pixel group, the display substrate further comprises a sensing connection line, a fifth contact hole, a sixth contact hole, a seventh contact hole, an eighth contact hole, and a ninth contact hole, the sensing connection line is arranged in the same layer as the conductive light-shielding structure, the fifth contact hole, the sixth contact hole, the seventh contact hole, the eighth contact hole, and the ninth contact hole are located in the interlayer insulating layer and the buffer layer, In two adjacent subpixel groups, the sensing line is connected to the sensing connection line via the fifth contact hole; the third source of the third color subpixel in the first subpixel group is connected to the sensing connection line via the sixth contact hole; the third source of the fourth color subpixel in the first subpixel group is connected to the sensing connection line via the seventh contact hole; the third source of the first color subpixel in the first subpixel group is connected to the sensing connection line via the eighth contact hole; and the third source of the second color subpixel in the second subpixel group is connected to the sensing connection line via the ninth contact hole.

[0059] For example, in a display board according to one embodiment of the present disclosure, the sensing connection line comprises a third main body, a fifth recess, a sixth recess, a seventh recess, an eighth recess, and a ninth recess, wherein the orthographic projection of the fifth recess on the base board at least partially overlaps with the orthographic projection of the fifth contact hole on the base board, the orthographic projection of the sixth recess on the base board at least partially overlaps with the orthographic projection of the sixth contact hole on the base board, the orthographic projection of the seventh recess on the base board at least partially overlaps with the orthographic projection of the seventh contact hole on the base board, the orthographic projection of the eighth recess on the base board at least partially overlaps with the orthographic projection of the eighth contact hole on the base board, and the orthographic projection of the ninth recess on the base board at least overlaps with the orthographic projection of the ninth contact hole on the base board at They partially overlap, and the thickness of the fifth recess, sixth recess, seventh recess, eighth recess and ninth recess in the direction perpendicular to the base substrate is all smaller than the thickness of the third main body in the direction perpendicular to the base substrate. The area of ​​the fifth recess adjacent to the sensing line is larger than the orthographic area of ​​the fifth recess on the base substrate, the area of ​​the sixth recess away from the base substrate is larger than the orthographic area of ​​the sixth recess on the base substrate, the area of ​​the seventh recess away from the base substrate is larger than the orthographic area of ​​the seventh recess on the base substrate, the area of ​​the eighth recess away from the base substrate is larger than the orthographic area of ​​the eighth recess on the base substrate, and the area of ​​the ninth recess away from the base substrate is larger than the orthographic area of ​​the ninth recess on the base substrate.

[0060] For example, in a display substrate according to one embodiment of the present disclosure, the orthographic projection of at least one of the fifth recess, the sixth recess, the seventh recess, the eighth recess, and the ninth recess on the base substrate at least partially overlaps with the orthographic projection of the optical filter of the color filter layer on the base substrate.

[0061] For example, in a display substrate according to one embodiment of the present disclosure, in the second direction, the sensing connection line is located on the side of the second gate line away from the first gate line, the orthographic projection of the second color filter in the first subpixel group on the base substrate at least partially overlaps with the orthographic projection of the sixth recess in the first subpixel group adjacent to it in the second direction, the orthographic projection of the third color filter in the first subpixel group on the base substrate at least partially overlaps with the orthographic projection of the seventh recess adjacent to it in the second direction, and the orthographic projection of the first color filter in the second subpixel group on the base substrate at least partially overlaps with the orthographic projection of the ninth recess adjacent to it in the second direction.

[0062] For example, in a display substrate according to one embodiment of the present disclosure, in the subpixel group, the orthographic projection of the first color filter on the base substrate at least partially overlaps with the orthographic projection of the power connection line on the base substrate, the orthographic projection of the second color filter on the base substrate at least partially overlaps with the orthographic projection of the power connection line on the base substrate and the orthographic projection of the first gate line on the base substrate, respectively, and the orthographic projection of the third color filter on the base substrate at least partially overlaps with the orthographic projection of the power connection line on the base substrate.

[0063] For example, in a display substrate according to one embodiment of the present disclosure, in the subpixel group, the orthographic projection of the first color filter on the base substrate at least partially overlaps with the orthographic projection of the sensing connection line on the base substrate, the orthographic projection of the second color filter on the base substrate at least partially overlaps with the orthographic projection of the sensing connection line on the base substrate, and the orthographic projection of the third color filter on the base substrate at least partially overlaps with the orthographic projection of the sensing connection line on the base substrate.

[0064] For example, in a display board according to one embodiment of the present disclosure, the data lines include a first data line, a second data line, a third data line, and a fourth data line, and in the subpixel group, the first data line and the second data line are located between the first color subpixel and the second color subpixel, the first data line is connected to the second source of the first color subpixel, the second data line is connected to the second source of the second color subpixel, the third data line and the fourth data line are located between the third color subpixel and the fourth color subpixel, the third data line is connected to the second source of the third color subpixel, and the fourth data line is connected to the second source of the fourth color subpixel.

[0065] For example, in a display substrate according to one embodiment of the present disclosure, in the subpixel group, the orthographic projection of the first color filter on the base substrate at least partially overlaps with the orthographic projection of the second data line on the base substrate, the orthographic projection of the second color filter on the base substrate at least partially overlaps with the orthographic projection of the third data line on the base substrate, and the orthographic projection of the third color filter on the base substrate at least partially overlaps with the orthographic projection of the fourth data line on the base substrate.

[0066] For example, in a display substrate according to one embodiment of the present disclosure, the first thin-film transistor further comprises a first active layer located in the semiconductor layer and having a first channel region, and a first source region and a first drain region located on both sides of the first channel region, the first gate located in the gate layer, the orthographic projection of the first gate on the base substrate at least partially overlapping with the orthographic projection of the first channel region on the base substrate, the first source and the first drain both located in the conductive layer, the display substrate further comprises a first via hole and a second via hole, the first via hole and the second via hole are located in the interlayer insulating layer, the first source is connected to the first source region via the first via hole, and the first drain is connected to the first drain region via the second via hole.

[0067] For example, in a display substrate according to one embodiment of the present disclosure, the orthographic projection of the first channel region on the base substrate is within the orthographic projection of the first main body portion on the base substrate.

[0068] For example, in a display substrate according to one embodiment of the present disclosure, the display substrate further comprises a fourth via hole located in an interlayer insulating layer, the second drain is connected to the conductive block via the fourth via hole, and the conductive light-shielding structure further comprises a second insulating portion whose orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the fourth via hole on the base substrate.

[0069] For example, in a display substrate according to one embodiment of the present disclosure, the second insulating portion includes a second hollow portion filled with the material of the buffer layer.

[0070] For example, in a display substrate according to one embodiment of the present disclosure, the second hollow portion comprises a second hollow ring, and both the inner and outer portions of the second hollow ring are made of the conductive light-shielding material.

[0071] For example, in a display substrate according to one embodiment of the present disclosure, the second insulating portion is an oxidized portion.

[0072] For example, in a display substrate according to one embodiment of the present disclosure, the orthographic projection shapes of the first via hole and the fourth via hole on the base substrate are both anisotropic patterns and have a long side.

[0073] For example, in a display substrate according to one embodiment of the present disclosure, in the subpixel group, the long side of the first via hole of the second color subpixel and the long side of the first via hole of the third color subpixel both extend along the first direction, and the long side of the first via hole of the first color subpixel and the long side of the first via hole of the fourth color subpixel both extend along the second direction.

[0074] For example, in a display substrate according to one embodiment of the present disclosure, in the subpixel group, the long side of the fourth via hole of the second color subpixel and the long side of the fourth via hole of the third color subpixel both extend along the second direction, and the long side of the fourth via hole of the first color subpixel and the long side of the fourth via hole of the fourth color subpixel both extend along the first direction.

[0075] For example, in a display substrate according to one embodiment of the present disclosure, in the subpixel group, the center of the fourth via hole of the first color subpixel, the center of the fourth via hole of the second color subpixel, the center of the fourth via hole of the third color subpixel, and the center of the fourth via hole of the fourth color subpixel are offset in the second direction, the centers of the fourth via hole of the first color subpixel and the center of the fourth via hole of the fourth color subpixel lie on a first virtual line, and the centers of the fourth via hole of the second color subpixel and the center of the fourth via hole of the third color subpixel lie on a second virtual line parallel to the first virtual line.

[0076] For example, in a display substrate according to one embodiment of the present disclosure, the material of the conductive light-shielding structure is selected from one or more of molybdenum and titanium, and the material of the conductive layer is selected from one or more of copper, molybdenum and titanium.

[0077] For example, in a display substrate according to one embodiment of the present disclosure, the conductive layer comprises a first submetal layer and a second submetal layer laminated perpendicular to the base substrate, wherein the material of the first submetal layer is copper and the material of the second submetal layer is a molybdenum-titanium alloy.

[0078] For example, in a display substrate according to one embodiment of the present disclosure, the material of the gate layer is selected from one or more of copper, molybdenum, and titanium.

[0079] For example, in a display substrate according to one embodiment of the present disclosure, the thickness of the conductive light-shielding structure in the direction perpendicular to the base substrate is in the range of 90-120 nanometers, and the thickness of the conductive layer in the direction perpendicular to the base substrate is in the range of 200-600 nanometers.

[0080] At least one embodiment of the present disclosure further provides a display device comprising a display substrate as described in any one of the above paragraphs.

[0081] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, comprising the steps of: forming a conductive light-shielding material layer on a base substrate; patterning the conductive light-shielding material layer to form a conductive light-shielding structure; forming a buffer layer on the side of the conductive light-shielding structure away from the base substrate; forming a semiconductor layer on the side of the buffer layer away from the conductive light-shielding structure; forming an interlayer insulating layer on the side of the semiconductor layer away from the buffer layer; forming a first contact hole in the interlayer insulating layer and the buffer layer; and The method includes the step of forming a conductive layer on the side of the insulating layer away from the semiconductor layer, wherein the conductive layer comprises a conductive structure, the conductive light-shielding structure comprises a first body portion and a first recess, the average thickness of the first recess in the direction perpendicular to the base substrate is smaller than the average thickness of the first body portion in the direction perpendicular to the base substrate, the first contact hole penetrates the interlayer insulating layer and the buffer layer, the conductive structure is connected to the first recess via the first contact hole, and the area of ​​the surface of the first recess adjacent to the conductive layer is larger than the orthographic area of ​​the first recess on the base substrate.

[0082] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the step of forming a first contact hole in the interlayer insulating layer and the buffer layer includes the step of forming a first buffer portion and a second buffer portion in the buffer layer, wherein the side of the first buffer portion away from the base substrate is in contact with the conductive layer, the side of the first buffer portion closer to the base substrate is in contact with the conductive light-shielding structure, the side of the second buffer portion away from the base substrate is in contact with the interlayer insulating layer, and the side of the second buffer portion closer to the base substrate is in contact with the conductive light-shielding structure.

[0083] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the first contact hole is provided with a side wall, the side wall comprises at least a first sub-side wall located in the interlayer insulating layer and a second sub-side wall located in the buffer layer, the angle between the first sub-side wall and the base substrate is a first gradient angle, the angle between the second sub-side wall and the base substrate is a second gradient angle, the first gradient angle is smaller than the second gradient angle, and the contact portion between the second sub-side wall and the first buffer portion is located between the first buffer portion and the second buffer portion.

[0084] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the side wall of the first contact hole further comprises a third sub-side wall located in the first buffer portion, and the angle between the third sub-side wall and the base substrate is a third gradient angle, which is different from the first gradient angle, the second gradient angle, and the third gradient angle.

[0085] For example, a method for manufacturing a display substrate according to one embodiment of the present disclosure further includes the steps of forming a planar layer having an anode hole on the side of the conductive layer away from the interlayer insulating layer, and forming an anode layer on the side of the planar layer away from the conductive layer to form a plurality of subpixels on the base substrate, each subpixel having an anode, the anode having a light-emitting part, a drive part, and an extension part connecting the light-emitting part and the drive part, the drive part being at least partially located in the anode hole, and in at least one subpixel, the orthographic projection of the first contact hole on the base substrate at least partially overlaps with the orthographic projection of the drive part on the base substrate, and the display substrate having power lines located in the conductive layer and located in the conductive layer The device further comprises a sensing line, the power line and the sensing line are arranged in a first direction and both extend in a second direction intersecting the first direction, the plurality of subpixels comprises a first subpixel pair and a second subpixel pair, the first subpixel pair comprises two subpixels located on both sides of the power line, the second subpixel pair comprises two subpixels located on both sides of the sensing line, the first subpixel pair and the second subpixel pair are arranged alternately in the first direction, and in two of the subpixels of the second subpixel pair, the orthographic projection of the anode hole and the first recess on the base substrate has a first overlap region, the area of ​​the first overlap region is smaller than the area of ​​the orthographic projection of the first contact hole on the base substrate.

[0086] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the conductive layer further comprises a first source and a first drain, and the conductive structure is the first drain.

[0087] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the semiconductor layer comprises a first active layer having a first channel region and a first source region and a first drain region located on both sides of the first channel region, the manufacturing method further includes the step of forming a first contact hole in the interlayer insulating layer and the buffer layer, and forming a first via hole and a second via hole in the interlayer insulating layer, the first source being connected to the first source region via the first via hole, and the first drain being connected to the first drain region via the second via hole.

[0088] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the interlayer insulating layer and the buffer layer are patterned simultaneously by the same etching process to form the first via hole and the first contact hole.

[0089] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the interlayer insulating layer and the buffer layer are patterned by a halftone mask process to form the first via hole and the first contact hole.

[0090] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the step of patterning the interlayer insulating layer and the buffer layer by a halftone mask process to form the first via hole and the first contact hole is to form a first photoresist on the side of the interlayer insulating layer away from the base substrate, to expose and develop the first photoresist using the first halftone mask to form a first photoresist pattern comprising a first photoresist complete removal portion, a first photoresist partial removal portion and a first photoresist holding portion, and to etch the interlayer insulating layer using the first photoresist pattern as a mask. The method further includes the steps of removing the interlayer insulating layer corresponding to the first photoresist complete removal portion, ashing the first photoresist pattern to remove the first photoresist partial removal portion and thin the first photoresist holding portion to form a second photoresist pattern, and etching the buffer layer using the second photoresist pattern as a mask, wherein the orthographic projection of the first contact hole on the base substrate coincides with the orthographic projection of the first photoresist complete removal portion on the base substrate, and the orthographic projection of the first via hole on the base substrate coincides with the orthographic projection of the first photoresist partial removal portion on the base substrate.

[0091] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the conductive light-shielding structure further comprises a first insulating portion in which the orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate, and the orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the first source region on the base substrate.

[0092] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the first insulating portion includes a first hollow portion filled with the material of the buffer layer, and the step of patterning the conductive light-shielding material layer to form the conductive light-shielding structure includes the step of patterning the conductive light-shielding material layer by the same patterning process to form the first main body portion, the first recess and the first hollow portion.

[0093] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the step of patterning the conductive light-shielding material layer to form a conductive light-shielding structure includes the steps of forming a photoresist on the side of the conductive light-shielding structure away from the base substrate, exposing and developing the photoresist using a second halftone mask to form a third photoresist pattern having a second photoresist complete removal portion, a second photoresist partial removal portion, and a second photoresist holding portion, etching the conductive light-shielding material layer using the third photoresist pattern as a mask to remove the conductive light-shielding material layer corresponding to the second photoresist complete removal portion, a step of ashing the third photoresist pattern to remove the second photoresist partial removal portion and thin the second photoresist holding portion to form a fourth photoresist pattern, and etching the conductive light-shielding material layer using the fourth photoresist pattern as a mask, wherein the orthographic projection of the first main body portion on the base substrate overlaps with the orthographic projection of the second photoresist holding portion on the base substrate, and the orthographic projection of the first recess on the base substrate overlaps with the orthographic projection of the second photoresist partial removal portion on the base substrate.

[0094] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the first recess includes a first edge portion in which the thickness in a direction perpendicular to the base substrate gradually decreases in the direction from the edge of the first recess toward the center of the first recess.

[0095] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the first recess includes a first edge portion in which the fourth gradient angle of the surface adjacent to the conductive layer changes continuously in a direction perpendicular to the base substrate.

[0096] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the surface of the first recess adjacent to the conductive structure is a continuous arc surface, or a combined surface formed by combining at least a portion of continuous arc surfaces and at least a portion of flat surfaces.

[0097] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the first recess includes a first edge portion, and the fourth gradient angle α of the surface of the first edge portion adjacent to the conductive layer satisfies the following formula.

number

[0098] For example, in the method for manufacturing a display substrate according to one embodiment of the present disclosure, when k=2, the fourth gradient angle is in the range of 1-π / 18.

[0099] For example, in a method for manufacturing a display substrate according to one embodiment of the present disclosure, the size of the first recess in the direction parallel to the base substrate in orthographic projection on the base substrate is in the range of 5 to 10 microns. [Brief explanation of the drawing]

[0100] To more clearly illustrate the technical concepts of the embodiments of this disclosure, the drawings of the embodiments will be briefly described below, and it is clear that the drawings described below are not limiting to this disclosure, but only relate to some embodiments of this disclosure.

[0101] To more clearly illustrate the technical concepts of the embodiments of this disclosure, the drawings of the embodiments will be briefly described below, and it is clear that the drawings described below are not limiting to this disclosure, but only relate to some embodiments of this disclosure.

[0102] [Figure 1] Figure 1 is a schematic cross-sectional view of a display substrate using a top-gate type oxide thin-film transistor. [Figure 2A] Figure 2A is a schematic cross-sectional view of another display board. [Figure 2B] Figure 2B is a schematic cross-sectional view of the contact holes of the display board. [Figure 3] Figure 3 is a schematic cross-sectional view of a via hole in a display board. [Figure 4] Figure 4 is a schematic plan view of a display substrate according to one embodiment of the present disclosure. [Figure 5A] Figure 5A is a schematic cross-sectional view of a display substrate according to one embodiment of the present disclosure, shown along line AA' in Figure 4. [Figure 5B] Figure 5B is a schematic cross-sectional view of a display substrate according to one embodiment of the present disclosure, shown along the line BB' in Figure 4. [Figure 5C] Figure 5C is a schematic diagram of the light focusing effect of a recess in a display substrate according to one embodiment of the present disclosure. [Figure 5D] Figure 5D is a schematic diagram of an anode hole in a display substrate according to one embodiment of the present disclosure. [Figure 6A] Figure 6A is a schematic cross-sectional view of the first recess of a display substrate according to one embodiment of the present disclosure. [Figure 6B] Figure 6B is a schematic cross-sectional view of the first recess of a display substrate according to one embodiment of the present disclosure. [Figure 7A] Figure 7A is a schematic plan view of a pixel driving circuit of a display substrate according to one embodiment of the present disclosure. [Figure 7B] Figure 7B is a schematic plan view of a pixel driving circuit of a display substrate according to one embodiment of the present disclosure. [Figure 8] Figure 8 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to one embodiment of the present disclosure. [Figure 9] Figure 9 is a timing diagram of signals on each signal line of a pixel driving circuit of a display board according to one embodiment of the present disclosure. [Figure 10A] Figure 10A is a schematic plan view of a conductive light-shielding structure of a display substrate according to one embodiment of the present disclosure. [Figure 10B] Figure 10B is a schematic plan view of a conductive light-shielding structure of another display substrate according to one embodiment of the present disclosure. [Figure 10C] Figure 10C is a schematic plan view of a conductive light-shielding structure of another display substrate according to one embodiment of the present disclosure. [Figure 11A] Figure 11A is a schematic plan view of another display board according to one embodiment of the present disclosure. [Figure 11B] Figure 11B is a schematic diagram of the light focusing effect of a power supply recess or a sensing recess on a display board according to one embodiment of the present disclosure. [Figure 11C] Figure 11C is a schematic cross-sectional view of a power supply recess of a display board according to one embodiment of the present disclosure, in a direction perpendicular to the base board. [Figure 11D] Figure 11D is a schematic cross-sectional view of a sensing recess of a display substrate according to one embodiment of the present disclosure, in a direction perpendicular to the base substrate. [Figure 12] Figure 12 is a schematic plan view of another display substrate according to one embodiment of the present disclosure. [Figure 13] Figure 13 is a schematic cross-sectional view of the first drain of a display substrate according to one embodiment of the present disclosure. [Figure 14] Figure 14 is a schematic diagram of a display device according to one embodiment of the present disclosure. [Figure 15] Figure 15 is a flowchart of a method for manufacturing a display substrate according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0103] To further clarify the purpose, technical proposal and advantages of the embodiments of this disclosure, the technical proposal of the embodiments of this disclosure will be clearly and completely described below with reference to the drawings of the embodiments of this disclosure. Clearly, the embodiments described are a part of the embodiments of this disclosure, but not all of them. All other embodiments that a person skilled in the art can obtain without requiring any creative work based on the embodiments of this disclosure described are within the scope of this disclosure.

[0104] Unless otherwise defined, technical or scientific terms used in this disclosure have the general meanings that are understandable to those skilled in the art. The terms “First,” “Second,” and similar terms used in this disclosure do not indicate any order, number, or importance, but are merely used to distinguish different components. Similar terms such as “equip” or “include” mean that the element or component listed before the term includes the elements or components listed after the term, and their equivalents, and do not exclude other elements or components.

[0105] While typical liquid crystal display panels use amorphous silicon as their active layer, such thin-film transistors struggle to meet the driving requirements of self-emissive display devices that demand high-mobility current drive. Therefore, active-matrix organic light-emitting diode (AMOLED) displays generally require the use of thin-film transistors with high carrier mobility. Typically, small active-matrix AMOLED displays can use thin-film transistors with low-temperature polysilicon (LTPS) as the active layer, while larger active-matrix AMOLED displays can use thin-film transistors with oxide as the active layer.

[0106] Through research, the inventors of this invention have found that, compared to bottom-gate thin-film transistors, top-gate thin-film transistors have the characteristic of being short-channel, and by effectively increasing their on-current Ion, the display effect can be greatly improved and power consumption reduced. Furthermore, because the overlap area between the gate and source / drain of a top-gate thin-film transistor is small, the resulting parasitic capacitance is also small, and therefore the possibility of defects such as gate and source / drain short circuits occurring in top-gate thin-film transistors is also reduced.

[0107] Figure 1 is a schematic cross-sectional view of a display substrate using a top-gate oxide thin-film transistor. As shown in Figure 1, the display substrate 10 comprises a base substrate 11, a light-shielding layer 12, a buffer layer 13, an active layer 14, a gate insulating layer 15, a gate 16, an interlayer insulating layer 17, and a conductive layer 18. The manufacturing process of the display substrate 10 includes the steps of forming a light-shielding layer 12 on the base substrate 11, forming a buffer layer 13 on the side of the light-shielding layer 12 away from the base substrate 11, forming an oxide semiconductor layer on the side of the buffer layer 13 away from the base substrate 11, patterning the oxide semiconductor layer to form an active layer 14 and completing a conductor doping process in the non-channel region, forming a gate insulating layer 15 on the side of the active layer 14 away from the base substrate 11, and forming a gate 16 on the side of the gate insulating layer 15 away from the active layer 14. For example, the gate insulating layer 15 and the gate 16 can be manufactured in a single mask process by a self-alignment process. Alternatively, an interlayer insulating layer 17 may be formed on the side of the gate 16 away from the base substrate 11, and the display substrate on which the interlayer insulating layer 17 is formed may be etched, and via holes H1 and H2 may be formed in the interlayer insulating layer 17, and contact holes CNT may be formed collectively in the interlayer insulating layer 17 and the buffer layer 13 by etching in synchronization with H1 and H2. Alternatively, the buffer layer 13 and the interlayer insulating layer 17 may be sequentially etched during the manufacturing process of the array substrate to form nested contact holes CNT in the interlayer insulating layer 17 and the buffer layer 13. A conductive layer 18 may be formed on the side of the interlayer insulating layer 17 away from the base substrate 11, and the conductive layer 18 includes a source S and a drain D, the source S is connected to the source region of the active layer 14 via a first via hole H1, the drain D is connected to the drain region of the active layer 14 via a second via hole H2, and further connected to the light-shielding layer 12 via contact holes CNT.

[0108] As shown in Figure 1, drain D is connected to the drain region of the active layer 14 via a second via hole H2, and further connected to the light-shielding layer 12 via a contact hole CNT, so that the light-shielding layer 12 and drain D have the same potential, and drain D is also electrically connected to the anode 25. Figure 2A is a schematic cross-sectional view of another display substrate. As shown in Figure 2A, since the anode 25, drain D and light-shielding layer 12 have the same potential, the anode 25, drain D and light-shielding layer 12 can form a sandwich capacitor together with the electrode of the conductive layer 18 (which may not necessarily be drain D, but could be the drain of another thin-film transistor in the pixel driving circuit) and the conductive block 19 of the active layer.

[0109] In the above manufacturing process, for some via holes such as via hole H1 and via hole H2, only the interlayer insulating layer needs to be etched, while for other via holes such as contact hole CNT, at least two insulating layers, such as the interlayer insulating layer and the buffer layer, need to be etched. These two types of holes require different etching depths and different materials to be etched, and therefore, controlling the actual process of simultaneously forming these two types of holes is extremely difficult. Figure 2B is a schematic cross-sectional view of a contact hole in a display substrate. As shown in Figure 2B, the contact hole has different gradient angles in different film layers, reducing the contact area between the drain and the light-shielding layer. In the case shown in Figure 2B, the contact resistance between the drain and the light-shielding layer is high, making it prone to phenomena such as poor contact, thus significantly affecting the electrical connection effect. On the other hand, Figure 3 is a schematic cross-sectional view of a via hole in an array substrate. As shown in Figure 3, in some embodiments, the active layer itself is designed to be thin and prone to partial loss or removal by etching, so the via hole directly penetrates the active layer and buffer layer and contacts the light-shielding layer. In this case, the source and drain of the thin-film transistor are electrically connected via a light-shielding layer, so applying a voltage to the source will cause a bright spot defect.

[0110] In contrast, embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device. The display substrate comprises a base substrate and a plurality of subpixels located on the base substrate, each subpixel comprising a conductive light-shielding structure located on the base substrate, a buffer layer located on the side of the conductive light-shielding structure away from the base substrate, a semiconductor layer located on the side of the buffer layer away from the conductive light-shielding structure, an interlayer insulating layer located on the side of the semiconductor layer away from the buffer layer, and a conductive layer having a conductive structure located on the side of the interlayer insulating layer away from the semiconductor layer, the conductive light-shielding structure comprises a first body portion and a first recess, the average thickness of the first recess in the direction perpendicular to the base substrate is smaller than the average thickness of the first body portion in the direction perpendicular to the base substrate, the display substrate further comprises a first contact hole, the first contact hole penetrates the interlayer insulating layer and the buffer layer, the conductive structure is electrically connected to the first recess via the first contact hole, and the area of ​​the surface of the first recess adjacent to the conductive layer is larger than the orthographic area of ​​the first recess on the base substrate. As a result, by arranging the first recess in the conductive light-shielding structure of the display substrate, the contact area between the first drain and the conductive light-shielding structure is increased, resulting in more sufficient contact, which reduces contact resistance and improves the electrical connection effect between the first drain and the conductive light-shielding structure.

[0111] The display substrate, its manufacturing method, and display device according to the embodiments of this disclosure will be described in detail below with reference to the drawings.

[0112] One embodiment of the present disclosure provides a display substrate. Figure 4 is a schematic plan view of a display substrate according to one embodiment of the present disclosure. Figure 5A is a schematic cross-sectional view of the display substrate according to one embodiment of the present disclosure along line AA' in Figure 4. Figure 5B is a schematic cross-sectional view of the display substrate according to one embodiment of the present disclosure along line BB' in Figure 4. Figure 5C is a schematic diagram of the light focusing effect of the recess in the display substrate according to one embodiment of the present disclosure. Figure 5D is a schematic diagram of the anode hole in the display substrate according to one embodiment of the present disclosure. Note that Figure 4 is a plan view from the anode layer of the display substrate to the base substrate of the display substrate.

[0113] As shown in Figures 4 and 5A, the display substrate 100 comprises a base substrate 110 and a plurality of subpixels 300 located on the base substrate 110, each subpixel 300 comprising a conductive light-shielding structure 122, a buffer layer 130, a semiconductor layer 140, an interlayer insulating layer 170, and a conductive layer 180. The conductive light-shielding structure 122 is located on the base substrate 110, the buffer layer 130 is located on the side of the conductive light-shielding structure 122 away from the base substrate 110, the semiconductor layer 140 is located on the side of the buffer layer 130 away from the conductive light-shielding structure 122, the interlayer insulating layer 170 is located on the side of the semiconductor layer 140 away from the buffer layer 130, and the conductive layer 180 is located on the side of the interlayer insulating layer 170 away from the semiconductor layer 140, and the conductive layer 180 comprises a conductive structure 181, for example, the conductive structure 181 may be a first drain 1841. For example, the buffer layer 130 has the effect of insulating the conductive light-shielding structure 122 from the semiconductor layer 140, while the buffer layer 130 further covers defects or burrs on the base substrate 110, thereby improving the quality of the semiconductor layer 120 formed on the buffer layer 130.

[0114] As shown in Figures 4 and 5A, the conductive light-shielding structure 122 comprises a first main body portion 1220 and a first recess 1224, wherein the average thickness of the first recess 1224 in the direction perpendicular to the base substrate 110 is smaller than the average thickness of the first main body portion 1220 in the direction perpendicular to the base substrate 110. The display substrate 100 further comprises a first contact hole 251, which penetrates the interlayer insulating layer 170 and the buffer layer 130, and the conductive structure 181 is connected to the first recess 1224 via the first contact hole 251, wherein the area of ​​the surface of the first recess 1224 adjacent to the conductive layer 180 is larger than the orthographic projection area of ​​the first recess 1224 on the base substrate 110.

[0115] In the display substrate according to the embodiment of the present disclosure, the conductive light-shielding structure comprises a first main body and a first recess, and the conductive structure is connected to the first recess via a first contact hole. Because the first recess is recessed in the conductive light-shielding structure, the area of ​​the surface of the first recess adjacent to the first drain is larger than the area of ​​the first recess as orthogonal projection on the base substrate. As a result, the display substrate can increase the contact area between the first drain and the conductive light-shielding structure, and by making the contact more sufficient, the contact resistance can be reduced, the electrical connection effect between the first drain and the conductive light-shielding structure can be improved, and the charge and discharge efficiency of the capacitor formed by the conductive structure can be effectively improved.

[0116] In some examples, as shown in Figures 4 and 5A, each subpixel 300 further comprises a planarization layer 210 located on the side of the conductive layer 180 away from the semiconductor layer 140 and having an anode hole 263, and an anode 225 located on the side of the planarization layer 210 away from the semiconductor layer 140 and having a light-emitting portion 225A, a drive portion 225B, and an extension portion 225C connecting the light-emitting portion 225A and the drive portion 225B, wherein the drive portion 225B is at least partially located within the anode hole 263. In each subpixel 300, the orthographic projection of the first contact hole 251 on the base substrate 110 at least partially overlaps the orthographic projection of the drive portion 225B on the base substrate 110. As a result, by positioning the drive unit 225B of the anode 225 above the first contact hole 251 and positioning the drive unit 225 above the first recess 1224, the first recess 1224 can be thinned to reduce its light-shielding ability, while the drive unit 225B of the anode 225 can block light that passes through the first recess 1224. Furthermore, by positioning the drive unit 225 of the anode 225 and increasing the area of ​​the anode 225, the capacitance value of the sandwich capacitor composed of anodes can be increased.

[0117] In some examples, as shown in Figures 4 and 5A, the display substrate 100 further comprises power lines 186 located in the conductive layer 180 and sensing lines 187 located in the conductive layer 180, and a plurality of subpixels 300 comprising a first subpixel pair 360A and a second subpixel pair 360B, the first subpixel pair 360A comprising two subpixels 300 located on either side of the power line 186, the second subpixel pair 360B comprising two subpixels 300 located on either side of the sensing line 187, the first subpixel pair 360A and the second subpixel pair 360B are arranged alternately, and in two subpixels 300 of the second subpixel pair 360B, the orthographic projection of the anode hole 263 and the first recess 1224 on the base substrate 110 has a first overlap region 410, the area of ​​the first overlap region 410 is smaller than the area of ​​the orthographic projection of the first contact hole 251 on the base substrate 110. The power line 186 and the sensing line 187 are arranged in a first direction and both extend along a second direction intersecting the first direction. As a result, in the two subpixels 300 of the second subpixel pair 360B, the anode hole 263 and the first recess 1224 have a first overlapping region 410, and therefore, when the first recess 1224 is thinned to reduce light shielding, the anode 225 at the position of the anode hole 263 has a curved interface, thereby focusing the light and avoiding the effect of light transmitted through the first recess 1224 on normal display.

[0118] In some examples, as shown in Figure 5D, the anode 225 further includes a recessed structure 2258 at the edge of the anode hole 263, with the recess direction oriented toward the conductive light-shielding structure 122. This allows the recessed structure to reflect light transmitted through the first recess when the first recess 1224 is thinned to reduce light-shielding performance, since it has at least two inclined surfaces. Furthermore, the recessed structure itself is a microstructure, and it further scatters light transmitted through the first recess, thereby further avoiding the influence of light transmitted through the first recess 1224 on normal display. Note that the edge position of the anode hole refers to the boundary between the anode hole and the surface of the planarization layer that is separated from the semiconductor layer.

[0119] For example, the conductive structure 181 may be the first drain 1841 of the conductive layer 180, and the first drain 1841 may be the drain of the first thin-film transistor of the pixel driving circuit of the subpixel 300.

[0120] In some examples, the material of the conductive light-shielding structure 122 may be selected from one or more of molybdenum and titanium, and the material of the conductive layer 180 may be selected from one or more of copper, molybdenum, and titanium. For example, the conductive layer 180 may be a multilayer structure in which a copper layer is located on top and a molybdenum-titanium mixture is located on the bottom, in which case the molybdenum-titanium mixture located on the bottom can prevent the diffusion of the copper material located on top and avoid affecting the electrical connection properties of the signal line. Of course, the embodiments of this disclosure include, but are not limited to, the conductive light-shielding structure and the first drain may be manufactured from other materials.

[0121] In some examples, the thickness of the conductive light-shielding structure perpendicular to the base substrate is in the range of 90-120 nanometers, and the thickness of the conductive layer perpendicular to the base substrate is in the range of 200-600 nanometers.

[0122] In some examples, the semiconductor layer material may be an oxide semiconductor such as indium gallium zinc oxide (IGZO). This results in high carrier mobility for the thin-film transistors in the pixel driving circuit of the array substrate.

[0123] In some examples, the interlayer insulating layer may be made from one or two different materials and manufactured by deposition using processes at different temperatures. For example, the material of the interlayer insulating layer may be selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0124] In some examples, the buffer layer material may also be selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride. Note that the buffer layer and the interlayer insulating layer typically use different materials, and even if the elemental composition of the buffer layer and the interlayer insulating layer is the same, the proportions of these elements will differ.

[0125] For example, the total thickness of the interlayer insulating layer is in the range of 350-600 nanometers. For example, the total thickness of the interlayer insulating layer may be 400 nanometers.

[0126] In some examples, as shown in Figures 4 and 5A, the first recess 1224 includes a first edge portion 12240 in which the thickness in the direction perpendicular to the base substrate 110 decreases continuously and gradually from the edge of the first recess 1224 toward the center of the first recess 1224. The average thickness of the first recess 1224 in the direction perpendicular to the base substrate is smaller than the average thickness of the first main body in the direction perpendicular to the base substrate, which may affect the light shielding properties of the first recess. However, in the display substrate according to this example, since the thickness of the first edge portion or the entire first recess in the direction perpendicular to the base substrate decreases continuously and gradually, the surface of the conductive structure away from the base substrate at the location of the first recess is convex, and this convex surface has the function of focusing light. If light can pass through the first recess, this convex surface can focus the light, thereby preventing a portion of the ambient light from being reflected into the substrate without control, and thus avoiding the influence of ambient light on the normal display of the display substrate. Furthermore, the "center of the first recess" refers to the center of the planar shape of the orthographic projection of the first recess on the base substrate. If the orthographic projection of the first recess on the base substrate has a regular shape, the center may also be the geometric center of the planar shape. If the orthographic projection of the first recess on the base substrate has an irregular shape, the center may also be the center of the longest straight line between two points on the planar shape. Additionally, the "edge of the first recess" may be the edge of the orthographic projection of the first recess on the base substrate.

[0127] For example, as shown in Figure 5C, the surface of the conductive structure 181 that is separated from the base substrate 110 at the location of the first recess 1224 is a convex surface, and this convex surface has the function of focusing light. If light can pass through the first recess, this convex surface can focus the light, thereby preventing a portion of the ambient light from being reflected into the substrate without control, and thus avoiding the influence of ambient light on the normal display of the display substrate.

[0128] In some examples, as shown in Figures 4 and 5A, the fourth gradient angle of at least the portion of the first recess 122 adjacent to the edge, for example, the surface of the first edge portion 12240 adjacent to the conductive layer 180, changes continuously in a direction perpendicular to the base substrate 110. This allows light to pass through the first recess, but the first recess prevents light from passing through the entire display substrate and affecting the display effect of the light-emitting area by allowing the convex surface of the conductive structure located at the position of the first recess, away from the base substrate, to focus the light.

[0129] In some examples, as shown in Figures 4 and 5A, the surface of the first recess 1224 adjacent to a conductive structure such as the first drain 1841 is a continuous arcuate surface or a combined surface formed by combining at least some continuous arcuate surfaces and at least some planes. The continuous arcuate surface or the combined surface formed by combining at least some continuous arcuate surfaces and at least some planes can focus light, thereby preventing the light from passing through the entire display substrate and being observed by the user, even if light can pass through the first recess. Of course, embodiments of this disclosure include, but are not limited to, the surface of the first recess adjacent to the first drain may also be a curved surface.

[0130] In some examples, as shown in Figures 4 and 5A, the orthographic projection of the first contact hole 251 on the base substrate 110 overlaps at least partially with the orthographic projection of the first recess 1224 on the base substrate 110. Thereafter, a conductive structure 181 of the conductive layer 180, for example, a first drain 1841, can be connected to the first recess 1224 via the first contact hole 251.

[0131] In some examples, as shown in Figure 4, the projected shape of the entire first recess 1224 on the base substrate 110 may be isotropic, such as circular, or anisotropic, such as square, rectangular, elliptical, or racetrack-shaped, and the embodiments of this disclosure are not limited thereto.

[0132] Figure 6A is a schematic cross-sectional view of the first recess of a display substrate according to one embodiment of the present disclosure. Figure 6B is a schematic cross-sectional view of the first recess of a display substrate according to one embodiment of the present disclosure. As shown in Figures 6A and 6B, the first recess 1224 includes a first edge portion 1224, and the fourth gradient angle α of the surface of the first edge portion 12240 adjacent to the conductive layer 180 satisfies the following formula.

number

[0133] In some examples, the gradient angle α at each position on the surface adjacent to the first drain 1841 of the first recess 1224 is in the range of 1-π / 18. For example, the gradient angle α at each position on the surface adjacent to the first drain 1841 of the first recess 1224 is in the range of 1-π / 36.

[0134] In some examples, as shown in Figures 6A and 6B, the size of the first recess 1224 in the orthographic projection parallel to the base substrate 110 is in the range of 5–10 microns. That is, the width of the first recess 1224 is in the range of 5–10 microns.

[0135] For example, as shown in Figures 6A and 6B, the size of the first recess 1224 in the direction parallel to the base substrate 110 in orthographic projection is 7.8 microns.

[0136] In some examples, as shown in Figures 6A and 6B, the buffer layer 130 comprises a first buffer portion 131, the side away from the base substrate 110 being in contact with the conductive layer 180 and the side closer to the base substrate 110 being in contact with the conductive light-shielding structure 122, and a second buffer portion 132, the side away from the base substrate 110 being in contact with the interlayer insulating layer 170 and the side closer to the base substrate 110 being in contact with the conductive light-shielding structure 122. As a result, when the conductive structure 181 is deposited in the first contact hole 251, the first buffer portion 131 supports a part of the conductive structure, preventing disconnection defects due to excessive steps or excessive gradient angles of the conductive structure. This results in a high yield for the display substrate.

[0137] For example, the first buffer portion 131 is located within the first contact hole 251 and is positioned in contact with the conductive light-shielding structure 122, while the second buffer portion 132 is located on the side of the first buffer portion 131 away from the center of the first recess 1224.

[0138] In some examples, as shown in Figures 6A and 6B, the sidewall of the first contact hole 251 comprises at least a first sub-sidewall 2512 located in the interlayer insulating layer 170 and a second sub-sidewall 2514 located in the buffer layer 130, the angle between the first sub-sidewall 2512 and the base substrate 110 is a first gradient angle β, the angle between the second sub-sidewall 2514 and the base substrate 110 is a second gradient angle γ, the first gradient angle β is smaller than the second gradient angle γ, and the contact portion between the second sub-sidewall 2514 and the first buffer portion 131 is located between the first buffer portion 131 and the second buffer portion 132. In this display substrate, since the materials of the buffer layer and the interlayer insulating layer are different, their etching efficiencies by the etching solution also differ, and as a result, the gradient angles of the first sub-sidewall and the second sub-sidewall tend to differ. Furthermore, because the above-mentioned sub-sidewalls may not actually be smooth planes due to process conditions and other reasons, the gradient angle between each sub-sidewall and the base substrate may be the angle between the line connecting a plurality of points arranged at equal intervals in the cross-section of each sub-sidewall and the base substrate.

[0139] In some examples, as shown in Figures 6A and 6B, the side wall of the first contact hole 251 further comprises a third sub-side wall 2516 located in the first buffer portion 131, and the angle between the third sub-side wall 2516 and the base substrate 110 forms a third gradient angle, which is different from the first gradient angle β, the second gradient angle γ, and the third gradient angle θ.

[0140] For example, the second gradient angle γ is greater than the third gradient angle θ, and the first gradient angle β is greater than the third gradient angle θ.

[0141] In some examples, as shown in Figures 6A and 6B, the ratio of the length of the first buffer portion 131 to the average thickness of the first buffer portion 131 along the radial direction of the first contact hole 251 is greater than the ratio of the projected length of the first sub-sidewall 2512 on the base substrate 110 to the average thickness of the interlayer insulating layer 170.

[0142] In some cases, as shown in Figures 6A and 6B, the ratio of the projected length of the first sub-sidewall 2512 on the base substrate 110 to the average thickness of the interlayer insulating layer 170 along the radial direction of the first contact hole 251 is greater than the ratio of the projected length of the second sub-sidewall 2514 on the base substrate 110 to the average thickness of the buffer layer 130.

[0143] For example, as shown in Figures 6A and 6B, the sidewall of the first contact hole 251 comprises a first sub-sidewall 2512 located in the interlayer insulating layer 170, a second sub-sidewall 2514 located in the first buffer portion 131, and a third sub-sidewall 2516 located in the second buffer portion 132. The first sub-sidewall 2512 is connected to the second sub-sidewall 2514, and the second sub-sidewall 2514 is connected to the third sub-sidewall 2516. The first gradient angle β of the first sub-sidewall 2512 and the second gradient angle γ of the second sub-sidewall 2514 are different from the third gradient angle θ of the third sub-sidewall 2516. In this display substrate, since the materials of the buffer layer and the interlayer insulating layer are different, their etching efficiencies by the etching solution are also different, and as a result, the gradient angles of the first sub-sidewall and the second sub-sidewall tend to differ.

[0144] For example, by manufacturing the buffer layer by depositing it in a process at different temperatures, the buffer layer can have different densities within it, and the first and second buffer portions can be formed. Of course, the embodiments of this disclosure include, but are not limited to, the first and second buffer portions may be manufactured by other suitable methods.

[0145] In some examples, as shown in Figures 6A and 6B, the first gradient angle β of the first sub-sidewall 2512 is smaller than the second gradient angle γ of the second sub-sidewall 2514, the second gradient angle γ of the second sub-sidewall 2514 is larger than the third gradient angle θ of the third sub-sidewall 2516, and the first gradient angle β of the first sub-sidewall 2512 is larger than the third gradient angle θ of the third sub-sidewall 2516. In other words, the second gradient angle γ is larger than the first gradient angle β, and the first gradient angle β is larger than the third gradient angle θ.

[0146] For example, the fourth gradient angle α is smaller than the third gradient angle θ of the third sub-side wall.

[0147] For example, as shown in Figures 6A and 6B, the first gradient angle β of the first sub-side wall 2512 is in the range of 45-75 degrees, the second gradient angle γ of the second sub-side wall 2514 is in the range of 75-90 degrees, and the third gradient angle θ of the third sub-side wall 2516 is in the range of 3-15 degrees.

[0148] For example, as shown in Figures 6A and 6B, the size of the third sub-sidewall 2516 in the direction parallel to the base substrate 110 in orthographic projection is in the range of 0.2-1 micron.

[0149] For example, the size of the third sub-sidewall 2516 in the direction parallel to the base substrate 110 in orthographic projection is 0.5 microns.

[0150] In some examples, as shown in Figures 6A and 6B, the size L of the first recess 1224 in the direction parallel to the base substrate 110 in orthographic projection on the base substrate 110 satisfies the following equation.

number

[0151] For example, the size L of the first recess 1224 in the direction parallel to the base substrate 110 in orthographic projection on the base substrate 110 satisfies the following equation.

number

[0152] In some examples, as shown in Figures 6A and 6B, the first recess 1224 includes a first edge portion 12240, and the fourth gradient angle α of the surface of the first edge portion 12240 adjacent to the conductive layer 180 is smaller than the third gradient angle of the third sub-sidewall 2516, satisfying the following equation.

number

[0153] In some examples, as shown in Figures 4 and 5A, the display substrate 100 further comprises a gate insulating layer 150 and a gate layer 160, where the gate insulating layer 150 is located on the side of the semiconductor layer 140 away from the base substrate 110, and the gate layer 160 is located between the gate insulating layer 150 and the interlayer insulating layer 170. As a result, the pixel driving circuit of the display substrate 100 uses a top-gate thin-film transistor, has short-channel characteristics, effectively increases its on-current Ion, thereby significantly improving the display effect and reducing power consumption.

[0154] In some examples, as shown in Figures 4 and 5A, the display substrate 100 further comprises a passivation layer 190, a color filter layer 200, a planarization layer 210, and an anode layer 220, wherein the passivation layer 190 is located on the side of the conductive layer 180 away from the base substrate 110, the color filter layer 200 is located on the side of the passivation layer 190 away from the conductive layer 180, and comprises at least three different color optical filters 350, the planarization layer 210 is located on the side of the color filter layer 200 away from the passivation layer 190, and the anode layer 220 is located on the side of the planarization layer 210 away from the color filter layer 200.

[0155] Figure 7A is a schematic plan view of a pixel driving circuit of a display substrate according to one embodiment of the present disclosure. Figure 7B is a schematic plan view of a pixel driving circuit of a display substrate according to one embodiment of the present disclosure. As shown in Figures 4, 5A, 5B, 7A, and 7B, each subpixel 300 is provided with a pixel driving circuit 320, the pixel driving circuit 320 is provided with a first thin-film transistor T1, the first thin-film transistor T1 further comprises a first active layer 141, a first gate 161, a first source 1821, and the first drain 1841, the first active layer 141 is located in the semiconductor layer 140 and comprises a first channel region 141C, and a first source region 141S and a first drain region 141D located on both sides of the first channel region 141C, the first gate 161 is located in the gate layer 160 and the orthographic projection of the first gate 161 on the base substrate 110 at least partially overlaps with the orthographic projection of the first channel region 141C on the base substrate 110, and the first source 1821 and the first drain 1841 are both located in the conductive layer 180.

[0156] In some examples, the material of the gate layer 160 may be selected from one or more of copper, molybdenum, and titanium. For example, the gate layer 160 may be a multilayer structure in which a copper layer is located on top and a molybdenum-titanium mixture is located on the bottom, in which case the molybdenum-titanium mixture located on the bottom can prevent the diffusion of the copper material located on top and avoid affecting the electrical connection properties of the signal line. Of course, the embodiments of this disclosure include, but are not limited to, the first and second gates may also be made of other materials.

[0157] For example, the gate layer may be a single-layer or multi-layer structure, and the embodiments of this disclosure are not limited thereto.

[0158] In some examples, as shown in Figures 5A, 7A, and 7B, the display substrate 100 further comprises a first via hole 261 and a second via hole 262, the first via hole 261 and the second via hole 262 located within the interlayer insulating layer 170, the first source 1821 connected to the first source region 141S via the first via hole 261, and the first drain 1841 connected to the first drain region 141D via the second via hole 262. Thus, the first gate, first active layer, first source, and first drain can constitute the first thin-film transistor. The first thin-film transistor may be a top-gate type thin-film transistor, which has the characteristics of a short channel and can effectively increase its on-current Ion, thereby greatly improving the display effect and reducing power consumption.

[0159] In some examples, as shown in Figures 5B, 7A, and 7B, the second thin-film transistor T2 further comprises a second active layer 142, a second gate 162, a second source 1822, and a second drain 1842, wherein the second active layer 142 is located in the semiconductor layer 140 and comprises a second channel region 142C, and a second source region 142S and a second drain region 142D located on either side of the second channel region 142C, the second gate 162 is located in the gate layer 160 and the orthographic projection of the second gate 162 on the base substrate 110 at least partially overlaps the orthographic projection of the second channel region 142C on the base substrate 110, and the second source 1822 and the second drain 1842 are both located in the conductive layer 180. The second source 1822 is connected to the second source region 142S via a via hole H3 in the interlayer insulating layer 170, and the second drain 1842 is connected to the second drain region 142D via a via hole H4 in the interlayer insulating layer 170. Thus, the second gate, second active layer, second source, and second drain can constitute the second thin-film transistor. The second thin-film transistor may be a top-gate type thin-film transistor, which has the characteristics of a short channel, effectively increasing its on-current Ion, thereby greatly improving the display effect and reducing power consumption.

[0160] In some examples, as shown in Figures 5B, 7A, and 7B, the third thin-film transistor T3 further comprises a third active layer 143, a third gate 163, a third source 1823, and a third drain 1843, wherein the third active layer 143 is located in the semiconductor layer 140 and comprises a third channel region 143C, and a third source region 143S and a third drain region 143D located on either side of the third channel region 143C, the third gate 163 is located in the gate layer 160 and the orthographic projection of the third gate 163 on the base substrate 110 at least partially overlaps with the orthographic projection of the third channel region 143C on the base substrate 110, and the third source 1823 and third drain 1843 are both located in the conductive layer 180. The third source 1823 is connected to the third source region 143S via a via hole H5 in the interlayer insulating layer 170, and the third drain 1843 is connected to the third drain region 143D via a via hole H6 in the interlayer insulating layer 170. Thus, the third gate, third active layer, third source, and third drain can constitute the third thin-film transistor. The third thin-film transistor may be a top-gate type thin-film transistor, which has the characteristics of a short channel, effectively increasing its on-current Ion, thereby greatly improving the display effect and reducing power consumption.

[0161] In some examples, as shown in Figures 4, 5A, 5B, 7A, and 7B, the anode holes 263 can penetrate the passivation layer 190 and the planarization layer 210, and the anode 225 is connected to the first drain 1841 via the anode holes 263 in the passivation layer 190 and the planarization layer 210. This allows the display substrate to emit light by applying a drive current to the anode using a first thin-film transistor, thereby driving the light-emitting layer corresponding to the anode.

[0162] In some examples, the first via hole 261, the second via hole 262, the first contact hole 251, and the anode hole 263 are arranged sequentially, as shown in Figures 7A and 7B.

[0163] For example, the orthographic projection shapes of the first via hole 261, the second via hole 262, the first contact hole 251, and the anode hole 263 on the base substrate 110 may be isotropic shapes such as circles, or anisotropic shapes such as rectangles, ellipses, or racetrack shapes, and the embodiments of this disclosure are not limited thereto. Furthermore, the specific orthographic projection shapes of the first via hole, the second via hole, the first contact hole, and the third via hole on the base substrate can be adjusted at each position by adjusting the extension direction of the long or short side of the hole according to the local actual space constraints of the display substrate layout.

[0164] In some examples, as shown in Figures 4, 5A, 5B, 7A, and 7B, the pixel driving circuit 320 further comprises a second thin-film transistor T2 and a third thin-film transistor T3, the second thin-film transistor T2 comprising a second gate 162, a second source 1822, and a second drain 1842, and the third thin-film transistor T3 comprising a third gate 163, a third source 1823, and a third drain 1843. The semiconductor layer 140 further comprises a conductive block 147.

[0165] Figure 8 is an equivalent circuit diagram of a pixel driving circuit for a display substrate according to one embodiment of the present disclosure. As shown in Figures 7A, 7B and 8, the first source 1821 of the first thin-film transistor T1 is connected to the power line 186, the second thin-film transistor T2 has its second source 1822 connected to the data line 185 and its second gate 162 connected to the first gate line 165. For example, the portion of the first gate line 165 that overlaps with the second channel region 142C of the second active layer 142 of the second thin-film transistor T2 is the second gate 162, and its second drain 1842 is connected to the first gate 161 and the conductor block 147 of the first thin-film transistor T1, respectively, the third thin-film transistor T3 has its third gate 163 connected to the second gate line 166, its third source 1823 connected to the sensing line 187, and its third drain 1843 connected to the first drain 1841 of the first thin-film transistor T1. At this time, the anode 225, the conductive light-shielding structure 122, and the second drain 1842 and the conductive block 147 located between the anode 225 and the conductive light-shielding structure 122 form a sandwich capacitor, i.e., a storage capacitor Cst of the pixel driving circuit. At this time, the conductive light-shielding structure 122 and the anode 225 are at the same potential (when the first thin-film transistor is turned on, the conductive light-shielding structure and the anode are electrically connected via a third via hole), and are one pole of the storage capacitor, while the conductive block 147 is the other pole of the storage capacitor.

[0166] For example, as shown in Figures 5B, 7A, and 7B, the conductive block 147 is located in the semiconductor layer 140 and is not connected to the active layers of the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3. In other words, the conductive block 147 is a conductive semiconductor block independent of the active layers of the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3. Of course, embodiments of this disclosure include, but are not limited to, the conductive block being connected to the active layers of the first thin-film transistor, the second thin-film transistor, and the third thin-film transistor, with a non-conductive semiconductor interposed between these active layers.

[0167] For example, as shown in Figures 7A and 7B, the portion of the second gate line 166 that overlaps with the third channel region 143C of the third active layer 143 of the third thin-film transistor T3 is the third gate 163. As a result, the display substrate can position a portion of the third thin-film transistor T3 outside the position of the first main body 1220, that is, the orthographic projection of a portion of the third thin-film transistor T3 on the base substrate 110 is outside the orthographic projection of the first main body 1220 on the base substrate 110. As a result, the display substrate can utilize the space on both sides of the second gate line 166, thereby optimizing the distribution of transistors and improving space utilization. For example, as shown in Figures 7A and 7B, since the portion of the second gate line 166 that overlaps with the third channel region 143C of the third active layer 143 of the third thin-film transistor T3 is the third gate 163, a portion of the third thin-film transistor T3 may also be located on the side of the second gate line 166 away from the first main body 1220.

[0168] In some examples, as shown in Figures 7A and 7B, the second drain 1842 and the first gate 161 are connected to the drain region of the second active layer 142 via the same via hole, thereby reducing the area that the second drain 1842 shields from the first gate 161 and reducing the risk of damaging the ILD layer and causing a short circuit due to the inheritance of the film deposition morphology of the actual process. Furthermore, the second drain 1842 and the first gate 161 can be connected to the drain region of the second active layer 142 via the same via hole, which can further reduce the number of via holes on the second active layer 142 and improve product yield.

[0169] Figure 9 is a timing diagram of signals on each signal line of a pixel driving circuit of a display board according to one embodiment of the present disclosure. The operation flow of the pixel driving circuit of the present disclosure will be described below with reference to the equivalent circuit diagram shown in Figure 8 and the timing diagram shown in Figure 9.

[0170] As shown in Figures 8 and 9, it is illustrated that the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3 in Figure 8 are all P-type transistors. During the data writing and reset phases, both the first gate line 165 and the second gate line 166 are ON signals, the second thin-film transistor T2 and the third thin-film transistor T3 are ON, and the data signal DT is transmitted via the second thin-film transistor T2 to the first gate 161 of the first thin-film transistor T1 and the first pole of the storage capacitor Cst, i.e., the conductive block 147. At this time, the sensing line 187 and A reset signal is written to the anode 225 via the third thin-film transistor T3, the first thin-film transistor T1 turns on, and the anode 225 is charged to the operating voltage. During the light emission phase, both the signals on the first gate line 165 and the second gate line 166 are off signals. Due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst does not change, the first thin-film transistor T1 operates in a saturated state, and the current does not change. At this time, the drive current from the power line 186 flows to the anode 225 via the first thin-film transistor T1, thereby driving the corresponding light-emitting layer and causing it to emit light.

[0171] As shown in Figures 8 and 9, the operation flow of the pixel driving circuit further includes an external compensation step, in which the signals on the first gate line 165 and the second gate line 166 are both ON signals, the second thin-film transistor T2 and the third thin-film transistor T3 are both ON, and the data signal DT is transmitted to the first gate 161 of the first thin-film transistor T1 via the second thin-film transistor T2. At this time, the analog-to-digital converter can write a reset signal to node S via the sensing line 187 and the third thin-film transistor T3, the first transistor T1 is ON, node S is charged until the first thin-film transistor is OFF, and the digital-to-analog converter can sample the voltage on the sensing line 187 to obtain the threshold voltage of the first thin-film transistor T1. Note that this external compensation step can be performed when the power supply of the display device is OFF.

[0172] In some examples, as shown in Figures 4, 5A, 7A, and 7B, the orthographic projection of the first channel region 141C on the base substrate 110 lies within the orthographic projection of the first body portion 1220 on the base substrate 110. This allows the first body portion 1220 to shield from light to the first channel region 141C, thereby stabilizing the first thin-film transistor, further improving display quality, and extending its service life.

[0173] For example, as shown in Figures 4, 5A, 7A, and 7B, the orthographic projection of the pixel driving circuit 320 on the base substrate 110 overlaps at least partially with the orthographic projection of the conductive light-shielding structure 122 on the base substrate 110. This allows various transistors or storage capacitors throughout the pixel driving circuit 320 to avoid illumination by ambient light, and further improves the stability of the pixel driving circuit 320.

[0174] In some examples, as shown in Figures 4 and 5A, the conductive light-shielding structure 122 may further include a first insulating portion 1221 whose orthographic projection on the base substrate 110 at least partially overlaps with the orthographic projection of the first via hole 261 on the base substrate 110, and whose orthographic projection on the base substrate 110 at least partially overlaps with the orthographic projection of the first source region 141S on the base substrate 110. The first insulating portion is part of the conductive light-shielding structure and insulates the first insulating portion from the other parts of the conductive light-shielding structure. In the display substrate, if the semiconductor layer itself is thin and partially missing the first source region, when the etching solution etches downward from the first source region to the first insulating portion, the first insulating portion is insulated from the other parts of the conductive light-shielding structure, so that even if the first source is connected to the first insulating portion via the first via hole, the first source is not electrically connected to the other parts of the conductive light-shielding structure. This allows the display substrate to reduce process risk and improve yield.

[0175] Figure 10A is a schematic plan view of a conductive light-shielding structure for a display substrate according to one embodiment of the present disclosure. As shown in Figure 10A, the first insulating portion 1221 includes a first hollow portion 1221A filled with the material of the buffer layer 130. Thus, the first insulating portion 1221 may be insulated from other parts of the conductive light-shielding structure 122 via the first hollow portion 1221A. Note that the first insulating portion 1221 itself may be the first hollow portion 1221A, that is, the first insulating portion 1221 may be the portion from which the conductive light-shielding structure 122 has been removed.

[0176] Figure 10B is a schematic plan view of a conductive light-shielding structure for another display substrate according to one embodiment of the present disclosure. As shown in Figure 10B, the first hollow portion 1221A may be a first hollow ring, that is, the first hollow portion is an annular hollow portion. Both the inner portion 1221B and the outer portion of the first hollow ring 1221A are made of the material of the conductive light-shielding structure 122. As a result, the first insulating portion 1221 can be insulated from other parts of the conductive light-shielding structure 122 by arranging the first hollow ring 1221A.

[0177] Figure 10C is a schematic plan view of a conductive light-shielding structure of another display substrate according to one embodiment of the present disclosure. As shown in Figure 10C, the first insulating portion 1221 is an oxidized portion. In other words, the first insulating portion 1221 can be formed by oxidizing a part of the conductive light-shielding structure 122 through an oxidation process.

[0178] Figure 11A is a schematic plan view of another display substrate according to one embodiment of the present disclosure. As shown in Figure 11A, each subpixel 300 includes a drive region 310 and an emission region 330, and the conductive light-shielding structure 122 is located in the drive region 310. In this display substrate, the orthographic projection of the pixel drive circuit 310 on the base substrate 110 overlaps with the drive region 310. By arranging the conductive light-shielding structure 122 in the drive region 310, it is possible to prevent ambient light from affecting the thin-film transistors of the pixel drive circuit, and to prevent ambient light from passing through the drive region and affecting the normal display of the display substrate. The emission direction of the display substrate may be from the anode layer to the base substrate, i.e., the display substrate uses a lower emission mode, or it may be from the base substrate to the anode layer, i.e., the display substrate uses an upper emission mode.

[0179] In some examples, as shown in Figure 11A, the display board 100 further comprises a first gate line 165, a second gate line 166, a data line 185, a power line 186, and a sensing line 187, wherein the first gate line 165 and the second gate line 166 are both located in the gate layer 160 and extend along a first direction, and the data line 185, the power line 186, and the sensing line 187 are all located in the conductive layer 180 and extend along a second direction. The multiple subpixels 300 are arranged in an array along the first and second directions to form multiple subpixel rows 370 arranged along the second direction and multiple subpixel columns 380 arranged along the first direction. In each subpixel row 370, the first gate line 165 is located between the drive region 310 and the light-emitting region 330, the second gate line 166 is located between two adjacent subpixel rows 370, and the power line 186, sensing line 187, and data line 185 are all located between two adjacent subpixel columns 380. The first direction may be the row direction of the subpixel array, and the second direction may be the column direction of the subpixel array.

[0180] In some examples, as shown in Figure 11A, the first source 1821 of the first thin-film transistor T1 is connected to the power line 186 via the first connector 1868, the second source 1822 of the second thin-film transistor T2 is connected to the data line 185 via the second connector 1858, the first connector 1868A is located on the same layer as the power line 186, and the second connector 1858 is located on the same layer as the data line 185.

[0181] In some examples, as shown in Figure 11A, the direction from the first source 1821 to the first drain 1841 (i.e., the extension direction of the first channel region) intersects with the extension direction of the first connector 1868, and the direction from the second source 1822 to the second drain 1842 (i.e., the extension direction of the second channel region) intersects with the extension direction of the second connector 1858.

[0182] For example, as shown in Figure 11A, the direction from the third source 1823 to the third drain 1843 (i.e., the extension direction of the second channel region) intersects with the extension direction of the second gate line 166. This allows, on the one hand, the portion of the second gate line 166 that overlaps with the third channel region 143C of the third active layer 143 of the third thin-film transistor T3 to function as the third gate 163, thereby utilizing the space on both sides of the second gate line 166, optimizing the transistor distribution, and improving space utilization. On the other hand, it eliminates the need for a gate portion protruding or bent from the second gate line 166, thereby further reducing the voltage drop of the second gate line 166 and improving the electrical performance of the second gate line 166.

[0183] For example, as shown in Figure 11A, the direction from the first source 1821 to the first drain 1841 (i.e., the extension direction of the first channel region) is approximately parallel to the extension direction of the power line 186, and the direction from the second source 1822 to the second drain 1842 (i.e., the extension direction of the second channel region) is approximately parallel to the extension direction of the data line 185. Note that "approximately parallel" above may include being perfectly parallel, and may also include the angle between the two directions being less than 10 degrees.

[0184] For example, as shown in Figure 11A, the direction from the third source 1823 to the third drain 1843 (i.e., the extension direction of the second channel region) is approximately parallel to the extension direction of the sensing line 187.

[0185] In some examples, as shown in Figure 11A, the display substrate 100 includes the power lines 186 and power connection lines 1865, where the power lines 186 are located in the conductive layer 180 and the power connection lines 1865 are located in the same layer as the conductive light-shielding structure 122, that is, the power connection lines 1865 and the conductive light-shielding structure 122 can be formed using the same film layer by the same patterning process.

[0186] In some examples, as shown in Figure 11A, the power connection line 1865 comprises a second main body 1865A and a plurality of power recesses 1865K, where the average thickness of each power recess 1865K in the direction perpendicular to the base substrate 110 is smaller than the average thickness of each power recess 1865A in the direction perpendicular to the base substrate 110, and the area of ​​the surface of each power recess 1865K adjacent to the conductive layer 180 is larger than the orthographic area of ​​each power recess 1865K on the base substrate 110.

[0187] In this example, as shown in Figure 11A, the power connection line 1865 comprises a second main body 1865A and a plurality of power recesses 1865K, the plurality of power recesses 1865K being used to electrically connect the power line 186 to the pixel driving circuit 320 of a plurality of sub-pixels 300. The power recesses 1865K are recessed into the power connection line 1865, and the area of ​​the surface of each power recess 1865K that is close to the conductive layer 180 is larger than the orthographic projection area of ​​the power recess 1865K on the base substrate 110. This increases the contact area for electrical connection, resulting in better contact, reduced contact resistance, improved electrical connection effect, and effectively avoidance of problems such as voltage drop (IR drop).

[0188] Figure 11B is a schematic diagram of the light focusing effect of a power recess or sensing recess on a display substrate according to one embodiment of the present disclosure. As shown in Figures 11A and 11B, the orthographic projection of at least one of the multiple power recesses 1865K on the base substrate 110 overlaps at least partially with the orthographic projection of the optical filter 350 of the color filter layer 200 on the base substrate 110. Similar to the first recess, the power recess can also focus light, and because the power recess overlaps at least partially with the optical filter, ambient light is focused onto the corresponding optical filter, thereby effectively preventing display unevenness due to ambient light and avoiding any impact on viewing comfort.

[0189] Figure 11C is a schematic cross-sectional view of a power recess of a display substrate in a direction perpendicular to the base substrate according to one embodiment of the present disclosure. As shown in Figure 11C, the gradient angle of the surface of the power recess 1865K adjacent to the conductive layer 180 may be the same as the gradient angle of the surface of the first recess adjacent to the conductive layer. Of course, embodiments of the present disclosure include, but are not limited to, this, and the gradient angle of the surface of the power recess adjacent to the conductive layer may be different from the gradient angle of the surface of the first recess adjacent to the conductive layer.

[0190] In some examples, as shown in Figure 11C, the power recess 1865K, similar to the first recess 1224, includes a second edge portion 18650 in which the thickness in the direction perpendicular to the base substrate 110 decreases continuously and gradually from the edge of the power recess 1865K toward the center of the power recess 1865K. The average thickness in the direction perpendicular to the base substrate of the portion of the power recess adjacent to the edge is smaller than the average thickness in the direction perpendicular to the base substrate of the first main body, which may affect the light shielding properties of the power recess. However, in the display board according to this example, the thickness of at least the portion adjacent to the edge of the power recess, i.e., the second edge portion 18650 in the direction perpendicular to the base board, is continuously and gradually decreases. Therefore, the surface of the conductive portion (e.g., part of the power line) at the location of the power recess that is away from the base board is convex, and this convex surface has the function of focusing light. If light can pass through the power recess, this convex surface can focus the light, thereby preventing a portion of the ambient light from being reflected into the inside of the board without control, and thus avoiding the influence of ambient light on the normal display of the display board.

[0191] For example, as shown in Figure 11C, the surface of the conductive portion (e.g., part of the power line) at the location of the power recess 1865K that is separated from the base substrate 110 is a convex surface. This convex surface has the function of focusing light, and when light can pass through the power recess, the convex surface can focus the light, thereby preventing a portion of the ambient light from being reflected into the substrate without control, and thus avoiding the influence of ambient light on the normal display of the display substrate.

[0192] In some examples, as shown in Figure 11C, the fifth gradient angle of at least the portion adjacent to the edge of the power recess 1865K, for example, the surface of the second edge portion 18650 adjacent to the conductive layer 180, changes continuously in a direction perpendicular to the base substrate 110, similar to the first recess 1224. This allows light to pass through the power recess, but the convex surface of the conductive portion at the location of the power recess, which is away from the base substrate, to focus the light, preventing the light from passing through the entire display substrate and affecting the display effect of the light-emitting region.

[0193] In some examples, as shown in Figure 11C, the display board 100 further comprises a power contact hole 551 located in the interlayer insulating layer 170 and the buffer layer 130, for example, the power contact hole 551 penetrating the interlayer insulating layer 170 and the buffer layer 130. The orthographic projection of the power contact hole 551 on the base board 110 at least partially overlaps the orthographic projection of the power recess 1865K on the base board 110.

[0194] In some examples, as shown in Figure 11C, the buffer layer 130 includes a third buffer portion 133 located within the power contact hole 551, with its side away from the base substrate 110 in contact with the power connection line and its side closer to the base substrate in contact with the conductive light-shielding structure, and a fourth buffer portion 134 located on the side of the third buffer portion 133 away from the center of the power recess 1865K. As a result, when the conductive layer (e.g., the portion corresponding to the power line) is deposited in the power contact hole 551, the third buffer portion 133 supports a portion of the conductive structure, preventing disconnection failures due to excessive steps or gradient angles of the conductive structure. This results in a high yield for the display substrate.

[0195] In some examples, as shown in Figure 11C, the sidewall of the power contact hole 551 comprises a fourth sub-sidewall 5512 located in the interlayer insulating layer 170, a fifth sub-sidewall 5514 located in the fourth buffer layer 134, and a sixth sub-sidewall 5516 located in the third buffer section 133. The fourth sub-sidewall 5512 is connected to the fifth sub-sidewall 5514, and the fifth sub-sidewall 5514 is connected to the sixth sub-sidewall 5516. The angle between the fourth sub-sidewall 5512 and the base substrate 110 is the sixth gradient angle β', the angle between the fifth sub-sidewall 5514 and the base substrate 110 is the seventh gradient angle γ', and the angle between the sixth sub-sidewall 5516 and the base substrate 110 is the eighth gradient angle θ'. The sixth, seventh, and eighth gradient angles are different. The contact point between the fifth sub-side wall 5514 and the third buffer section 133 is located between the third buffer section 133 and the fourth buffer section 134.

[0196] In this display substrate, the buffer layer and the interlayer insulating layer are made of different materials, resulting in different etching efficiencies for them using the etching solution. Consequently, the gradient angles of the fourth sub-sidewall, the fifth sub-sidewall, and the sixth sub-sidewall formed tend to differ.

[0197] For example, the buffer layer can be manufactured by depositing it using a process at different temperatures, thereby creating a buffer layer with different densities within it, and further forming the third and fourth buffer sections. Of course, the embodiments of this disclosure include, but are not limited to, the third and fourth buffer sections, and may be manufactured by other suitable methods.

[0198] In some examples, as shown in Figure 11C, the sixth gradient angle β' is smaller than the seventh gradient angle γ', the seventh gradient angle γ' is larger than the eighth gradient angle θ', and the sixth gradient angle β' is larger than the eighth gradient angle θ'. In other words, the seventh gradient angle γ' is larger than the sixth gradient angle β', and the sixth gradient angle β' is larger than the eighth gradient angle θ'.

[0199] For example, the fourth gradient angle α is smaller than the eighth gradient angle θ'.

[0200] In some examples, since the power recess is formed on a linear or elongated power connection wire, the angles of the side walls of the power contact hole corresponding to the power recess and the first contact hole corresponding to the first recess may be different. For example, the seventh gradient angle γ' of the power contact hole is smaller than the third gradient angle γ of the first contact hole. As a result, the sixth gradient angle of the power contact hole is small, the fifth sub-side wall becomes smoother, and defects such as wire breakage can be better prevented. Of course, embodiments of this disclosure include, but are not limited to, the seventh gradient angle γ' of the power contact hole may be greater than or equal to the second gradient angle γ of the first contact hole.

[0201] In some examples, the eighth slope angle θ' of the power supply contact hole is greater than the third slope angle θ of the first contact hole, thereby reducing the size of the third buffer section and improving the electrical connection effect with the power supply recess. Of course, embodiments of the present disclosure include, but are not limited to, the eighth slope angle of the power supply contact hole being smaller than the fourth slope angle of the first contact hole.

[0202] In some examples, as shown in Figure 11A, the display substrate 100 includes the sensing line 187 and the sensing connection line 1875, where the sensing line 187 is located in the conductive layer 180 and the sensing connection line 1875 is located in the same layer as the conductive light-shielding structure 122, that is, the power connection line 1865 and the conductive light-shielding structure 122 can be formed using the same film layer by the same patterning process.

[0203] In some examples, as shown in Figure 11A, the sensing connection line 1875 comprises a third main body 1875A and a plurality of sensing recesses 1875K, where the average thickness of the sensing recesses 1875K in the direction perpendicular to the base substrate 110 is smaller than the average thickness of the third main body 1875A in the direction perpendicular to the base substrate 110, and the area of ​​the surface of the sensing recess 1875K adjacent to the conductive layer 180 is larger than the orthographic area of ​​the sensing recess 1875K on the base substrate 110.

[0204] In this example, the sensing connection line 1875 comprises a third main body 1875A and a plurality of sensing recesses 1875K, the plurality of sensing recesses 1875K being used to electrically connect the sensing line 187 to the pixel driving circuit 320 of a plurality of sub-pixels 300. The sensing recesses 1875K are recessed into the sensing connection line 1875, and the area of ​​the surface of each sensing recess 1875K adjacent to the conductive layer 180 is larger than the orthographic projection area of ​​the sensing recess 1875K on the base substrate 110. This increases the contact area for electrical connection, resulting in better contact, which in turn reduces contact resistance, improves the electrical connection effect, and effectively avoids problems such as voltage drop (IR drop).

[0205] In some examples, as shown in Figures 11A and 11B, the orthographic projection of at least one of the multiple sensing recesses 1875K on the base substrate 110 at least partially overlaps with the orthographic projection of the optical filter 350 of the color filter layer 200 on the base substrate 110. Similar to the first recess, the power recess can also focus light, and because the power recess at least partially overlaps with the optical filter, ambient light is focused onto the corresponding optical filter, thereby effectively preventing display unevenness due to ambient light and avoiding any impact on viewing comfort.

[0206] Figure 11D is a schematic cross-sectional view of a sensing recess of a display substrate according to one embodiment of the present disclosure, in a direction perpendicular to the base substrate. As shown in Figure 11D, the gradient angle of the surface of the sensing recess 1875K adjacent to the conductive layer 180 may be the same as the gradient angle of the surface of the first recess adjacent to the conductive layer. Of course, embodiments of the present disclosure include, but are not limited to, this, and the gradient angle of the surface of the sensing recess adjacent to the conductive layer may be different from the gradient angle of the surface of the first recess adjacent to the conductive layer.

[0207] In some examples, as shown in Figure 11D, the sensing recess 1875K, similar to the first recess 1224, includes a third edge portion 18750 in which the thickness in the direction perpendicular to the base substrate 110 decreases continuously and gradually in the direction from the edge of the sensing recess 1875K toward the center of the sensing recess 1875K. The average thickness in the direction perpendicular to the base substrate of the portion of the sensing recess adjacent to the edge is smaller than the average thickness in the direction perpendicular to the base substrate of the first main body, which may affect the light shielding of the sensing recess. However, in the display substrate according to this example, since the thickness in the direction perpendicular to the base substrate decreases continuously and gradually at least in the portion adjacent to the edge of the sensing recess, the surface of the conductive portion (e.g., part of the sensing line) away from the base substrate at the location of the sensing recess is convex, and this convex surface has the function of focusing light. If light can pass through the sensing recess, this convex surface can focus the light, thereby preventing a portion of the ambient light from being reflected into the interior of the substrate without control, and avoiding the influence of ambient light on the normal display of the display substrate.

[0208] For example, as shown in Figure 11D, the surface of the conductive portion (e.g., part of the sensing line) at the location of the sensing recess 1875K that is separated from the base substrate 110 is a convex surface. This convex surface has the function of focusing light, and when light can pass through the sensing recess, the convex surface can focus the light, thereby preventing a portion of the ambient light from being reflected into the substrate without control, and thus avoiding the influence of ambient light on the normal display of the display substrate.

[0209] In some examples, as shown in Figure 11D, the ninth gradient angle of the surface of the third edge portion 18750 adjacent to the conductive layer 180 changes continuously in a direction perpendicular to the base substrate 110, similar to the first recess 1224. This prevents light from passing through the sensing recess, as the convex surface of the conductive portion at the location of the sensing recess, away from the base substrate, can focus the light, thereby preventing light from passing through the entire display substrate and affecting the display effect of the light-emitting area.

[0210] In some examples, as shown in Figure 11D, the display substrate 100 further comprises a sensing contact hole 552 located in the interlayer insulating layer 170 and the buffer layer 130, for example, the sensing contact hole 552 penetrates the interlayer insulating layer 170 and the buffer layer 130. The orthographic projection of the sensing contact hole 552 on the base substrate 110 at least partially overlaps the orthographic projection of the sensing recess 1875K on the base substrate 110.

[0211] In some examples, as shown in Figure 11D, the buffer layer 130 comprises a fifth buffer portion 135 located within the sensing contact hole 552 and positioned in contact with the sensing connection line 1875, and a sixth buffer portion 136 located on the side of the fifth buffer portion 135 away from the center of the sensing recess 1875K. Thereafter, when the conductive layer (e.g., the portion corresponding to the sensing line) is deposited in the sensing contact hole 552, the fifth buffer portion 135 supports a portion of the conductive structure, preventing disconnection failures due to excessive steps or gradient angles of the conductive structure. As a result, the display board has a high yield.

[0212] In some examples, as shown in Figure 11D, the side of the fifth buffer section 135 away from the base substrate 110 is positioned in contact with the sensing connection line 1875, and the side of the fifth buffer section 135 closer to the base substrate 110 is positioned in contact with the conductive light-shielding structure 122.

[0213] In some examples, as shown in Figure 11D, the sidewall of the sensing contact hole 552 comprises a seventh sub-sidewall 5522 located in the interlayer insulating layer 170, an eighth sub-sidewall 5524 located in the sixth buffer layer 136, and a ninth sub-sidewall 5526 located in the fifth buffer section 135, the seventh sub-sidewall 5522 being connected to the eighth sub-sidewall 5524, the eighth sub-sidewall 5524 being connected to the ninth sub-sidewall 5526, the angle between the seventh sub-sidewall 5522 and the base substrate 110 being the tenth gradient angle β'', the angle between the eighth sub-sidewall 5524 and the base substrate 110 being the eleventh gradient angle γ'', and the angle between the ninth sub-sidewall 5526 and the base substrate 110 being the twelfth gradient angle θ'', which are different from the tenth, eleventh, and twelfth gradient angles. In this display substrate, the buffer layer and the interlayer insulating layer are made of different materials, resulting in different etching efficiencies for them using the etching solution. Consequently, the gradient angles of the 7th sub-sidewall, the 8th sub-sidewall, and the 9th sub-sidewall formed by these layers tend to differ.

[0214] For example, the buffer layer can be manufactured by depositing it in a process at different temperatures, thereby creating a buffer layer with different densities within it, and further forming the fifth and sixth buffer sections. Of course, the embodiments of this disclosure include, but are not limited to, the fifth and sixth buffer sections, and may be manufactured by other suitable methods.

[0215] In some examples, as shown in Figure 11D, the 10th gradient angle β'' is smaller than the 11th gradient angle γ'', the 11th gradient angle γ'' is larger than the 12th gradient angle θ'', and the 10th gradient angle β'' is larger than the 12th gradient angle θ''. That is, the 11th gradient angle γ'' is larger than the 10th gradient angle β'', and the 10th gradient angle β'' is larger than the 12th gradient angle θ''. Of course, embodiments of this disclosure include, but are not limited to, these.

[0216] For example, the fourth gradient angle α is smaller than the twelfth gradient angle θ''.

[0217] In some examples, since the sensing recess is formed on a linear or elongated sensing connection wire, the angles of the side walls of the sensing contact hole corresponding to the sensing recess and the first contact hole corresponding to the first recess may be different. For example, the 11th gradient angle γ'' of the sensing contact hole is smaller than the 3rd gradient angle γ of the first contact hole. As a result, the 8th sub-side wall becomes smoother because the 11th gradient angle of the sensing contact hole is small, which can prevent disconnection defects and the like. Of course, embodiments of this disclosure include but are not limited to this, and the 11th gradient angle γ'' of the sensing contact hole may be greater than or equal to the 3rd gradient angle γ of the first contact hole.

[0218] In some examples, the 12th gradient angle θ'' of the sensing contact hole is greater than the 3rd gradient angle θ of the first contact hole, thereby reducing the size of the 5th buffer and improving the electrical connection effect with the sensing recess. Of course, embodiments of the present disclosure include, but are not limited to, the 12th gradient angle of the sensing contact hole being smaller than the 3rd gradient angle of the first contact hole.

[0219] The other specific shapes and sizes of the power supply recess and the sensing recess are described in the related explanation of the first recess shown in Figures 6A and 6B, and will not be repeated here.

[0220] In some examples, as shown in Figure 11A, a plurality of subpixels 300 comprises a first-color subpixel 300A, a second-color subpixel 300B, a third-color subpixel 300C, and a fourth-color subpixel 300D, and in each subpixel row 370, the first-color subpixel 300A, the second-color subpixel 300B, the third-color subpixel 300C, and the fourth-color subpixel 300D are sequentially arranged along a first direction to form a subpixel group 390, and the power line 186 is located between the second-color subpixel 300B and the third-color subpixel 300C within the subpixel group 390.

[0221] In some examples, as shown in Figure 11A, the display board 100 further comprises power connection lines 1865 arranged in the same layer as the conductive light-shielding structure 122, and power lines 186 may be connected to the power connection lines 1865 via contact holes that penetrate the interlayer insulating layer and the buffer layer.

[0222] In some examples, as shown in Figure 11A, the display board 100 further comprises a second contact hole 252, a third contact hole 253, and a fourth contact hole 254, the second contact hole 252, the third contact hole 253, and the fourth contact hole 254 located in the interlayer insulating layer 170 and the buffer layer 130, and in the subpixel group 390, the power line 186 is connected to the power connection line 1865 via the second contact hole 252, the first source 1821 of the second color subpixel 300B is connected to the same layer as the power line 186, and the first source 1821 of the third color subpixel 300C is connected to the same layer as the power line 186. Note that the above-mentioned same-layer connection means that the first source and the power line are directly connected via a connection line located on the same layer.

[0223] In some examples, as shown in Figure 11A, the first source 1821 of the first color subpixel 300A is connected to the power supply line 1865 via the third contact hole 253, and the first source 1821 of the fourth color subpixel 300D is connected to the power supply line 1865 via the fourth contact hole 254. This allows one power supply line to drive four subpixels simultaneously in each pixel row, thereby reducing the wiring density.

[0224] In some examples, as shown in Figure 11A, the power connection line 1865 comprises a second body portion 1865A, a second recess 1865B, a third recess 1865C, and a fourth recess 1865D, wherein the orthographic projection of the second recess 1865B on the base substrate 110 at least partially overlaps with the orthographic projection of the second contact hole 252 on the base substrate 110, the thickness of the second recess 1865B in the direction perpendicular to the base substrate 110 is smaller than the thickness of the second body portion 1865A in the direction perpendicular to the base substrate 110, and the area of ​​the surface of the second recess 1865B adjacent to the power connection line 186 is larger than the area of ​​the orthographic projection of the second recess 1865B on the base substrate 110. In the display board, the power connection line 186 can be connected to the second recess 1865B of the power connection line 1865 via the second contact hole 252. Because the second recess 1865B has a recessed structure, the area of ​​the surface of the second recess adjacent to the power line is larger than the orthographic area of ​​the second recess on the base substrate. As a result, the display substrate can increase the contact area between the power line and the power connection line, resulting in better contact, which in turn reduces contact resistance and improves the electrical connection effect between the power line and the power connection line.

[0225] Similar to the first recess, the thickness of the second recess, from its edge to its center, decreases continuously and gradually in the direction perpendicular to the base substrate, at least in the portion adjacent to the edge of the second recess. The average thickness of the second recess in the direction perpendicular to the base substrate is smaller than the thickness of the second main body in the direction perpendicular to the base substrate, which may affect the light-shielding properties of the second recess. In the display substrate according to this example, because the thickness of the second recess in the direction perpendicular to the base substrate decreases continuously and gradually, even if light can pass through the second recess, the second recess can focus the light, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate. Similarly, the surface of the second recess adjacent to the power lines is an arcuate or bent surface.

[0226] In some examples, as shown in Figure 11A, the orthographic projection of the third recess 1865C on the base substrate 110 at least partially overlaps with the orthographic projection of the third contact hole 253 on the base substrate 110, the thickness of the third recess 1865C in the direction perpendicular to the base substrate 110 is smaller than the thickness of the second main body 1865A in the direction perpendicular to the base substrate 110, and the area of ​​the surface of the third recess 1865C away from the base substrate 110 is larger than the area of ​​the orthographic projection of the third recess 1865C on the base substrate 110. In the display board, the first source 1821 of the first color subpixel 300A may be connected to the third recess 1865C of the power connection line 1865 via the third contact hole 253, for example, by connecting the first source of the first color subpixel and the third recess via a connection line arranged in a conductive layer. Because the third recess is a recessed structure, the area of ​​the surface of the third recess away from the base substrate is larger than the area of ​​the orthographic projection of the third recess on the base substrate. As a result, the display board can increase the contact area between the first source of the first color subpixel and the power connection line, resulting in better contact, which in turn reduces contact resistance and improves the electrical connection effect between the first source of the first color subpixel and the power connection line.

[0227] Similar to the first recess, the thickness of the third recess, from its edge to its center, decreases continuously and gradually in the direction perpendicular to the base substrate, at least in the portion adjacent to the edge of the third recess. The average thickness of the third recess in the direction perpendicular to the base substrate is smaller than the thickness of the second main body in the direction perpendicular to the base substrate, which may affect the light-shielding properties of the third recess. In the display substrate according to this example, because the thickness of the third recess in the direction perpendicular to the base substrate decreases continuously and gradually, even if light can pass through the third recess, the third recess can focus the light, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate. Similarly, the surface of the third recess adjacent to the power lines may be an arcuate surface or a bent surface.

[0228] In some examples, as shown in Figure 11A, the orthographic projection of the fourth recess 1865D on the base substrate 110 at least partially overlaps with the orthographic projection of the fourth contact hole 254 on the base substrate 110, the thickness of the fourth recess 1865D in the direction perpendicular to the base substrate 110 is smaller than the thickness of the second main body 1865A in the direction perpendicular to the base substrate 110, and the area of ​​the surface of the fourth recess 1865D away from the base substrate 110 is larger than the area of ​​the orthographic projection of the fourth recess 1865D on the base substrate 110. In the display substrate, the first source 1821 of the fourth color subpixel 300D may be connected to the fourth recess 1865D of the power connection line 1865 via the fourth contact hole 254, for example, by connecting the first source of the fourth color subpixel and the fourth recess via a connection line arranged in a conductive layer. Because the fourth recess is a recessed structure, the area of ​​the surface of the fourth recess away from the base substrate is larger than the area of ​​the orthographic projection of the fourth recess on the base substrate. As a result, the display board can increase the contact area between the first source of the fourth color subpixel and the power connection line, resulting in better contact, which in turn reduces contact resistance and improves the electrical connection effect between the first source of the fourth color subpixel and the power connection line.

[0229] Similar to the first recess, the thickness of the fourth recess decreases continuously and gradually from the edge to the center of the fourth recess, at least in the portion adjacent to the edge of the fourth recess, in the direction perpendicular to the base substrate. The average thickness of the fourth recess in the direction perpendicular to the base substrate is smaller than the thickness of the second main body in the direction perpendicular to the base substrate, which may affect the light-shielding properties of the fourth recess. In the display substrate according to this example, because the thickness of the fourth recess in the direction perpendicular to the base substrate decreases continuously and gradually, even if light can pass through the fourth recess, the fourth recess can focus the light, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate. Similarly, the surface of the fourth recess adjacent to the power lines may be an arcuate surface or a bent surface.

[0230] In some examples, as shown in Figure 11A, the orthographic projection of at least one of the second recess 1865B, the third recess 1865C, and the fourth recess 1865D on the base substrate 110 at least partially overlaps with the orthographic projection of the optical filter 350 of the color filter layer 200 on the base substrate 110, thereby effectively preventing display unevenness due to ambient light and avoiding any impact on viewing comfort.

[0231] In some examples, as shown in Figure 11A, the second color subpixel 300B is equipped with a first color filter 351, thereby emitting first color light; the third color subpixel 300C is equipped with a second color filter 352, thereby emitting second color light; and the fourth color subpixel 300D is equipped with a third color filter 353, thereby emitting third color light. For example, the first color subpixel 300D does not have an optical filter, thereby emitting white light. As a result, the display board can achieve full-color display, and the use of white subpixels increases the brightness and contrast of the display board.

[0232] For example, the first color may be red (R), the second color may be green (G), and the third color may be blue (B). Of course, the embodiments of this disclosure include, but are not limited to, these three colors may be other colors.

[0233] In some examples, as shown in Figure 11A, the display substrate 100 further comprises a pixel definition layer 370, the pixel definition layer 370 comprising a plurality of apertures 375 on which optical filters 350 are placed.

[0234] For example, as shown in Figure 11A, the multiple openings 375 include a first opening 3751, a second opening 3752, and a third opening 3753, where the first color filter 351 is at least partially located in the first opening 3751, the second color filter 352 is at least partially located in the second opening 3752, and the third color filter 353 is at least partially located in the third opening 3753. The shortest distance J3 between the outer edge of the third color filter 353 and the third opening 3753 is greater than the shortest distance J2 between the outer edge of the first color filter 351 and the first opening 3751, and also greater than the shortest distance J1 between the outer edge of the second color filter 352 and the second opening 3752. Of course, the embodiments of this disclosure include, but are not limited to, the shortest distance between the outer edge of the second color filter and the second aperture, depending on the requirements of different products, may be greater than the shortest distance between the outer edge of the first color filter and the first aperture, and between the outer edge of the third color filter and the third aperture, or the shortest distance between the outer edge of the first color filter and the first aperture, may be greater than the shortest distance between the outer edge of the second color filter and the second aperture, and between the outer edge of the third color filter and the third aperture.

[0235] In some examples, as shown in Figure 11A, most of the first color filter 351 is located in the light-emitting region 330 of the first color subpixel 300A, most of the second color filter 352 is located in the light-emitting region 330 of the second color subpixel 300B, and most of the third color filter 353 is located in the light-emitting region 330 of the third color subpixel 300C.

[0236] In some examples, as shown in Figure 11A, in the subpixel group 390, the orthographic projection of at least one of the first color filter 351 and the second color filter 352 on the base substrate 110 at least partially overlaps with the orthographic projection of the second recess 1865B on the base substrate 110, and the orthographic projection of the third color filter 351 on the base substrate 110 at least partially overlaps with the orthographic projection of the fourth recess 1865D on the base substrate 110. As a result, even if the thickness of the second or fourth recess is thin and affects light shielding, the first and second color filters can further shield the second recess, and the third color filter can further shield the fourth recess, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate.

[0237] Furthermore, if the thickness of the second recess decreases continuously and gradually from the edge to the center of the second recess in a direction perpendicular to the base substrate, even if light passes through the second recess, the second recess can focus the light onto at least one of the first and second color filters, thereby effectively preventing ambient light from passing through the entire display substrate. Similarly, if the thickness of the fourth recess decreases continuously and gradually from the edge to the center of the fourth recess in a direction perpendicular to the base substrate, even if light passes through the fourth recess, the fourth recess can focus the light onto the third color filter, thereby effectively preventing display unevenness due to ambient light and avoiding any impact on viewing comfort.

[0238] For example, as shown in Figure 11A, the overlapping area between the orthographic projection of the third color filter 351 on the base substrate 110 and the orthographic projection of the fourth recess 1865D on the base substrate 110 is larger than the overlapping area between the orthographic projection of the first color filter 351 or the second color filter 352 on the base substrate 110 and the orthographic projection of the second recess 1865B on the base substrate 110.

[0239] In some examples, as shown in Figure 11A, the sensing line 187 is located between two adjacent sub-pixel groups 390 in the first direction, and the two adjacent sub-pixel groups 390 in the first direction comprise a first sub-pixel group 391 and a second sub-pixel group 392. The display board 100 further comprises a sensing connection line 1875, a fifth contact hole 255, a sixth contact hole 256, a seventh contact hole 257, an eighth contact hole 258, and a ninth contact hole 259, wherein the sensing connection line 1875 is located in the same layer as the conductive light-shielding structure 122, and the fifth contact hole 255, sixth contact hole 256, seventh contact hole 257, eighth contact hole 258, and ninth contact hole 259 are located within the interlayer insulating layer 170 and the buffer layer 130. In two adjacent sub-pixel groups 390, the sensing line 187 is connected to the sensing connection line 1875 via the fifth contact hole 255. For clarification, Figure 11A does not show the entire second subpixel group; the configuration of the second subpixel group can be understood by referring to the configuration of the first subpixel group.

[0240] In some examples, as shown in Figure 11A, the third source 1843 of the third color subpixel 300C in the first subpixel group 391 is connected to the sensing connection line 1875 via the sixth contact hole 256, and the third source 1843 of the fourth color subpixel 300D in the first subpixel group 391 is connected to the sensing connection line 1875 via the seventh contact hole 257. The third source 1843 of the first color subpixel 300A in the second subpixel group 392 is connected to the sensing connection line 1875 via the eighth contact hole 358, and the third source 1843 of the second color subpixel 300B in the second subpixel group 392 is connected to the sensing connection line 1875 via the ninth contact hole 359. This allows one sensing line to drive four subpixels simultaneously in each pixel row, thereby reducing the wiring density. Furthermore, since the third source of each of the four subpixels is connected to the sensing connection line via a contact hole, the space required for the pixel driving circuit of each subpixel can be made approximately the same, thus simplifying the arrangement of the pixel driving circuit for each subpixel.

[0241] In some examples, as shown in Figure 11A, the sensing connection line 1875 comprises a third body portion 1875A, a fifth recess 1875B, a sixth recess 1875C, a seventh recess 1875D, an eighth recess 1875E, and a ninth recess 1875F, wherein the orthographic projection of the fifth recess 1875B on the base substrate 110 at least partially overlaps with the orthographic projection of the fifth contact hole 255 on the base substrate 110, and the orthographic projection of the sixth recess 1875C on the base substrate 110 overlaps with the orthographic projection of the sixth contact hole 266 on the base substrate 110. The projections overlap at least partially, with the orthographic projection of the seventh recess 1875D on the base substrate 110 at least partially overlapping with the orthographic projection of the seventh contact hole 257 on the base substrate 110, the orthographic projection of the eighth recess 1875E on the base substrate 110 at least partially overlapping with the orthographic projection of the eighth contact hole 258 on the base substrate 110, and the orthographic projection of the ninth recess 1875F on the base substrate 110 at least partially overlapping with the orthographic projection of the ninth contact hole 259 on the base substrate 110.

[0242] In some examples, as shown in Figure 11A, the thickness of the fifth recess 1875B in the direction perpendicular to the base substrate 110 is smaller than the thickness of the third main body 1875A in the direction perpendicular to the base substrate 110, and the area of ​​the surface of the fifth recess 155 adjacent to the sensing line 187 is larger than the orthographic area of ​​the fifth recess 1875B on the base substrate 110. In this display board, the sensing line 187 is connected to the fifth recess 1875B of the sensing connection line 1875 via the fifth contact hole 255. Because the fifth recess 1865B is a recessed structure, the area of ​​the surface of the fifth recess adjacent to the sensing line is larger than the orthographic area of ​​the fifth recess on the base substrate. As a result, the display board can increase the contact area between the sensing line and the sensing connection line, resulting in better contact, which in turn reduces contact resistance and improves the electrical connection effect between the sensing line and the sensing connection line.

[0243] Similar to the first recess, the thickness of the fifth recess decreases continuously and gradually from the edge to the center of the fifth recess, in the direction perpendicular to the base substrate. The average thickness of the fifth recess in the direction perpendicular to the base substrate is smaller than the thickness of the third main body in the direction perpendicular to the base substrate, which may affect the light shielding properties of the fifth recess. In the display substrate according to this example, because the thickness of the fifth recess in the direction perpendicular to the base substrate decreases continuously and gradually, even if light can pass through the fifth recess, the fifth recess can focus the light, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate. Similarly, the surface of the fifth recess adjacent to the power lines is an arcuate or bent surface.

[0244] In some examples, as shown in Figure 11A, the thickness of the sixth recess 1875C in the direction perpendicular to the base substrate 110 is smaller than the thickness of the third main body 1875A in the direction perpendicular to the base substrate 110, and the area of ​​the surface of the sixth recess 1875C away from the base substrate 110 is larger than the orthographic area of ​​the sixth recess 1875C on the base substrate 110. In this display board, the third source 1843 of the third color subpixel 300C in the first subpixel group 391 is connected to the sixth recess 1875C of the sensing connection line 1875 via the sixth contact hole 356. Because the sixth recess 1865C is a recessed structure, the area of ​​the surface of the sixth recess 1865C away from the base substrate 110 is larger than the orthographic area of ​​the sixth recess 1865C on the base substrate 110. As a result, the display board can increase the contact area between the third source of the third color subpixel in the first subpixel group and the sensing connection line, resulting in more sufficient contact, thereby reducing contact resistance and improving the electrical connection effect between the third source of the third color subpixel in the first subpixel group and the sensing connection line.

[0245] Similar to the first recess, the thickness of the sixth recess decreases continuously and gradually from the edge to the center of the sixth recess, in the direction perpendicular to the base substrate. The average thickness of the sixth recess in the direction perpendicular to the base substrate is smaller than the thickness of the third main body in the direction perpendicular to the base substrate, which may affect the light-shielding properties of the sixth recess. In the display substrate according to this example, because the thickness of the sixth recess in the direction perpendicular to the base substrate decreases continuously and gradually, even if light can pass through the sixth recess, the sixth recess can focus the light, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate. Similarly, the surface of the sixth recess adjacent to the power lines is an arcuate or bent surface.

[0246] In some examples, as shown in Figure 11A, the thickness of the seventh recess 1875D in the direction perpendicular to the base substrate 110 is smaller than the thickness of the third main body 1875A in the direction perpendicular to the base substrate 110, and the area of ​​the surface of the seventh recess 1875D away from the base substrate 110 is larger than the orthographic area of ​​the seventh recess 1875D on the base substrate 110. In this display board, the third source 1843 of the fourth color subpixel 300D in the first subpixel group 391 is connected to the seventh recess 1875D of the sensing connection line 1875 via the seventh contact hole 357. Because the seventh recess 1875D is a recessed structure, the area of ​​the surface of the seventh recess 1865D away from the base substrate 110 is larger than the orthographic area of ​​the seventh recess 1865D on the base substrate 110. As a result, the display board can increase the contact area between the third source of the fourth color subpixel in the first subpixel group and the sensing connection line, resulting in more sufficient contact, thereby reducing contact resistance and improving the electrical connection effect between the third source of the fourth color subpixel in the first subpixel group and the sensing connection line.

[0247] Similar to the first recess, the thickness of the seventh recess decreases continuously and gradually from the edge to the center of the seventh recess, in the direction perpendicular to the base substrate. The average thickness of the seventh recess in the direction perpendicular to the base substrate is smaller than the thickness of the third main body in the direction perpendicular to the base substrate, which may affect the light-shielding properties of the seventh recess. In the display substrate according to this example, because the thickness of the seventh recess in the direction perpendicular to the base substrate decreases continuously and gradually, even if light can pass through the seventh recess, the seventh recess can focus the light, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate. Similarly, the surface of the seventh recess adjacent to the power lines is an arcuate or bent surface.

[0248] In some examples, as shown in Figure 11A, the thickness of the eighth recess 1875E in the direction perpendicular to the base substrate 110 is smaller than the thickness of the third main body 1875A in the direction perpendicular to the base substrate 110, and the area of ​​the surface of the eighth recess 1875E away from the base substrate 110 is larger than the orthographic area of ​​the eighth recess 1875E on the base substrate 110. In the display substrate, the third source 1843 of the first color subpixel 300A in the second subpixel group 392 is connected to the eighth recess 1875E of the sensing connection line 1875 via the eighth contact hole 358. Because the eighth recess 1875E is a recessed structure, the area of ​​the surface of the eighth recess 1865E away from the base substrate 110 is larger than the orthographic area of ​​the eighth recess 1865E on the base substrate 110. As a result, the display board can increase the contact area between the third source of the first color subpixel in the second subpixel group and the sensing connection line, resulting in more sufficient contact, thereby reducing contact resistance and improving the electrical connection effect between the third source of the first color subpixel in the second subpixel group and the sensing connection line.

[0249] Similar to the first recess, the thickness of the eighth recess decreases continuously and gradually from the edge to the center of the eighth recess, in the direction perpendicular to the base substrate. The average thickness of the eighth recess in the direction perpendicular to the base substrate is smaller than the thickness of the third main body in the direction perpendicular to the base substrate, which may affect the light shielding properties of the eighth recess. In the display substrate according to this example, because the thickness of the eighth recess in the direction perpendicular to the base substrate decreases continuously and gradually, even if light can pass through the eighth recess, the eighth recess can focus the light, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate. Similarly, the surface of the eighth recess adjacent to the power lines is an arcuate or bent surface.

[0250] In some examples, as shown in Figure 11A, the thickness of the ninth recess 1875F in the direction perpendicular to the base substrate 110 is smaller than the thickness of the third main body 1875A in the direction perpendicular to the base substrate 110, and the area of ​​the surface of the ninth recess 1875F away from the base substrate 110 is larger than the orthographic area of ​​the ninth recess 1875F on the base substrate 110. In this display board, the third source 1843 of the second color subpixel 300B in the second subpixel group 392 is connected to the ninth recess 1875F of the sensing connection line 1875 via the ninth contact hole 359. Because the ninth recess 1875F is a recessed structure, the area of ​​the surface of the ninth recess 1865F away from the base substrate 110 is larger than the orthographic area of ​​the ninth recess 1865F on the base substrate 110. As a result, the display board can increase the contact area between the third source of the second color subpixel in the second subpixel group and the sensing connection line, resulting in more sufficient contact, thereby reducing contact resistance and improving the electrical connection effect between the third source of the second color subpixel in the second subpixel group and the sensing connection line.

[0251] Similar to the first recess, the thickness of the ninth recess decreases continuously and gradually from the edge to the center of the ninth recess in the direction perpendicular to the base substrate. The average thickness of the ninth recess in the direction perpendicular to the base substrate is smaller than the thickness of the third main body in the direction perpendicular to the base substrate, which may affect the light shielding properties of the ninth recess. In the display substrate according to this example, because the thickness of the ninth recess in the direction perpendicular to the base substrate decreases continuously and gradually, even if light can pass through the ninth recess, the ninth recess can focus the light, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate. Similarly, the surface of the ninth recess adjacent to the power lines is an arcuate or bent surface.

[0252] In some examples, as shown in Figure 11A, the orthographic projection of at least one of the fifth recess 1875B, sixth recess 1875C, seventh recess 1875D, eighth recess 1875E, and ninth recess 1875F on the base substrate 110 at least partially overlaps with the orthographic projection of the optical filter 350 of the color filter layer 200 on the base substrate 110, thereby effectively preventing display unevenness due to ambient light and avoiding any impact on viewing comfort.

[0253] In some examples, as shown in Figure 11A, in the second direction, the sensing connection line 1875 is located on the side of the second gate line 162 away from the first gate line 161, and the orthographic projection of the second color filter 352 in the first subpixel group 391 on the base substrate 110 overlaps at least partially with the orthographic projection of the sixth recess 1875C of the adjacent first subpixel group 391 on the base substrate 110 in the second direction. Thus, even if the thickness of the sixth recess is thin and affects light shielding, the second color filter in the first subpixel group can further shield the sixth recess, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate.

[0254] Furthermore, if the thickness of the sixth recess decreases continuously and gradually from the edge of the sixth recess to the center of the sixth recess in a direction perpendicular to the base substrate, even if light passes through the sixth recess, the sixth recess can focus the light onto the second color filter, thereby effectively preventing ambient light from passing through the entire display substrate.

[0255] In some examples, as shown in Figure 11A, the orthographic projection of the third color filter 353 in the first subpixel group 391 on the base substrate 110 overlaps at least partially with the orthographic projection of the seventh recess 1875D of the first subpixel group 391 adjacent to it in the second direction on the base substrate 110. As a result, even if the thinness of the seventh recess affects light shielding, the third color filter in the first subpixel group can further shield the seventh recess, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate.

[0256] Furthermore, if the thickness of the seventh recess decreases continuously and gradually from the edge to the center of the seventh recess in a direction perpendicular to the base substrate, even if light passes through the seventh recess, the seventh recess can focus the light onto the third color filter, thereby effectively preventing ambient light from passing through the entire display substrate.

[0257] In some cases, as shown in Figure 11A, the orthographic projection of the first color filter 351 in the second subpixel group 392 on the base substrate 110 overlaps at least partially with the orthographic projection of the ninth recess 1875F adjacent to it in the second direction on the base substrate 110. As a result, even if the thinness of the ninth recess affects light shielding, the first color filter in the second subpixel group can further shield the ninth recess, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate.

[0258] Furthermore, if the thickness of the ninth recess decreases continuously and gradually from the edge of the ninth recess to the center of the ninth recess in a direction perpendicular to the base substrate, even if light passes through the ninth recess, the ninth recess can focus the light onto the first color filter, thereby effectively preventing ambient light from passing through the entire display substrate.

[0259] For example, as shown in Figure 11A, the overlapping area between the orthographic projection of the third color filter 351 on the base substrate 110 and the orthographic projection of the sensing recess 1875K on the base substrate 110 is larger than the overlapping area between the orthographic projection of the first color filter 351 or the second color filter 352 on the base substrate 110 and the orthographic projection of the sensing recess 1875K on the base substrate 110.

[0260] In some examples, as shown in Figure 11A, the orthographic projection of the first color filter 351 on the base substrate 110 in the subpixel group 390 at least partially overlaps with the orthographic projection of the power connection line 1865 on the base substrate 110, thereby allowing adjustment of the capacitance values ​​of various capacitors in the pixel driving circuit to achieve excellent electrical performance. The orthographic projection of the second color filter 352 on the base substrate 110 also at least partially overlaps with the orthographic projection of the power connection line 1865 and the first gate line 161 on the base substrate 110, respectively, thereby allowing adjustment of the capacitance values ​​of various capacitors in the pixel driving circuit to achieve excellent electrical performance. The orthographic projection of the third color filter 353 on the base substrate 110 also at least partially overlaps with the orthographic projection of the power connection line 1865 on the base substrate 110, thereby allowing adjustment of the capacitance values ​​of various capacitors in the pixel driving circuit to achieve excellent electrical performance.

[0261] In some examples, as shown in Figure 11A, in the subpixel group 390, the orthographic projection of the first color filter 351 on the base substrate 110 at least partially overlaps with the orthographic projection of the sensing connection line 1875 on the base substrate 110, the orthographic projection of the second color filter 352 on the base substrate 110 at least partially overlaps with the orthographic projection of the sensing connection line 1875 on the base substrate 110, and the orthographic projection of the third color filter 353 on the base substrate 110 at least partially overlaps with the orthographic projection of the sensing connection line 1875 on the base substrate 110. As a result, the display substrate can adjust the capacitance values ​​of various capacitors in the pixel driving circuit by adjusting the overlap relationship between the optical filters and the sensing connection lines, thereby achieving excellent electrical performance. In some examples, as shown in Figure 11A, the data line 185 comprises a first data line 185A, a second data line 185B, a third data line 185C, and a fourth data line 185D, and in the subpixel group 390, the first data line 185A and the second data line 185B are located between the first color subpixel 300A and the second color subpixel 300B, the first data line 185A is located on the side of the second data line 185B away from the second color subpixel 300B, and the first data line 185A is the second source 184 of the first color subpixel 300A The second data line 185B is connected to the second source 1842 of the second color subpixel 300B, the third data line 185C and the fourth data line 185D are located between the third color subpixel 300C and the fourth color subpixel 300D, the third data line 185 is located on the side of the fourth data line 185D away from the fourth color subpixel 300D, the third data line 185C is connected to the second source 1842 of the third color subpixel 300C, and the fourth data line 185D is connected to the second source 1842 of the fourth color subpixel 300D. Thus, the display board drives one subpixel row with one data line.

[0262] In some examples, as shown in Figure 11A, in the subpixel group 390, the orthographic projection of the first color filter 351 on the base substrate 110 at least partially overlaps with the orthographic projection of the second data line 185A on the base substrate 110, the orthographic projection of the second color filter 352 on the base substrate 110 at least partially overlaps with the orthographic projection of the third data line 185C on the base substrate 110, and the orthographic projection of the third color filter 353 on the base substrate 110 at least partially overlaps with the orthographic projection of the fourth data line 185D on the base substrate 110.

[0263] In some examples, as shown in Figure 11A, the display substrate 100 further comprises a fourth via hole 264 located within the interlayer insulating layer 170, and a second drain 1842 is connected to the conductive block 147 via the fourth via hole 264. The conductive light-shielding structure 122 further comprises a second insulating portion 1222 whose orthographic projection on the base substrate 110 at least partially overlaps with the orthographic projection of the fourth via hole 264 on the base substrate 110. The second insulating portion is part of the conductive light-shielding structure and insulates from other parts of the conductive light-shielding structure. In the display substrate, if the semiconductor layer itself is thin and the second drain region is partially missing, when the etching solution etches downward from the second drain region to the second insulating portion, the second insulating portion is insulated from other parts of the conductive light-shielding structure, so even if the second drain is connected to the second insulating portion via a third via hole, the second drain is not electrically connected to other parts of the conductive light-shielding structure. This allows the display substrate to reduce process risk and improve yield.

[0264] In some examples, as shown in Figure 10A, the second insulating portion 1222 includes a second hollow portion 1222A filled with the material of the buffer layer 130. This allows the second insulating portion 1222 to be insulated from the rest of the conductive light-shielding structure 122 via the second hollow portion 1222A. The second insulating portion 1222 itself may also be the second hollow portion 1222A, meaning that the second insulating portion 1222 may be the portion from which the conductive light-shielding structure 122 has been removed.

[0265] In some examples, as shown in FIG. 10B, the second hollow portion 1222A may be a second hollow ring, that is, the second hollow portion may be an annular hollow portion. Both the inner part and the outer part of the second hollow ring 1222A are made of the material of the conductive light-shielding structure 122. Thereby, the second insulating portion 1222 can be insulated from other parts of the conductive light-shielding structure 122 by disposing the second hollow ring 1222A.

[0266] In some examples, as shown in FIG. 10C, the second insulating portion 1222 is an oxidized portion. That is, a part of the conductive light-shielding structure 122 is oxidized by an oxidation process to form the second insulating portion 1222.

[0267] In some examples, as shown in FIG. 11A, the shapes of the orthographic projections of the first via hole 261 and the fourth via hole 264 on the base substrate 110 are both anisotropic patterns and have long sides.

[0268] In some examples, as shown in FIG. 11A, in the sub-pixel group 390, the long side or the extension direction of the first via hole 261 of the second color sub-pixel 300B and the long side of the first via hole 261 of the third color sub-pixel 300C both extend along the first direction, and the long side of the first via hole 261 of the first color sub-pixel 300A and the long side of the first via hole 261 of the fourth color sub-pixel 300D both extend along the second direction. In the pixel driving circuits of the second color sub-pixel 300B and the third color sub-pixel 300C, since the power supply signal flows from the first source 1821 to the first drain 1841 of the first thin film transistor T1, and the direction from the first source 1821 to the first drain 1841 is the second direction, the long side or the extension direction of the first via hole 261 of the second color sub-pixel 300B and the long side of the first via hole 261 of the third color sub-pixel 300C both extend along the first direction, so that the sizes of the first via hole 261 of the second color sub-pixel 300B and the first via hole 261 of the third color sub-pixel 300C in the first direction increase, and the cross-sectional area of the flowing current increases, thereby reducing the contact resistance.

[0269] In some examples, as shown in Figure 11A, in the subpixel group 390, the long side of the fourth via hole 264 of the second color subpixel 300B and the long side of the fourth via hole 264 of the third color subpixel 300C both extend along the second direction, while the long side of the fourth via hole 264 of the first color subpixel 300A and the long side of the fourth via hole 264 of the fourth color subpixel 300D both extend along the first direction.

[0270] Figure 12 is a schematic plan view of another display substrate according to one embodiment of the present disclosure. As shown in Figure 12, since different color subpixels can use thin-film transistors with different aspect ratios, the positions of the fourth via holes of different color subpixels may differ. For example, as shown in Figure 12, in the subpixel group 390, the centers of the fourth via holes 264 of the first color subpixel 300A, the second color subpixel 300B, the third color subpixel 300C, and the fourth color subpixel 300D are offset in a second direction, the centers of the fourth via holes 264 of the first color subpixel 300A and the fourth color subpixel 300D lie on a first virtual line 401, and the centers of the fourth via holes 264 of the second color subpixel 300B and the third color subpixel 300C lie on a second virtual line 402 parallel to the first virtual line. This prevents the formation of regular bright lines caused by ambient light being reflected by the fourth via hole of the first color subpixel 300A, the fourth via hole of the second color subpixel 300B, the fourth via hole of the third color subpixel 300C, and the fourth via hole of the fourth color subpixel 300D, thereby improving display quality.

[0271] Figure 13 is a schematic cross-sectional view of the first drain of a display substrate according to one embodiment of the present disclosure. As shown in Figure 13, the conductive layer 180 or first drain 1841 comprises a first submetal layer 1841A and a second submetal layer 1841B laminated in a direction perpendicular to the base substrate 110, wherein the material of the first submetal layer 1841A is copper and the material of the second submetal layer 1841B is a molybdenum titanium alloy.

[0272] One embodiment of the present disclosure further provides a display device. Figure 14 is a schematic diagram of a display device according to one embodiment of the present disclosure. As shown in Figure 14, the display device 500 comprises the display substrate 100. Thereafter, the display device has beneficial technical effects corresponding to the technical effects of the provided display substrate. For example, in the display device, the conductive structure is connected to the first recess via the first contact hole. Because the first recess is recessed into the conductive light-shielding structure, the area of ​​the surface of the first recess adjacent to the conductive layer is larger than the orthographic area of ​​the first recess on the base substrate. Thereafter, the contact area between the conductive structure, such as the first drain, and the conductive light-shielding structure is increased, the contact becomes more sufficient, thereby reducing contact resistance, improving the electrical connection effect between the conductive structure and the conductive light-shielding structure, and effectively improving the charge-discharge efficiency of the capacitor formed by the conductive structure.

[0273] For example, the display device may be an electronic product such as a television, tablet PC, laptop computer, digital photo frame, navigator, or smartphone.

[0274] One embodiment of the present disclosure further provides a method for manufacturing a display substrate. Figure 15 is a flowchart of a method for manufacturing a display substrate according to one embodiment of the present disclosure. As shown in Figure 15, the method for manufacturing the display substrate includes the following steps S101 to S107.

[0275] Step S101: A conductive light-shielding material layer is formed on the base substrate.

[0276] For example, the base substrate may be a transparent substrate made of inorganic materials such as glass and substrates. Alternatively, the base substrate may also be a transparent substrate made of organic materials such as polyimide, polycarbonate, or polyethylene terephthalate.

[0277] For example, the base substrate may be a flexible substrate such as a polyimide substrate. Of course, the embodiments of this disclosure include, but are not limited to, a rigid substrate.

[0278] For example, the material of the conductive light-shielding layer may be selected from one or more of molybdenum and titanium. Of course, the embodiments of this disclosure include, but are not limited to, the material of the conductive light-shielding layer may be made from other materials.

[0279] For example, a conductive light-shielding material layer is formed on a base substrate by a film deposition process such as a sputtering process or a vapor deposition process.

[0280] Step S102: The conductive light-shielding material layer is patterned to form a conductive light-shielding structure.

[0281] For example, the process of patterning a conductive light-shielding material layer may include exposure, development, and etching processes.

[0282] For example, first, a photoresist is applied to a conductive light-shielding material layer, then a photoresist pattern is formed on the conductive light-shielding material layer by an exposure and development process, then the conductive light-shielding material is etched using the photoresist pattern, and finally the photoresist pattern is peeled off to form a conductive light-shielding structure.

[0283] In step S103, a buffer layer is formed on the side of the conductive light-shielding structure that is away from the base substrate.

[0284] For example, the buffer layer material may be at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0285] For example, the thickness of the buffer layer may be in the range of 380-420 nanometers. Of course, the embodiments of this disclosure include, but are not limited to, the thickness of the buffer layer, and it may be set according to actual requirements.

[0286] In step S104, a semiconductor layer is formed on the side of the buffer layer that is away from the conductive light-shielding structure.

[0287] For example, the material of the semiconductor layer may be an oxide semiconductor such as indium gallium zinc oxide (IGZO).

[0288] For example, the semiconductor layer is formed on the side away from the conductive light-shielding structure of the buffer layer by a vapor deposition process. Of course, the embodiments of the present disclosure include but are not limited to this, and the semiconductor layer can also be formed by other suitable processes.

[0289] For example, the thickness of the semiconductor layer may be in the range of 35 - 45 nanometers, for example, 40 nanometers. Of course, the embodiments of the present disclosure include but are not limited to this, and the thickness of the semiconductor layer can be set according to actual needs.

[0290] Step S105: Form an interlayer insulating layer on the side of the semiconductor layer away from the buffer layer.

[0291] For example, the material of the interlayer insulating layer may be selected from at least one of silicon nitride, silicon oxide, and silicon oxynitride. Of course, the embodiments of the present disclosure include but are not limited to this, and the material of the interlayer insulating layer may be other materials. Note that the material of the interlayer insulating layer may be the same as or different from the material of the buffer layer. Even if the materials of the interlayer insulating layer and the buffer layer are the same, different process temperatures can be used for the interlayer insulating layer and the buffer layer, so that the densities of the formed film layers are also different, and furthermore, the etched taper angles of the interlayer insulating layer and the buffer layer are also different.

[0292] For example, the thickness of the interlayer insulating layer may be in the range of 350 - 600 nanometers, for example, 400 nanometers. Of course, the embodiments of the present disclosure include but are not limited to this, and the thickness of the interlayer insulating layer can be set according to actual needs.

[0293] Step S106: Form a first contact hole in the interlayer insulating layer and the buffer layer.

[0294] For example, a first contact hole is formed in the interlayer insulating layer and the buffer layer by an etching process (e.g., a wet etching process).

[0295] In step S107, a conductive layer is formed on the side of the interlayer insulating layer away from the semiconductor layer. The conductive layer comprises a conductive structure such as a first drain, and the conductive light-shielding structure comprises a first main body and a first recess. The average thickness of the first recess in the direction perpendicular to the base substrate is smaller than the average thickness of the first main body in the direction perpendicular to the base substrate. A first contact hole penetrates the interlayer insulating layer and the buffer layer. The conductive structure is connected to the first recess via the first contact hole. The area of ​​the surface of the first recess adjacent to the conductive layer is larger than the orthographic projection area of ​​the first recess on the base substrate.

[0296] In the method for manufacturing a display substrate according to an embodiment of the present disclosure, the conductive light-shielding structure comprises a first main body and a first recess, and the first drain is connected to the first recess via a first contact hole. Because the first recess is recessed in the conductive light-shielding structure, the area of ​​the surface of the first recess adjacent to the first drain is larger than the area of ​​the first recess projected onto the base substrate. As a result, the display substrate manufactured by this method has a larger contact area between the first drain and the conductive light-shielding structure, resulting in more sufficient contact, which reduces contact resistance and improves the electrical connection effect between the first drain and the conductive light-shielding structure, thereby effectively improving the charge and discharge efficiency of the capacitor formed by the conductive structure.

[0297] For example, the material of the conductive layer may be selected from one or more of copper, molybdenum, and titanium. Of course, the embodiments of this disclosure include, but are not limited to, the conductive layer may be made of other materials.

[0298] In some examples, the thickness of the conductive light-shielding structure in the direction perpendicular to the base substrate is in the range of 90-120 nanometers, and the thickness of the conductive layer in the direction perpendicular to the base substrate is in the range of 200-600 nanometers.

[0299] In some examples, the manufacturing method of the display substrate includes the step of forming a first contact hole in the interlayer insulating layer and the buffer layer, and the step of forming a first buffer portion and a second buffer portion in the buffer layer, wherein the side of the first buffer portion away from the base substrate is in contact with a conductive layer, the side of the first buffer portion close to the base substrate is in contact with a conductive light-shielding structure, the side of the second buffer portion away from the base substrate is in contact with the interlayer insulating layer, and the side of the second buffer portion close to the base substrate is in contact with a conductive light-shielding structure. As a result, when the conductive structure is deposited in the first contact hole, the first buffer portion supports a part of the conductive structure, preventing disconnection defects due to excessive steps or excessive gradient angles of the conductive structure. As a result, the display substrate has a high yield.

[0300] In some examples, the first contact hole has a side wall, the side wall comprises at least a first sub-side wall located in the interlayer insulating layer and a second sub-side wall located in the buffer layer, the angle between the first sub-side wall and the base substrate is a first gradient angle, the angle between the second sub-side wall and the base substrate is a second gradient angle, the first gradient angle is smaller than the second gradient angle, and the contact portion between the second sub-side wall and the first buffer portion is located between the first buffer portion and the second buffer portion.

[0301] In some examples, the side wall of the first contact hole further comprises a third sub-side wall located in the first buffer section, and the angle between the third sub-side wall and the base substrate forms a third gradient angle, which is different from the first, second, and third gradient angles. A specific description of the side wall of the first contact hole can be found in the related descriptions in Figures 6A and 6B, and will not be repeated here.

[0302] In some examples, the method for manufacturing the display substrate further includes the steps of forming a planar layer having an anode hole on the side away from the interlayer insulating layer of a conductive layer, such as a source-drain metal layer, and forming an anode layer on the side of the planar layer away from the conductive layer to form a plurality of subpixels on a base substrate, each subpixel having an anode, the anode comprising a light-emitting part, a drive part, and an extension connecting the light-emitting part and the drive part, the drive part being at least partially located within the anode hole, and in at least one subpixel, the orthographic projection of the first contact hole on the base substrate at least partially overlaps with the orthographic projection of the drive part on the base substrate, and the display substrate has power lines located in the conductive layer, The device further comprises a sensing line located in a conductive layer, the power line and sensing line are arranged in a first direction and both extend in a second direction intersecting the first direction, and the plurality of subpixels comprises a first subpixel pair and a second subpixel pair, the first subpixel pair comprises two subpixels located on both sides of the power line, the second subpixel pair comprises two subpixels located on both sides of the sensing line, the first subpixel pair and the second subpixel pair are arranged alternately in the first direction, and in two subpixels of the second subpixel pair, the orthographic projection of the anode hole and the first recess on the base substrate has a first overlap region, the area of ​​the first overlap region is smaller than the area of ​​the orthographic projection of the first contact hole on the base substrate.Therefore, in two subpixels of the second subpixel pair, the anode hole and the first recess have a first overlap region, and therefore, when the first recess is thinned to reduce light shielding, the anode at the position of the anode hole has a curved interface, thereby allowing light to be focused and avoiding the effect of light transmitted through the first recess on normal display.

[0303] In some examples, the anode further includes a recessed structure at the edge of the anode hole, with the recess direction oriented toward the conductive light-shielding structure. This allows the recessed structure to reflect light transmitted through the first recess when the first recess is thinned to reduce light-shielding performance, since it has at least two inclined surfaces. Furthermore, since the recessed structure itself is a microstructure, it can scatter light transmitted through the first recess, thereby further avoiding the effect of light transmitted through the first recess on normal display. The edge position of the anode hole refers to the boundary between the anode hole and the surface of the planarization layer that separates from the semiconductor layer.

[0304] In some examples, the conductive layer further comprises a first source and a first drain, and the conductive structure is the first drain.

[0305] In some examples, the conductive layer further comprises a first source, and the semiconductor layer comprises a first active layer comprising a first channel region and a first source region and a first drain region located on both sides of the first channel region, and the method for manufacturing the display substrate further comprises forming a first contact hole in the interlayer insulating layer and the buffer layer, and forming a first via hole and a second via hole in the interlayer insulating layer, wherein the first source is connected to the first source region via the first via hole, and the first drain is connected to the first drain region via the second via hole.

[0306] In some cases, the interlayer insulating layer and buffer layer are patterned simultaneously by the same etching process to form the first via hole and the first contact hole. In this case, even if the bottom size of the first contact hole is small, the area of ​​the surface of the first recess adjacent to the first drain is larger than the orthographic projection area of ​​the first recess on the base substrate. Therefore, the display substrate manufactured by this method of manufacturing the display substrate can increase the contact area between the first drain and the conductive light-shielding structure, resulting in better contact, which in turn reduces contact resistance and improves the electrical connection effect between the first drain and the conductive light-shielding structure.

[0307] In some examples, the interlayer insulating layer and buffer layer may be patterned by a halftone mask process to form the first via hole and the first contact hole.

[0308] For example, the step of patterning an interlayer insulating layer and a buffer layer by a halftone mask process to form a first via hole and a first contact hole includes the steps of forming a first photoresist on the side of the interlayer insulating layer away from the base substrate, exposing and developing the first photoresist using a first halftone mask to form a first photoresist pattern comprising a first photoresist complete removal area, a first photoresist partial removal area, and a first photoresist holding area, etching the interlayer insulating layer using the first photoresist pattern as a mask to remove the interlayer insulating layer corresponding to the first photoresist complete removal area, a step of ashing the first photoresist pattern to remove the first photoresist partial removal area and thin the first photoresist holding area to form a second photoresist pattern, and etching the buffer layer using the second photoresist pattern as a mask, wherein the orthographic projection of the first contact hole on the base substrate coincides with the orthographic projection of the first photoresist complete removal area on the base substrate, and the orthographic projection of the first via hole on the base substrate coincides with the orthographic projection of the first photoresist partial removal area on the base substrate. The above definition of overlap includes both complete overlap and partial overlap (overlap of more than 80%).

[0309] In some examples, the conductive light-shielding structure further comprises a first insulating portion in which the orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate, and the orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the first source region on the base substrate. The first insulating portion is part of the conductive light-shielding structure and insulates from the other parts of the conductive light-shielding structure. If the semiconductor layer itself is thin and the first source region is partially missing, when the etching solution etches downward from the first source region to the first insulating portion, the first insulating portion is insulated from the other parts of the conductive light-shielding structure, so even if the first source is connected to the first insulating portion via the first via hole, the first source is not electrically connected to the other parts of the conductive light-shielding structure. This allows the display substrate to reduce process risk and improve yield.

[0310] For example, as shown in Figure 10A, the first insulating portion 1221 includes a first hollow portion 1221A filled with the material of the buffer layer 130. Thus, the first insulating portion 1221 may be insulated from other parts of the conductive light-shielding structure 122 via the first hollow portion 1221A. Note that the first insulating portion 1221 itself may be the first hollow portion 1221A; in other words, the first insulating portion 1221 may be the portion from which the conductive light-shielding structure 122 has been removed.

[0311] For example, as shown in Figure 10B, the first hollow portion 1221A may be a first hollow ring, that is, the first hollow portion may be an annular hollow portion. Both the inner and outer portions of the first hollow ring 1221A are made of the same material as the conductive light-shielding structure 122. Thus, the first insulating portion 1221 achieves isolation from other parts of the conductive light-shielding structure 122 by arranging the first hollow ring 1221A.

[0312] For example, as shown in Figure 10C, the first insulating portion 1221 is an oxidized portion. In other words, the first insulating portion 1221 can be formed by oxidizing a part of the conductive light-shielding structure 122 through an oxidation process.

[0313] In some examples, when the first insulating portion is the first insulating portion 1221 shown in Figures 10A and 10B, the step of patterning the conductive light-shielding material layer to form a conductive light-shielding structure includes the step of patterning the conductive light-shielding material layer by the same patterning process to form a first body portion, a first recess, and a first hollow portion. In other words, the first recess and the first hollow portion are formed by the same patterning process, thereby eliminating the masking process and further reducing costs.

[0314] In some examples, the step of patterning a conductive light-shielding material layer to form a conductive light-shielding structure includes the steps of forming a photoresist on the side of the conductive light-shielding structure away from the base substrate, exposing and developing the photoresist using a second halftone mask to form a third photoresist pattern comprising a second photoresist complete removal portion, a second photoresist partial removal portion, and a second photoresist holding portion, etching the conductive light-shielding material layer using the third photoresist pattern as a mask to remove the conductive light-shielding material layer corresponding to the second photoresist complete removal portion, ashing the third photoresist pattern to remove the second photoresist partial removal portion and thin the second photoresist holding portion to form a fourth photoresist pattern, and etching the conductive light-shielding material layer using the fourth photoresist pattern as a mask, wherein the orthographic projection of the first main body portion on the base substrate coincides with the orthographic projection of the second photoresist holding portion on the base substrate, and the orthographic projection of the first recess on the base substrate coincides with the orthographic projection of the second photoresist partial removal portion on the base substrate. As a result, the manufacturing method can form the first recess and the first hollow portion using a halftone mask in the same masking process, thereby eliminating the masking process and further reducing costs. The above overlap includes complete overlap and partial overlap (overlap of more than 80%).

[0315] In some examples, the first recess includes a first edge portion, and the thickness of at least the portion of the first recess adjacent to the edge, for example, the first edge portion perpendicular to the base substrate, decreases continuously and gradually in the direction from the edge toward the center of the first recess. The average thickness of the first recess perpendicular to the base substrate is smaller than the average thickness of the first body perpendicular to the base substrate, which may affect the light shielding properties of the first recess. Because the thickness of the first recess perpendicular to the base substrate decreases continuously and gradually, even if light can pass through the first recess, the first recess can focus the light, thereby preventing ambient light from passing through the entire display substrate and avoiding the effect of ambient light on the normal display of the display substrate.

[0316] In some examples, the gradient angle of at least the portion of the first recess adjacent to the edge, i.e., the portion adjacent to the conductive layer of the first edge, changes continuously in a direction perpendicular to the base substrate. This allows the first recess to focus the light, even if it passes through it, thereby preventing the light from passing through the entire display substrate and being observed by the user.

[0317] In some examples, the surface of the first recess adjacent to the first drain is a continuous arcuate surface, or a combined surface formed by combining at least some continuous arcuate surfaces and at least some planes. Even if the continuous arcuate surface, or the combined surface formed by combining at least some continuous arcuate surfaces and at least some planes, can focus light and thereby allow light to pass through the first recess, the first recess can prevent light from passing through the entire display substrate and being observed by the user.

[0318] In some examples, the orthographic projection of the first contact hole on the base substrate overlaps, at least partially, with the orthographic projection of the first recess on the base substrate. This allows the first drain of the conductive layer to be connected to the first recess via the first contact hole.

[0319] In some examples, the fourth gradient angle α of the surface adjacent to the conductive layer of the first edge satisfies the following equation.

number

[0320] In some examples, when k=2, the fourth gradient angle is in the range of 1-π / 18.

[0321] For example, the size of the first recess in the orthographic projection parallel to the base substrate is in the range of 5-10 microns.

[0322] In some examples, the step of forming a first contact hole in the interlayer insulating layer and the buffer layer includes the step of forming a first buffer portion and a second buffer portion in the buffer layer, wherein the first buffer portion is located within the first contact hole and is positioned in contact with the conductive light-shielding structure, and the second buffer portion is located on the side of the first buffer portion away from the center of the first recess.

[0323] In some examples, the step of forming a conductive layer on the side of the interlayer insulating layer away from the semiconductor layer may include forming a source-drain metal material layer on the side of the interlayer insulating layer away from the semiconductor layer, for example, by a deposition process, and then etching the formed source-drain metal material layer using a mask to form a conductive layer having the first drain.

[0324] In some examples, the method for manufacturing the display substrate further includes the steps of forming a passivation layer on the side of the conductive layer away from the base substrate, forming a color filter layer on the side of the passivation layer away from the conductive layer, forming a planarization layer on the side of the color filter layer away from the passivation layer, and forming an anode layer on the side of the planarization layer away from the color filter layer.

[0325] For example, the material for the planarization layer may be an organic material such as an organic resin. Of course, the embodiments of this disclosure include, but are not limited to, this.

[0326] For example, each subpixel further comprises an anode located in the anode layer. The display substrate further comprises a third via hole located in the passivation layer, and the anode is connected to a first drain via the third via hole. Thus, the display substrate can apply a drive current to the anode by a first thin-film transistor, driving the light-emitting layer corresponding to the anode to produce light-emitting display.

[0327] In some examples, the method for manufacturing the display substrate further includes the step of forming a pixel definition layer on the side of the anode layer away from the color filter layer. The pixel definition layer comprises a plurality of apertures, which are arranged in a one-to-one correspondence with the anodes of a plurality of subpixels, and each aperture partially exposes the corresponding anode.

[0328] In some examples, the method for manufacturing the display substrate further includes the step of forming an emissive layer on the side of the pixel definition layer away from the anode layer. The emissive layer contacts the exposed portions of the anodes of the subpixels through the plurality of openings.

[0329] In some examples, the method for manufacturing the display substrate further includes the step of forming a cathode on the side away from the anode of the light-emitting layer. Thus, the anode, light-emitting layer, and cathode can constitute a light-emitting unit.

[0330] The following points need to be explained.

[0331] (1) The drawings of the embodiments of this disclosure relate only to the structures relating to the embodiments of this disclosure, and other structures should refer to conventional designs.

[0332] (2) Features of the same and different embodiments of the present disclosure can be combined with each other, as long as they do not contradict each other.

[0333] The foregoing are merely exemplary embodiments of the present disclosure and do not limit the scope of protection of the present disclosure, which is determined by the appended claims. [Explanation of symbols]

[0334] 100 Display board 110 Base board 122 Conductive light-shielding structure 130 buffer layers 140 Semiconductor Layers 170 Interlayer insulating layer 180 Conductive layer 181 Conductive structure 251 First Contact Hole 300 subpixels 1220 First main body 1224 First recess

Claims

1. A display board, The device comprises a base substrate and a plurality of subpixels located on the base substrate, Each of the aforementioned subpixels is A conductive light-shielding structure located on the base substrate, A buffer layer located on the side of the conductive light-shielding structure away from the base substrate, A semiconductor layer located on the side of the buffer layer away from the conductive light-shielding structure, An interlayer insulating layer located on the side of the semiconductor layer away from the buffer layer, The interlayer insulating layer comprises a conductive layer located on the side away from the semiconductor layer and having a conductive structure, The conductive light-shielding structure comprises a first main body and a first recess, The display board further comprises a first contact hole, The first contact hole penetrates the interlayer insulating layer and the buffer layer, The conductive structure is electrically connected to the first recess via the first contact hole, the area of ​​the surface of the first recess adjacent to the conductive layer is larger than the orthographic area of ​​the first recess on the base substrate, and the average thickness of the first recess in the direction perpendicular to the base substrate is smaller than the average thickness of the first main body in the direction perpendicular to the base substrate. The aforementioned buffer layer, A first buffer portion is provided, the side away from the base substrate being in contact with the conductive layer and the side closer to the base substrate being in contact with the conductive light-shielding structure, A display board comprising: a second buffer portion, the side away from the base substrate being in contact with the interlayer insulating layer and the side closer to the base substrate being in contact with the conductive light-shielding structure.

2. The first contact hole is provided with a side wall, The aforementioned side wall is The first sub-sidewall located in the interlayer insulating layer, The buffer layer comprises at least a second sub-side wall located in the buffer layer, The display substrate according to claim 1, wherein the angle between the first sub-side wall and a plane parallel to the plane on which the main surface of the base substrate is located forms a first gradient angle, the angle between the second sub-side wall and a plane parallel to the plane on which the main surface of the base substrate is located forms a second gradient angle, the first gradient angle is smaller than the second gradient angle, and the contact portion between the second sub-side wall and the first buffer portion is located between the first buffer portion and the second buffer portion.

3. The side wall of the first contact hole is The first buffer section further comprises a third sub-side wall, The display substrate according to claim 2, wherein the angle between the third sub-side wall and the plane parallel to the plane on which the main surface of the base substrate is located is a third gradient angle, and is different from the first gradient angle, the second gradient angle, and the third gradient angle.

4. The display substrate according to claim 3, wherein, along the radial direction of the first contact hole, the ratio of the length of the first buffer portion to the average thickness of the first buffer portion is greater than the ratio of the projected length of the first sub-sidewall on the base substrate to the average thickness of the interlayer insulating layer.

5. The display substrate according to claim 3, wherein, along the radial direction of the first contact hole, the ratio of the projected length of the first sub-sidewall on the base substrate to the average thickness of the interlayer insulating layer is greater than the ratio of the projected length of the second sub-sidewall on the base substrate to the average thickness of the buffer layer.

6. The display board according to claim 3, wherein the second gradient angle is greater than the third gradient angle, and the first gradient angle is greater than the third gradient angle.

7. The size L of the first recess in the direction parallel to the base substrate in the orthographic projection on the base substrate satisfies the following equation: [Math 1] The display substrate according to claim 6, wherein A is the maximum thickness of the first buffer portion, B is the maximum thickness of the second buffer portion, C is the maximum thickness of the interlayer insulating layer, β is the first gradient angle, γ is the second gradient angle, θ is the third gradient angle, and D is the maximum size of the first contact hole in the direction parallel to the base substrate in the orthographic projection on the base substrate.

8. The display substrate according to any one of claims 1 to 7, wherein the first recess has a first edge portion in which the thickness in a direction perpendicular to the base substrate gradually decreases in the direction from the edge of the first recess toward the center of the first recess.

9. The first recess is provided with a first edge portion, and the fourth gradient angle α of the surface of the first edge portion adjacent to the conductive layer satisfies the following equation: [Math 2] The display substrate according to any one of claims 1 to 8, wherein Lmax is the maximum hole diameter of the first recess in orthographic projection on the base substrate, H is the average thickness of the first main body, k is a constant greater than 1 and less than or equal to 2, and the unit of the fourth gradient angle α is radians.

10. The first recess comprises a first edge portion, and the fourth gradient angle α of the surface of the first edge portion adjacent to the conductive layer is smaller than the third gradient angle of the third sub-side wall, satisfying the following equation: [Math 3] A display substrate according to any one of claims 3 to 7, wherein in the formula, A is the maximum thickness of the first buffer portion, B is the maximum thickness of the second buffer portion, C is the maximum thickness of the interlayer insulating layer, β is the first gradient angle, γ is the second gradient angle, θ is the third gradient angle, and D is the maximum size of the first contact hole in the direction parallel to the base substrate in the orthographic projection on the base substrate.

11. A planarization layer located on the side of the conductive layer away from the semiconductor layer and having an anode hole, The planarized layer is located on the side away from the semiconductor layer and comprises a light-emitting portion, a drive portion, and an extension portion connecting the light-emitting portion and the drive portion, and further comprises an anode in which the drive portion is at least partially located within the anode hole, In at least one of the subpixels, the orthographic projection of the first contact hole on the base substrate overlaps at least partially with the orthographic projection of the drive unit on the base substrate. The system further comprises a power line located in the conductive layer and a sensing line located in the conductive layer, The power line and the sensing line are arranged in a first direction, and both extend in a second direction that intersects the first direction. The plurality of subpixels comprises a first subpixel pair and a second subpixel pair, the first subpixel pair comprises two subpixels located on both sides of the power line, the second subpixel pair comprises two subpixels located on both sides of the sensing line, and the first subpixel pair and the second subpixel pair are arranged alternately in the first direction. The display substrate according to claim 10, wherein in the two subpixels of the second subpixel pair, the orthographic projection of the anode hole and the first recess on the base substrate has a first overlapping region, and the area of ​​the first overlapping region is smaller than the area of ​​the orthographic projection of the first contact hole on the base substrate.

12. The display substrate according to claim 11, wherein the anode further comprises a recessed structure at the edge position of the anode hole, the recess direction of which is toward the conductive light-shielding structure.

13. The display substrate according to any one of claims 1 to 12, wherein the orthographic projection of the first contact hole on the base substrate at least partially overlaps with the orthographic projection of the first recess on the base substrate.

14. The display substrate according to any one of claims 1 to 13, wherein each sub-pixel is provided with a pixel driving circuit, the pixel driving circuit is provided with a first thin-film transistor, and the conductive structure is the first drain of the first thin-film transistor.

15. The first thin-film transistor is A first active layer located in the semiconductor layer and comprising a first channel region, and first source regions and first drain regions located on both sides of the first channel region, The first source located in the conductive layer further comprises, The display board according to claim 14, further comprising a first via hole and a second via hole, wherein the first via hole and the second via hole are located within the interlayer insulating layer, the first source is connected to the first source region via the first via hole, and the first drain is connected to the first drain region via the second via hole.

16. The conductive light-shielding structure is The display substrate according to claim 15, further comprising a first insulating portion in which the orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate, and the orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the first source region on the base substrate.

17. A gate insulating layer located between the semiconductor layer and the interlayer insulating layer, A gate layer located between the gate insulating layer and the interlayer insulating layer, A passivation layer located on the side of the conductive layer away from the base substrate, A color filter layer located on the side of the passivation layer away from the conductive layer, comprising at least three different colored optical filters, Furthermore, it is equipped with an anode layer, The display substrate according to claim 11, wherein the planarization layer is located on the side of the color filter layer away from the passivation layer, the anode layer is located on the side of the planarization layer away from the color filter layer, and the anode is located in the anode layer.

18. The conductive light-shielding structure further comprises power connection lines arranged in the same layer as the aforementioned conductive light-shielding structure, The display substrate according to claim 17, wherein the power connection line comprises a second main body and a plurality of power recesses, the average thickness of each power recess in the direction perpendicular to the base substrate is smaller than the average thickness of the second main body in the direction perpendicular to the base substrate, and the area of ​​the surface of each power recess adjacent to the conductive layer is larger than the orthographic area of ​​each power recess on the base substrate.

19. The display substrate according to claim 18, wherein the orthographic projection of at least one of the plurality of power recesses on the base substrate at least partially overlaps with the orthographic projection of the optical filter of the color filter layer on the base substrate.

20. The conductive light-shielding structure further comprises a sensing connection wire arranged in the same layer as the aforementioned conductive light-shielding structure, The display substrate according to claim 17, wherein the sensing connection line comprises a third main body and a plurality of sensing recesses, the average thickness of each sensing recess in the direction perpendicular to the base substrate is smaller than the average thickness of the third main body in the direction perpendicular to the base substrate, and the area of ​​the surface of each sensing recess adjacent to the conductive layer is larger than the area of ​​the sensing recess as orthogonal projection onto the base substrate.

21. The display substrate according to claim 20, wherein the orthographic projection of at least one of the plurality of sensing recesses on the base substrate at least partially overlaps with the orthographic projection of the optical filter of the color filter layer on the base substrate.

22. The display substrate according to claim 11, wherein each subpixel comprises a drive region and a light-emitting region, the conductive light-shielding structure is located in the drive region, the drive portion of the anode is located in the drive region, and the light-emitting portion of the anode is located in the light-emitting region.

23. A display device, A display device comprising a display board according to any one of claims 1 to 22.

Images