Trigger unit design method

Abstract

This application discloses a method for designing a trigger unit, which includes the steps of: analyzing a signal delay of a clock control signal in a digital circuit; selecting a clock gating circuit from a plurality of different types of clock gating circuits according to the signal delay of the clock control signal; and combining at least one edge triggered flip-flop and the selected clock gating circuit into a trigger unit, in which the plurality of different types of clock gating circuits enable or disable a first clock signal according to the clock control signal to generate a second clock signal, and the edge triggered flip-flop transmits data at an edge of the second clock signal. The design method for the trigger unit selects a clock gating circuit from a plurality of different types of clock gating circuits according to the delay condition of the clock control signal, which can not only eliminate glitches in the clock signal generated by the clock gating circuit, but also reduce the number of logic elements of the clock gating circuit, reduce the power consumption of the clock gating circuit, and is suitable for a flip-flop group with any number of edge triggered flip-flops.

Description

Technical Field

[0005]

[0001] This application claims the priority of a Chinese patent application filed on January 28, 2022, with an application number of 202210107336.2 and a title of "Design Method of Trigger Unit", and incorporates it herein by reference to all the specifications, claims, attached drawings, and abstract of the above-mentioned Chinese patent application.

[0002] The present invention relates to the technology of integrated circuits, and more specifically, to a design method of a trigger unit.

Background Art

[0003] Electronic design automation software (EDA) is an important tool for processes such as functional design, integration, verification, and physical design of integrated circuits. In digital circuit design EDA, a standard cell library is a basic part of the back-end design process of an integrated circuit chip. By using pre-designed and optimized library units, automatic logic integration and layout wiring can be performed to improve design efficiency. Through the optimized library units, the performance of the circuit can be improved and power consumption can be reduced.

[0004] In the digital part of an integrated circuit, a gate circuit is used to perform combinational logic on multiple signals to generate a logic operation result, and an edge-triggered flip-flop is used to store the logic operation result. According to the differences in logic operations, gate circuits can be divided into AND gates, OR gates, NOT gates, NAND gates, ANDOR gates, XOR gates, etc. The logic operation result of a gate circuit is, for example, a pulse signal, and a steady-level signal corresponding to the logic state is generated based on this pulse signal.

[0005] An edge-triggered flip-flop is an information storage device with memory capabilities, used to store the results of memory logic operations. For example, edge-triggered flip-flops are the most basic logic units that make up various sequence digital circuit modules and are important unit circuits in digital circuit modules. Referring to Figures 1 and 2, depending on the type of edge-triggered flip-flop, the edge-triggered flip-flop 110 is triggered on the rising or falling edge of a clock signal, allowing input data to be transmitted from the input terminal to the output terminal in order to acquire output data. The edge-triggered flip-flop 110 is, for example, a D-type flip-flop. For example, a D-type flip-flop transmits data on the trigger edge of a clock signal and holds the data unchanged until the next trigger edge.

[0006] The power consumption of an edge-triggered flip-flop consists of static power consumption and dynamic power consumption. Static power consumption is mainly caused by leakage current, while dynamic power consumption is mainly caused by signal inversion. Inversion of the data signal of an edge-triggered flip-flop causes additional data power consumption in the subsequent combinational logic, and inversion of the clock signal also causes clock power consumption in the edge-triggered flip-flop itself. Therefore, it is necessary to optimize the design of edge-triggered flip-flops in the digital circuit EDA standard cell library, and it is expected that the dynamic power consumption of edge-triggered flip-flops will be further reduced. [Overview of the Initiative]

[0007] In view of the above problems, the present invention provides a method for designing a trigger unit that selects a clock gating circuit from a plurality of different types of clock gating circuits according to the delay condition of the clock control signal, reduces the number of logic elements of the clock gating circuit, and reduces the power consumption of the clock gating circuit.

[0008] According to the present invention, a method for designing a trigger unit is provided, which includes the steps of: analyzing the signal delay of a clock control signal in a digital circuit; selecting a clock gating circuit from a plurality of different types of clock gating circuits according to the signal delay of the clock control signal; and combining at least one edge-triggered flip-flop and the selected clock gating circuit in a trigger unit, wherein the plurality of different types of clock gating circuits generate a second clock signal by enabling or disabling a first clock signal according to the clock control signal, and the edge-triggered flip-flop transmits data on the edge of the second clock signal.

[0009] Preferably, the plurality of different types of clock gating circuits include at least one of a first clock gating circuit and a second clock gating circuit, and the first clock gating circuit and the second clock gating circuit maintain the second clock signal at a predetermined level for at least one clock cycle in which the clock signal is reversed from an enabled state to an disabled state.

[0010] Preferably, during a clock cycle in which the clock control signal remains in an inactive state, the first clock gating circuit and the second clock gating circuit maintain the second clock signal at the predetermined level.

[0011] Preferably, in a clock cycle in which the clock control signal inverts from an inactive state to an active state, the first clock gating circuit and the second clock gating circuit copy the first clock signal as the second clock signal.

[0012] Preferably, in a clock cycle in which the clock control signal remains active, the first clock gating circuit and the second clock gating circuit copy the first clock signal as the second clock signal.

[0013] Preferably, the first clock gating circuit generates the second clock signal by performing a logical OR operation on the inverted signal of the clock control signal and the first clock signal.

[0014] Preferably, the second clock gating circuit generates the second clock signal by performing a logical AND operation on the clock control signal and the first clock signal.

[0015] Preferably, the plurality of different types of clock gating circuits further include a third clock gating circuit, the third clock gating circuit maintaining the second clock signal at a predetermined level for at least the next clock cycle in which the clock control signal inverts from an enabled state to an disabled state.

[0016] Preferably, the third clock gating circuit generates the second clock signal by performing a logical AND operation on the latch signal of the clock control signal and the first clock signal.

[0017] Preferably, the signal delay of the clock control signal varies within a range between a minimum delay and a maximum delay.

[0018] Preferably, if both the minimum delay and the maximum delay are in the first level stage of the first clock signal, one of the first clock gating circuit and the second clock gating circuit is selected according to the start edge of the first level stage.

[0019] Preferably, if the starting edge of the first level stage is a rising edge, the selected clock gating circuit is the first clock gating circuit.

[0020] Preferably, if the starting edge of the first level stage is a falling edge, the selected clock gating circuit is the second clock gating circuit.

[0021] Preferably, the predetermined level is the level of the first level stage.

[0022] Preferably, when the minimum delay and the maximum delay are respectively at the first level stage and the second level stage of the first clock signal, the selected clock gating circuit is a third clock gating circuit.

[0023] Preferably, the predetermined level is the level of the second level stage.

[0024] Preferably, the step of combining with the trigger unit selects the clock cycle of data transmission by the edge-triggered flip-flop according to the type of the selected clock gating circuit or the type of the edge-triggered flip-flop.

[0025] Preferably, when the start edge of the first level stage is the same as the trigger edge of the edge-triggered flip-flop, in the clock cycle when the clock control signal is inverted, the second clock signal provides the trigger edge of the edge-triggered flip-flop.

[0026] Preferably, when the start edge of the first level stage is on the opposite side of the trigger edge of the edge-triggered flip-flop, in the clock cycle before the clock cycle when the clock control signal is inverted, the second clock signal provides the trigger edge of the edge-triggered flip-flop.

[0027] Preferably, the step of combining with the trigger unit includes the step of inverting the second clock signal to generate a third clock signal.

[0028] Preferably, when the start edge of the first-level stage is the same as the trigger edge of the edge-trigger flip-flop, in the clock cycle in which the clock control signal is inverted, the second clock signal provides the trigger edge of the edge-trigger flip-flop.

[0029] Preferably, when the start edge of the first-level stage is on the opposite side of the trigger edge of the edge-trigger flip-flop, in the clock cycle in which the clock control signal is inverted, the third clock signal provides the trigger edge of the edge-trigger flip-flop.

[0030] Preferably, the high level of the clock control signal indicates an active state, and the low level indicates an inactive state.

[0031] According to an embodiment of the present invention, in a method for designing a trigger unit, a clock gating circuit is selected from a plurality of different types of clock gating circuits according to the delay condition of a clock control signal. By utilizing the circuit characteristics of different types of clock gating circuits under different delay conditions of the clock control signal, glitches of the clock signal generated by the clock gating circuit can be removed. In the clock cycle in which the clock control signal maintains an inactive state, the second clock signal generated by the clock gating circuit disables the clock inversion and data transmission of the edge-trigger flip-flop, thereby reducing the dynamic power consumption of the edge-trigger flip-flop.

[0032] In a preferred embodiment, if the minimum and maximum delay ranges of the clock control signal are both in a single level stage, and the starting edge of that level stage is a rising edge, a first clock gating circuit is selected, and the first clock gating circuit performs a logical OR operation on the inverted signal of the clock control signal and the first clock signal to generate the second clock signal. The clock gating circuit can eliminate glitches in the clock signal generated, and in the clock cycle in which the clock control signal inverts from an enabled state to an disabled state, the second clock signal generated by the clock gating circuit disables the clock inversion of the edge-triggered flip-flop, thereby reducing the dynamic power consumption of the edge-triggered flip-flop.

[0033] In a preferred embodiment, if the minimum and maximum delay ranges of the clock control signal are both in a single level stage, and the starting edge of that level stage is a falling edge, a second clock gating circuit is selected, and the second clock gate circuit performs a logical AND operation on the clock control signal and the first clock signal to generate the second clock signal. Glitches in the clock signal generated by the clock gating circuit can be eliminated. In a clock cycle in which the clock control signal inverts from an enabled state to an disabled state, the second clock signal generated by the clock gating circuit disables the clock inversion of the edge-triggered flip-flop, thereby reducing the dynamic power consumption of the edge-triggered flip-flop.

[0034] In a preferred embodiment, when selecting a first clock gating circuit and a second clock gating circuit, the latch can be omitted, and glitches in the clock signal generated by the clock gating circuit can be eliminated. Therefore, less hardware logic is used in the clock gating circuit, and the operating power consumption of the clock gating circuit itself is reduced. Any number of edge-triggered flip-flops in a trigger unit can share a clock gating circuit to form a flip-flop group. If the flip-flop group includes, for example, one, two, or any number of edge-triggered flip-flops, the increase in power consumption due to the power consumption of the clock gating circuit itself is much smaller than the decrease in power consumption of the edge-triggered flip-flops due to the clock gating, so the trigger unit can always achieve a reduction in power consumption.

[0035] Furthermore, the circuit design method for this trigger unit optimizes the combination of the clock gating circuit and edge-triggered flip-flop, enabling simplification and reduction of layout area. This combination circuit of clock gating and edge-triggered flip-flops can be used as a library unit in a standard cell library and applied under various conditions to improve the performance and design efficiency of digital circuits. [Brief explanation of the drawing]

[0036] The embodiments of the present invention will be described below with reference to the drawings, thereby making the above and other objectives, features, and advantages of the present invention clearer.

[0037] [Figure 1] Figures 1 and 2 show schematic circuit diagrams and waveform diagrams of edge-triggered flip-flops within an integrated circuit, respectively. [Figure 2] Figures 1 and 2 show schematic circuit diagrams and waveform diagrams of edge-triggered flip-flops within an integrated circuit, respectively. [Figure 3] Figure 3 shows a schematic circuit diagram of the trigger unit. [Figure 4] Figures 4 and 5 show schematic circuit diagrams and waveform diagrams of conventional clock gating circuits, respectively. [Figure 5] Figures 4 and 5 show schematic circuit diagrams and waveform diagrams of conventional clock gating circuits, respectively. [Figure 6] Figures 6, 7a, and 7b show schematic circuit diagrams and waveform diagrams of a clock gating circuit according to the first embodiment of the present invention, respectively. [Figure 7a] Figures 6, 7a, and 7b show schematic circuit diagrams and waveform diagrams of a clock gating circuit according to the first embodiment of the present invention, respectively. [Figure 7b] Figures 6, 7a, and 7b show schematic circuit diagrams and waveform diagrams of a clock gating circuit according to the first embodiment of the present invention, respectively. [Figure 8] Figures 8, 9a, and 9b show schematic circuit diagrams and waveform diagrams of a clock gating circuit according to a second embodiment of the present invention, respectively. [Figure 9a] Figures 8, 9a, and 9b show schematic circuit diagrams and waveform diagrams of a clock gating circuit according to a second embodiment of the present invention, respectively. [Figure 9b] Figures 8, 9a, and 9b show schematic circuit diagrams and waveform diagrams of a clock gating circuit according to a second embodiment of the present invention, respectively. [Figure 10] Figure 10 shows a flowchart of the design method for a trigger unit according to a third embodiment of the present invention. [Figure 11] Figure 11 shows the combination of a clock gating circuit and an edge trigger flip-flop in the trigger unit design method shown in Figure 10. [Figure 12] Figure 12 shows another combination of the clock gating circuit and edge-triggered flip-flops in the trigger unit design method shown in Figure 10. [Modes for carrying out the invention]

[0038] The present invention will be described in more detail below with reference to the attached drawings. In each drawing, identical elements are indicated by similar reference numerals. For clarity, parts of the figures are not drawn to scale. Also, some well-known parts may not be shown.

[0039] To gain a clearer understanding of the present invention, many specific details of the invention, such as device structure, materials, dimensions, processing steps, and techniques, are described below. However, as those skilled in the art will understand, the present invention can be realized without these specific details.

[0040] The present invention can be presented in various forms, some of which are described below.

[0041] Figure 3 shows a schematic circuit diagram of the trigger unit. The trigger unit 200 includes an edge-triggered flip-flop 110 and a clock gating circuit 130. The clock gating circuit 130 is used to gate the clock signal CK of the edge-triggered flip-flop 110. In this embodiment, the edge-triggered flip-flop 110 is, for example, a D-type flip-flop.

[0042] The edge-triggered flip-flop 110 includes a data input terminal, a data output terminal, and a clock input terminal. The clock gating circuit 130 includes an input terminal, an output terminal, and a control terminal. The input terminal of the clock gating circuit 130 receives the clock signal CLK, the output terminal provides the clock signal CK, and the control terminal receives the clock control signal EN. The data input terminal of the edge-triggered flip-flop 110 receives the input data Di, the clock input terminal receives the clock signal CK, and the data output terminal provides the output data Do.

[0043] At the trigger edge of the clock signal CK, for example the rising edge, the edge-triggered flip-flop 110 transmits the input data from the data input terminal to the data output terminal. Therefore, the signal level corresponding to the output data at the data output terminal of the edge-triggered flip-flop 110 depends on the signal level of the input data at the data input terminal up to the arrival of the trigger edge of the clock signal CK, and remains unchanged in the clock cycle after the trigger edge of the clock signal CK. The data output terminal of the edge-triggered flip-flop 110 may include two complementary output terminals.

[0044] The clock gating circuit 130 performs logical operations on the clock control signal EN and the clock signal CLK to generate the clock signal CK for the edge-triggered flip-flop 110.

[0045] In the trigger unit described above, the clock gating circuit 130 controls the transmission of the clock signal according to the state of the clock control signal EN.

[0046] In clock cycles in which the clock control signal EN remains active, the clock gating circuit 130 copies the clock signal CLK to the clock signal CK and provides the clock signal CK to the clock input terminal of the edge-triggered flip-flop 110. In clock cycles in which the clock control signal EN remains inactive, the clock gating circuit 130 disables the clock signal CLK and maintains the clock signal CK at a predetermined level.

[0047] If the clock signal CK is maintained at a predetermined level, the clock signal CK cannot provide a trigger edge for the edge-triggered flip-flop 110, and therefore the clock inversion and data transmission of the edge-triggered flip-flop 110 can be disabled. Furthermore, the edge-triggered flip-flop 110 prevents data from entering the subsequent digital circuit, thereby avoiding additional data power consumption due to the inversion of the data signal of the subsequent combinational logic.

[0048] Figure 4 shows a schematic circuit diagram of a conventional clock gating circuit. Referring to Figure 3, the clock gating circuit 130 and the edge trigger flip-flop 110 together form a trigger unit, and the clock gating circuit 130 provides the clock signal CK to the edge trigger flip-flop 110.

[0049] The clock gating circuit 130 includes a latch 131 and an AND gate 132. The latch 131 latches the clock control signal EN at the first level stage T1 of the clock signal CLK and transmits the clock control signal EN at the second level stage T2 of the clock signal CLK. The AND gate performs a logical AND operation on the latch signal EN_a and the clock signal CLK to generate the clock signal CK.

[0050] Latch 131 includes a first input terminal, a second input terminal, and an output terminal. AND gate 132 also includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of latch 131 receives the clock signal CLK, and the second input terminal receives the clock control signal EN. The first input terminal of AND gate 132 receives the clock signal CLK, and its second input terminal is connected to the output terminal of latch 131, which provides the clock signal CK.

[0051] Using an edge-triggered flip-flop triggered by a rising edge as an example, the clock control signal EN will be described by indicating the active state as a high level and the inactive state as a low level. Each clock cycle of the clock signal CLK includes a consecutive first level stage T1 and a second level stage T2, each having a high level and a low level, between adjacent rising edges. The clock signal CK provides the trigger edge for the edge-triggered flip-flop 110, which transmits input data from the input terminal to the output terminal at the trigger edge.

[0052] Referring to Figure 5, the input data Di and the clock control signal EN each have a signal delay Td relative to the edge of the clock signal. The regions between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are represented by the shaded areas. The signal delay Td of the clock control signal EN varies between the minimum delay Tdmin and the maximum delay Tdmax.

[0053] As shown in Figure 5, the minimum delay Tdmin and the maximum delay Tdmax are in the first level stage T1 and the second level stage T2, respectively, and the inversion operation of the clock control signal EN may occur in the first level stage T1 of the clock signal CLK, and may also occur in the second level stage T2 of the clock signal CLK.

[0054] At time t0, the clock signal CLK reaches its first rising edge, and the clock control signal EN is enabled. In the clock cycle starting at time t0, the clock control signal EN inverts from the enabled state to the disabled state. At the first level stage T1 of the clock signal CLK, the signal level of the latch signal EN_a at the output terminal of the latch 131 remains at its previous state, i.e., high level. At the second level stage T2 of the clock signal CLK, the latch 131 transmits the clock control signal EN from the input terminal to the output terminal.

[0055] If the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, then in the clock cycle in which the clock control signal inverts, the latch signal EN_a is a copy version of the clock signal CLK. If the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, then a glitch appears in the latch signal EN_a at the second level stage T2 of the clock signal CLK. The clock signal CK is the result of a logical AND operation between the clock signal CLK and the latch signal EN_a, and this logical AND operation can remove the glitch in the latch signal EN_a at the second level stage T2 of the clock signal CLK.

[0056] Therefore, in the clock cycle starting at time t0, the clock gating circuit 130 copies the clock signal CLK to the clock signal CK and provides the rising edge of the clock signal CK. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t0, which is, for example, a low level as shown in Figure 5.

[0057] At time t1, the clock signal CLK reaches its second rising edge, and the clock control signal EN is in an inactive state. In the clock cycle starting at time t1, the clock control signal EN remains in an inactive state. At the first level stage T1 of the clock signal CLK, the signal level of the latch signal EN_a at the output terminal of latch 131 remains in its previous state, i.e., low level. At the second level stage T2 of the clock signal CLK, latch 131 transmits the clock control signal EN from the input terminal to the output terminal. In this clock cycle, because the clock control signal EN remains in a low level state, EN_a also remains at a low level, and the clock signal CK remains at a low level due to the product operation of the clock signal CLK and the latch signal EN_a.

[0058] At time t2, the clock signal CLK reaches its third rising edge, and the clock control signal EN is in an inactive state. In the clock cycle starting at time t2, the clock control signal EN inverts from the inactive state to the active state. At the first level stage T1 of the clock signal CLK, the signal level of the latch signal EN_a at the output terminal of latch 131 remains in its previous state, i.e., low level. At the second level stage T2 of the clock signal CLK, latch 131 transmits the clock control signal EN from the input terminal to the output terminal. If the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, then in the clock cycle in which the clock control signal inverts, the latch signal EN_a is a copy version of the clock signal CLK. If the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, then a glitch appears in the latch signal EN_a at the second level stage T2 of the clock signal CLK. The clock signal CK is the result of a logical AND operation between the clock signal CLK and the latch signal EN_a, and this logical AND operation can remove the glitch in the latch signal EN_a at the second level stage T2 of the clock signal CLK.

[0059] Therefore, in the two clock cycles starting at time t1, the clock gating circuit 130 disables the clock signal CLK and does not provide the rising edge of the clock signal CK, so that the signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, which is, for example, a low level as shown in Figure 5.

[0060] The clock gating circuit 130 described above controls the transmission of the clock signal according to the state of the clock control signal EN.

[0061] In a clock cycle in which the clock control signal EN inverts from the enabled state to the disabled state, the clock gating circuit 130 copies the clock signal CLK to the clock signal CK. At this time, the clock signal CK provides the trigger edge for the edge-triggered flip-flop 110. The clock gating circuit 130 enables clock inversion and data transmission for the edge-triggered flip-flop 110. The output data Do 110 provided by the edge-triggered flip-flop 110 is the input data Di for the current trigger edge.

[0062] In the clock cycle in which the clock control signal EN inverts from an inactive state to an active state, the clock gating circuit 130 disables the clock signal CLK and maintains the clock signal CK at a predetermined level. At this time, the clock signal CK cannot provide a trigger edge for the edge-triggered flip-flop 110, and the clock gating circuit 130 disables the clock inversion and data transmission of the edge-triggered flip-flop 110. Since the edge-triggered flip-flop 110 retains the input data Di of the previous trigger edge, the dynamic power consumption of the edge-triggered flip-flop 110 can be reduced.

[0063] The clock gating circuit 130 described above does not have high timing requirements for the clock control signal EN. If it is desired to disable data transmission at a predetermined time, the inversion operation of the clock control signal EN from the enabled state to the disabled state can be completed in the last complete clock cycle before the predetermined time, and the inversion operation of the clock control signal EN from the disabled state to the enabled state can be completed in the last clock cycle starting from the predetermined time.

[0064] The inventor noted that the trigger unit provided in the standard cell library of the digital circuit EDA uses the aforementioned clock gating circuit 130. The clock gating circuit 130 includes a latch 131 for removing any glitches that may appear in the clock signal CK of the edge-triggered flip-flop 110.

[0065] However, latch 131 uses a lot of hardware logic, which would make the operating power consumption of the clock gating circuit 130 itself too high. The operating power consumption of the clock gating circuit 130 itself can even exceed the power consumption of the edge-triggered flip-flops reduced by the clock gating. In a trigger unit, the clock gating circuit 130 can provide a clock signal CK to multiple edge-triggered flip-flops 110 in a flip-flop group. When using the clock gating circuit 130, the circuit design limitation is that the number of edge-triggered flip-flops in the flip-flop group is 3 to 8 or more, which ensures that the operating power consumption of the clock gating circuit 130 itself in the trigger unit 200 is less than the power consumption of some edge-triggered flip-flops 110 reduced by the clock gating circuit 130.

[0066] Furthermore, the inventor noted that most conventional EDA tools can obtain the signal delay Td of the clock control signal EN, and that the signal delay Td of the clock control signal EN can be calculated and set using optimized circuit design and circuit simulation, thereby the range of the minimum delay Tdmin and maximum delay Tdmax of the signal delay Td is in a selected level stage of the clock signal CLK.

[0067] The inventors designed clock gating circuits 230 and 330, described later, but by selecting a different clock gating circuit depending on the delay condition of the clock control signal EN, the same functionality as clock gating circuit 130 can be obtained without using a latch. In the standard cell library of digital circuit EDA, clock gating circuits 230 and 330 can be used in a redesigned trigger unit. Therefore, the power consumption of the integrated circuit can be further reduced, the cost of the trigger unit can be lowered, and the power consumption of the clock gating circuit itself can be reduced, thus overcoming the limitations of the above circuit design.

[0068] Figure 6 shows a schematic circuit diagram of a clock gating circuit according to the first embodiment of the present invention. Referring to Figure 3, the clock gating circuit 230 and the edge trigger flip-flop 110 together form a trigger unit, and the clock gating circuit 230 provides the clock signal CK to the edge trigger flip-flop 110.

[0069] The clock gating circuit 230 includes a NOT gate 231 and an OR gate 232. In the clock gating circuit 230, the clock signal CK is the result of a logical OR operation between the clock signal CLK and the inverted signal EN_a of the clock control signal EN.

[0070] The OR gate 232 includes a first input terminal, a second input terminal, and an output terminal. The NOT gate 231 includes an input terminal and an output terminal. The first input terminal of the OR gate 232 receives the clock signal CLK. The second input terminal of the OR gate 232 is connected to the output terminal of the NOT gate 231 and receives the inverted signal EN_a of the clock control signal EN via the NOT gate 231. The output terminal of the OR gate 232 provides the clock signal CK.

[0071] In this embodiment, an edge-triggered flip-flop triggered by a rising edge is used as an example, and the clock control signal EN is described by indicating the active state as a high level and the inactive state as a low level. Each clock cycle of the clock signal CLK includes a consecutive first level stage T1 and a second level stage T2, having a high level and a low level, respectively, between adjacent rising edges. The clock signal CK provides the trigger edge for the edge-triggered flip-flop 110, and the edge-triggered flip-flop 110 transmits input data from the input terminal to the output terminal at the trigger edge.

[0072] In this embodiment, the input data Di and the clock control signal EN each have a signal delay Td with respect to the edge of the clock signal. The regions between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are represented by the shaded areas. The signal delay Td of the clock control signal EN varies between the minimum delay Tdmin and the maximum delay Tdmax.

[0073] Referring to Figure 7a, both the minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are in the first level stage T1, and the inversion operation of the clock control signal EN can only occur in the first level stage T1 of the clock signal CLK. The starting edge of the first level stage T1 is the rising edge.

[0074] At time t0, the clock signal CLK reaches its first rising edge, and the clock control signal EN is active. In the clock cycle starting at time t0, the clock control signal EN inverts from the active state to the inactive state. The clock signal CK is the result of the logical OR operation between the clock signal CLK and the inverted signal EN_a. At the first level stage T1 of the clock signal CLK, the clock signal CK is always high. At the second level stage T2 of the clock signal CLK, the clock signal CK is always high. Therefore, if the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, the clock signal CK remains high during the clock cycle in which the clock control signal inverts from the active state to the inactive state.

[0075] Therefore, when the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, in the clock cycle starting at time t0, the clock gating circuit 230 disables the clock signal CLK and provides the rising edge of the clock signal CK. After the setup time following the rising edge has elapsed, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t0, which is, for example, the low level shown in Figure 7a.

[0076] At time t1, the clock signal CLK reaches its second rising edge, and the clock control signal EN is disabled. In the clock cycle starting at time t1, the clock control signal EN remains disabled and is at a low level, for example, as shown in Figure 7a. The clock signal CK is the result of the logical OR operation of the clock signal CLK and the inverted signal EN_a. In this clock cycle, since the clock control signal EN is always low, the inverted signal EN_a is always high, and the result of the OR operation, i.e., the clock signal CK, is also always high. Since the clock signal CK does not provide a rising edge, the signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, and is at a low level, for example, as shown in Figure 7a.

[0077] At time t2, the clock signal CLK reaches its third rising edge, and the clock control signal EN is inactive. In the clock cycle starting at time t2, the clock control signal EN inverts from the inactive state to the active state. The clock signal CK is the result of the logical OR operation of the clock signal CLK and the inverted signal EN_a. At the first level stage T1 of the clock signal CLK, the clock signal CK is always high. At the second level stage T2 of the clock signal CLK, the clock signal CK is always low. Therefore, if the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, then in the clock cycle in which the clock control signal inverts from the inactive state to the active state, the clock signal CK is a copy version of the clock signal CLK.

[0078] Therefore, if the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, in the clock cycle starting at time t2, the clock gating circuit 230 copies the clock signal CLK to the clock signal CK, but does not provide the rising edge of the clock signal, and the signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, which is, for example, a low level as shown in Figure 7a.

[0079] Furthermore, at time t3, the clock signal CLK reaches its fourth rising edge. The clock control signal EN is active for the entire clock cycle starting at time t3, with the clock signal CK being a copy version of the clock signal CLK. The clock gating circuit 230 copies the clock signal CLK to the clock signal CK and provides the rising edge of the clock signal CK, thereby enabling the clock signal and data transmission of the edge-triggered flip-flop. After a setup time has elapsed following the rising edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t3, i.e., it is high. From time t3 onward, the clock control signal EN remains active, with the clock signal CK being a copy version of the clock signal CLK, and as the clock signal CLK transitions, the edge-triggered flip-flop 110 receives the input data at the data input terminal at the trigger edge of the second clock signal and transmits it to the data output terminal.

[0080] Referring to Figure 7b, both the minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are in the second level stage T2, and the inversion operation of the clock control signal EN can only occur in the second level stage T1 of the clock signal CLK. The starting edge of the second level stage T2 is a falling edge.

[0081] At time t0, the clock signal CLK reaches its first rising edge, and the clock control signal EN is active. In the clock cycle starting at time t0, the clock control signal EN inverts from the active state to the inactive state. The clock signal CK is the result of the logical OR operation between the clock signal CLK and the inverted signal EN_a. At the first level stage T1 of the clock signal CLK, the clock signal CK is always high. At the second level stage T2 of the clock signal CLK, the signal level of the clock signal CK is related to the signal delay of the clock control signal EN. If the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, then at the second level stage T2 of the clock signal CLK, the clock signal CK may invert from high to low at the start of the second level stage T2, and then invert from low to high at some point after time ta in the second level stage T2, and this transition may repeat, resulting in a glitch.

[0082] Therefore, if the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, a glitch appears in the clock signal CK generated by the clock gating circuit 230 in the clock cycle starting at time t0. The glitch provides an additional rising edge that changes with the clock control signal EN, and after a setup time has elapsed following the additional rising edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at the additional rising edge. On the one hand, the input data Di of the edge-triggered flip-flop 110 is in an uncertain state due to its own signal delay, and on the other hand, the additional rising edge provided by the glitch in the clock signal CK coincides with the uncertain state of the input data Di. Therefore, after a setup time has elapsed following the additional rising edge, the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the additional rising edge and is in an uncertain state, for example, as shown in Figure 7b.

[0083] At time t1, the clock signal CLK reaches its second rising edge, and the clock control signal EN is disabled. Similar to Figure 7a, in the clock cycle starting at time t1, the clock signal CK remains high and provides neither a rising nor a falling edge. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, resulting in an uncertain state as shown, for example, in Figure 7b.

[0084] At time t2, the clock signal CLK reaches its third rising edge, and the clock control signal EN is disabled. In the clock cycle starting at time t2, the clock control signal EN inverts from the disabled state to the enabled state. The clock signal CK is the result of the logical OR operation between the clock signal CLK and the inverted signal EN_a. At the first level stage T1 of the clock signal CLK, the clock signal CK is always high level. At the second level stage T2 of the clock signal CLK, the signal level of the clock signal CK is related to the signal delay of the clock control signal EN. If the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, then at the second level stage T2 of the clock signal CLK, it coincides with the inversion time of the clock control signal EN, causing the clock signal CK to invert from the high level state to the low level state, resulting in a glitch.

[0085] Therefore, if the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, a glitch occurs in the clock signal CK generated by the clock gating circuit 230 in the clock cycle starting at time t2. However, the glitch can only provide an additional falling edge that changes with the clock control signal EN, and the transition may provide a trigger edge for the edge-triggered flip-flop 110. Thus, the signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, resulting in an uncertain state, for example, as shown in Figure 7b.

[0086] Furthermore, at time t3, the clock signal CLK reaches its fourth rising edge. The clock control signal EN is active throughout the entire clock cycle starting at time t3, and the clock signal CK is a copy version of the clock signal CLK. The clock gating circuit 230 copies the clock signal CLK to the clock signal CK and provides the rising edge of the clock signal CK, thereby enabling the clock signal and data transmission of the edge-triggered flip-flop. After the setup time has elapsed following the rising edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t3, i.e., it is high level. From time t3 onward, the clock control signal EN remains active, and the clock signal CK is a copy version of the clock signal CLK. When the clock signal CLK transitions, the edge-triggered flip-flop 110 receives the input data at the data input terminal and transmits it to the data output terminal at the trigger edge of the second clock signal.

[0087] The clock gating circuit 230 described above exhibits different circuit characteristics depending on the delay conditions of the clock control signal EN. Under the condition that both the minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are in the first level stage T1, and the start edge of the first level stage T1 is a rising edge, the clock gating circuit 230 shown in Figure 6 is selected instead of the clock gating circuit 130 shown in Figure 4.

[0088] In clock cycles where the clock control signal EN remains active, the clock gating circuit 230 copies the clock signal CLK to the clock signal CK and provides the clock signal CK to the clock input terminal of the edge-triggered flip-flop 110. In clock cycles where the clock control signal EN remains inactive, the clock gating circuit 230 disables the clock signal CLK. Therefore, the clock gating circuit 230 can be used to disable clock inversion and data transmission of the edge-triggered flip-flop 110.

[0089] In a clock cycle in which the clock control signal EN inverts from an enabled state to an disabled state, the clock gating circuit 230 disables the clock signal CLK and maintains the clock signal CK at a predetermined level. At this time, the clock signal CK still provides a trigger edge for the edge-triggered flip-flop 110, and the clock gating circuit 230 enables data transmission by the edge-triggered flip-flop 110, with the output data Do provided by the edge-triggered flip-flop 110 being the input data Di of the current trigger edge. The clock gating circuit 230 disables the clock inversion of the edge-triggered flip-flop 110, thereby reducing the dynamic power consumption of the edge-triggered flip-flop 110 due to the inversion of the clock signal CK.

[0090] In a clock cycle in which the clock control signal EN inverts from an inactive state to an active state, the clock gating circuit 230 copies the clock signal CLK to the clock signal CK, enabling the clock inversion of the edge-triggered flip-flop 110. At this time, the clock signal CK cannot provide a trigger edge for the edge-triggered flip-flop 110, and the clock gating circuit 230 disables data transmission of the edge-triggered flip-flop 110. This allows the edge-triggered flip-flop 110 to retain the input data Di of the previous trigger edge, reducing the dynamic power consumption of the edge-triggered flip-flop 110 due to data transmission.

[0091] The timing requirement of the clock gating circuit 230 for the clock control signal EN is that the inversion of the clock control signal EN occurs at a level stage after the trigger edge of one clock cycle of the clock signal CLK, in this example, at the first level stage T1. If it is desirable to disable data transmission at a predetermined time, the inversion operation of the clock control signal EN from the enabled state to the disabled state is completed within the first level stage T1 of the last complete clock cycle before the predetermined time, and the inversion operation of the clock control signal EN from the disabled state to the enabled state is completed within the first level stage T1 of the clock signal CLK of the last clock cycle starting from the predetermined time.

[0092] Compared to the clock gating circuit 130 shown in Figure 4, the clock gating circuit 230 in this embodiment omits latches, uses less hardware logic, and consumes less operating power itself. In a trigger unit, any number of edge-triggered flip-flops 110 can share the clock gating circuit 230 to form a flip-flop group. When a flip-flop group includes any number of edge-triggered flip-flops 110, the increase in power consumption due to the power consumption of the clock gating circuit 230 itself is much smaller than the power consumption of the edge-triggered flip-flops 110 reduced by clock gating, and therefore the power consumption of the trigger unit can always be reduced.

[0093] Figure 8 shows a schematic circuit diagram of a clock gating circuit according to a second embodiment of the present invention. Referring to Figure 3, the clock gating circuit 330 and the edge trigger flip-flop 110 together form a trigger unit, and the clock gating circuit 330 provides the clock signal CK to the edge trigger flip-flop 110.

[0094] The clock gating circuit 330 includes an AND gate 331. In the clock gating circuit 330, the clock signal CK is the result of a logical AND operation between the clock signal CLK and the clock control signal EN.

[0095] The AND gate 331 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the AND gate 331 receives a clock signal CLK, the second input terminal receives a clock control signal EN, and the output terminal provides a clock signal CK.

[0096] In this embodiment, using an edge-triggered flip-flop triggered by a falling edge as an example, the clock control signal EN is described by indicating the active state as a high level and the inactive state as a low level. Each clock cycle of the clock signal CLK includes a consecutive first level stage T1 and a second level stage T2, having a low level and a high level, respectively, between adjacent falling edges. The clock signal CK provides the trigger edge for the edge-triggered flip-flop 110, and the edge-triggered flip-flop 110 transmits input data from the input terminal to the output terminal at the trigger edge.

[0097] In this embodiment, the input data Di and the clock control signal EN each have a signal delay Td with respect to the edge of the clock signal. The regions between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are represented by the shaded areas. The signal delay Td of the clock control signal EN varies between the minimum delay Tdmin and the maximum delay Tdmax.

[0098] Referring to Figure 9a, both the minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are in the first level stage T1, and the inversion operation of the clock control signal EN can only occur in the first level stage T1 of the clock signal CLK. The starting edge of the first level stage T1 is a falling edge.

[0099] At time t0, the clock signal CLK reaches its first falling edge, and the clock control signal EN is active. In the clock cycle starting at time t0, the clock control signal EN inverts from the active state to the inactive state. The clock signal CK is the result of the logical AND operation of the clock signal CLK and the clock control signal EN. At the first level stage T1 of the clock signal CLK, the clock signal CK is always low. At the second level stage T2 of the clock signal CLK, the clock signal CK is always low. Therefore, if the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, the clock signal CK remains low during the clock cycle in which the clock control signal inverts from the active state to the inactive state.

[0100] Therefore, if the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, the clock gating circuit 330 disables the clock signal CLK in the clock cycle starting at time t0, but provides the falling edge of the clock signal CK. After the setup time has elapsed following the falling edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t0, which is, for example, the low level shown in Figure 9a.

[0101] At time t1, the clock signal CLK reaches its second falling edge, and the clock control signal EN is disabled. In the clock cycle starting at time t1, the clock control signal EN remains disabled and is at a low level, as shown in Figure 9a. The clock signal CK is the result of the logical AND operation of the clock signal CLK and the clock control signal EN. In this clock cycle, since the clock control signal EN is always low, the result of the AND operation, i.e., the clock signal CK, is also always low. The clock signal CK does not provide a falling edge, and the signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, which is, for example, a low level, as shown in Figure 9a.

[0102] At time t2, the clock signal CLK reaches its third falling edge, and the clock control signal EN is inactive. In the clock cycle starting at time t2, the clock control signal EN inverts from the inactive state to the active state. The clock signal CK is the result of the logical AND operation of the clock signal CLK and the clock control signal EN. At the first level stage T1 of the clock signal CLK, the clock signal CK is always low. At the second level stage T2 of the clock signal CLK, the clock signal CK is always high. Therefore, the signal delay Td of the clock control signal EN is such that, in the clock cycle in which the clock control signal inverts from the inactive state to the active state, the clock signal CK is a copy version of the clock signal CLK, provided that the first level stage T1 of the clock signal CLK is as follows:

[0103] Therefore, if the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, in the clock cycle starting at time t2, the clock gating circuit 330 copies the clock signal CLK to the clock signal CK, but does not provide a falling edge for the clock signal, and the signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, which is, for example, a low level as shown in Figure 9a.

[0104] Furthermore, at time t3, the clock signal CLK reaches its fourth falling edge. The clock control signal EN is active throughout the entire clock cycle starting at time t3, and the clock signal CK is a copy version of the clock signal CLK. The clock gating circuit 330 copies the clock signal CLK to the clock signal CK and provides a falling edge for the clock signal CK, thereby enabling the clock signal and data transmission of the edge-triggered flip-flop. After a setup time has elapsed following the falling edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t3, i.e., it is high. From time t3 onward, the clock control signal EN can remain active, and the clock signal CK is a copy version of the clock signal CLK. When the clock signal CLK transitions, the edge-triggered flip-flop 110 receives the input data from the data input terminal and transmits it to the data output terminal at the trigger edge of the second clock signal.

[0105] Referring to Figure 9b, both the minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are in the second level stage T2, and the inversion operation of the clock control signal EN can only occur in the second level stage T2 of the clock signal CLK. The starting edge of the second level stage T2 is the rising edge.

[0106] At time t0, the clock signal CLK reaches its first falling edge, and the clock control signal EN is active. In the clock cycle starting at time t0, the clock control signal EN inverts from active to inactive. The clock signal CK is the result of the logical AND operation of the clock signal CLK and the clock control signal EN. At the first level stage T1 of the clock signal CLK, the clock signal CK is always low. At the second level stage T2 of the clock signal CLK, the signal level of the clock signal CK is related to the signal delay of the clock control signal EN. If the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, then at the second level stage T2 of the clock signal CLK, the clock signal CK may invert from low to high at the start of the second level stage T2, and then invert from high to low at some point after time ta in the second level stage T2, resulting in a glitch.

[0107] Therefore, if the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, a glitch appears in the clock signal CK generated by the clock gating circuit 330 in the clock cycle starting at time t0. The glitch provides an additional falling edge that changes with the clock control signal EN, and after a setup time has elapsed following the additional falling edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at the additional falling edge. On the one hand, the input data Di of the edge-triggered flip-flop 110 is in an uncertain state due to its own signal delay, and on the other hand, the additional falling edge provided by the glitch in the clock signal CK coincides with the uncertain state of the input data Di. Therefore, after a setup time has elapsed following the additional falling edge, the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the additional falling edge and is in an uncertain state, for example, as shown in Figure 9b.

[0108] At time t1, the clock signal CLK reaches its second falling edge, and the clock control signal EN is inactive. Similar to Figure 9a, in the clock cycle starting at time t1, the clock signal CK remains at a low level, providing neither a rising nor a falling edge. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, resulting in an uncertain state, for example, as shown in Figure 9b.

[0109] At time t2, the clock signal CLK reaches its third falling edge, and the clock control signal EN is disabled. In the clock cycle starting at time t2, the clock control signal EN flips from the disabled state to the enabled state. The clock signal CK is the result of the logical AND operation of the clock signal CLK and the clock control signal EN. At the first level stage T1 of the clock signal CLK, the clock signal CK is always low level. At the second level stage T2 of the clock signal CLK, the signal level of the clock signal CK is related to the signal delay of the clock control signal EN. If the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, a glitch occurs at the second level stage T2 of the clock signal CLK because the clock signal CK flips from the low level state to the high level state, similar to the flip time of the clock control signal EN.

[0110] Therefore, if the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, a glitch appears in the clock signal CK generated by the clock gating circuit 330 in the clock cycle starting at time t2. However, the glitch can only provide an additional rising edge that changes with the clock control signal EN, and the transition may provide a trigger edge for the edge-triggered flip-flop 110. Thus, the signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, resulting in an uncertain state, for example, as shown in Figure 9b.

[0111] Furthermore, at time t3, the clock signal CLK reaches its fourth falling edge. The clock control signal EN is active throughout the entire clock cycle starting at time t3, and the clock signal CK is a copy version of the clock signal CLK. The clock gating circuit 330 copies the clock signal CLK to the clock signal CK and provides a falling edge for the clock signal CK, thereby enabling the clock signal and data transmission of the edge-triggered flip-flop. After a setup time has elapsed following the falling edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t3, i.e., it is high. From time t3 onward, the clock control signal EN can remain active, and the clock signal CK is a copy version of the clock signal CLK. When the clock signal CLK transitions, the edge-triggered flip-flop 110 receives the input data from the data input terminal and transmits it to the data output terminal at the trigger edge of the second clock signal.

[0112] The clock gating circuit 330 described above exhibits different circuit characteristics depending on the delay conditions of the clock control signal EN. Under the condition that both the minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are in the first level stage T1, and the starting edge of the first level stage T1 is a falling edge, the clock gating circuit 330 shown in Figure 8 is selected instead of the clock gating circuit 130 shown in Figure 4.

[0113] In clock cycles where the clock control signal EN remains active, the clock gating circuit 330 copies the clock signal CLK to the clock signal CK and provides the clock signal CK to the clock input terminal of the edge-triggered flip-flop 110. In clock cycles where the clock control signal EN remains inactive, the clock gating circuit 330 disables the clock signal CLK. Therefore, the clock gating circuit 330 can be used to disable clock inversion and data transmission of the edge-triggered flip-flop 110.

[0114] In a clock cycle in which the clock control signal EN inverts from an enabled state to an disabled state, the clock gating circuit 330 disables the clock signal CLK and maintains the clock signal CK at a predetermined level. At this time, the clock signal CK still provides a trigger edge for the edge-triggered flip-flop 110, and the clock gating circuit 330 enables data transmission by the edge-triggered flip-flop 110, with the output data Do provided by the edge-triggered flip-flop 110 being the input data Di of the current trigger edge. The clock gating circuit 330 disables the clock inversion of the edge-triggered flip-flop 110, thereby reducing the dynamic power consumption of the edge-triggered flip-flop 110 due to the inversion of the clock signal CK.

[0115] In the clock cycle in which the clock control signal EN inverts from an inactive state to an active state, the clock gating circuit 330 copies the clock signal CLK to the clock signal CK, enabling the clock inversion of the edge-triggered flip-flop 110. At this time, the clock signal CK cannot provide a trigger edge for the edge-triggered flip-flop 110, so the clock gating circuit 330 disables data transmission of the edge-triggered flip-flop 110, allowing the edge-triggered flip-flop 110 to retain the input data Di of the previous trigger edge, thereby reducing the dynamic power consumption of the edge-triggered flip-flop 110 due to data transmission.

[0116] The timing requirement for the clock gating circuit 330 with respect to the clock control signal EN is that the inversion of the clock control signal EN occurs at a level stage after the trigger edge of one clock cycle of the clock signal CLK, in this example, at the first level stage T1. If it is desirable to disable data transmission at a predetermined time, the inversion operation of the clock control signal EN from the enabled state to the disabled state is completed within the first level stage T1 of the last complete clock cycle before the predetermined time, and the inversion operation of the clock control signal EN from the disabled state to the enabled state is completed within the first level stage T1 of the clock signal CLK of the last clock cycle starting from the predetermined time.

[0117] Compared to the clock gating circuit 130 shown in Figure 4, the clock gating circuit 330 in this embodiment omits latches, uses less hardware logic, and consumes less operating power itself. In a trigger unit, any number of edge-triggered flip-flops 110 can share the clock gating circuit 330 to form a flip-flop group. When a flip-flop group includes any number of edge-triggered flip-flops 110, the increase in power consumption due to the power consumption of the clock gating circuit 330 itself is much smaller than the power consumption of the edge-triggered flip-flops 110 reduced by clock gating, and therefore the power consumption of the trigger unit can always be reduced.

[0118] Figure 10 shows a flowchart of the design method for a trigger unit according to a third embodiment of the present invention.

[0119] The design method for the trigger unit includes steps S01 to S07.

[0120] In step S01, the signal delay Td of the clock control signal EN in the digital circuit is analyzed.

[0121] The signal delay of a clock control signal EN is the computation time from the clock edge until the clock control signal stably inverts, when a digital circuit generates the clock control signal. Most existing EDA tools can obtain the signal delay Td of the clock control signal EN. This signal delay Td varies, for example, within the range of a minimum delay Tdmin and a maximum delay Tdmax.

[0122] Next, depending on the signal delay Td of the clock control signal EN, the clock gating circuit for the edge-triggered flip-flop is selected from several different types of clock gating circuits.

[0123] By selecting from several different types of clock gating circuits based on the signal delay Td of the clock control signal EN, and by combining and applying multiple different types of clock gating circuits, a better low-power solution can be achieved. The clock gating circuit performs logical operations on the clock control signal EN and the clock signal CLK to generate the clock signal CK.

[0124] Each clock cycle of the clock signal CLK includes a consecutive first level stage T1 and a second level stage T2, where the first level stage T1 and the second level stage T2 each have a first level and a second level that are inverted from each other. When the first level is high, the starting edge of the first level stage T1 is a rising edge, and when the first level is low, the starting edge of the first level stage T1 is a falling edge.

[0125] In step S02, it is determined whether the delay range of the clock control signal is in the first level stage.

[0126] In this step, one of the first clock gating circuit and the second clock gating circuit is selected depending on the type of delay range of the clock control signal EN.

[0127] The signal delay Td of the clock control signal EN varies between a minimum delay Tdmin and a maximum delay Tdmax. The minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are compared with the first-level stage T1 of the clock signal CLK to determine whether the delay range of the clock control signal EN is within the first-level stage.

[0128] When the signal delay Td of the clock control signal EN satisfies the conditions Tdmin < T1 and Tdmax < T1, the delay range of the clock control signal EN is within the first-level stage. At this time, the inversion operation of the clock control signal EN can occur only at a single-level stage of the clock signal CLK. Further, step S03 is executed to select either the first clock gating circuit shown in FIG. 6 or the second clock gating circuit shown in FIG. 8.

[0129] When the signal delay Td of the clock control signal EN satisfies the conditions Tdmin < T1 and Tdmax > T1, the delay range of the clock control signal EN includes a period in which the first-level stage and the second-level stage are adjacent to each other. At this time, the inversion operation of the clock control signal EN can occur at any level stage of the clock signal CLK. Further, step S06 is executed to select the third clock gating circuit shown in FIG. 4.

[0130] In step S03, further, the type of the start edge of the first-level stage is determined.

[0131] In this step, either the first clock gating circuit or the second clock gating circuit is selected according to the type of the start edge of the first-level stage T1.

[0132] When the start edge of the first-level stage T1 is a rising edge, step S04 is executed to select the first clock gating circuit shown in FIG. 6.

[0133] As mentioned above, in the clock gating circuit shown in Figure 6, in the clock cycle in which the clock control signal EN inverts from the enabled state to the disabled state, the clock signal CK of the clock gating circuit disables the clock signal CLK but provides the rising edge of the clock signal CK. In the clock cycle in which the clock control signal EN inverts from the disabled state to the enabled state, the clock gating circuit copies the clock signal CLK to the clock signal CK but does not provide the rising edge of the clock signal. Therefore, as long as the clock control signal EN inverts at the first level stage T1 of the clock signal CLK, and the starting edge of the first level stage T1 is a rising edge, the glitch in the clock signal of the edge-triggered flip-flop can be eliminated, thereby allowing the edge-triggered flip-flop to operate normally.

[0134] If the starting edge of the first level stage T1 is a falling edge, step S05 is performed to select the second clock gating circuit shown in Figure 8.

[0135] As described above, in the clock gating circuit shown in Figure 8, during the clock cycle in which the clock control signal EN inverts from the enabled state to the disabled state, the clock signal CK of the clock gating circuit masks the clock signal CLK, but provides the falling edge of the clock signal CK. During the clock cycle in which the clock control signal EN inverts from the disabled state to the enabled state, the clock gating circuit copies the clock signal CLK to the clock signal CK, but does not provide the falling edge of the clock signal. Therefore, as long as the clock control signal EN inverts at the first level stage T1 of the clock signal CLK, and the starting edge of the first level stage T1 is a falling edge, the glitch in the clock signal of the edge-triggered flip-flop can be eliminated, thereby allowing the edge-triggered flip-flop to operate normally.

[0136] In step S06, the third clock gating circuit shown in Figure 4 is selected.

[0137] As described above, the clock gating circuit shown in Figure 4 includes a latch and can eliminate glitches in the clock signal of the edge-triggered flip-flop, regardless of whether the clock control signal EN inverts at the first level stage T1 or the second level stage T2 of the clock signal CLK, thereby allowing the edge-triggered flip-flop to operate normally.

[0138] In step S07, at least one edge-triggered flip-flop and a selected clock gating circuit are combined into a trigger unit.

[0139] For example, the output terminal of the selected clock gating circuit is connected to the clock input terminal of at least one edge-triggered flip-flop to form a trigger unit.

[0140] Figure 11 shows the combination of a clock gating circuit and an edge-triggered flip-flop in the trigger unit design method shown in Figure 10.

[0141] Let's explain using the first clock gating circuit shown in Figure 6 as an example. In a clock cycle in which the clock control signal EN inverts from the enabled state to the disabled state, the clock signal CK of the first clock gating circuit masks the clock signal CLK, but provides the rising edge of the clock signal CK.

[0142] Depending on the trigger edge of the edge-triggered flip-flop 110, the edge-triggered flip-flop 110 can be classified into rising edge-triggered or falling edge-triggered types. After selecting the type of clock gating circuit, the edge-triggered flip-flop and the clock gating circuit are combined into a trigger unit. The first and second clock gating circuits directly generate a second clock signal to provide a trigger edge to any type of edge-triggered flip-flop.

[0143] When a trigger unit is configured by combining a selected clock gating circuit and an edge-triggered flip-flop, a trigger edge is provided using a trigger method corresponding to the type of edge-triggered flip-flop.

[0144] Referring to Figure 11, the method for combining trigger units includes steps S11 to S14. In step S11, the first clock gating circuit is selected. In step S12, it is further determined whether the selected edge-triggered flip-flop is a rising edge or a falling edge.

[0145] If the edge-triggered flip-flop is rise-edge triggered, step S13 is executed. In step S13, the first clock gating circuit uses the rise edge provided by the second clock signal CK, which is generated in the clock cycle in which the clock control signal EN inverts from the enabled state to the disabled state, as the trigger edge of the edge-triggered flip-flop. That is, the edge-triggered flip-flop can transmit data at the trigger edge of the current clock cycle in which the clock control signal CK inverts.

[0146] If the edge-triggered flip-flop is a falling-edge-triggered flip-flop, step S14 is executed. In step S14, the first clock gating circuit uses the falling edge provided by the second clock signal CK, which is generated in the clock cycle prior to the clock cycle in which the clock control signal EN reverses from the enabled state to the disabled state, as the trigger edge of the edge-triggered flip-flop. That is, the edge-triggered flip-flop can transmit data on the trigger edge of the clock cycle prior to the clock cycle in which the clock control signal CK reverses.

[0147] Figure 12 shows the combination of a clock gating circuit and an edge-triggered flip-flop in the trigger unit design method shown in Figure 10.

[0148] The first clock gating circuit shown in Figure 6 will be explained as an example. In the first clock gating circuit, during the clock cycle in which the clock control signal EN inverts from the enabled state to the disabled state, the clock signal CK of the clock gating circuit masks the clock signal CLK, but provides the rising edge of the clock signal CK.

[0149] Depending on the trigger edge of the edge-triggered flip-flop 120, the edge-triggered flip-flop 120 can be divided into rising edge-triggered and falling edge-triggered types. After selecting the type of clock gating circuit, the edge-triggered flip-flop and the clock gating circuit are combined into a trigger unit. The first and second clock gating circuits can directly generate a second clock signal, invert the second clock signal to generate a third clock signal, and provide a trigger edge to any type of edge-triggered flip-flop.

[0150] When a selected clock gating circuit and an edge-triggered flip-flop are combined into a trigger unit, a trigger edge is provided for the trigger method corresponding to the type of edge-triggered flip-flop.

[0151] Referring to Figure 12, another method of combining trigger units includes steps S21 to S24. In step S21, the first clock gating circuit is selected. In step S22, it is further determined whether the selected edge-triggered flip-flop is a rising edge or a falling edge.

[0152] If the edge-triggered flip-flop is rise-edge triggered, step S23 is executed. In step S23, the first clock gating circuit uses the rise edge provided by the second clock signal CK, which is generated in the clock cycle in which the clock control signal EN inverts from the enabled state to the disabled state, as the trigger edge of the edge-triggered flip-flop. That is, the edge-triggered flip-flop can transmit data on the trigger edge of the current clock cycle in which the clock control signal CK inverts.

[0153] If the edge-triggered flip-flop is a falling-edge trigger, step S24 is executed. In step S24, the second clock signal is inverted to generate a third clock signal. The first clock gating circuit generates the second clock signal CK in the clock cycle in which the clock control signal EN inverts from the active state to the inactive state. The falling edge provided by the inverted signal of the second clock signal CK is set as the trigger edge of the edge-triggered flip-flop, i.e., the trigger edge of the current clock cycle in which the clock control signal CK inverts, and the edge-triggered flip-flop can transmit data.

[0154] The trigger unit design method described above explains one of three types of clock gating circuits for edge-triggered flip-flops, depending on the signal delay of the clock control signal. In digital circuit design, the clock control signal can be controlled to invert only at the first level stage of the clock signal CLK. Therefore, depending on the type of edge-triggered flip-flop, the clock gating circuit for the edge-triggered flip-flop can be selected from two types of clock gating circuits.

[0155] In the trigger unit described above, a flip-flop triggered by the rising and falling edges of a clock signal was used as an example. However, only one structure of edge-triggered flip-flops within a trigger unit is shown. However, the present invention is not limited to this. It is understood that other edge-triggered flip-flops, such as edge-triggered flip-flops with a reset function, can also be technically improved by applying the present invention.

[0156] In this specification, relational terms such as “First” and “Second” are used solely to distinguish one entity or operation from another, and do not necessarily require or imply that there is an actual relationship or order between these entities or operations. Furthermore, the terms “includes,” “contains,” or any other variations thereof are intended to cover non-exclusive inclusion, thereby including not only those elements but also other elements not expressly listed, or elements specific to the process, method, article, or equipment. Without further limitation, the elements defined by the statement “includes…” do not preclude the existence of additional identical elements in the process, method, article, or equipment containing said elements.

[0157] As described above, these embodiments do not comprehensively describe all details, nor are they limited to the specific embodiments illustrating the invention. In light of the above description, it is clear that many modifications and variations are possible. These embodiments are selected and described in detail herein to better illustrate the principles and practical applications of the invention, thereby enabling those skilled in the art to make effective use of the invention and to modify it accordingly. The invention is limited only by the claims, their entirety, and their equivalents.

Claims

1. In a digital circuit, the steps include analyzing the signal delay of the clock control signal related to the first clock signal, If the range of the signal delay of the clock control signal is within the first level stage of the first clock signal, the step of selecting one of the first clock gating circuit and the second clock gating circuit according to the type of start edge of the first level stage and generating a second clock signal, The process includes the step of combining at least one edge-triggered flip-flop and the selected clock gating circuit into a trigger unit, The edge-triggered flip-flop transmits data at the edge of the second clock signal. The first clock gating circuit and the second clock gating circuit maintain the second clock signal at a predetermined level at least during the clock cycle in which the clock signal is inverted from an enabled state to an disabled state. If the start edge of the first level stage is a rising edge, the first clock gating circuit is selected to generate the second clock signal by performing at least a logical OR operation on the inverted signal of the clock control signal and the first clock signal. If the start edge of the first level stage is a falling edge, the second clock gating circuit is selected to generate the second clock signal by performing at least a logical AND operation on the clock control signal and the first clock signal. How to design a trigger unit.

2. The design method according to claim 1, wherein, in a clock cycle in which the clock control signal remains in an inactive state, the first clock gating circuit and the second clock gating circuit maintain the second clock signal at the predetermined level.

3. The design method according to claim 1, wherein in a clock cycle in which the clock control signal inverts from an inactive state to an active state, the first clock gating circuit and the second clock gating circuit copy the first clock signal as the second clock signal.

4. The design method according to claim 1, wherein in a clock cycle in which the clock control signal remains active, the first clock gating circuit and the second clock gating circuit copy the first clock signal as the second clock signal.

5. The design method according to claim 1, wherein the first clock gating circuit generates the second clock signal by performing a logical OR operation on the inverted signal of the clock control signal and the first clock signal.

6. The design method according to claim 1, wherein the second clock gating circuit generates the second clock signal by performing a logical AND operation with respect to the clock control signal and the first clock signal.

7. The design method according to claim 1, wherein when one of the first clock gating circuit and the second clock gating circuit is selected, the predetermined level is the level of the first level step.

8. The signal delay varies within a range between a minimum delay and a maximum delay, In the second level stage, the first clock signal operates in a different state than in the first level stage. If the minimum delay and the maximum delay exist in the first level stage and the second level stage of the first clock signal, respectively, the design method further includes selecting a third clock gating circuit, the third clock gating circuit maintaining the second clock signal at a predetermined level for at least the next clock cycle in which the clock control signal inverts from an enabled state to an disabled state. The design method according to claim 1, wherein the third clock gating circuit generates the second clock signal by performing a logical AND operation on the latch signal of the clock control signal and the first clock signal.

9. The design method according to claim 8, wherein when the third clock gating circuit is selected, the predetermined level is the level of the second level step.

10. The design method according to claim 1, wherein the step of combining with a trigger unit includes the step of selecting a clock cycle for data transmission by the edge-triggered flip-flop, depending on the type of selected clock gating circuit and the type of edge-triggered flip-flop.

11. The design method according to claim 10, wherein, if the starting edge of the first level stage is the same as the trigger edge of the edge-triggered flip-flop, the second clock signal provides the trigger edge of the edge-triggered flip-flop in the clock cycle in which the clock control signal inverts from an enabled state to an disabled state.

12. The design method according to claim 10, wherein, if the starting edge of the first level stage is on the opposite side of the trigger edge of the edge-triggered flip-flop, the second clock signal provides the trigger edge of the edge-triggered flip-flop in the clock cycle prior to the clock cycle in which the clock control signal reverses from an enabled state to an disabled state.

13. The design method according to claim 1, wherein the step of combining with a trigger unit includes the step of inverting the second clock signal to generate a third clock signal.

14. The design method according to claim 13, wherein, if the starting edge of the first level stage is the same as the trigger edge of the edge-triggered flip-flop, the second clock signal provides the trigger edge of the edge-triggered flip-flop in the clock cycle in which the clock control signal inverts from an enabled state to an disabled state.

15. The design method according to claim 13, wherein, if the starting edge of the first level stage is on the opposite side of the trigger edge of the edge-triggered flip-flop, the third clock signal provides the trigger edge of the edge-triggered flip-flop in the clock cycle in which the clock control signal reverses from an enabled state to an disabled state.

16. The design method according to claim 1, wherein a high level of the clock control signal indicates an enabled state, and a low level indicates an disabled state.

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