control device

Abstract

To provide a control apparatus capable of shortening a time required to investigate a cause of a failure occurring before firmware is booted.SOLUTION: A control apparatus comprises a first unit and a second unit. A first hardware circuit of the first unit includes: a first counter; a signal output unit for outputting a synchronization signal to the second unit; and a time information output unit that outputs a first value of the first counter to the second unit when the synchronization signal is output. A second hardware circuit of the second unit includes: a second counter; a difference calculation unit that calculates a first difference between a second value and a first value of the second counter when the synchronization signal is received; and a correction unit that corrects the second counter based on the first difference.SELECTED DRAWING: Figure 1

Description

Technical Field

[0004] , , , , , , , ,

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[0001] The present disclosure relates to a control device.

Background Art

[0002] In various production sites, FA (Factory Automation) technology using a control device such as a PLC (Programmable Logic Controller) has been widely spread. A PLC generally includes a basic unit (CPU (Central Processing Unit) unit) and an expansion unit. The counter (timer) of the CPU unit and the counter of the expansion unit are synchronized so that there is no time lag between the data obtained from the CPU unit and the data obtained from the expansion unit.

[0003] For example, Japanese Patent Application Laid-Open No. 2017-79009 (Patent Document 1) discloses a technique for synchronizing the time of the CPU unit timer and the time of the expansion unit timer. Specifically, a synchronization signal is transmitted from the CPU unit to the expansion unit. The expansion unit synchronizes the time of the expansion unit timer with the time of the CPU unit timer in response to the synchronization signal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the technology described in Japanese Patent Publication No. 2017-79009, the CPU of the CPU unit executes a process to transmit a synchronization signal by running firmware. Therefore, the CPU unit timer and the extension unit timer cannot be synchronized until after the firmware has started. Consequently, the CPU unit timer and the extension unit timer are not synchronized before the firmware starts. As a result, if a malfunction occurs before the firmware starts, it becomes difficult to organize the order in which events occur between multiple units, and it takes time to investigate the cause of the malfunction.

[0006] This disclosure has been made in view of the above-mentioned problems, and its purpose is to provide a control device that can shorten the time required to investigate the cause of a malfunction that occurred before the firmware was started. [Means for solving the problem]

[0007] According to one example of the present disclosure, the control device comprises a first unit and a second unit that exchange data. The first unit includes a first hardware circuit. The second unit includes a second hardware circuit. The first hardware circuit includes a first counter, a signal output unit that outputs a synchronization signal to the second unit, and a time information output unit that outputs a first value of the first counter when the synchronization signal is output to the second unit. The second hardware circuit includes a second counter, a difference calculation unit that calculates a first difference between a second value and a first value of the second counter when the synchronization signal is received, and a correction unit that corrects the second counter based on the first difference.

[0008] According to the above disclosure, the synchronization process between the first counter and the second counter is performed by the first hardware circuit of the first unit and the second hardware circuit of the second unit. Therefore, the synchronization process between the first counter and the second counter begins immediately after power is supplied to the control device. Consequently, the first counter and the second counter are synchronized before the firmware is started. This makes it easy to organize the order in which events occur in the first unit and the second unit, even before the firmware is started. As a result, the time required to investigate the cause of a malfunction that occurred before the firmware was started can be reduced.

[0009] In the above disclosure, the first hardware circuit further comprises a third counter. The second hardware circuit further comprises a fourth counter. The signal output unit repeatedly outputs a synchronization signal. The time information output unit further outputs to the second unit a second difference between the value of the third counter when the previous synchronization signal was output and the value of the third counter when the current synchronization signal is output. The difference calculation unit further calculates a third difference between the value of the fourth counter when the previous synchronization signal was received and the value of the fourth counter when the current synchronization signal is received, and calculates a fourth difference between the second difference and the third difference. The correction unit corrects the second counter based on the fourth difference.

[0010] According to the above disclosure, the fourth difference represents the difference between the count of the third counter and the count of the fourth counter during the period from when the previous synchronization signal was output until when the current synchronization signal is output. Since the first counter and the third counter are included in the same hardware circuit, they count up at the same period according to the clock of the same clock source. Similarly, since the second counter and the fourth counter are included in the same hardware circuit, they count up at the same period according to the clock of the same clock source. Therefore, the difference between the count of the first counter and the count of the second counter during the period is also the fourth difference. The correction unit corrects the second counter based on the fourth difference, thereby correcting the discrepancy between the values ​​of the first counter and the second counter caused by the oscillation error of the clock source.

[0011] Alternatively, the signal output unit may output a synchronization signal each time the value of the first counter increases by a certain amount. The time information output unit further outputs a certain value to the second unit. The second hardware circuit further includes a measurement unit that measures a second difference between the value of the second counter when the previous synchronization signal was output and the value of the second counter when the current synchronization signal is output. The difference calculation unit further calculates a third difference between the second difference and a certain value. The correction unit corrects the second counter based on the third difference.

[0012] According to the above disclosure, the third difference is the difference between the count of the first counter and the count of the second counter during a period in which the value of the first counter increases by a fixed amount. The correction unit corrects the second counter based on the third difference, thereby correcting the discrepancy between the values ​​of the first counter and the second counter caused by the oscillation error of the clock source. Furthermore, the size of the first and second hardware circuits can be reduced compared to a configuration that includes third and fourth counters.

[0013] In the above disclosure, the first unit further comprises a first light-emitting element that flashes according to the value of a first counter. The second unit further comprises a second light-emitting element that flashes according to the value of a second counter.

[0014] According to the above disclosure, the flashing cycles of the first light-emitting element and the second light-emitting element are synchronized, giving the user a sense of unity. Conversely, the user can recognize that some kind of abnormality has occurred by visually noticing that the flashing cycles of the first light-emitting element and the second light-emitting element are not synchronized.

[0015] In the above disclosure, the first unit further comprises a processor that executes firmware. The firmware includes an instruction for a signal output unit to set a timing for outputting a synchronization signal. The signal output unit outputs a synchronization signal when the value of a first counter reaches the timing. The firmware further includes an instruction for calculating a fifth difference between a second value and the above timing, and an instruction for correcting the second counter based on the fifth difference. After the firmware is started, the processor disables the operation of the time information output unit.

[0016] According to the above disclosure, after the firmware is started, the processor can synchronize the first counter and the second counter according to the firmware.

[0017] In the above disclosure, the first hardware circuit is an ASIC or FPGA. The second hardware circuit is an ASIC or FPGA. [Effects of the Invention]

[0018] According to this disclosure, the time required to investigate the cause of a malfunction that occurred before the firmware was started can be reduced. [Brief explanation of the drawing]

[0019] [Figure 1] This figure schematically shows an example of the configuration of the control device according to this embodiment. [Figure 2] It is a diagram schematically showing the configuration of a control device according to a reference form. [Figure 3] It is a schematic diagram showing a configuration example of a unit of a control device according to the present embodiment. [Figure 4] It is a diagram showing a signal waveform using UART. [Figure 5] It is a diagram showing a signal waveform corresponding to time information (value X1). [Figure 6] It is a diagram showing the flow of data accompanying the waveform of a synchronization signal. [Figure 7] It is a diagram schematically showing the configuration of a control device according to Modification 1. [Figure 8] It is a diagram schematically showing the configuration of a control device according to Modification 2. [Figure 9] It is a diagram schematically showing the configuration of a control device according to Modification 3. [Figure 10] It is a diagram showing the flow of data accompanying the waveform of a synchronization signal in Modification 3. [Figure 11] It is a diagram showing a signal distribution method when there are multiple extended units.

Embodiments for Carrying Out the Invention

[0020] Embodiments of the present invention will be described in detail with reference to the drawings. For the same or corresponding parts in the drawings, the same reference numerals are given and the description thereof will not be repeated.

[0021] §1 Application Example First, an example of a scenario to which the present invention is applied will be described. FIG. 1 is a diagram schematically showing an example of the configuration of a control device 1 according to the present embodiment. The control device 1 corresponds to, for example, a PLC. In the following description, as a typical example of the "control device", a PLC will be described as a specific example, but it is not limited to a PLC, and the technical idea disclosed in this specification is applicable to any control device.

[0022] As shown in Figure 1, the control device 1 includes a CPU unit 100 and an expansion unit 200 for exchanging data. In Figure 1, the control device 1 is shown to have one expansion unit 200, but it may have multiple expansion units 200. The CPU unit 100 is connected to the expansion unit 200 via a data bus 2 and signal lines 3 and 4.

[0023] The CPU unit 100 has a program execution unit that executes programs created according to the controlled object. More specifically, the CPU unit 100 corresponds to an arithmetic processing unit that executes system programs and various user programs.

[0024] The expansion unit 200 can be detachably attached to the CPU unit 100 to extend the functionality of the control device 1. The expansion unit 200 is configured, for example, to perform communication processing or information processing and to mediate between the network and the control device 1.

[0025] The CPU unit 100 includes a CPU 10, memory 11, storage 12, and hardware circuitry 13. The expansion unit 200 includes a CPU 20, memory 21, storage 22, and hardware circuitry 23.

[0026] CPU 10 reads firmware and various user programs stored in storage 12, loads them into memory 11, and executes them. Similarly, CPU 20 reads various programs stored in storage 22, loads them into memory 21, and executes them.

[0027] Hardware circuits 13 and 23 are, for example, FPGAs (Field-Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits).

[0028] The hardware circuit 13 includes a free-run counter (hereinafter referred to as "FRC") 131, a synchronization signal output unit 132, and a latch unit 133.

[0029] The FRC131 is a counter that counts up at a fixed period. The FRC131 is, for example, a 64-bit counter. Note that various other counters may be used instead of the FRC131.

[0030] The synchronization signal output unit 132 outputs a synchronization signal to the expansion unit 200 at any desired timing using the signal line 3. The synchronization signal output unit 132 arbitrarily generates the timing of the synchronization signal output. Alternatively, the synchronization signal output unit 132 may use the timing when the value of FRC 131 reaches a set value as the timing of the synchronization signal output. The synchronization signal output from the synchronization signal output unit 132 is also input to the latch unit 133.

[0031] The latch unit 133 latches the value X1 of FRC131 when the synchronization signal is output. Furthermore, the latch unit 133 outputs the held value X1 to the expansion unit 200 using the signal line 4. The value X1 latched by the latch unit 133 is time information indicating the time when the synchronization signal was output.

[0032] The hardware circuit 23 includes an FRC 231, a latch unit 232, a difference calculation unit 233, and an FRC correction unit 234.

[0033] The FRC231 is a counter that counts up at a fixed period. The FRC231 is, for example, a 64-bit counter. However, various other counters may be used instead of the FRC231.

[0034] The latch unit 232 latches the value X2 of FRC231 when it receives a synchronization signal from signal line 3. The latch unit 232 outputs the held value X2 to the difference calculation unit 233.

[0035] The difference calculation unit 233 calculates the difference Y1 (=X2-X1) between the value X2 output from the latch unit 232 (i.e., the value of FRC231 when the synchronization signal is received) and the value X1 received from signal line 4 (i.e., the value of FRC131 when the synchronization signal is output). The difference calculation unit 233 outputs the difference Y1 to the FRC correction unit 234.

[0036] The FRC correction unit 234 corrects FRC231 based on the difference Y1. That is, the FRC correction unit 234 corrects the value of FRC231 by the difference Y1 so that FRC131 and FRC231 are synchronized.

[0037] Next, we will explain the flow of the synchronization process of FRC131 and FRC231 that is executed in the control device 1.

[0038] First, the synchronization signal output unit 132 of the CPU unit 100 outputs a synchronization signal to the expansion unit 200. The synchronization signal is also output to the latch unit 133 (see (1) in the figure).

[0039] Next, the latch unit 133 of the CPU unit 100 latches the value X1 of FRC131 when the synchronization signal is output, in response to the input of the synchronization signal (see (2) in the figure). The latch unit 232 of the expansion unit 200 latches the value X2 of FRC231 when the synchronization signal is received, in response to the input of the synchronization signal (see (3) in the figure).

[0040] The latch unit 133 outputs the value X1 (time information indicating the timing when the synchronization signal was output) to the expansion unit 200 (see (4) in the figure). In other words, the latch unit 133 outputs the value X1 of FRC131 at the time the synchronization signal was output to the expansion unit 200.

[0041] The latch unit 232 outputs the value X2 it holds to the difference calculation unit 233 (see (5) in the figure). The difference calculation unit 233 calculates the difference Y1 between the value X2 held by the latch unit 232 and the value X1 received from the CPU unit 100 (see (6) in the figure). The difference calculation unit 233 outputs the calculated difference Y1 to the FRC correction unit 234 (see (7) in the figure).

[0042] The FRC correction unit 234 corrects FRC231 based on the difference Y1 (see (8) in the figure). This synchronizes FRC231 and FRC131. Processes (1) to (8) are executed repeatedly.

[0043] Thus, according to this embodiment, the synchronization process between FRC231 and FRC131 is performed by the hardware circuit 13 of the CPU unit 100 and the hardware circuit 23 of the expansion unit 200. Therefore, the synchronization process between FRC231 and FRC131 starts immediately after power is turned on to the control device 1. Consequently, FRC231 and FRC131 synchronize before the firmware stored in storage 12 is started.

[0044] Figure 2 is a schematic diagram showing the configuration of the control device 1Z according to the reference embodiment. As shown in Figure 2, the control device 1Z differs from the control device 1 shown in Figure 1 in that it is equipped with a CPU unit 100Z and an expansion unit 200Z, respectively, instead of the CPU unit 100 and expansion unit 200.

[0045] CPU unit 100Z differs from CPU unit 100 in that it includes hardware circuit 13Z instead of hardware circuit 13. Hardware circuit 13Z differs from hardware circuit 13 in that it does not have a latch portion 133.

[0046] The expansion unit 200Z differs from the expansion unit 200 in that it includes hardware circuit 23Z instead of hardware circuit 23. The hardware circuit 23Z differs from hardware circuit 23 in that it does not have a difference calculation unit 233.

[0047] Thus, in the control device 1Z, the hardware circuits 13Z and 23Z do not include the latch unit 133 and the difference calculation unit 233. Therefore, the hardware circuits 13Z and 23Z alone cannot synchronize FRC231 and FRC131. For this reason, the firmware stored in the storage 12 is used to synchronize FRC231 and FRC131.

[0048] The firmware includes an instruction to set a timing X1 for outputting a synchronization signal to the synchronization signal output unit 132 of the hardware circuit 13Z, and an instruction to read the value X1 held in the latch unit 232. Furthermore, the firmware includes an instruction to calculate the difference Y1 between the value X2 and the timing X1, and an instruction to cause the FRC correction unit 234 to correct the FRC 231 based on the difference Y1. The CPU 10 performs the synchronization process as follows, according to the firmware containing such instructions.

[0049] First, the CPU 10 of the CPU unit 100Z sets the timing X1 for outputting the synchronization signal to the synchronization signal output unit 132 (see (11) in the figure). When the value of FRC 131 reaches timing X1, the synchronization signal output unit 132 outputs the synchronization signal to the expansion unit 200Z (see (12) in the figure).

[0050] The latch section 232 of the expansion unit 200Z latches the value X2 of FRC231 when it receives a synchronization signal, in response to the input of the synchronization signal (see (13) in the figure).

[0051] The CPU 10 reads the value X2 held in the latch unit 232 via the data bus 2 (see (14) in the figure). The CPU 10 calculates the difference Y1 (=X2-X1) between the read X2 and the timing X1 set in the synchronization signal output unit 132, and sets the difference Y1 in the FRC correction unit 234 (see (15) in the figure).

[0052] The FRC correction unit 234 corrects the FRC 231 based on the difference Y1 (see (16) in the figure). As a result, the FRC 231 and the FRC 131 are synchronized. The processes (11) to (16) are repeatedly executed.

[0053] The CPU 10 performs the processes (11), (14), and (15) in the figure by executing firmware. That is, the synchronization process between the FRC 231 and the FRC 131 is started after the firmware is activated. Therefore, the FRC 131 and the FRC 231 are not synchronized from when the control device 1Z is powered on until the firmware is activated. As a result, if a problem occurs during this period, it becomes difficult to arrange the order of events in the CPU unit 100Z and the expansion unit 200Z, and it takes time to investigate the cause of the problem.

[0054] In contrast, in the control device 1 according to the present embodiment, the FRC 231 and the FRC 131 are synchronized before the firmware is activated. Therefore, even from when the power is turned on until the firmware is activated, it becomes easy to arrange the order of events in the CPU unit 100 and the expansion unit 200. As a result, the time required to investigate the cause of a problem that occurred before the firmware was activated can be shortened.

[0055] §2 Specific Example <A. Configuration Example of Units of Control Device> FIG. 3 is a schematic diagram showing a configuration example of units of the control device 1 according to the present embodiment. As shown in FIG. 3, the control device 1 includes a CPU unit 100, one or more expansion units 200, and one or more function units 300. The CPU unit 100 is connected to one or more expansion units 200 via a data bus 2 and signal lines 3, 4. The CPU unit 100 is also connected to one or more function units 300 via a data bus 5.

[0056] The functional unit 300 has the function of a so-called I / O unit that exchanges signals with the equipment and devices to be controlled and various devices (such as sensors and actuators) arranged therein.

[0057] The data bus 2 is a bus of an I / O serial interface that follows, for example, PCIe (PCI Express), although it is not limited thereto.

[0058] The signal line 3 is an optical fiber cable or an electrical signal cable and transmits a synchronization signal. The signal line 3 is connected between the signal port 11OP of the CPU unit 100 and the signal port 210P of the expansion unit 20O. The CPU unit 100 transmits a synchronization signal to the expansion unit 200 using the signal line 3.

[0059] The signal line 4 is an optical fiber cable or an electrical signal cable and transmits time information (value X1). The signal line 4 is connected between the signal port 111P of the CPU unit 100 and the signal port 211P of the expansion unit 200. The CPU unit 100 transmits time information (value X1) to the expansion unit 200 using the signal line 4.

[0060] <B. Transmission of Time Information> The hardware circuits 13, 23 communicate time information (value X1) using, for example, an asynchronous serial communication UART (Universal Asynchronous Receiver Transmitter).

[0061] FIG. 4 is a diagram showing a signal waveform using UART. As shown in FIG. 4, in UART, communication is performed in units of 8-bit data blocks. A Start bit and a Stop bit are respectively communicated before and after the 8-bit data block.

[0062] FIG. 5 is a diagram showing a signal waveform corresponding to time information (value X1). When the value X1 of FRC131 is represented by 64 bits, as shown in FIG. 5, eight 8-bit data blocks are transmitted.

[0063] <C. Example of Signal Waveform> FIG. 6 is a diagram showing the data flow associated with the waveform of the synchronization signal. In the example shown in FIG. 6, the synchronization signal is output at a fixed period. The fixed period is, for example, several milliseconds to several tens of milliseconds.

[0064] At the timing when the synchronization signal is asserted, the value X1 of FRC131 is latched by the latch unit 133, and the value X2 of FRC231 is latched by the latch unit 232.

[0065] The time information indicating the value X1 held in the latch unit 133 is transmitted to the extension unit 200, for example, using UART.

[0066] The difference calculation unit 233 calculates the difference Y (= X2 - X1) between the value X2 held in the latch unit 232 and the value X1 indicated by the transmitted time information. The value of FRC231 is corrected by the FRC correction unit 234 using the difference Y1.

[0067] <D. FRC Correction Method> The FRC correction unit 234 corrects the value of FRC231 by subtracting the difference Y1 from the value of FRC231.

[0068] Note that the FRC correction unit 234 may subtract the difference Y1 from the value of FRC 231 at once. Alternatively, the FRC correction unit 234 may divide the difference Y1 into a plurality of correction units, and repeatedly subtract the correction units from the value of FRC 231 a plurality of times at a correction period. The correction unit and the correction period are set in advance. For example, when the difference Y1 is 2 ns, the correction unit is 1 ns, and the correction period is 100 ns, the FRC correction unit 234 subtracts 1 ns from the value of FRC 231 at the time t1 immediately after the difference Y1 is calculated. Then, the FRC correction unit 234 subtracts 1 ns from the value of FRC 231 at the time t1 + 100 ns. As a result, FRC 231 and FRC 131 are gradually synchronized. As a result, it is possible to suppress the value of FRC 231 from changing extremely.

[0069] <E. Processing after Firmware Startup> When the storage 12 of the CPU unit 100 stores firmware including instructions for the processes (11), (14), and (15) shown in FIG. 2, after the startup of the firmware, the synchronization process according to (11) to (16) shown in FIG. 2 is executed. Therefore, when the storage 12 stores the firmware, the CPU 10 invalidates the operation of outputting time information by the latch unit 133 after the startup of the firmware. For example, the latch unit 133 has a flag, and is set to perform the operation of outputting time information when the flag is "1" and not to perform the operation of outputting time information when the flag is "0". The CPU 10 may switch the flag to "0" after the startup of the firmware. When the flag is switched to "0", time information is not output from the CPU unit 100 to the expansion unit 200, and thus the operation of the difference calculation unit 233 is also invalidated in the expansion unit 200. As a result, after the startup of the firmware, the synchronization process according to (1) to (8) shown in FIG. 1 is not executed.

[0070] As described above, before the startup of the firmware, the synchronization process according to (1) to (8) shown in FIG. is repeatedly executed, and after the startup of the firmware, the synchronization process according to (11) to (16) shown in FIG. 2 is repeatedly executed.

[0071] <F. Modified Example 1> In the CPU unit 100, the FRC 131 included in the hardware circuit 13 counts up according to a clock generated using a clock oscillator (not shown) outside the hardware circuit 13. Similarly, in the expansion unit 200, the FRC 231 included in the hardware circuit 23 counts up according to a clock generated using a clock oscillator (not shown) outside the hardware circuit 23. Therefore, due to the oscillation error (also referred to as static jitter) between the clock oscillator of the CPU unit 100 and the clock oscillator of the expansion unit 200, a slight deviation may occur between the period during which the FRC 131 counts up and the period during which the FRC 231 counts up. As a result, even if the values of the FRC 131 and the FRC 231 are once synchronized, they will gradually deviate thereafter. The control device according to Modified Example 1 corrects the deviation (hereinafter referred to as "clock deviation") between the values of the FRC 131 and the FRC 231 caused by static jitter.

[0072] FIG. 7 is a diagram schematically showing the configuration of the control device 1A according to Modified Example 1. As shown in FIG. 7, the control device 1A includes a CPU unit 100A and an expansion unit 200A. The CPU unit 100A is different from the CPU unit 100 shown in FIG. 1 in that it includes a hardware circuit 13A instead of the hardware circuit 13. The expansion unit 200A is different from the expansion unit 200 shown in FIG. 1 in that it includes a hardware circuit 23A instead of the hardware circuit 23. In FIG. 7, the illustration of the memories 11, 21 and the storages 12, 22 is omitted.

[0073] The hardware circuit 13A is different from the hardware circuit 13 in that it has a latch section 133A instead of the latch section 133 and further has an FRC 134. The synchronization signal output section 132 of the hardware circuit 13A repeatedly outputs a synchronization signal.

[0074] FRC134 is a counter that counts up at a fixed period, for example, a 64-bit counter. Note that various other counters may be used instead of FRC134. FRC131 and FRC134 count up according to a clock generated by a clock oscillator (not shown) provided in the CPU unit 100A. Therefore, FRC131 and FRC134 count up at the same period.

[0075] In addition to the operation of the latch unit 133, the latch unit 133A performs the following operations. Specifically, the latch unit 133A latches the value X3 of FRC134 when the synchronization signal is output. Furthermore, the latch unit 133A calculates the difference dX3 (=X3-X3') between the value X3' of FRC134 that was latched when the synchronization signal was previously output and the newly latched value X3, and outputs the difference dX3 to the expansion unit 200A.

[0076] Hardware circuit 23A differs from hardware circuit 23 in that it has a latch unit 232A, a difference calculation unit 233A, and an FRC correction unit 234A instead of a latch unit 232, a difference calculation unit 233, and an FRC correction unit 234, and also has an FRC 235.

[0077] The FRC235 is a counter that counts up at a fixed period, for example, a 64-bit counter. Various other counters may be used instead of the FRC235. The FRC231 and FRC235 count up according to a clock generated by a clock oscillator (not shown) provided in the expansion unit 200A. Therefore, the FRC231 and FRC235 count up at the same period.

[0078] In addition to the operation of the latch unit 232, the latch unit 232A performs the following operations. Specifically, the latch unit 232A latches the value X4 of FRC235 when it receives a synchronization signal from signal line 3. The latch unit 232A calculates the difference dX4 (=X4-X4') between the value X4' of FRC235 that was latched when the synchronization signal was received last time and the newly latched value X4, and outputs the difference dX4 to the difference calculation unit 233A.

[0079] In addition to the operation of the difference calculation unit 233, the difference calculation unit 233A performs the following operations. Specifically, the difference calculation unit 233A calculates the difference Y2 (=dX4-dX3) between the difference dX4 output from the latch unit 232A and the difference dX3 received from the signal line 4. The difference calculation unit 233A outputs the difference Y2 to the FRC correction unit 234A.

[0080] In addition to the operation of the FRC correction unit 234, the FRC correction unit 234A performs the following operation: that is, the FRC correction unit 234A corrects the FRC 231 based on the difference Y2.

[0081] Next, we will explain the process for correcting clock deviations caused by static jitter, which is performed in the control device 1A.

[0082] First, the synchronization signal output unit 132 of the CPU unit 100A outputs a synchronization signal to the expansion unit 200A. The synchronization signal is also output to the latch unit 133A (see (21) in the figure).

[0083] Next, the latch unit 133A of the CPU unit 100A latches the value X3 of FRC134 when the synchronization signal is output, in response to the input of the synchronization signal (see (22) in the figure). The latch unit 232A of the expansion unit 200A latches the value X4 of FRC235 when the synchronization signal is received, in response to the input of the synchronization signal (see (23) in the figure).

[0084] The latch unit 133A calculates the difference dX3 between the value X3' of the FRC134 that was latched when the synchronization signal was last output and the newly latched value X3, and outputs the difference dX3 to the expansion unit 200A (see (24) in the figure).

[0085] The latch unit 232A calculates the difference dX4 between the value X4' of the FRC235 that was latched when the synchronization signal was previously input and the newly latched value X4, and outputs the difference dX4 to the difference calculation unit 233A (see (25) in the figure). The difference calculation unit 233A calculates the difference Y2 between the difference dX4 and the difference dX3 (see (26) in the figure). The difference calculation unit 233A outputs the calculated difference Y2 to the FRC correction unit 234 (see (27) in the figure).

[0086] The FRC correction unit 234A corrects the FRC 231 based on the difference Y2 (see (28) in the figure).

[0087] The difference Y2 represents the difference between the count of FRC134 and the count of FRC235 during the period from when the previous synchronization signal was output to when the current synchronization signal is output. As mentioned above, FRC131 and 134 count up in the same period. Furthermore, FRC231 and 235 count up in the same period. Therefore, the difference between the count of FRC131 and the count of FRC231 during the period is also the difference Y2. The FRC correction unit 234A corrects the value of FRC231 by the difference Y2, thereby correcting the clock deviation caused by static jitter.

[0088] In control device 1A, as shown in Figure 1 (1)~( 8 According to the synchronization process, FRC231 is initially synchronized with FRC131. However, clock deviations due to static jitter continue to occur. Therefore, the FRC correction unit 234A periodically corrects FRC231 based on the difference Y2. For example, the FRC correction unit 234 corrects the clock deviation at a predetermined correction period. If T1 is the period from when the previous synchronization signal is output to when the current synchronization signal is output, and T2 is the correction period, then the FRC correction unit 234 only needs to correct FRC231 by (Y2 / T1) × T2 at each correction period. This ensures that clock deviations due to static jitter are always canceled out.

[0089] In addition, as a cause of the deviation between the values of FRC131 and FRC231, there is dynamic jitter in addition to static jitter. The dynamic jitter includes, for example, the transmission delay of the synchronization signal. According to the first modification, the clock deviation caused by the static jitter is always canceled. Therefore, even if the output period of the synchronization signal is lengthened, it is possible to avoid the deviation between the values of FRC131 and FRC231 caused by the dynamic jitter from becoming too large. As a result, when the synchronization process according to (11) to (16) shown in FIG. 2 is repeatedly executed after the firmware is started, the load required for the synchronization process by the CPU10 is reduced.

[0090] After the firmware is started, the CPU10 may only invalidate the output operation of the time information by the latch unit 133A and enable the output operation of the difference dX3 by the latch unit 133A. Thereby, even after the firmware is started, the hardware circuits 13A and 23A can continue to correct the clock deviation caused by the static jitter.

[0091] Alternatively, after the firmware is started, the CPU10 may invalidate the output operation of the difference dX3 by the latch unit 133A. In this case, the firmware includes an instruction to calculate the difference Y2 between the difference dX3 calculated by the latch unit 133A and the difference dX4 calculated by the latch unit 232A, and an instruction to correct FRC231 based on the difference Y2. The CPU10 may correct FRC231 based on the difference Y2 according to these instructions of the firmware. Thereby, after the firmware is started, the CPU10 can continue to correct the clock deviation caused by the static jitter. However, in this case, modification of the firmware is required. In order to omit the modification of the firmware, it is preferable that the CPU10 enables the output operation of the difference dX3 by the latch unit 133A after the firmware is started.

[0092] <G. Second Modification> FIG. 8 is a diagram schematically showing the configuration of the control device 1B according to the second modification. As shown in FIG. 8, the control device 1B includes a CPU unit 100B and an expansion unit 200B. The CPU unit 100B is different from the CPU unit 100 shown in FIG. 1 in that it includes a hardware circuit 13B instead of the hardware circuit 13. The expansion unit 200B is different from the expansion unit 200 shown in FIG. 1 in that it includes a hardware circuit 23B instead of the hardware circuit 23. In FIG. 8, the illustration of the memories 11 and 21 and the storages 12 and 22 is omitted. Also, the second modification may be combined with the first modification.

[0093] The hardware circuit 13B is different from the hardware circuit 13 in that it includes a light-emitting element 135. The hardware circuit 23B is different from the hardware circuit 23 in that it includes a light-emitting element 236.

[0094] The light-emitting elements 135 and 236 are, for example, light-emitting diodes. The light-emitting elements 135 and 236 blink according to the values of FRC131 and 231, respectively. Specifically, the light-emitting elements 135 and 236 emit light at the timing when FRC131 and 231 reach preset values. Before the firmware is started, FRC131 and 231 are synchronized by the processes of (1) to ( 8 [[ID=]) in FIG. 1. After the firmware is started, FRC131 and 231 are synchronized by the processes of (11) to ( ) in FIG. 2. 16 ) Therefore, the light-emitting elements 135 and 236 emit light at the same timing. As a result, in the control device 1B, the blinking periods of the light-emitting elements of each unit are synchronized, and a sense of unity can be given to the user. Conversely, the user can recognize that some abnormality has occurred by visually confirming that the blinking periods of the light-emitting elements of each unit are not synchronized.

[0095] <H. Third Modification> In Modification 1, each of the CPU unit 100A and the expansion unit 200A is equipped with two FRCs. As a result, the size of the hardware circuitry increases. Modification 3 is a configuration that suppresses the increase in the size of the hardware circuitry while continuously correcting the clock deviation caused by static jitter.

[0096] Figure 9 is a schematic diagram showing the configuration of the control device 1C according to the modified example 3. As shown in Figure 9, the control device 1C comprises a CPU unit 100C and an expansion unit 200C. The CPU unit 100C differs from the CPU unit 100A shown in Figure 7 in that it includes hardware circuit 13C instead of hardware circuit 13A. The expansion unit 200C differs from the expansion unit 200A shown in Figure 7 in that it includes hardware circuit 23C instead of hardware circuit 23A. Note that, as in Figure 7, the memory 11, 21 and storage 12, 22 are not shown in Figure 9.

[0097] Hardware circuit 13C differs from hardware circuit 13A in that it has a synchronization signal output unit 132C, a latch unit 133C, and a signal interval count unit 136 instead of a synchronization signal output unit 132, a latch unit 133A, and an FRC 134.

[0098] The signal interval counting unit 136 includes a counter that counts up according to a clock generated using a clock oscillator (not shown) provided in the CPU unit 100C. The signal interval counting unit 136 outputs an output instruction to the synchronization signal output unit 132C when the counter value reaches a certain value T. After outputting the output instruction to the synchronization signal output unit 132C, the signal interval counting unit 136 resets the counter value to 0.

[0099] The value T corresponds to a fixed period for outputting the synchronization signal and is set in advance. If the frequency of the clock generated using a clock oscillator (not shown) is 125 MHz, the value T is, for example, 125000 (equivalent to 1 ms). In this case, the signal interval counting unit 136 only needs to include a 16-bit counter. That is, the signal interval counting unit 136 includes a counter that is smaller in scale than the 64-bit FRC134 (see Figure 7). Therefore, compared to the first modification, the increase in the scale of the hardware circuit 13C is suppressed.

[0100] The synchronization signal output unit 132C outputs a synchronization signal to the expansion unit 200C in response to an output instruction received from the signal interval count unit 136. The synchronization signal output from the synchronization signal output unit 132C is also input to the latch unit 133C.

[0101] The FRC131 also counts up according to the clock generated using a clock oscillator (not shown) provided in the CPU unit 100C. Therefore, the counter included in the signal interval counting unit 136 and the FRC131 count up at the same period.

[0102] The latch unit 133C operates in the same manner as the latch unit 133 shown in Figure 1. That is, the latch unit 133C latches the value X1 of the FRC 131 when the synchronization signal is output and outputs time information including the held value X1 to the expansion unit 200C. Furthermore, the latch unit 133C includes the value T set in the signal interval count unit 136 in the time information.

[0103] Hardware circuit 23C differs from hardware circuit 23A in that it has a latch unit 232, a difference calculation unit 233C, an FRC correction unit 234C, and a signal interval measurement unit 237 instead of a latch unit 232A, a difference calculation unit 233A, an FRC correction unit 234A, and an FRC 235.

[0104] The signal interval measurement unit 237 includes a counter that counts up according to a clock generated using a clock oscillator (not shown) provided in the expansion unit 200C. When the signal interval measurement unit 237 receives a synchronization signal, it outputs the counter value T1 to the difference calculation unit 233C and resets the counter value to 0. As a result, the value T1 output from the signal interval measurement unit 237 represents the count-up from the time the previous synchronization signal was received to the time the current synchronization signal was received.

[0105] The value T1 approximately coincides with the constant period during which the synchronization signal is output. The value T1 is approximately the same as the value T. Therefore, the signal interval measurement unit 237 only needs to include a counter of the same size as the signal interval count unit 136. In other words, the signal interval measurement unit 237 only needs to include a counter smaller in scale than the 64-bit FRC235 (see Figure 7). As a result, the increase in the size of the hardware circuit 23C is suppressed compared to the first modification.

[0106] The FRC231 also counts up according to the clock generated using a clock oscillator (not shown) provided in the expansion unit 200C. Therefore, the counter included in the signal interval measurement unit 237 and the FRC231 count up at the same period. Accordingly, the signal interval measurement unit 237 measures the value T1 as the difference between the value of the FRC231 when the previous synchronization signal was output and the value of the FRC231 when the current synchronization signal is output.

[0107] The difference calculation unit 233C operates in the same manner as the difference calculation unit 233 shown in Figure 1. Specifically, the difference calculation unit 233C calculates the difference Y1 (=X2-X1) between the value X2 output from the latch unit 232 (i.e., the value of FRC231 when the synchronization signal is received) and the value X1 received from the CPU unit 100C (i.e., the value of FRC131 when the synchronization signal is output). Furthermore, the difference calculation unit 233C calculates the difference Z (=T1-T) between the value T1 received from the signal interval measurement unit 237 and the value T received from the CPU unit 100C. The difference calculation unit 233C outputs the differences Y1 and Z to the FRC correction unit 234C.

[0108] In addition to the operation of the FRC correction unit 234 shown in Figure 1, the FRC correction unit 234C corrects the FRC 231 based on the difference Z.

[0109] Next, the flow of the correction process performed in the control device 1C will be explained. First, when the signal interval counting unit 136 of the CPU unit 100C reaches a preset value T, it outputs an output instruction to the synchronization signal output unit 132C and resets the counter value to 0 (see (31) in the figure).

[0110] Next, the synchronization signal output unit 132C outputs a synchronization signal to the expansion unit 200C according to the output instruction. The synchronization signal is also output to the latch unit 133C of the CPU unit 100C (see (32) in the figure).

[0111] The latch unit 133C latches the value X1 of FRC131 at the time the synchronization signal is output, and outputs time information including the value X1 and the value T set in the signal interval count unit 136 to the expansion unit 200C (see (33) in the figure).

[0112] The latch unit 232 of the expansion unit 200C latches the value X2 of FRC231 when it receives the synchronization signal, and outputs the value X2 to the difference calculation unit 233C (see (34) in the figure).

[0113] The signal interval measurement unit 237 of the expansion unit 200C measures a value T1, which is the count-up from the timing of the previous synchronization signal to the timing of the current synchronization signal, in response to the input of the synchronization signal, and outputs the value T1 to the difference calculation unit 233C (see (35) in the figure).

[0114] Next, the difference calculation unit 233C calculates the difference Y1 between value X2 and value X1, and the difference Z between value T1 and value T (see (36) in the figure). The difference calculation unit 233C outputs the calculated differences Y1 and Z to the FRC correction unit 234C (see (37) in the figure).

[0115] Next, the FRC correction unit 234C corrects the FRC 231 based on the difference Y1,Z (see (38) in the figure). The method for correcting the FRC 231 based on the difference Y1 is as described above.

[0116] The correction method for FRC231 based on the difference Z is the same as the correction method for FRC231 based on the difference Y2.

[0117] The difference Z represents the difference between the count of the signal interval count unit 136 and the count of the signal interval measurement unit 237 during the period from when the previous synchronization signal was output until when the current synchronization signal is output. As described above, the counter included in the signal interval count unit 136 and the FRC 131 count up at the same period. Furthermore, the counter included in the signal interval measurement unit 237 and the FRC 231 count up at the same period. Therefore, the difference Z is a clock deviation caused by static jitter.

[0118] Clock deviations caused by static jitter are constantly occurring. Therefore, the FRC correction unit 234C periodically corrects the FRC 231 based on the difference Z. For example, the FRC correction unit 234C corrects the clock deviation at a predetermined correction period. If T1 is the period from when the previous synchronization signal was output to when the current synchronization signal is output, and T2 is the correction period, then the FRC correction unit 234C only needs to correct the FRC 231 by (Z / T1) × T2 at each correction period. This ensures that clock deviations caused by static jitter are always canceled out.

[0119] Figure 10 shows the data flow associated with the waveform of the synchronization signal in Modification 3. Figure 10 shows the data flow related to the correction of clock deviation caused by static jitter.

[0120] As shown in Figure 10, the synchronization signal is output at a constant period indicated by the value T. When the synchronization signal is asserted, time information including the value T is output from the CPU unit 100C to the expansion unit 200C.

[0121] The signal interval measurement unit 237 of the expansion unit 200C measures a value T1, which is the count-up value from the timing of receiving the previous synchronization signal to the timing of receiving the current synchronization signal. For example, when a synchronization signal is received at timing t1, a value T11, which is the count-up value from the timing t0 of receiving the previous synchronization signal to the timing t1, is measured. Then, the difference Z1 between the value T11 and the value T is calculated, and the FRC 231 is corrected based on the difference Z1.

[0122] The clock deviation caused by static jitter also depends on factors such as temperature. Therefore, the value T1 measured each time a synchronization signal is received can vary depending on the environment. Thus, by measuring the value T1 at a fixed period, the clock deviation caused by static jitter is appropriately corrected according to the environment.

[0123] <I. When there are multiple expansion units> FIG. 11 is a diagram showing a signal distribution method when there are multiple expansion units. As shown in FIG. 11, each of the signal lines 3 and 4 connects the CPU unit 100 and a plurality of expansion units 200 in a multi-drop configuration. Therefore, the synchronization signal and time information output from the CPU unit 100 are distributed to the plurality of expansion units 200 via the signal lines 3 and 4, respectively.

[0124] On the other hand, the data bus 2 compliant with PCIe connects the CPU unit 100 and each of the plurality of expansion units 200 in a one-to-one manner.

[0125] In FIG. 11, the CPU unit 100 may be replaced with any of the CPU units 100A, 100B, and 100C. Also, each of the plurality of expansion units 200 may be replaced with any of the expansion units 200A, 200B, and 200C.

[0126] §3 Supplementary Note As described above, the present embodiment includes the following disclosure.

[0127] (Configuration 1) Control device (1,1A,1B,1C), It comprises a first unit (100, 100A, 100B, 100C) and a second unit (200, 200A, 200B, 200C) for exchanging data. The first unit includes a first hardware circuit (13, 13A, 13B, 13C), The second unit includes a second hardware circuit (23, 23A, 23B, 23C), The first hardware circuit described above is: The first counter (131), A signal output section (132, 132C) outputs a synchronization signal to the second unit, It includes a time information output unit (133, 133A, 133C) that outputs a first value of the first counter when the synchronization signal is output to the second unit, The second hardware circuit is, The second counter (231), A difference calculation unit (233, 233A, 233C) calculates a first difference between the second value of the second counter and the first value when the aforementioned synchronization signal is received, A control device having a correction unit (234, 234A, 234C) that corrects the second counter based on the first difference.

[0128] (Configuration 2) The first hardware circuit (13A) further includes a third counter (134), The second hardware circuit (23A) further includes a fourth counter (235), The signal output unit (132) repeatedly outputs the synchronization signal, The time information output unit (133A) further outputs to the second unit (200A) a second difference between the value of the third counter when the previous synchronization signal was output and the value of the third counter when the current synchronization signal was output. The difference calculation unit (233A) further, A third difference is calculated between the value of the fourth counter when the previous synchronization signal was received and the value of the fourth counter when the current synchronization signal was received. Calculate the fourth difference between the second difference and the third difference, The correction unit (234A) corrects the second counter based on the fourth difference, as described in configuration 1, and is the control device (1A).

[0129] (Composition 3) The signal output unit (132C) outputs the synchronization signal each time the value of the first counter increases by a certain amount. The aforementioned time information output unit (133C) further outputs the aforementioned constant value to the second unit, The second hardware circuit (23C) further includes a measuring unit (237) that measures a second difference between the value of the second counter when the previous synchronization signal was output and the value of the second counter when the current synchronization signal is output. The difference calculation unit (233C) further calculates a third difference between the second difference and the constant value, The control device (1C) according to claim 1, wherein the correction unit (234C) corrects the second counter based on the third difference.

[0130] (Composition 4) The first unit (100B) further comprises a first light-emitting element (135) that flashes according to the value of the first counter, The second unit ( 200B The control device (1B) according to any one of configurations 1 to 3 further comprises a second light-emitting element (236) that blinks according to the value of the second counter.

[0131] (Composition 5) The first unit further comprises a processor (10) that runs firmware, The firmware includes a command to the signal output unit to set the timing for outputting the synchronization signal, The signal output unit outputs the synchronization signal when the value of the first counter reaches the timing. The aforementioned firmware further, An instruction to calculate a fifth difference between the second value and the timing, Includes an instruction to correct the second counter based on the fifth difference, The control device according to Configuration 1, wherein the processor disables the operation of the time information output unit after the firmware is started.

[0132] (Composition 6) The first hardware circuit described above is an ASIC or FPGA, The control device according to any one of configurations 1 to 5, wherein the second hardware circuit is an ASIC or FPGA.

[0133] While embodiments of the present invention have been described, the embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present invention is defined by the claims, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of Symbols]

[0134] 1,1A,1B,1C,1Z Control unit, 2,5 Data bus, 3,4 Signal lines, 10,20 CPU, 11,21 Memory, 12,22 Storage, 13,13A,13B,13C,13Z,23,23A,23B,23C,23Z Hardware circuits, 100,100A,100B,100C,100Z CPU unit, 110P,111P,210P,211P Signal ports, 132,132C Synchronization signal output unit, 133,133A,133C,232,232A Latch unit, 135,236 Light-emitting element, 136 Signal interval count unit, 200,200A,200B,200C,200Z Expansion unit, 233,233A,233C Difference calculation part, 234,234A,234C FRC Correction unit, 237 signal interval measurement unit, 300 function unit.

Claims

1. A control device, It comprises a first unit and a second unit for exchanging data, The first unit includes a first hardware circuit, The second unit includes a second hardware circuit, The first hardware circuit is, The first counter and A signal output unit that outputs a synchronization signal to the second unit, It includes a time information output unit that outputs a first value of the first counter when the synchronization signal is output to the second unit, The second hardware circuit is, The second counter, A difference calculation unit calculates a first difference between the second value of the second counter and the first value when the synchronization signal is received, The device includes a correction unit for correcting the second counter, The first hardware circuit further comprises a third counter, The second hardware circuit further includes a fourth counter, The signal output unit repeatedly outputs the synchronization signal, The time information output unit further outputs to the second unit the second difference between the value of the third counter when the previous synchronization signal was output and the value of the third counter when the current synchronization signal was output. The difference calculation unit further, A third difference is calculated between the value of the fourth counter when the previous synchronization signal was received and the value of the fourth counter when the current synchronization signal was received. Calculate the fourth difference between the second difference and the third difference, The correction unit is a control device that corrects the second counter based on the first difference and the fourth difference.

2. A control device, It comprises a first unit and a second unit for exchanging data, The first unit includes a first hardware circuit, The second unit includes a second hardware circuit, The first hardware circuit is, The first counter and A signal output unit that outputs a synchronization signal to the second unit, It includes a time information output unit that outputs a first value of the first counter when the synchronization signal is output to the second unit, The second hardware circuit is, The second counter, A difference calculation unit calculates a first difference between the second value of the second counter and the first value when the synchronization signal is received, The device includes a correction unit for correcting the second counter, The signal output unit outputs the synchronization signal each time the value of the first counter increases by a certain amount. The time information output unit further outputs the constant value to the second unit. The second hardware circuit further includes a measuring unit that measures a second difference between the value of the second counter when the previous synchronization signal was output and the value of the second counter when the current synchronization signal is output. The difference calculation unit further calculates a third difference between the second difference and the constant value, The correction unit is a control device that corrects the second counter based on the first difference and the third difference.

3. A control device, It comprises a first unit and a second unit for exchanging data, The first unit includes a first hardware circuit, The second unit includes a second hardware circuit, The first hardware circuit is, The first counter and A signal output unit that outputs a synchronization signal to the second unit, It includes a time information output unit that outputs a first value of the first counter when the synchronization signal is output to the second unit, The second hardware circuit is, The second counter, A difference calculation unit calculates a first difference between the second value of the second counter and the first value when the synchronization signal is received, It includes a correction unit that corrects the second counter based on the first difference, The first unit further comprises a first light-emitting element that flashes according to the value of the first counter, The control device further comprises a second light-emitting element that flashes according to the value of the second counter.

4. The first unit further comprises a first light-emitting element that flashes according to the value of the first counter, The control device according to claim 1 or 2, wherein the second unit further comprises a second light-emitting element that flashes according to the value of the second counter.

5. A control device, It comprises a first unit and a second unit for exchanging data, The first unit includes a first hardware circuit, The second unit includes a second hardware circuit, The first hardware circuit is, The first counter and A signal output unit that outputs a synchronization signal to the second unit, It includes a time information output unit that outputs a first value of the first counter when the synchronization signal is output to the second unit, The second hardware circuit is, The second counter, A difference calculation unit calculates a first difference between the second value of the second counter and the first value when the synchronization signal is received, The device includes a correction unit for correcting the second counter, The first unit further comprises a processor that runs firmware, The firmware includes an instruction to the signal output unit to set a first timing for outputting the synchronization signal, The signal output unit outputs the synchronization signal at an arbitrary second timing before the firmware is started, and outputs the synchronization signal when the value of the first counter reaches the first timing after the firmware is started. The aforementioned firmware further, A first instruction for calculating a fifth difference between the second value and the first timing, The system includes a second instruction that causes the second counter to be corrected based on the fifth difference, The processor, after the firmware is started, disables the operation of the time information output unit. The correction unit corrects the second counter based on the first difference before the firmware is started, and corrects the second counter based on the fifth difference in accordance with the first and second commands after the firmware is started.

6. The first hardware circuit is an ASIC or FPGA, The control device according to any one of claims 1 to 5, wherein the second hardware circuit is an ASIC or an FPGA.

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