Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of satisfactorily forming a metal film in a contact hole when a silicide layer is formed at the bottom of the contact hole in an interlayer insulating film.SOLUTION: A semiconductor device includes a semiconductor substrate, a plurality of trenches provided on the upper surface side of the semiconductor substrate, an insulated gate electrode structure (6,7) embedded inside the plurality of trenches, an interlayer insulating film 20 provided on the upper surface of the semiconductor substrate and the insulated gate electrode structure (6, 7), and a silicide layer 31 provided at the bottom of a contact hole 20a penetrating the interlayer insulating film 20 and in contact with the upper surface of the semiconductor substrate sandwiched between the adjacent trenches 11, and at least a part of the lower surface 31a of the silicide layer 31 is located above the lower surface 20b of the interlayer insulating film 20.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] In a trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET) or insulated-gate bipolar transistor (IGBT), a through-hole (contact hole) is formed in the interlayer insulating film on the mesa to expose the mesa, which is sandwiched between adjacent trenches, in order to connect the mesa to the source electrode or emitter electrode. A barrier metal such as a titanium film and a titanium nitride film is deposited in the contact hole, and then the inside of the contact hole is filled with a tungsten film before the source electrode or emitter electrode is deposited. To prevent the tungsten (W) of the tungsten film from diffusing into the silicon (Si) of the mesa, and to improve adhesion, the titanium film at the bottom of the contact hole is silicided to form a titanium silicide layer before the tungsten film is embedded.

[0003] Patent Document 1 discloses a semiconductor device having a transistor section and a diode section, and having a lifetime control region inside a semiconductor substrate. Patent Document 2 discloses that the first metal film of the barrier metal included in the surface electrode formed on the entire surface of the cell region in which the IGBT is formed is made of a Group VIII metal material such as nickel or cobalt. Patent Document 3 discloses that contact holes are opened, a silicon thin film and a barrier metal are sequentially deposited, or that after sequentially depositing the barrier metal and silicon thin film, heat treatment is performed to form a silicide. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] International Publication No. 2020 / 036015 [Patent Document 2] Japanese Patent Publication No. 2011-181840 [Patent Document 3] Japanese Patent Publication No. 2002-198325 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] When forming a titanium silicide layer by silicideizing the titanium film at the bottom of the contact hole, the titanium (Ti) in the titanium film reacts with the silicon (Si) in the mesa region, reducing the volume of the mesa region. This causes the contact hole to expand below the interlayer insulating film, forming an overhang on the interlayer insulating film. As a result, it may not be possible to properly deposit metal films such as titanium nitride films or tungsten films within the contact hole after the titanium silicide layer has been formed. This raises concerns such as the diffusion of tungsten (W) from the tungsten film into the silicon (Si) in the mesa region.

[0006] The present invention aims to provide a semiconductor device and a method for manufacturing the same that can successfully form a metal film inside a contact hole when a silicide layer is formed at the bottom of the contact hole of an interlayer insulating film. [Means for solving the problem]

[0007] To achieve the above objective, one aspect of the present invention provides a semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of trenches provided on the upper surface side of the semiconductor substrate; (c) an insulated gate type electrode structure embedded inside the plurality of trenches; (d) an interlayer insulating film provided on the upper surfaces of the semiconductor substrate and the insulated gate type electrode structure; and (e) a silicide layer provided at the bottom of a contact hole penetrating the interlayer insulating film and in contact with the upper surface of the semiconductor substrate sandwiched between adjacent trenches, wherein at least a portion of the lower surface of the silicide layer is located above the lower surface of the interlayer insulating film.

[0008] Another aspect of the present invention is a method for manufacturing a semiconductor device, which mainly includes: (a) a step of forming a plurality of trenches from the upper surface side of a semiconductor substrate, and a step of embedding an insulated gate electrode structure in each of the plurality of trenches; (b) a step of depositing an interlayer insulating film on the upper surfaces of the semiconductor substrate and the insulated gate electrode structure; (c) a step of forming a contact hole in the interlayer insulating film located on the semiconductor substrate sandwiched between adjacent trenches; and (d) a step of forming a silicide layer inside the contact hole such that at least a part of the lower surface of the silicide layer is located above the lower surface of the interlayer insulating film.

Advantages of the Invention

[0009] According to the present invention, when forming a silicide layer at the bottom of a contact hole in an interlayer insulating film, a semiconductor device and a method for manufacturing the same can be provided, in which a metal film can be well formed in the contact hole.

Brief Description of the Drawings

[0010] [Figure 1] It is a plan view showing an example of a semiconductor device according to the first embodiment. [Figure 2] It is a cross-sectional view taken along the line A-A in FIG. 1. [Figure 3] It is an enlarged view of region A in FIG. 2. [Figure 4] It is a cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] It is a cross-sectional view following FIG. 4 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] It is a cross-sectional view following FIG. 5 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] It is a cross-sectional view following FIG. 6 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] It is a cross-sectional view following FIG. 7 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9]A cross-sectional view following FIG. 8 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] A cross-sectional view following FIG. 9 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] A cross-sectional view following FIG. 10 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] A cross-sectional view following FIG. 11 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] A cross-sectional view for explaining a method for manufacturing a semiconductor device according to a comparative example. [Figure 14] A cross-sectional view following FIG. 13 for explaining a method for manufacturing a semiconductor device according to a comparative example. [Figure 15] A cross-sectional view following FIG. 14 for explaining a method for manufacturing a semiconductor device according to a comparative example. [Figure 16] A cross-sectional view following FIG. 15 for explaining a method for manufacturing a semiconductor device according to a comparative example. [Figure 17] A cross-sectional view following FIG. 16 for explaining a method for manufacturing a semiconductor device according to a comparative example. [Figure 18] A cross-sectional view for explaining a method for manufacturing a semiconductor device according to a first modification of the first embodiment. [Figure 19] A cross-sectional view for explaining a method for manufacturing a semiconductor device according to a second modification of the first embodiment. [Figure 20] A cross-sectional view following FIG. 19 for explaining a method for manufacturing a semiconductor device according to a second modification of the first embodiment. [Figure 21] A cross-sectional view for explaining a method for manufacturing a semiconductor device according to a third modification of the first embodiment. [Figure 22] A cross-sectional view following FIG. 21 for explaining a method for manufacturing a semiconductor device according to a third modification of the first embodiment. [Figure 23] A cross-sectional view for explaining a method for manufacturing a semiconductor device according to a fourth modification of the first embodiment. [Figure 24] This is a cross-sectional view following Figure 23, illustrating a method for manufacturing a semiconductor device according to a fourth modified example of the first embodiment. [Figure 25] This is a cross-sectional view following Figure 24, illustrating a method for manufacturing a semiconductor device according to a fourth modified example of the first embodiment. [Figure 26] This is a cross-sectional view of a semiconductor device according to a fifth modified example of the first embodiment. [Figure 27] This is a cross-sectional view showing an example of a semiconductor device according to the second embodiment. [Figure 28] This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 29] This is a cross-sectional view following Figure 28, illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 30] This is a cross-sectional view following Figure 29 illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0011] The first and second embodiments of the present invention will be described below with reference to the drawings. In the drawings referred to in the following description, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following description. Furthermore, it goes without saying that there are parts where the relationships and ratios of dimensions differ between drawings.

[0012] In this specification, the source region of a MOSFET is "one main region (first main region)" that can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). In thyristors such as MOS-controlled electrostatic induction thyristors (SI thyristors), "one main region" can be selected as the cathode region. The drain region of a MOSFET is "the other main region (second main region)" of the semiconductor device that can be selected as the collector region in the case of an IGBT, or as the anode region in the case of an SI thyristor. In this specification, when simply referred to as "main region," it means either the first main region or the second main region that is reasonable according to the common technical knowledge of those skilled in the art.

[0013] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of the present invention. For example, it is obvious that if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.

[0014] Furthermore, the following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The + and - attached to n and p indicate semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without + and - markings. However, even if two semiconductor regions are marked with the same n, this does not mean that the impurity concentrations in each semiconductor region are exactly the same.

[0015] (First Embodiment) <Structure of a semiconductor device> Figure 1 is a plan view of a portion of the active region of the semiconductor device according to the first embodiment, viewed from the top (front) side. As shown in Figure 1, the semiconductor device according to the first embodiment includes a transistor section 101, which includes a transistor element such as an IGBT, and a diode section 102, which includes a diode element, on the same semiconductor chip. For example, the semiconductor device according to the first embodiment is a reverse-conducting IGBT (RC-IGBT) that includes an IGBT, which is the transistor section 101, and a freewheeling diode (FWD), which is the diode section 102 and is connected in antiparallel to the IGBT, on the same semiconductor chip. The transistor section 101 and the diode section 102 may be arranged alternately in the left-right direction in Figure 1.

[0016] Figure 2 shows a cross-section obtained by cutting through the transistor section 101 and diode section 102 in Figure 1 with line AA. As shown in Figure 2, the semiconductor device according to the first embodiment includes a semiconductor substrate 10. The semiconductor substrate 10 is made of, for example, a silicon (Si) substrate. However, the semiconductor substrate 10 is not limited to a Si substrate, and may be a semiconductor substrate made of a semiconductor with a wider band gap than Si (wide bandgap semiconductor), such as silicon carbide (SiC), gallium nitride (GaN), diamond (C), or aluminum nitride (AlN).

[0017] The semiconductor substrate 10 is a first conductivity type (n - The transistor section 101 includes an n-type drift layer 1. In the transistor section 101, an n-type storage layer 2 with a higher impurity concentration than the drift layer 1 is provided on the upper surface of the drift layer 1. The lower surface of the storage layer 2 is in contact with the upper surface of the drift layer 1. By providing the storage layer 2, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage can be reduced.

[0018] In the transistor section 101, the upper surface of the storage layer 2 has a second conductivity type (p - A base region 3 of type ( ) is provided. The lower surface of the base region 3 is in contact with the upper surface of the storage layer 2. On the upper surface side of the base region 3, n +A first main region (emitter region) 4 of the type is provided. The lower surface of the emitter region 4 is in contact with the upper surface of the base region 3. The impurity concentration of the emitter region 4 is higher than the impurity concentrations of the drift layer 1 and the storage layer 2.

[0019] On the other hand, in the diode section 102, an n-type storage layer 2 with a higher impurity concentration than the drift layer 1 is provided on the upper surface side of the drift layer 1. The storage layer 2 of the diode section 102 is not required. The lower surface of the storage layer 2 is in contact with the upper surface of the drift layer 1. On the upper surface side of the storage layer 2, p - A type anode region 13 is provided. The lower surface of the anode region 13 is in contact with the upper surface of the storage layer 2. The anode region 13 extends to the upper surface of the semiconductor substrate 10. The anode region 13 may be provided to the same depth as the base region 3 of the transistor section 101 and with the same impurity concentration.

[0020] In the transistor section 101 and the diode section 102, a plurality of trenches 11 are provided spaced apart from each other in the depth direction from the upper surface of the semiconductor substrate 10. In the transistor section 101, the trenches 11 penetrate the emitter region 4, the base region 3, and the storage layer 2 to reach the drift layer 1. The sides of the trenches 11 are in contact with the sides of the emitter region 4, the base region 3, and the storage layer 2. In the diode section 102, the trenches 11 penetrate the anode region 13 and the storage layer 2 to reach the drift layer 1. The sides of the trenches 11 are in contact with the sides of the anode region 13 and the storage layer 2.

[0021] Between adjacent trenches 11, a mesa region is provided, which is the upper part of the semiconductor substrate 10. The mesa region is the area of ​​the semiconductor substrate 10 sandwiched between adjacent trenches 11, and is the area above the deepest part of the trench 11. The mesa region of the transistor section 101 is provided with the upper part of the drift layer 1, the storage layer 2, the base region 3, and the emitter region 4. The mesa region of the diode section 102 is provided with the upper part of the drift layer 1, the storage layer 2, and the anode region 13.

[0022] A gate insulating film 6 is provided so as to cover the bottom and sides of the trench 11. As the gate insulating film 6, one single layer film of any of the following can be used: silicon dioxide film (SiO2 film), silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a composite film made by stacking multiple of these.

[0023] Inside the trench 11, a gate electrode 7 is embedded via a gate insulating film 6. The gate insulating film 6 and the gate electrode 7 constitute an insulated gate electrode structure (6,7). As the material for the gate electrode 7, for example, a polysilicon film (doped polysilicon film) with high impurity concentrations of impurities such as phosphorus (P) or boron (B) can be used.

[0024] In the transistor section 101, some of the multiple insulated gate electrode structures (6,7) may be gate trenches connected to the gate runner, while the remaining insulated gate electrode structures (6,7) may be dummy trenches not connected to the gate runner. Similarly, in the diode section 102, some of the multiple insulated gate electrode structures (6,7) may be dummy trenches not connected to the gate runner.

[0025] As shown in Figure 1, on the planar pattern, the multiple trenches 11 have linear (striped) portions that extend parallel to each other in one direction (the vertical direction in Figure 1). In the transistor section 101, parallel to the extension direction (longitudinal direction) of the trenches 11, p + Type contact areas 5 and n +The emitter regions 4 are arranged alternately and periodically. The contact region 5 is in contact with the emitter region 4. The contact region 5 is located on the upper side of the base region 3 shown in Figure 2. The lower surface of the contact region 5 is in contact with the upper surface of the base region 3. The impurity concentration of the contact region 5 is higher than that of the base region 3. In the diode section 102, the anode region 13 has a linear (striped) portion that extends parallel to the extension direction of the trench 11.

[0026] As shown in Figure 2, an interlayer insulating film 20 is provided on the upper surface of the semiconductor substrate 10 and the insulated gate type electrode structure (6,7). The interlayer insulating film 20 is composed of single-layer films such as undoped silicon oxide films (SiO2 films) that do not contain phosphorus (P) or boron (B), referred to as "NSG," phosphorus-doped silicon oxide films (PSG films), boron-doped silicon oxide films (BSG films), boron and phosphorus-doped silicon oxide films (BPSG films), silicon nitride films (Si3N4 films), or laminates thereof.

[0027] The interlayer insulating film 20 located on the mesa portion of the semiconductor substrate 10 is provided with contact holes 20a that penetrate the interlayer insulating film 20. A connecting conductor portion (contact plug) 30 is embedded in the contact hole 20a. In the transistor portion 101, the lower surface of the connecting conductor portion 30 is in contact with the upper surfaces of the emitter region 4 and the contact region 5. In the diode portion 102, the lower surface of the connecting conductor portion 30 is in contact with the upper surface of the anode region 13.

[0028] Surface electrodes 40 are provided on the interlayer insulating film 20. In the transistor section 101, the surface electrodes 40 are electrically connected to the emitter region 4 and the contact region 5 via the connecting conductor section 30 and function as emitter electrodes. In the diode section 102, the surface electrodes 40 are electrically connected to the anode region 13 via the connecting conductor section 30 and function as anode electrodes.

[0029] In Figure 1, the interlayer insulating film 20, connecting conductor portion 30, and surface electrode 40 shown in Figure 2 are omitted. Also, in Figure 1, the positions of the contact holes 20a of the interlayer insulating film 20 shown in Figure 2 are schematically shown with dashed lines. The contact holes 20a have linear (striped) portions that extend parallel to the longitudinal direction of the trench 11 on the planar pattern. In the transistor portion 101, the contact holes 20a are provided on the upper side of the emitter region 4 and the contact region 5. In the diode portion 102, the contact holes 20a are provided on the upper side of the anode region 13.

[0030] Figure 3 shows an enlarged cross-section of region A, which includes the connecting conductor portion 30 of the transistor portion 101 in Figure 2. The enlarged cross-section of the region including the connecting conductor portion 30 of the diode portion 102 in Figure 2 has the same configuration as the cross-section shown in Figure 3.

[0031] As shown in Figure 3, a protrusion 4a is provided on the upper part of the emitter region 4. The protrusion 4a is provided at approximately the center of the mesa region sandwiched between adjacent trenches 11, and spaced apart from the trenches 11. The height h1 of the protrusion 4a is, for example, about 20 nm or more and 300 nm or less. The width w1 of the protrusion 4a is, for example, about 20% or more and 90% or less of the width w2 of the mesa region.

[0032] Furthermore, a similar protrusion is provided on the upper part of the contact area 5 shown in Figure 1. Specifically, the protrusion has a linear (striped) portion that extends parallel to the direction of extension of the trench 11, at approximately the center of the mesa portion sandwiched between adjacent trenches 11 on the planar pattern.

[0033] As shown in Figure 3, the interlayer insulating film 20 has an insulated gate type electrode structure (6,7) and a first insulating film 21 provided on the upper side of the emitter region 4, and a second insulating film 22 provided on the upper side of the first insulating film 21. For example, the first insulating film 21 is made of a high-temperature oxide film (HTO film), and the second insulating film 22 is made of a BPSG film. The thickness of the second insulating film 22 is greater than the thickness of the first insulating film 21. Although Figure 3 illustrates a case where the interlayer insulating film 20 has a two-layer structure, the interlayer insulating film may also have a single-layer structure or a laminated structure of three or more layers.

[0034] The contact holes 20a of the interlayer insulating film 20 are provided in a tapered shape, for example, narrowing from the top to the bottom. The top surface of the protrusion 4a is exposed on the bottom surface of the contact hole 20a. The width of the bottom surface of the contact hole 20a is approximately equal to the width w1 of the protrusion 4a. The side surface of the protrusion 4a is in contact with the side surface of the first insulating film 21. The top surface of the protrusion 4a is located above the bottom surface 20b of the interlayer insulating film 20, which is the bottom surface of the first insulating film 21.

[0035] A connecting conductor portion 30 is embedded within the contact hole 20a. The connecting conductor portion 30 comprises a titanium silicide layer 31, which is a silicide layer made of titanium silicide (TiSi2); a titanium nitride film 32, which is a barrier metal film made of titanium nitride (TiN); and a tungsten film 33, which is a metal film made of tungsten (W).

[0036] The thickness of the titanium silicide layer 31 is, for example, between 20 nm and 80 nm. The thickness of the titanium nitride film 32 is, for example, between 20 nm and 140 nm. The thickness of the tungsten film 33 is, for example, between 100 nm and 1500 nm.

[0037] The titanium silicide layer 31 is provided at the bottom of the contact hole 20a. The lower surface 31a of the titanium silicide layer 31 is in contact with the upper surface of the protrusion 4a. The side surface of the titanium silicide layer 31 is in contact with the first insulating film 21. Figure 3 illustrates the case where the lower surface 31a of the titanium silicide layer 31 is flat and the entire lower surface 31a of the titanium silicide layer 31 is located above the position of the lower surface 20b of the interlayer insulating film 20.

[0038] Furthermore, it is sufficient that at least the end portion of the lower surface 31a of the titanium silicide layer 31 that is in contact with the first insulating film 21 is located above the lower surface 20b of the interlayer insulating film 20. For example, the lower surface 31a of the titanium silicide layer 31 may have a curved shape that is convex downwards, and the central portion of the lower surface 31a of the titanium silicide layer 31 may be located below the end portion and also below the position of the lower surface 20b of the interlayer insulating film 20.

[0039] The titanium nitride film 32 is provided so as to cover the upper surface of the titanium silicide layer 31 and the side surface of the contact hole 20a. The lower surface of the titanium nitride film 32 located at the bottom of the contact hole 20a is in contact with the upper surface of the titanium silicide layer 31. The titanium nitride film 32 located on the side surface of the contact hole 20a is in contact with the side surfaces of the first insulating film 21 and the second insulating film 22.

[0040] The tungsten film 33 is provided within the contact hole 20a via the titanium nitride film 32 and the titanium silicide layer 31 so as to fill the contact hole 20a. The titanium nitride film 32 and the tungsten film 33 may also be provided so as to extend not only within the contact hole 20a but also onto the upper surface of the second insulating film 22.

[0041] Surface electrodes 40 are provided on the upper surfaces of the titanium nitride film 32, the tungsten film 33, and the second insulating film 22. The surface electrodes 40 are electrically connected to the emitter region 4 via the connecting conductor portion 30. The surface electrodes 40 can be made of metals such as aluminum (Al), Al alloys, or copper (Cu). Examples of Al alloys include Al-silicon (Si), Al-copper (Cu)-Si, and Al-Cu.

[0042] As shown in Figure 2, a lifetime control region 60 is provided inside the drift layer 1. The lifetime control region 60 is uniformly provided, for example, throughout the entire transistor section 101 and the diode section 102. Alternatively, the lifetime control region 60 may be provided selectively only in the diode section 102 and not in the transistor section 101. Or, the lifetime control region 60 may be provided selectively in a part of the transistor section 101.

[0043] The lifetime control region 60 is composed of crystal defects (point defects) formed by, for example, helium (He) or protons (hydrogen) injected as lifetime killers. By providing the lifetime control region 60, the characteristics of the semiconductor device can be improved and enhanced.

[0044] In the transistor section 101 and the diode section 102, an n-type buffer layer 8 with a higher impurity concentration than the drift layer 1 is provided on the lower side of the drift layer 1. The upper surface of the buffer layer 8 is in contact with the lower surface of the drift layer 1. The buffer layer 8 functions as a field stop layer that prevents the depletion layer extending from the lower side of the base region 3 and the anode region 13 from reaching the second main region (collector region) 9 and the cathode region 12, which will be described later.

[0045] In the transistor section 101, on the lower side of the buffer layer 8, p +A collector region 9 of type 1 is provided. The upper surface of the collector region 9 is in contact with the lower surface of the buffer layer 8. The impurity concentration of the collector region 9 is higher than that of the base region 3. On the other hand, in the diode section 102, the lower surface of the buffer layer 8 has n with a higher impurity concentration than that of the buffer layer 8. + A cathode region 12 of a certain type is provided. The upper surface of the cathode region 12 is in contact with the lower surface of the buffer layer 8. The cathode region 12 is provided at the same depth as the buffer layer 8. The side surface of the cathode region 12 is in contact with the side surface of the collector region 9.

[0046] A back electrode 50 is provided on the lower side of the collector region 9 and the cathode region 12. The back electrode 50 can be made of, for example, a single layer of gold (Au) or a metal film stacked in the order of titanium (Ti), nickel (Ni), and gold (Au). The back electrode 50 functions as a collector electrode in the transistor section 101 and as a cathode electrode in the diode section 102.

[0047] In the transistor section 101, when a positive voltage is applied to the back electrode 50 with the front electrode 40 at ground potential, and a positive voltage above a threshold is applied to the gate electrode 7, an inversion layer (channel) is formed on the side of the trench 11 in the base region 3, and the transistor enters an ON state. In the ON state, current flows from the back electrode 50 to the front electrode 40 via the collector region 9, buffer layer 8, drift layer 1, storage layer 2, the inversion layer of the base region 3, and the emitter region 4. On the other hand, when the voltage applied to the gate electrode 7 is below the threshold, an inversion layer is not formed in the base region 3, resulting in an OFF state, and no current flows from the back electrode 50 to the front electrode 40. The diode section 102 conducts a reverse current when the transistor section 101 turns off.

[0048] <Manufacturing method for semiconductor devices> Next, an example of a method for manufacturing a semiconductor device according to the first embodiment will be described with reference to FIGS. 1 to 12 and the like. FIGS. 6 to 11 show cross-sections corresponding to FIG. 3. Note that the method for manufacturing the semiconductor device described below is an example, and it is needless to say that various other manufacturing methods including this modification can be realized as long as they are within the scope of the gist described in the claims.

[0049] First, an n-type semiconductor substrate 10 that will form the n-type drift layer 1 shown in FIG. 2 is prepared. Next, the photolithography process and the ion implantation process are repeatedly performed, and the impurity ions implanted into the semiconductor substrate 10 are activated by heat treatment. As a result, as shown in FIGS. 1 and 2, in the transistor portion 101, an n-type accumulation layer 2, a p-type base region 3, an n-type emitter region 4, and a p-type contact region 5 (see FIG. 1) are formed on the upper part of the semiconductor substrate 10. Also, in the diode portion 102, an n-type accumulation layer 2 and a p-type anode region 13 are formed on the upper part of the semiconductor substrate 10.

[0050] Next, by photolithography technology and dry etching, the emitter region 4, the contact region 5, the base region 3, the anode region 13, a part of the accumulation layer 2, and a part of the drift layer 1 are selectively removed from the upper surface side of the semiconductor substrate 10. As a result, as shown in FIG. 4, a plurality of trenches 11 are formed on the upper part of the semiconductor substrate 10.

[0051] ​​​​​​​​​​​​Next, a gate insulating film 6 is formed on the bottom and sides of the trench 11, as well as on the upper surfaces of the emitter region 4, contact region 5, and anode region 13, by thermal oxidation or chemical vapor deposition (CVD). Then, a polysilicon film (doped polysilicon film) with high concentrations of impurities such as phosphorus (P) and boron (B) is deposited on the inside of the trench 11 via the gate insulating film 6 by CVD or the like. Subsequently, the polysilicon film and the gate insulating film 6 on the semiconductor substrate 10 are selectively removed by photolithography and dry etching. As a result, as shown in Figure 5, an insulated gate electrode structure (6,7) consisting of the gate insulating film 6 and the gate electrode 7 of the polysilicon film is formed inside the trench 11.

[0052] Next, a photoresist film is applied to the upper surfaces of the insulated gate electrode structure (6,7), emitter region 4, contact region 5, and anode region 13, and the photoresist film is patterned using photolithography. The patterned photoresist film is used as an etching mask, and a portion of the emitter region 4 and the insulated gate electrode structure (6,7) is selectively removed by dry etching. As a result, a protrusion 4a is formed on the upper part of the emitter region 4, as shown in Figure 6. Similarly, protrusions are also formed on the upper part of the contact region 5 of the transistor section 101 and on the upper part of the anode region 13 of the diode section 102, as shown in Figure 1. The height h2 of the protrusion 4a is higher than the height h1 of the protrusion 4a shown in Figure 3.

[0053] Next, a first insulating film 21, which is an HTO film, and a second insulating film 22, which is a BPSG film, are sequentially deposited on the upper surfaces of the insulated gate electrode structure (6,7), emitter region 4, contact region 5, and anode region 13 using a CVD method or the like. As a result, as shown in Figure 7, an interlayer insulating film 20 composed of the first insulating film 21 and the second insulating film 22 is formed. The first insulating film 21 and the second insulating film 22 have steps 21a and 22a, respectively, corresponding to the protrusions 4a. After depositing the second insulating film 22, the upper surface of the second insulating film 22 may be flattened by reflow. The upper surface of the protrusions 4a is located above the lower surface of the interlayer insulating film 20.

[0054] Next, a photoresist film is applied to the upper surface of the interlayer insulating film 20, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an etching mask, a portion of the interlayer insulating film 20 is selectively removed by dry etching to open a contact hole 20a so as to expose the upper surface of the protrusion 4a, as shown in Figure 8. The width of the contact hole 20a is approximately equal to the width w1 of the upper surface of the protrusion 4a. The entire upper surface of the protrusion 4a is exposed, while the upper surfaces of the flat parts of the mesa other than the protrusion 4a are covered with the interlayer insulating film 20 and are not exposed.

[0055] Furthermore, after opening the contact hole 20a, p-type impurities such as boron (B) or boron fluoride (BF2) may be selectively ion-implanted into the convex portion of the contact region 5 shown in Figure 1, and then heat-treated to activate the p-type impurity ions, thereby making it easier to extract the hole.

[0056] Next, the native oxide film at the bottom of the contact hole 20a is removed using hydrofluoric acid (HF) or the like. Then, a titanium film 34 is deposited on the upper surface of the protrusion 4a, the side surface of the contact hole 20a, and the upper surface of the second insulating film 22 by sputtering or vapor deposition, as shown in Figure 9. The thickness of the titanium film 34 is, for example, about 20 nm to 80 nm.

[0057] Next, a heat treatment such as rapid heat treatment (RTA) is performed to react the titanium (Ti) of the titanium film 34 located at the bottom of the contact hole 20a with the silicon (Si) of the protrusion 4a, thereby forming a titanium silicide layer 31 at the bottom of the contact hole 20a, as shown in Figure 10. When the titanium silicide layer 31 is formed, the volume of the protrusion 4a decreases and the height h1 of the protrusion 4a becomes lower. However, a portion of the protrusion 4a remains, and the upper surface of the protrusion 4a and the lower surface 31a of the titanium silicide layer 31 are located above the lower surface 20b of the interlayer insulating film 20, thus preventing the formation of an overhang at the edge of the first insulating film 21.

[0058] In Figure 10, an example is shown where the entire titanium film 34 located at the bottom of the contact hole 20a is silicided. However, a portion of the titanium film 34 located at the bottom of the contact hole 20a may remain unreacted and on the upper surface of the titanium silicide layer 31.

[0059] Next, the titanium film 34 located on the upper surface of the second insulating film 22 and the side surface of the contact hole 20a is removed by wet etching or the like. If any unreacted titanium film 34 remains at the bottom of the contact hole 20a, this unreacted titanium film 34 is also removed. As a result, all of the titanium film 34 is removed.

[0060] Next, a titanium nitride film 32 is deposited on the upper surface of the titanium silicide layer 31, the side surface of the contact hole 20a, and the upper surface of the second insulating film 22 by sputtering or vapor deposition. Then, a tungsten film 33 is deposited by CVD or the like, as shown in Figure 11, so as to fill the contact hole 20a through the titanium nitride film 32. After that, the titanium nitride film 32 and the tungsten film 33 located on the upper surface of the second insulating film 22 are selectively removed by dry etching or the like. As a result, a connecting conductor portion 30 consisting of the titanium silicide layer 31, the titanium nitride film 32, and the tungsten film 33 is formed. Note that the titanium nitride film 32 and the tungsten film 33 located on the upper surface of the second insulating film 22 may be left in place without being removed.

[0061] Next, surface electrodes 40 are deposited on the upper surfaces of the connecting conductor portion 30 and the second insulating film 22 by sputtering or vapor deposition, as shown in Figure 3. Then, the semiconductor substrate 10 is ground from the bottom side by chemical mechanical polishing (CMP), etc., to adjust the thickness of the semiconductor substrate 10 to the product thickness.

[0062] Next, n-type impurities are sequentially ion-implanted at different depths across the entire lower surface of the semiconductor substrate 10. Subsequently, the impurity ions are activated by heat treatment to create an n-type buffer layer 8 and n-type impurities at the bottom of the semiconductor substrate 10. +A p-type cathode region 12 is formed. Next, an ion implantation mask is formed using photolithography technology, and p-type impurities are ion-implanted into the transistor section 101. Subsequently, the impurity ions are activated by heat treatment to reverse the conductivity type of the cathode region 12 of the transistor section 101, and p + It forms a collector region 9 of type 9.

[0063] Next, as shown in Figure 12, a lifetime control region 60 is uniformly formed inside the drift layer 1 by irradiating the semiconductor substrate 10 with a particle beam such as helium (He) from the upper side. Alternatively, a particle beam such as protons (H) or electron beams may be used instead of He. Furthermore, the irradiation may be performed from the lower side of the semiconductor substrate 10 instead of the upper side. In addition, the lifetime control region 60 may be locally formed by patterning a photoresist film using photolithography technology and using it as a shielding film.

[0064] Next, heat treatment (annealing) is performed. Annealing may be carried out in a hydrogen-containing atmosphere. By adjusting the formation of crystal defects in the lifetime control region 60 through annealing, the desired lifetime is achieved. In addition, as shown in Figure 12, irradiation with a particle beam damages the gate insulating film 6, causing dangling bonds to form at the interface between the semiconductor substrate 10 and the gate insulating film 6, which lowers the gate threshold. However, during this annealing process, hydrogen present in the atmosphere and in the semiconductor substrate 10 can reach the gate insulating film 6, terminating the dangling bonds and preventing a decrease in the gate threshold. Here, since the unreacted titanium film 34 is removed after the formation of the titanium silicide layer 31, the hydrogen during annealing is not absorbed by the titanium film 34 and can sufficiently reach the gate insulating film 6.

[0065] Furthermore, even in processes using hydrogen other than annealing after particle beam irradiation, such as the process of forming the tungsten film 33, the hydrogen can reach the gate insulating film 6 without being absorbed by the titanium film 34. In addition, even in heating processes other than annealing after particle beam irradiation, it is possible to prevent a decrease in the gate threshold due to damage to the gate insulating film 6, such as the formation of contact holes 20a.

[0066] Next, a back surface electrode 50 made of gold (Au) or the like is formed on the entire lower surface of the semiconductor substrate 10 by sputtering or vapor deposition. In this way, the semiconductor device according to the first embodiment is completed.

[0067] <Comparative Example> Next, the method for manufacturing a semiconductor device according to the comparative example will be described with reference to Figures 13 to 17, etc. The method for manufacturing a semiconductor device according to the comparative example is the same as the method for manufacturing a semiconductor device according to the first embodiment shown in Figure 5 up to the procedure for forming the insulated gate type electrode structure (6, 7).

[0068] Next, without forming a protrusion in the mesa portion sandwiched between adjacent trenches 11, the first insulating film 21 and the second insulating film 22 are sequentially deposited on the insulated gate electrode structure (6,7) and the upper surface of the emitter region 4 by CVD or the like, as shown in Figure 13, to form an interlayer insulating film 20.

[0069] Next, as shown in Figure 14, a contact hole 20a is opened in the interlayer insulating film 20 using photolithography and dry etching, exposing a portion of the emitter region 4. In Figure 14, the bottom surface of the contact hole 20a is carved into the top of the emitter region 4, but etching may be stopped when the top surface of the emitter region 4 is exposed.

[0070] Next, a titanium film 34 is deposited on the bottom and sides of the contact hole 20a and on the upper surface of the second insulating film 22 by CVD or the like, as shown in Figure 15. Then, the titanium film 34 located at the bottom of the contact hole 20a is silicided to form a titanium silicide layer 31, as shown in Figure 16. At this time, the volume of the emitter region 4 decreases, the area below the first insulating film 21 is gouged out, and overhangs 20c and 20d are formed at the edges of the first insulating film 21.

[0071] Next, as shown in Figure 17, a titanium nitride film 32 is deposited on the upper surface of the titanium silicide layer 31, the side surface of the contact hole 20a, and the upper surface of the second insulating film 22 by CVD or the like. However, because the overhangs 20c and 20d of the first insulating film 21 are formed, voids are formed in the titanium nitride film 32 at the locations of the overhangs 20c and 20d of the first insulating film 21, making it impossible to properly deposit the titanium nitride film 32.

[0072] Next, when a tungsten film is deposited using a CVD method or the like to fill the contact holes 20a via the titanium nitride film 32, the tungsten film cannot be properly formed at the locations of voids in the titanium nitride film 32. Therefore, there is a concern that the tungsten (W) in the tungsten film will diffuse into the silicon (Si) in the mesa region.

[0073] Even when the titanium film 34 and titanium nitride film 32 are deposited sequentially, and then the titanium film 34 is silicided to form the titanium silicide layer 31, the titanium nitride film 32 may be partially stretched as the volume of the emitter region 4 decreases during the formation of the titanium silicide layer 31, potentially leading to the formation of voids in the titanium nitride film 32.

[0074] Compared to the semiconductor device manufacturing method of the comparative example, according to the manufacturing method of the semiconductor device according to the first embodiment, a protrusion 4a is formed on the upper part of the emitter region 4 provided in the mesa portion sandwiched between adjacent trenches 11, as shown in Figure 6. As a result, as shown in Figure 10, when the titanium silicide layer 31 is formed, the lower surface 31a of the titanium silicide layer 31 is above the lower surface 20b of the interlayer insulating film 20, so that the formation of an overhang on the first insulating film 21 can be prevented. Therefore, after the formation of the titanium silicide layer 31, the titanium nitride film 32 can be deposited well, and then the tungsten film 33 can also be deposited well. Thus, it is possible to prevent the tungsten (W) of the tungsten film 33 from diffusing into the silicon (Si) of the mesa portion.

[0075] <First variation> The method for manufacturing a semiconductor device according to the first modification of the first embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that, as shown in Figure 18, when forming a protrusion 4a on the upper part of the emitter region 4, only a portion of the upper part of the emitter region 4 is selectively removed without removing the gate insulating film 6 and the gate electrode 7. Other steps in the method for manufacturing a semiconductor device according to the first modification of the first embodiment are the same as those in the method for manufacturing a semiconductor device according to the first embodiment.

[0076] According to the first modification of the first embodiment, when forming a protrusion 4a on the upper part of the emitter region 4, even if only a part of the upper part of the emitter region 4 is selectively removed without removing the gate insulating film 6 and the gate electrode 7, the titanium nitride film 32 and the tungsten film 33 can be formed well, similar to the first embodiment.

[0077] <Second variation> The method for manufacturing a semiconductor device according to the second modification of the first embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that, as shown in Figure 19, a titanium film 34 and a titanium nitride film 32 are sequentially deposited before forming the titanium silicide layer 31. After sequentially depositing the titanium film 34 and the titanium nitride film 32, the titanium film 34 located at the bottom of the contact hole 20a is silicided to form the titanium silicide layer 31. Other steps in the method for manufacturing a semiconductor device according to the second modification of the first embodiment are the same as those in the method for manufacturing a semiconductor device according to the first embodiment.

[0078] As a result, as shown in Figure 20, a connecting conductor portion 30 is formed consisting of a titanium silicide layer 31, a titanium film 34, a titanium nitride film 32, and a tungsten film 33. The titanium film 34 is provided in contact with the titanium silicide layer 31 and the titanium nitride film 32, sandwiched between the titanium silicide layer 31 and the titanium nitride film 32.

[0079] Note that Figure 20 illustrates a case where the titanium film 34 located on the upper surface of the titanium silicide layer 31 remains without being completely silicided, but it is also possible for the titanium film 34 located on the upper surface of the titanium silicide layer 31 to be completely silicided. In this case, the upper surface of the titanium silicide layer 31 is Titanium nitride film 32 In contact with the contact hole 20a, the titanium film 34 remains on the side surface of the contact hole 20a. Furthermore, the titanium film 34 and titanium nitride film 32 on the interlayer insulating film 20 do not need to be removed.

[0080] According to the second modification of the first embodiment, even when the titanium film 34 and the titanium nitride film 32 are sequentially deposited before the titanium silicide layer 31 is formed, the protrusions 4a are formed in advance, so the titanium nitride film 32 is not pulled significantly when the titanium silicide layer 31 is formed, thus preventing the titanium nitride film 32 from tearing. Therefore, similar to the first embodiment, the titanium nitride film 32 and the tungsten film 33 can be deposited well.

[0081] <Third variation> The method for manufacturing a semiconductor device according to the third modification of the first embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that, as shown in Figure 21, when the contact hole 20a of the interlayer insulating film 20 is opened, the width w3 of the bottom surface of the contact hole 20a is made wider than the width w1 of the protrusion 4a. The height of the bottom surface of the contact hole 20a is the same as the top surface of the protrusion 4a. The other steps of the method for manufacturing a semiconductor device according to the third modification of the first embodiment are the same as those of the method for manufacturing a semiconductor device according to the first embodiment. As a result, as shown in Figure 22, the width w3 of the titanium nitride film 32 located at the bottom of the contact hole 20a is wider than the width w1 of the titanium silicide layer 31.

[0082] According to the third modification of the first embodiment, for example, even if the positional accuracy of the contact hole 20a is low, by making the width w3 of the bottom surface of the contact hole 20a wider than the width w1 of the protrusion 4a, the entire upper surface of the protrusion 4a can be easily exposed. Therefore, similar to the first embodiment, the titanium nitride film 32 and the tungsten film 33 can be formed well.

[0083] <Fourth variation> In the method for manufacturing a semiconductor device according to the fourth modification of the first embodiment, as shown in Figure 23, the first insulating film 21 is deposited, the upper surface of the first insulating film 21 is leveled by etch-back or grinding, and then the second insulating film 22 is deposited. In Figure 23, the step 21a of the first insulating film 21 remains, but the step 21a may be completely removed. Alternatively, the upper surface of the first insulating film 21 may be further removed so that the height of the upper surface of the first insulating film 21 is approximately the same as the height of the upper surface of the protrusion 4a. When the second insulating film 22 is deposited, the position of the boundary between the first insulating film 21 and the second insulating film 22 may be brought closer to the height of the upper surface of the protrusion 4a so that it is approximately the same as the height of the upper surface of the protrusion 4a.

[0084] Next, contact holes 20a are opened in the interlayer insulating film 20 by CVD or the like, as shown in Figure 24. Figure 24 shows a case where the position of the contact holes 20a is misaligned and there is under-etching on the upper surface of the protrusion 4a. Not all of the upper surface of the protrusion 4a is exposed, and a part of the upper surface of the protrusion 4a is covered by the interlayer insulating film 20.

[0085] Next, as shown in Figure 25, the native oxide film on the mesa is removed with hydrofluoric acid (HF). At this time, by taking advantage of the fact that the etching selectivity ratio of HF between the first insulating film 21, which is HTO, and the second insulating film 22, which is BPSG, is different, and that the lateral etching spread of BPSG is greater than that of HTO, the entire upper surface of the protrusion 4a can be exposed.

[0086] According to the fourth modification of the first embodiment, even if the entire upper surface of the protrusion 4a is not exposed when the contact hole 20a is opened, the entire upper surface of the protrusion 4a can be exposed when the native oxide film is removed, and the titanium nitride film 32 and the tungsten film 33 can be formed well, similar to the first embodiment. Furthermore, by leveling the upper surface of the first insulating film 21 after depositing the first insulating film 21 and then depositing the second insulating film 22, the upper surface of the protrusion 4a can be made easier to expose. In addition, by forming the protrusion 4a such that its height is greater than the maximum displacement of the contact hole 20a, exposure and descent of the flat parts of the mesa other than the protrusion 4a can be prevented.

[0087] <Fifth variation> As shown in Figure 26, the semiconductor device according to the fifth modified example of the first embodiment has a mesa portion sandwiched between adjacent trenches 11. + emitter region 4 and p of type +The semiconductor device according to the first embodiment differs in that the contact area 5 of the type is provided in the direction of the arrangement of the plurality of trenches 11. The emitter area 4 and the contact area 5 may have linear (striped) portions that extend parallel to the extension direction of the trenches 11 on the planar pattern. The other configurations of the semiconductor device according to the fifth modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0088] According to the fifth modification of the first embodiment, the mesa portion sandwiched between adjacent trenches 11 is n + emitter region 4 and p of type + Even when the contact region 5 of the mold is provided in the direction of the arrangement of the multiple trenches 11, the titanium nitride film 32 and the tungsten film 33 can be formed well, similar to the first embodiment.

[0089] (Second Embodiment) <Structure of a semiconductor device> The basic configuration of the semiconductor device according to the second embodiment is substantially the same as that of the semiconductor device according to the first embodiment shown in Figures 1 and 2. Figure 27 shows a cross-section of the semiconductor device according to the second embodiment, corresponding to the cross-section of the semiconductor device according to the first embodiment shown in Figure 3. As shown in Figure 27, the configuration around the connecting conductor portion 30 of the semiconductor device according to the second embodiment differs from that of the semiconductor device according to the first embodiment.

[0090] As shown in Figure 27, an emitter region 4 is provided in the mesa between adjacent trenches 11. No protrusions are provided on the upper part of the emitter region 4. The bottom surface of the contact hole 20a of the interlayer insulating film 20 is provided to form a recess on the upper part of the emitter region 4. The bottom surface of the contact hole 20a may be provided to coincide with the upper surface of the emitter region 4.

[0091] A connecting conductor portion 30 is embedded in the contact hole 20a. The connecting conductor portion 30 comprises a silicon film 35 made of silicon (Si) such as polysilicon doped with a high concentration of p-type or n-type impurities, a titanium silicide layer 31 which is a silicide layer made of titanium silicide (TiSi2), a titanium nitride film 32 which is a barrier metal film made of titanium nitride (TiN), and a tungsten film 33 which is a metal film made of tungsten (W).

[0092] The thickness of the silicon film 35 is, for example, between 10 nm and 80 nm. The thickness of the titanium silicide layer 31 is, for example, between 20 nm and 80 nm. The thickness of the titanium nitride film 32 is, for example, between 20 nm and 140 nm. The thickness of the tungsten film 33 is, for example, between 100 nm and 1500 nm.

[0093] The silicon film 35 is provided so as to cover the bottom and sides of the contact hole 20a. The silicon film 35 is in contact with the emitter region 4 located at the bottom of the contact hole 20a, and is also in contact with the sides of the first insulating film 21 and the second insulating film 22 that are exposed on the sides of the contact hole 20a.

[0094] The titanium silicide layer 31 is provided so as to cover the bottom and sides of the contact hole 20a via the silicon film 35. The titanium silicide layer 31 is in contact with the silicon film 35. The lowest part of the bottom surface (bottom surface) 31a of the titanium silicide layer 31 is located above the bottom surface 20b of the interlayer insulating film 20.

[0095] The titanium nitride film 32 is provided so as to cover the bottom and sides of the contact hole 20a via the silicon film 35 and the titanium silicide layer 31. The titanium nitride film 32 is in contact with the titanium silicide layer 31.

[0096] The tungsten film 33 is provided inside the contact hole 20a via the silicon film 35, the titanium silicide layer 31, and the titanium nitride film 32, so as to fill the contact hole 20a. The tungsten film 33 is in contact with the titanium nitride film 32. The other components of the semiconductor device according to the second embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0097] <Manufacturing method for semiconductor devices> Next, an example of a semiconductor device manufacturing method according to the second embodiment will be described with reference to Figures 28 to 30, etc. Figures 28 to 30 show cross-sections corresponding to Figure 27. It should be noted that the semiconductor device manufacturing method described below is just one example, and it is of course possible to realize it by various other manufacturing methods, including this modification, as long as it is within the scope of the claims.

[0098] The method for manufacturing a semiconductor device according to the second embodiment is the same as the method for manufacturing a semiconductor device according to the first embodiment shown in Figure 5 up to the procedure for forming the insulated gate type electrode structure (6,7). Next, without forming a protrusion in the mesa portion sandwiched between adjacent trenches 11, the first insulating film 21 and the second insulating film 22 are sequentially deposited on the insulated gate type electrode structure (6,7) and the upper surface of the emitter region 4 by CVD or the like, as shown in Figure 13, to form an interlayer insulating film 20.

[0099] Next, as shown in Figure 14, a contact hole 20a is opened in the interlayer insulating film 20 using photolithography and dry etching, exposing a portion of the emitter region 4. In Figure 14, the bottom surface of the contact hole 20a is carved into the top of the emitter region 4, but etching may be stopped when the top surface of the emitter region 4 is exposed.

[0100] Next, as shown in Figure 28, a silicon film 35, such as polysilicon, doped with a high concentration of p-type or n-type impurities, is deposited on the bottom and sides of the contact hole 20a and on the top surface of the second insulating film 22 using a CVD method or the like. The top surface of the silicon film 35 located on the bottom surface of the contact hole 20a is located above the bottom surface of the interlayer insulating film 20. Subsequently, the silicon film 35 located on the top surface of the second insulating film 22 may be selectively removed, leaving the silicon film 35 only inside the contact hole 20a.

[0101] Next, ion implantation and heat treatment are performed to make the region of the silicon film 35 in contact with the emitter region 4 an n-type region and the region of the silicon film 35 in contact with the contact region 5 a p-type region. For example, after depositing a silicon film 35 doped with a high concentration of n-type impurities, p-type impurities such as boron (B) may be ion-implanted, and the p-type impurities may be activated by heat treatment to reverse the conductivity of the n-type region in contact with the contact region 5 of the silicon film 35 and selectively form a p-type region.

[0102] Next, a titanium film 34 is deposited by sputtering or vapor deposition, as shown in Figure 29. Then, a portion of the titanium film 34 and the silicon film 35 are reacted by heat treatment to form a titanium silicide layer 31 on the upper surface of the silicon film 35, as shown in Figure 30. The silicon film 35 is not completely silicided, and a portion of the silicon film 35 remains. Because the bottom and sides of the contact hole 20a are covered by the silicon film 35, it is possible to prevent the formation of an overhang on the first insulating film 21 when the titanium silicide layer 31 is formed.

[0103] Figure 30 illustrates a case where the entire titanium film 34 has been silicided, but a portion of the titanium film 34 may remain unreacted. If unreacted titanium film 34 remains, it may be removed.

[0104] Next, a titanium nitride film 32 is deposited on the titanium silicide layer 31 by sputtering or vapor deposition. Then, a tungsten film 33 is deposited on the titanium nitride film 32 by CVD or the like to fill the contact hole 20a. Next, the titanium nitride film 32 and tungsten film 33 located on the upper surface of the second insulating film 22 are selectively removed. As a result, a connecting conductor portion 30 is formed consisting of the silicon film 35, titanium silicide layer 31, titanium nitride film 32, and tungsten film 33 within the contact hole 20a.

[0105] Next, the second insulating film is formed by sputtering or vapor deposition, as shown in Figure 27. 22 Surface electrodes 40 are deposited on the upper surface and the upper surface of the connecting conductor portion 30. The subsequent steps are the same as those for the manufacturing method of the semiconductor device according to the first embodiment, so redundant explanations are omitted. In this way, the semiconductor device according to the second embodiment is completed.

[0106] According to the semiconductor device manufacturing method of the second embodiment, as shown in Figure 28, the silicon film 35 is deposited after opening the contact hole 20a. This prevents the formation of an overhang on the first insulating film 21 when the titanium silicide layer 31 is formed, as shown in Figure 29. Therefore, the titanium nitride film 32 and the tungsten film 33 can be successfully formed after the titanium silicide layer 31 is formed. Thus, it is possible to prevent the tungsten (W) of the tungsten film 33 from diffusing into the silicon (Si) of the mesa portion.

[0107] Furthermore, according to the semiconductor device manufacturing method of the second embodiment, since the unreacted titanium film 34 is removed after the titanium silicide layer 31 is formed, the hydrogen during annealing is not absorbed by the titanium film 34 and can reach the gate insulating film 6 sufficiently, similar to the semiconductor device manufacturing method of the first embodiment.

[0108] In addition, in the method for manufacturing a semiconductor device according to the second embodiment, instead of depositing the titanium nitride film 32 after silicide formation of the titanium film 34 to form the titanium silicide layer 31, the titanium film 34 and the titanium nitride film 32 may be deposited sequentially, and then the titanium film 34 may be silicided to form the titanium silicide layer 31. In this case as well, since the titanium nitride film 32 is not pulled significantly during the formation of the titanium silicide layer 31, it is possible to prevent the titanium nitride film 32 from tearing.

[0109] Furthermore, in the method for manufacturing a semiconductor device according to the second embodiment, a convex portion 4a may be formed on the mesa portion as shown in Figure 6 using the same procedure as in the method for manufacturing a semiconductor device according to the first embodiment, and after opening a contact hole 20a so as to expose the upper surface of the convex portion 4a as shown in Figure 8, a silicon film 35 may be deposited so as to cover the upper surface of the convex portion 4a. In this case as well, the titanium nitride film 32 and the tungsten film 33 can be formed well.

[0110] (Other embodiments) As described above, the first and second embodiments of the present invention have been presented, but the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0111] For example, although RC-IGBTs were used as examples of semiconductor devices according to the first and second embodiments, the method is also applicable to IGBTs other than RC-IGBTs. Furthermore, the p of the IGBT in the transistor section 101 shown in Figure 2 + The collector area 9 of type n + This can also be applied to MOSFETs with a drain region of a certain type.

[0112] Furthermore, while the titanium silicide layer 31 was exemplified in the first and second embodiments, a silicide layer composed of a compound of silicon and a metal such as nickel (Ni), tungsten (W), cobalt (Co), molybdenum (Mo), zinc (Zn), hafnium (Hf), platinum (Pt), palladium (Pd), iron (Fe), chromium (Cr), tantalum (Ta), or niobium (Nb) may be used instead. Also, while the titanium nitride film 32 was exemplified as the barrier metal film in the first and second embodiments, a barrier metal film such as titanium tungsten (TiW) or tantalum nitride (TaN) may be used instead. Also, while the tungsten film 33 was exemplified as the embedded metal film in the first and second embodiments, a metal film such as aluminum (Al) or copper (Cu) may be used instead of the tungsten film 33.

[0113] Furthermore, the configurations disclosed in the first and second embodiments can be combined as appropriate, within the bounds of consistency. Thus, it goes without saying that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined solely by the inventive features relating to the claims that are appropriate from the above description. [Explanation of Symbols]

[0114] 1…Drift layer 2…Accumulation layer 3…Base area 4…Emitter region 4a... protruding part 5… Contact area 6…Gate insulating film 7… Gate gate 8... Buffer layer 9...Collector area 10… Semiconductor substrates 11…Trench 12... Cathode region 13…Anode region 20…Interlayer insulating film 20a... Contact hole 30... Contact plug 31…Titanium silicide layer 32…Titanium nitride film 33...Tungsten film 34…Titanium film 35… Silicone film 40…Surface electrode 50…Back electrode 60…Lifetime control range 101... Transistor section 102... Diode section

Claims

1. Semiconductor substrate and A plurality of trenches provided on the upper surface side of the semiconductor substrate, An insulated gate type electrode structure embedded inside the plurality of trenches, An interlayer insulating film provided on the upper surface of the semiconductor substrate and the insulated gate type electrode structure, A silicide layer is provided at the bottom of a contact hole penetrating the interlayer insulating film, and is in contact with the upper surface of the semiconductor substrate sandwiched between adjacent trenches, Equipped with, A semiconductor device characterized in that at least a portion of the lower surface of the silicide layer is located above the lower surface of the interlayer insulating film in the mesa portion where the silicide layer is provided.

2. The semiconductor device according to claim 1, characterized in that the silicide layer is a titanium silicide layer.

3. The semiconductor device according to claim 1 or 2, further comprising a lifetime control region provided inside the semiconductor substrate.

4. The semiconductor device according to any one of claims 1 to 3, further comprising a titanium nitride film provided on the upper surface of the silicide layer and the side surface of the contact hole, and in contact with the upper surface of the silicide layer.

5. The semiconductor device according to claim 4, further comprising a tungsten film embedded inside the contact hole via the titanium nitride film.

6. A semiconductor substrate and A plurality of trenches provided on the upper surface side of the semiconductor substrate, An insulated gate type electrode structure embedded inside the aforementioned plurality of trenches, An interlayer insulating film provided on the upper surface of the semiconductor substrate and the insulated gate type electrode structure, A silicide layer is provided at the bottom of a contact hole penetrating the interlayer insulating film, and is in contact with the upper surface of the semiconductor substrate sandwiched between adjacent trenches, Equipped with, At least a portion of the lower surface of the silicide layer is located above the lower surface of the interlayer insulating film, A semiconductor device characterized in that the width of the silicide layer is narrower than the width of the bottom surface of the contact hole.

7. A transistor section provided on a part of the aforementioned semiconductor substrate, A diode portion provided on another part of the semiconductor substrate, A semiconductor device according to any one of claims 1 to 6, characterized in that it is a reverse-conducting insulated-gate bipolar transistor equipped with

8. A process of forming multiple trenches from the upper surface of a semiconductor substrate, The process involves embedding an insulated gate type electrode structure in each of the aforementioned multiple trenches, A step of depositing an interlayer insulating film on the upper surface of the semiconductor substrate and the insulated gate type electrode structure, A step of forming a contact hole in the interlayer insulating film located on the semiconductor substrate sandwiched between adjacent trenches, A step of forming a silicide layer inside the contact hole, such that at least a portion of the lower surface of the silicide layer is located above the lower surface of the interlayer insulating film in the mesa portion where the silicide layer is provided. A method for manufacturing a semiconductor device, characterized by including [the necessary components].

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that the silicide layer is a titanium silicide layer.

10. The step of embedding the insulated gate type electrode structure includes forming a protrusion on the upper part of the semiconductor substrate sandwiched between adjacent trenches, The step of forming the contact hole involves forming the contact hole so as to expose the upper surface of the protrusion, The process of forming the silicide layer involves depositing a titanium film on the upper surface of the protrusion and reacting the titanium film with a portion of the protrusion by heat treatment to form the silicide layer. The method for manufacturing a semiconductor device according to claim 8 or 9.

11. A step of forming a plurality of trenches from the upper surface side of a semiconductor substrate, The process involves embedding an insulated gate type electrode structure in each of the aforementioned multiple trenches, A step of depositing an interlayer insulating film on the upper surface of the semiconductor substrate and the insulated gate type electrode structure, A step of forming a contact hole in the interlayer insulating film located on the semiconductor substrate sandwiched between adjacent trenches, A step of forming a silicide layer inside the contact hole, such that at least a portion of the lower surface of the silicide layer is located above the lower surface of the interlayer insulating film, Includes, The step of embedding the insulated gate type electrode structure includes forming a protrusion on the upper part of the semiconductor substrate sandwiched between adjacent trenches, The step of forming the contact hole involves forming the contact hole so as to expose the upper surface of the protrusion, The process of forming the silicide layer involves depositing a titanium film on the upper surface of the protrusion and reacting the titanium film with a portion of the protrusion by heat treatment to form the silicide layer. A method for manufacturing a semiconductor device, characterized in that the width of the bottom surface of the contact hole is formed to be wider than the width of the protrusion.

12. The step of forming the silicide layer is, A silicon film and a titanium film are laminated on the inside of the contact hole. The silicide layer is formed by reacting the titanium film and at least a portion of the silicon film through heat treatment. The method for manufacturing a semiconductor device according to claim 8 or 9.

13. A step of forming a plurality of trenches from the upper surface side of a semiconductor substrate, The process involves embedding an insulated gate type electrode structure in each of the aforementioned multiple trenches, A step of depositing an interlayer insulating film on the upper surface of the semiconductor substrate and the insulated gate type electrode structure, A step of forming a contact hole in the interlayer insulating film located on the semiconductor substrate sandwiched between adjacent trenches, A step of forming a silicide layer inside the contact hole, such that at least a portion of the lower surface of the silicide layer is located above the lower surface of the interlayer insulating film, Includes, The step of embedding the insulated gate type electrode structure includes forming a protrusion on the upper part of the semiconductor substrate sandwiched between adjacent trenches, The step of forming the contact hole involves forming the contact hole so as to expose the upper surface of the protrusion, The process of forming the silicide layer involves depositing a titanium film on the upper surface of the protrusion and reacting the titanium film with a portion of the protrusion by heat treatment to form the silicide layer. A method for manufacturing a semiconductor device, characterized in that it further includes a step of removing the unreacted titanium film after the step of forming the silicide layer.

14. A step of forming a plurality of trenches from the upper surface side of a semiconductor substrate, The process involves embedding an insulated gate type electrode structure in each of the aforementioned multiple trenches, A step of depositing an interlayer insulating film on the upper surface of the semiconductor substrate and the insulated gate type electrode structure, A step of forming a contact hole in the interlayer insulating film located on the semiconductor substrate sandwiched between adjacent trenches, A step of forming a silicide layer inside the contact hole, such that at least a portion of the lower surface of the silicide layer is located above the lower surface of the interlayer insulating film, Includes, The step of forming the silicide layer is, A silicon film and a titanium film are laminated on the inside of the contact hole. By heat treatment, at least a portion of the titanium film and the silicon film are reacted to form the silicide layer. A method for manufacturing a semiconductor device, characterized in that it further includes a step of removing the unreacted titanium film after the step of forming the silicide layer.

15. The method for manufacturing a semiconductor device according to any one of claims 10 to 12, characterized in that the step of forming the silicide layer is to deposit a titanium nitride film after depositing the titanium film but before forming the silicide layer.

16. A step of forming a plurality of trenches from the upper surface side of a semiconductor substrate, The process involves embedding an insulated gate type electrode structure in each of the aforementioned multiple trenches, A step of depositing an interlayer insulating film on the upper surface of the semiconductor substrate and the insulated gate type electrode structure, A step of forming a contact hole in the interlayer insulating film located on the semiconductor substrate sandwiched between adjacent trenches, A step of forming a silicide layer inside the contact hole, such that at least a portion of the lower surface of the silicide layer is located above the lower surface of the interlayer insulating film, Includes, The step of embedding the insulated gate type electrode structure includes forming a protrusion on the upper part of the semiconductor substrate sandwiched between adjacent trenches, The step of forming the contact hole involves forming the contact hole so as to expose the upper surface of the protrusion, The process of forming the silicide layer involves depositing a titanium film on the upper surface of the protrusion and reacting the titanium film with a portion of the protrusion by heat treatment to form the silicide layer. A method for manufacturing a semiconductor device, characterized in that, after the step of forming the silicide layer, the method further includes the step of forming a titanium nitride film so as to be in contact with the upper surface of the silicide layer.

17. A step of forming a plurality of trenches from the upper surface side of a semiconductor substrate, The process involves embedding an insulated gate type electrode structure in each of the aforementioned multiple trenches, A step of depositing an interlayer insulating film on the upper surface of the semiconductor substrate and the insulated gate type electrode structure, A step of forming a contact hole in the interlayer insulating film located on the semiconductor substrate sandwiched between adjacent trenches, A step of forming a silicide layer inside the contact hole, such that at least a portion of the lower surface of the silicide layer is located above the lower surface of the interlayer insulating film, Includes, The step of forming the silicide layer is, A silicon film and a titanium film are laminated on the inside of the contact hole. By heat treatment, at least a portion of the titanium film and the silicon film are reacted to form the silicide layer. A method for manufacturing a semiconductor device, characterized in that, after the step of forming the silicide layer, the method further includes the step of forming a titanium nitride film so as to be in contact with the upper surface of the silicide layer.

18. A method for manufacturing a semiconductor device according to any one of claims 15 to 17, further comprising the step of filling the contact holes with a tungsten film via the titanium nitride film after the step of forming the titanium nitride film.

19. The method for manufacturing a semiconductor device according to claim 18, further comprising the step of irradiating the semiconductor substrate with a particle beam.

20. The method for manufacturing a semiconductor device according to claim 19, further comprising the step of annealing after the step of irradiating with a particle beam.

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