Semiconductor device and method for manufacturing the same

Abstract

Provided is a semiconductor device comprising: a semiconductor substrate; an interlayer insulating film which is provided above the semiconductor substrate and in which a contact hole having a stepped part on the lateral wall thereof is provided; and a contact part provided to the contact hole. The contact part has a barrier layer provided on the bottom surface and on the lateral wall of the contact hole. The barrier layer has a first region in contact with the stepped part and a second region in contact with the lateral wall of the contact hole in a region different from the first region. When the film thickness of the thickest portion in the first region is denoted as T, and the film thickness of the thinnest portion in the second region is denoted as t, 0.3T≤t≤0.95T is satisfied.

Description

Technical Field

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[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. <0‬000005>

Background Art

[0002] Patent Document 1 describes a semiconductor device having a structure in which “a step 14c is provided at the interface between the HTO film 11 and the BPSG film 12 on the side wall of the contact hole 14, and the width of the upper end side of the contact hole 14 is stepped wider than the width of the bottom side of the contact hole 14 due to the step 1‬4c”. [Prior Art Document] [Patent Document] [Patent Document 1] Reissued Patent No. 2019-093015 [Patent Document 2] Japanese Patent Application Laid-Open No. 63-205951 [Patent Document 3] Japanese Patent Application Laid-Open No. 5-29937‬5 [Patent Document 4] Japanese Patent Application Laid-Open No. 7-94448 [Patent Document 5] Japanese Patent Application Laid-Open No. 2001-223218 [Patent Document 6] Japanese Patent Application Laid-Open No. 2004-515921 [Patent Document 7] Japanese Patent Application Laid-Open No. 2007-511087 [Patent Document 8] Japanese Patent Application Laid-Open No. 2008-141050 Problems to be Solved [[ID=‬33]]

[0003] ‬It is preferable to equalize the film thickness of the barrier layer. General Disclosure ‬

[0004] ‬ ‬In a first aspect of the present invention, there are provided a semiconductor substrate, an interlayer insulating film provided above the semiconductor substrate and having a contact hole with a step portion on a side wall thereof, and a contact portion provided in the contact hole, the contact portion having a barrier layer provided on a side wall and a bottom surface of the contact hole, the barrier layer having a first region in contact with the step portion and a second region in contact with the side wall of the contact hole in a region below the first region. The aforementionedThe present invention provides a semiconductor device that satisfies 0.3T ≤ t ≤ 0.95T, where T is the film thickness of the thickest part of the first region and t is the film thickness of the thinnest part of the second region.

[0005] In the semiconductor device described above, the interlayer insulating film comprises a first interlayer insulating film provided in contact with the front surface of the semiconductor substrate and a second interlayer insulating film provided above the first interlayer insulating film, and the stepped portion may be formed at the boundary between the first interlayer insulating film and the second interlayer insulating film.

[0006] In any of the semiconductor devices described above, the contact portion may be a trench contact portion extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

[0007] In any of the semiconductor devices described above, the barrier layer may include a first barrier metal layer provided on the side wall of the contact hole, and a second barrier metal layer laminated on the first barrier metal layer in the contact hole.

[0008] In any of the semiconductor devices described above, the thickness of the second barrier metal layer above the stepped portion may be thicker than the thickness of the first barrier metal layer.

[0009] In any of the semiconductor devices described above, the thickness of the second barrier metal layer below the stepped portion may be thinner than the thickness of the first barrier metal layer.

[0010] In any of the above semiconductor devices, the film thickness T of the thickest part of the first region may be 3 nm or more and 120 nm or less, and the film thickness t of the thinnest part of the second region may be 1 nm or more and 114 nm or less.

[0011] In any of the above semiconductor devices, the first barrier metal layer in the first region membrane Thickness is 2 nm or more, 119 It is acceptable for it to be less than nm.

[0012] In any of the above semiconductor devices, the first barrier metal layer may contain one of Ti, TiN, Ta, or TaN.

[0013] In any of the above-described semiconductor devices, the second barrier metal layer may contain either TiN or TaN.

[0014] In any of the above semiconductor devices, the contact hole may be provided with a plug layer located inside the barrier layer.

[0015] In any of the above-described semiconductor devices, at least one or both of the barrier layer and / or the plug layer may be provided above the interlayer insulating film.

[0016] In any of the above semiconductor devices, the plug layer may contain either tungsten or molybdenum.

[0017] In any of the semiconductor devices described above, the side wall of the contact hole may have a forward taper.

[0018] In any of the above semiconductor devices, the side wall of the contact hole may have an inverse taper.

[0019] In any of the semiconductor devices described above, the height of the stepped portion in a direction perpendicular to the tangential direction of the side wall of the contact hole may be 15% or less of the opening width of the contact hole on the upper surface of the interlayer insulating film.

[0020] In any of the semiconductor devices described above, the thickness of the barrier layer may be 1 nm or more and 115 nm or less above the stepped portion, and 1 nm or more and 114 nm or less below the stepped portion.

[0021] In a second aspect of the present invention, there are steps of forming an interlayer insulating film having a contact hole with a stepped portion provided on a side wall above a semiconductor substrate, providing a barrier layer on side walls and a bottom surface of the contact hole, and providing a plug layer inside the barrier layer in the contact hole. The barrier layer has a first region in contact with the stepped portion and a second region in contact with the side wall of the contact hole in a region below the first region. The aforementioned Provided is a method for manufacturing a semiconductor device, in which when the film thickness of the thickest portion of the first region is T and the film thickness of the thinnest portion of the second region is t, 0.3T ≤ t ≤ 0.95T is satisfied.

[0022] In the method for manufacturing a semiconductor device described above, the step of providing the barrier layer may include steps of providing a first barrier metal layer on the side wall and the bottom surface in the contact hole, and providing a second barrier metal layer so as to be laminated on the first barrier metal layer in the contact hole.

[0023] In the method for manufacturing a semiconductor device according to any one of the above, after the step of providing the first barrier metal layer and before the step of providing the second barrier metal layer, there may be a step of etching the first region.

[0024] In the method for manufacturing a semiconductor device according to any one of the above, the first barrier metal layer in the first region membrane thickness is 2 nm or more, 119 nm or less.

[0025] In the method for manufacturing a semiconductor device according to any one of the above, the barrier layer may be formed by a sputtering method.

[0026] In the method for manufacturing a semiconductor device according to any one of the above, the plug layer may be formed by a CVD method.

[0027] In the method for manufacturing a semiconductor device according to any one of the above, the second barrier metal layer may be formed by a CVD method.

[0028] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0029] [Figure 1A] An example of a top view of the semiconductor device 100 is shown. [Figure 1B] An example of a cross-section from a-a' in Figure 1A is shown. [Figure 2A] A modified top view of the semiconductor device 100 is shown. [Figure 2B] A modified top view of the semiconductor device 100 is shown. [Figure 2C] A cross-section of a modified semiconductor device 100, specifically the b-b' section, is shown. [Figure 3A] This is an enlarged cross-sectional view of semiconductor device 100. [Figure 3B] This is an enlarged cross-sectional view of a modified semiconductor device 100. [Figure 3C] This is an enlarged cross-sectional view of a modified semiconductor device 100. [Figure 4] This is an enlarged cross-sectional view of the semiconductor device in the comparative example. [Figure 5] This is a flowchart showing an example of the manufacturing process for semiconductor device 100. [Figure 6A] An example of a manufacturing method for the semiconductor device 100 is shown. [Figure 6B] An example of a manufacturing method for the semiconductor device 100 is shown. [Figure 6C] An example of a manufacturing method for the semiconductor device 100 is shown. [Modes for carrying out the invention]

[0030] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0031] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0032] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0033] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0034] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type.

[0035] Figure 1A shows an example of a top view of a semiconductor device 100. In this example, the semiconductor device 100 is a semiconductor chip equipped with a transistor section 70. The semiconductor device 100 is not limited to a transistor, as long as it is a semiconductor element having a MOS gate structure on a semiconductor substrate 10.

[0036] The transistor section 70 is the region obtained by projecting the collector region 22, which is provided on the back side of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. However, the transistor section 70 may also be other transistors such as a MOSFET.

[0037] In this figure, the region around the active part of the semiconductor device 100 is shown, and other regions are omitted. For example, an edge termination structure may be provided in the negative region in the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these. In this example, for convenience, the negative edge in the Y-axis direction is described, but the same applies to other edges of the semiconductor device 100.

[0038] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate or a silicon carbide substrate. In this example, the semiconductor substrate 10 is a silicon substrate. In this specification, when simply referred to as a "top view," it means viewing from the top side of the semiconductor substrate 10. The semiconductor substrate 10 has a front surface 21 and a back surface 23, as described later.

[0039] The semiconductor device 100 in this example comprises a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 also includes an emitter electrode 52 and a gate metal layer 50 located above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and gate metal layer 50 are examples of the front-side metal layer 53, which will be described later. The gate trench 40 is an example of the MOS gate structure of the semiconductor device 100. While the semiconductor device 100 in this example is a transistor with a MOS gate structure, it may also be a diode with a MOS gate structure.

[0040] The emitter electrode 52 is located above the gate trench 40, dummy trench 30, emitter region 12, base region 14, contact region 15, and well region 17. The gate metal layer 50 is located above the connection portion 25 and the well region 17.

[0041] The emitter electrode 52 and the gate metal layer 50 are formed from a metal-containing material. At least a portion of the emitter electrode 52 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier layer 60 formed of titanium or a titanium compound below the region formed of aluminum, etc. The barrier layer 60 will be described later. The emitter electrode 52 and the gate metal layer 50 are provided separated from each other.

[0042] The emitter electrode 52 and gate metal layer 50 are provided above the semiconductor substrate 10, with an interlayer insulating film 38 in between. The interlayer insulating film 38 is omitted in Figure 1A. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.

[0043] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive part within the transistor section 70 via the connection section 25. A plug layer 64 made of tungsten or the like may be formed inside the contact hole 55. The plug layer 64 will be described later.

[0044] The contact hole 56 connects the emitter electrode 52 to the dummy conductive part in the dummy trench 30. A plug layer 64 made of tungsten or the like may be formed inside the contact hole 56.

[0045] The connection portion 25 is connected to the front-side metal layer 53, such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. In this example, the connection portion 25 may be provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0046] The gate trench portion 40 is an example of a plurality of trench portions extending in a predetermined stretching direction on the front surface 21 side of the semiconductor substrate 10. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 in this example may have two extended portions 41 that extend along a stretching direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connecting portion 43 that connects the two extended portions 41.

[0047] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extended portions 41 of the gate trench portion 40, electric field concentration at the ends of the extended portions 41 can be mitigated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25.

[0048] The dummy trench section 30 is an example of a plurality of trench sections extending in a predetermined stretching direction on the front surface 21 side of the semiconductor substrate 10. The dummy trench section 30 is a trench section electrically connected to the emitter electrode 52. The dummy trench section 30, like the gate trench section 40, is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). In this example, the dummy trench section 30 has an I-shape on the front surface 21 of the semiconductor substrate 10, but like the gate trench section 40, it may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench section 30 may have two extended portions extending along the stretching direction and a connecting portion connecting the two extended portions.

[0049] The transistor section 70 in this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are arranged in a repeating pattern. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extended sections 41.

[0050] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 may be greater than the ratio of the dummy trench portion 30, and vice versa. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all trenches as gate trench portions 40 and not have dummy trench portions 30.

[0051] The well region 17 is a second conductivity type region located on the front surface 21 side of the semiconductor substrate 10, closer to the drift region 18, which will be described later. The well region 17 is an example of a well region located on the peripheral side of the active portion 120. The well region 17 is, for example, of the P+ type. The well region 17 is formed within a predetermined range from the edge of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17. The bottom of the extending end of the gate trench portion 40 and the dummy trench portion 30 may be covered by the well region 17.

[0052] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided by extending in the stretching direction.

[0053] The mesa portion 71 is a mesa portion provided adjacent to the trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is the part of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be the portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The extended portion of each trench portion may be considered as one trench portion. That is, the region sandwiched between two extended portions may be considered as the mesa portion.

[0054] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are provided alternately in the stretching direction.

[0055] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, P-type. The base region 14 may be provided at both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Note that Figure 1A shows only one end of the base region 14 in the Y-axis direction.

[0056] The emitter region 12 is a first conductivity type region with a higher doping concentration than the drift region 18. In this example, the emitter region 12 is N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may extend in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0057] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0058] The contact region 15 is located above the base region 14 and is a region of a second conductivity type with a higher doping concentration than the base region 14. In this example, the contact region 15 is of type P+. In this example, the contact region 15 is located on the front surface 21 of the mesa portion 71. The contact region 15 may be located in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact region 15 is in contact with both the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also located below the contact hole 54.

[0059] Figure 1B shows an example of the a-a' cross-section in Figure 1A. The a-a' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross-section. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0060] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0061] The buffer region 20 is a first-conductivity region located on the back surface 23 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may function as a field stop layer to prevent the depletion layer extending from the underside of the base region 14 from reaching the collector region 22 of the second-conductivity region. The buffer region 20 may be omitted.

[0062] The collector region 22 is located below the buffer region 20 in the transistor section 70. The collector region 22 has a second conductivity type. In this example, the collector region 22 is of type P+.

[0063] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0064] The base region 14 is a second conductivity type region located above the drift region 18. The base region 14 is located in contact with the gate trench portion 40. The base region 14 may be located in contact with the dummy trench portion 30.

[0065] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0066] The storage region 16 is a first conductivity type region located on the front surface 21 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the storage region 16 is of type N+. However, the storage region 16 does not necessarily have to be provided.

[0067] The storage region 16 is provided in contact with the gate trench portion 40. The storage region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the storage region 16 is higher than the doping concentration of the drift region 18. The ion implantation dose of the storage region 16 may be 1.0E+12cm-2 or more and 1.0E+13cm-2 or less. Alternatively, the ion implantation dose of the storage region 16 may be 3.0E+12cm-2 or more and 6.0E+12cm-2 or less. By providing the storage region 16, the carrier implantation promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0068] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and storage region 16 is provided, each trench penetrates these regions as well and reaches the drift region 18. The statement that a trench penetrates a doping region is not limited to cases where the doping region is formed before the trenches are formed. Cases where doping regions are formed between the trenches after the trenches have been formed are also included in cases where the trenches penetrate a doping region.

[0069] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0070] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces an adjacent base region 14 on the mesa portion 71 side, with the gate insulating film 42 in between. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench within the base region 14.

[0071] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered with an interlayer insulating film 38 on the front surface 21.

[0072] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Similarly, contact holes 55 and 56 may be provided through the interlayer insulating film 38. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited thereto. In this example, the interlayer insulating film 38 may have a first interlayer insulating film 381 provided in contact with the front surface 21 and a second interlayer insulating film 382 provided above the first interlayer insulating film 381.

[0073] The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a BPSG (Boro-phospho Silicate Glass) film, a BSG (borosilicate glass) film, or a PSG (Phosphosilicate glass) film. The interlayer insulating film 38 may also contain a high-temperature silicon oxide (HTO) film. The first interlayer insulating film 381 and the second interlayer insulating film 382 may be made of the same material or different materials. In one example, the first interlayer insulating film 381 may be an HTO film and the second interlayer insulating film 382 may be a BPSG film. Furthermore, the interlayer insulating film 38 may have a layer structure of three or more layers.

[0074] Figure 2A shows a modified top view of the semiconductor device 100. In this example, only some components of the semiconductor device 100 are shown, and some components have been omitted.

[0075] The semiconductor substrate 10 has edges 102 when viewed from above. In this example, the semiconductor substrate 10 has two pairs of edges 102 that face each other when viewed from above. In this example, the X axis and Y axis are parallel to one of the edges 102.

[0076] The semiconductor substrate 10 is provided with an active section 120. The active section 120 is a region where the main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode 52 is provided above the active section 120, but it is omitted in this figure.

[0077] The active section 120 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 2A, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the front surface 21 of the semiconductor substrate 10. In other examples, the active section 120 may be provided with only one of the transistor section 70 and the diode section 80.

[0078] In this example, the region where the transistor section 70 is located is denoted by the symbol "I", and the region where the diode section 80 is located is denoted by the symbol "F". The transistor section 70 and the diode section 80 may each have a longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0079] The diode portion 80 is the region obtained by projecting the cathode region 82, which is provided on the back surface 23 of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The cathode region 82 will be described later. On the back surface 23 of the semiconductor substrate 10, a P+ type collector region 22 may be provided in the region other than the cathode region 82. In this specification, an extended region 85, which is an extension of the diode portion 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode portion 80. A collector region 22 may be provided on the back surface 23 of the extended region 85.

[0080] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad and a cathode pad. In this example, each pad is located near the edge 102. The vicinity of the edge 102 refers to the area between the edge 102 and the emitter electrode 52 in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires. The placement of each pad does not have to be near the edge 102.

[0081] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 of the active portion 120. The semiconductor device 100 is provided with gate wiring that connects the gate pad 112 and the gate trench portion 40. In Figure 2A, the gate wiring is hatched with diagonal lines.

[0082] The gate wiring in this example has an outer perimeter gate wiring 130 and an active-part gate wiring 131. The gate wiring may be constructed by combining either the gate metal layer 50 or the connection part 25, or both, as appropriate. The outer perimeter gate wiring 130 and the active-part gate wiring 131 may have the same configuration or different configurations. In a top view, the outer perimeter gate wiring 130 is positioned between the active part 120 and the edge 102 of the semiconductor substrate 10. In this example, the outer perimeter gate wiring 130 surrounds the active part 120 in a top view. In a top view, the area surrounded by the outer perimeter gate wiring 130 may be considered the active part 120. The outer perimeter gate wiring 130 is also connected to the gate pad 112. The outer perimeter gate wiring 130 is positioned above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be composed of a gate metal layer 50 and a connection part 25.

[0083] The inter-active-part gate wiring 131 is provided between multiple active parts 120. In Figure 2A, two active parts 120 are arranged side by side in the Y-axis direction. By providing the inter-active-part gate wiring 131 between multiple active parts 120 inside the semiconductor substrate 10, variations in the wiring length from the gate pad 112 can be reduced for each region of the semiconductor substrate 10.

[0084] The inter-active-part gate wiring 131 is connected to the gate trench portion of the active part 120. The inter-active-part gate wiring 131 is located above the semiconductor substrate 10. In this example, the inter-active-part gate wiring 131 is composed of a gate metal layer 50 and a connecting portion 25. The gate metal layer 50 may be a metal layer containing aluminum or the like.

[0085] The inter-active-part gate wiring 131 may be connected to the outer peripheral gate wiring 130. In this example, the inter-active-part gate wiring 131 extends in the X-axis direction, crossing the active part 120 from one outer peripheral gate wiring 130 to the other outer peripheral gate wiring 130, approximately in the center in the Y-axis direction. When the active part 120 is divided by the inter-active-part gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region.

[0086] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. In a top view, the edge termination structure 140 is provided between the active portion 120 and the edge 102. In this example, the edge termination structure 140 is positioned between the outer peripheral gate wiring 130 and the edge 102. The edge termination structure 140 mitigates electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 120.

[0087] Figure 2B shows a modified top view of the semiconductor device 100. The semiconductor device 100 in this example includes a transistor section 70 and a diode section 80. This figure is an enlarged top view of region A in Figure 2A.

[0088] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17, all located inside the front surface 21 of the semiconductor substrate 10. The gate trench 40 and the dummy trench 30 are examples of trenches.

[0089] The dummy trench portion 30 in this example may have a U-shape on the front surface 21 of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extended portions 31 that extend along the stretching direction and a connecting portion 33 that connects the two extended portions 31.

[0090] The semiconductor device 100 in this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor section 70 in this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80. However, the semiconductor device 100 does not necessarily have to include the boundary section 90.

[0091] The boundary portion 90 is provided in the transistor portion 70 and is adjacent to the diode portion 80. The boundary portion 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the boundary portion 90 does not have an emitter region 12. In this example, the trench portion of the boundary portion 90 is a dummy trench portion 30. In this example, the boundary portion 90 is arranged such that both ends in the X-axis direction are dummy trench portions 30.

[0092] The contact holes 54 are located above the base region 14 in the diode section 80. The contact holes 54 are located above the contact region 15 in the boundary section 90. None of the contact holes 54 are located above the well regions 17 located at both ends in the Y-axis direction.

[0093] The mesa portion 91 is provided at the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 91 has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0094] The mesa portion 81 is provided in the diode portion 80 in the region sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 81 has a well region 17 on the negative side in the Y-axis direction.

[0095] The emitter region 12 is provided in the mesa portion 71, but it does not need to be provided in the mesa portions 81 and 91. The contact region 15 is provided in the mesa portions 71 and 91, but it does not need to be provided in the mesa portion 81.

[0096] Figure 2C shows a cross-section of a modified example of the semiconductor device 100, specifically the b-b' section. This figure corresponds to the b-b' section of Figure 2B. In this example, the semiconductor device 100 includes a collector region 22 and a cathode region 82 on the back surface 23 side of the buffer region 20.

[0097] The contact area 15 is provided above the base area 14 in the mesa portion 91. The contact area 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross-sections, the contact area 15 may be provided on the front surface 21 of the mesa portion 71.

[0098] The storage region 16 is provided in the transistor section 70 and the diode section 80. In this example, the storage region 16 is provided across the entire surface of the transistor section 70 and the diode section 80. However, the storage region 16 does not necessarily have to be provided in the diode section 80.

[0099] The cathode region 82 is located below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is located below the boundary 90 in this example.

[0100] The semiconductor device 100 may be a power semiconductor device for controlling power, etc. The semiconductor device 100 in this example may have a vertical semiconductor structure in which a metal layer is provided on the back surface 23 side of the semiconductor substrate 10. However, the semiconductor device 100 may have a horizontal semiconductor structure in which a metal layer is not provided on the back surface 23 side.

[0101] In this example, the semiconductor device 100 is described using an RC-IGBT with a trench gate structure as an example. However, the semiconductor device 100 may also be a semiconductor device with a planar gate structure, or another semiconductor device such as a diode. The semiconductor device 100 may include an N-channel MOSFET or a P-channel MOSFET.

[0102] Figure 3A is an enlarged cross-sectional view of the semiconductor device 100. In this example, it shows an enlarged cross-sectional view near the contact portion 65 provided in the contact hole 54. The cross-section in this example is the XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The contact portion 65 comprises a barrier layer 60, a silicide layer 63, and a plug layer 64.

[0103] In this specification, the structure near the contact portion 65 may be described using the contact hole 54, but the same structure may be applied to other contact holes such as contact hole 55 and contact hole 56. That is, the barrier layer 60, silicide layer 63, and plug layer 64 may be provided in other contact holes such as contact hole 55 and contact hole 56.

[0104] The contact hole 54 has a stepped portion 39 on its side wall. The stepped portion 39 may be formed at the boundary between the first interlayer insulating film 381 and the second interlayer insulating film 382. The stepped portion 39 is a region on the side wall of the contact hole 54 that includes at least one inflection point. Alternatively, the stepped portion 39 may be a stepped region formed at the boundary between the first interlayer insulating film 381 and the second interlayer insulating film 382.

[0105] The height h of the stepped portion 39 may be 15% or less, 10% or less, or 5% or less of the opening width d of the contact hole 54 on the upper surface of the interlayer insulating film 38 in the alignment direction. In this example, the height h of the stepped portion 39 may be 120 nm or less, 80 nm or less, or 40 nm or less. In this specification, the height h of the stepped portion 39 is measured in a direction perpendicular to the tangential direction of the side wall of the second interlayer insulating film 382. From the side wall of the second interlayer insulating film 382 This may be the height up to the side wall of the first interlayer insulating film 381.

[0106] In this example, the side wall of the contact hole 54 has a forward taper. The taper angle of the side wall of the contact hole 54 may be 70 degrees or more and 90 degrees or less.

[0107] In this example, the aspect ratio of the contact hole 54 may be 2 or more, or 5 or more. The aspect ratio of the contact hole 54 may be 0.5 or more, or 10 or less. In this specification, the aspect ratio of the contact hole 54 is the value obtained by dividing the depth of the contact hole 54 in the depth direction of the semiconductor substrate 10 by the opening width d of the contact hole 54 on the upper surface of the interlayer insulating film 38.

[0108] The barrier layer 60 is provided above the silicide layer 63 in the contact hole 54. The barrier layer 60 is provided on the bottom surface of the contact hole 54 and on the side walls of the interlayer insulating film 38. In this example, the barrier layer 60 is provided on the top surface of the silicide layer 63 and on the side walls of the interlayer insulating film 38 in the contact hole 54. The barrier layer 60 may contain titanium (Ti) or tantalum (Ta). In this example, the barrier layer 60 has a first barrier metal layer 61 and a second barrier metal layer 62.

[0109] Furthermore, the barrier layer in this example has a first region 161 which is in contact with the stepped portion 39, a second region 162 which is below the first region 161 and is in contact with the side wall of the contact hole 54, and a third region 163 which is above the first region 161 and is in contact with the side wall of the contact hole 54.

[0110] The first barrier metal layer 61 is provided on the sidewall of the interlayer insulating film 38. The first barrier metal layer 61 may also be provided on the bottom surface of the contact hole 54. The first barrier metal layer 61 may contain at least one of titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN). As an example, the first barrier metal layer 61 is Ti.

[0111] In the first region 161, the thickness of the first barrier metal layer 61 may be between 2 nm and 119 nm. In the second region 162, the thickness of the first barrier metal layer 61 may be between 0.5 nm and 113 nm. Here, the thickness of the first barrier metal layer 61 may be the thickness of the first barrier metal layer 61 measured in a direction perpendicular to the tangential direction of the side wall of the contact hole 54.

[0112] The second barrier metal layer 62 is laminated on the first barrier metal layer 61 in the contact hole 54. At the bottom surface of the contact hole 54, the second barrier metal layer 62 is laminated on the silicide layer 63 provided on the front surface 21 of the semiconductor substrate 10. The second barrier metal layer 62 may contain at least one of titanium nitride (TiN) or tantalum nitride (TaN). As an example, the second barrier metal layer 62 is TiN.

[0113] The thickness of the second barrier metal layer 62 in the first region 161 may be between 2 nm and 119 nm. Alternatively, the thickness of the second barrier metal layer 62 in the second region 162 may be between 0.5 nm and 113 nm. Here, the thickness of the second barrier metal layer 62 may be the thickness of the second barrier metal layer 62 measured in a direction perpendicular to the tangential direction of the surface of the first barrier metal layer 61.

[0114] Above the stepped portion 39, the thickness of the second barrier metal layer 62 may be thicker than the thickness of the first barrier metal layer 61. Below the stepped portion 39, the thickness of the second barrier metal layer 62 may be thinner than the thickness of the first barrier metal layer 61.

[0115] The silicide layer 63 is provided on the upper surface of the semiconductor substrate 10 below the contact hole 54. The silicide layer 63 in this example is provided on the upper surface of the semiconductor substrate 10. The silicide layer 63 is formed by annealing the first barrier metal layer 61. The silicide layer 63 in this example is a titanium silicide layer formed by annealing Ti deposited on the bottom surface of the contact hole 54 as the first barrier metal layer 61. A portion of the first barrier metal layer 61 may remain unsilicified at the bottom surface of the contact hole 54.

[0116] The plug layer 64 is provided above the barrier layer 60 in the contact hole 54. The plug layer 64 may be provided in contact with the second barrier metal layer 62 in the contact hole 54. The plug layer 64 is a conductive material that fills the inside of the contact hole 54. The plug layer 64 may be made of a different material from the front metal layer 53. For example, the material of the plug layer 64 may be tungsten. The material of the plug layer 64 may be molybdenum. The plug layer 64 may not be provided, and the front metal layer 53 may be embedded in the contact hole 54.

[0117] The thickness of the barrier layer 60 in the first region 161 is greater than the thickness of the barrier layer 60 in the second region 162. Here, the thickness of the barrier layer 60 refers to the distance from the side wall of the contact hole 54 to the surface of the barrier layer 60 in a direction perpendicular to the tangential direction of the side wall of the contact hole 54.

[0118] When the maximum thickness of the barrier layer 60 in the first region 161 is T, and the minimum thickness of the barrier layer 60 in the second region 162 is t, then 0.3T ≤ t ≤ 0.95T and 0.5T ≤ t ≤ 0.9T may be true. That is, the thickness of the barrier layer 60 may be uniform in the first region 161 and the second region 162. In this specification, "uniform" thickness may mean satisfying 0.3T ≤ t ≤ 0.95T, 0.5T ≤ t ≤ 0.9T, or 0.5T ≤ t ≤ 0.8T. The thickness T of the barrier layer 60 in the first region 161 may be 3 nm or more and 120 nm or less.

[0119] The thickness of the barrier layer 60 above the stepped portion 39 may be thicker than the thickness of the barrier layer 60 below the stepped portion 39. For example, the thickness of the barrier layer 60 above the stepped portion 39 may be between 1 nm and 115 nm. Also, the thickness of the barrier layer 60 below the stepped portion 39 may be between 1 nm and 114 nm.

[0120] There may be two or more stepped portions 39. Furthermore, by providing two or more stepped portions 39, there may be multiple first regions 161. Among the multiple first regions 161, the region above the one closest to the upper surface of the interlayer insulating film 38 that contacts the sidewall of the contact hole 54 may be the third region 163, and the region different from the first region 161 and the third region 163 that contacts the sidewall of the contact hole 54 may be the second region 162.

[0121] Here, Figure 4 is an enlarged view of the cross-section near the contact portion in the comparative example. In the comparative example, there is a large difference in the thickness of the barrier layer 60 above the stepped portion 39 and below the stepped portion 39. When there is such a large difference in the thickness of the barrier layer 60, stress concentration may occur in the thinner portion below the stepped portion 39 during heat treatment such as annealing, which may cause the barrier layer 60 to rupture and expose a part of the semiconductor substrate 10. In that case, the fluoride used when forming the subsequent plug layer 64 may corrode the semiconductor substrate 10, which may affect the performance of the entire semiconductor device.

[0122] On the other hand, in the semiconductor device 100 in the embodiment, the thickness of the barrier layer 60 is uniform. Therefore, stress concentration does not occur during heat treatment, the fracture of the barrier layer 60 can be suppressed, and the performance of the semiconductor device 100 can be guaranteed.

[0123] Figure 3B is an enlarged cross-sectional view of a modified semiconductor device 100. In this example, an enlarged cross-sectional view near the contact hole 54 is shown. The cross-section in this example is the XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 3A in that it includes a trench contact portion as the contact portion 65.

[0124] The trench contact portion has a contact hole 54 and extends from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the lower end of the trench contact portion is deeper than the lower end of the emitter region 12. The lower end of the trench contact portion may be shallower than the lower end of the emitter region 12. In this example, the lower end of the trench contact portion is in contact with the base region 14, but it may also be in contact with a second conductivity type plug region with a higher doping concentration than the base region 14.

[0125] The barrier layer 60 may have a first barrier metal layer 61, a second barrier metal layer 62, and a silicide layer 63 in the trench contact area. The first barrier metal layer 61 is provided in contact with the side wall of the interlayer insulating film 38. The silicide layer 63 is provided in contact with the side wall of the semiconductor substrate 10 and the front surface 21 of the semiconductor substrate 10 in the trench contact area.

[0126] The second barrier metal layer 62 is laminated on the first barrier metal layer 61, which is provided in contact with the side wall of the interlayer insulating film 38, and on the silicide layer 63, which is provided in contact with the side wall and the front surface 21 of the semiconductor substrate 10. The plug layer 64 is provided inside the second barrier metal layer 62 in the contact hole 54.

[0127] Figure 3C is an enlarged cross-sectional view of a modified semiconductor device 100. In this example, an enlarged cross-sectional view near the contact hole 54 is shown. The cross-section in this example is the XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10.

[0128] The semiconductor device 100 in this example differs from the embodiment in Figure 3A in that the sidewall of the contact hole 54 has a reverse taper. The taper angle of the sidewall of the contact hole 54 may be 90 degrees or more and 110 degrees or less.

[0129] As shown in Figure 3C, a barrier layer 60 including a first barrier metal layer 61 and a second barrier metal layer 62 may be formed between the interlayer insulating film 38 and the surface metal layer 53. The barrier layer 60 may be formed not only inside the contact hole 54 but also in areas other than the contact hole 54 between the interlayer insulating film 38 and the surface metal layer 53. In addition, a plug layer 64 may be formed between the interlayer insulating film 38 and the surface metal layer 53. The plug layer 64 may be formed between the barrier layer 60 and the surface metal layer 53, as shown in Figure 3C.

[0130] In this example, we have described the case where all contact portions 65 are ordinary, but a semiconductor device 100 having a multilayer wiring structure may also have a similar configuration. Furthermore, the configuration of the contact holes 54, 55, and 56 may not be the linear shape shown in this example, but rather holes with dimensions in the arrangement direction and the extension direction that are approximately the same, square, elliptical, or rectangular shapes, or contact holes that extend in the extension direction and also in the arrangement direction, or a lattice shape that combines multiple contact holes extending in the arrangement direction and multiple contact holes extending in the extension direction.

[0131] Figure 5 is a flowchart showing an example of the manufacturing process for a semiconductor device 100. In step S100, the element structure on the front surface 21 of the semiconductor device 100 is formed. Step S100 may include the process of forming a dummy trench 30 and a gate trench 40 as the element structure on the front surface 21. Step S100 may also include the process of forming a base region 14, an emitter region 12, and a contact region 15, etc., as the element structure on the front surface 21 by ion implantation into the semiconductor substrate 10.

[0132] In step S102, an interlayer insulating film 38 is formed on top of the semiconductor substrate 10. The interlayer insulating film 38 may be formed by stacking multiple insulating films. In this example, it may be formed including, for example, a first interlayer insulating film 381 which is an HTO film and a second interlayer insulating film 382 which is a BPSG film.

[0133] In step S104, contact holes are formed by etching the interlayer insulating film 38. In step S104, contact holes such as contact holes 54, contact holes 55, and contact holes 56 may be formed in the interlayer insulating film 38. The etching method for the contact holes may be either dry etching, wet etching, or both.

[0134] As an example of etching in step S104, one method is to first form contact holes by dry etching, and then treat the contact holes for about 5 to 500 seconds using hydrofluoric acid or dilute hydrofluoric acid for purposes such as removing etching residue in the contact holes 54, 55, and 56 and removing the native oxide film on the surface of the exposed semiconductor substrate 10. The processing time for wet etching may be arbitrarily set considering the type and quality of the interlayer insulating film, the hydrofluoric acid concentration, the processing conditions, the desired contact shape dimensions, etc. Furthermore, the dry etching process and the wet etching process may be performed consecutively, and a process for forming another structure may be performed between the two processes.

[0135] In each contact hole, a step portion 39 may be formed at the boundary between the first interlayer insulating film 381 and the second interlayer insulating film 382. Generally, when the difference in etching rates between the multiple interlayer insulating films used is large, and when the etching process time is long, the step shape of the step portion 39 becomes larger.

[0136] In step S104, by controlling the formation time and conditions of the contact holes 54, 55, and 56, the height h of the stepped portion 39 can be set to 15% or less of the opening width d of each contact hole on the upper surface of the interlayer insulating film 38. In contact holes having an aspect ratio of the degree shown in this embodiment, if the first barrier metal layer 61 and the second barrier metal layer 62 are formed by sputtering and the thickness of each barrier metal layer is set to the degree shown in this embodiment, a uniform barrier layer 60 can be formed by setting the height h of the stepped portion 39 to 15% or less of the opening width d of each contact hole on the upper surface of the interlayer insulating film 38.

[0137] In step S106, the first barrier metal layer 61 is formed. In this example, the first barrier metal layer 61 is a Ti film formed by sputtering. In this example, the case in which a Ti film is formed as the first barrier metal layer 61 is described, but the first barrier metal layer 61 may be formed using a different type of metal (for example, Ta). Furthermore, when forming the first barrier metal layer 61, it is desirable that no native oxide film or the like is formed on the surface of the semiconductor substrate 10 at the bottom of the contact holes 54, 55, and 56, and that the semiconductor substrate 10 is exposed during the formation process.

[0138] In step S108, the first region 161 of the first barrier metal layer 61 is etched. The etching may be wet etching or dry etching. By etching the first region 161, the thickness of the first barrier metal layer 61, which is thickened in the first region 161 in contact with the step portion 39, can be reduced. When etching the first barrier metal layer 61, it is desirable to selectively remove part or all of the first barrier metal layer 61 on the side walls of the contact holes 54, 55, and 56, while leaving the first barrier metal layer 61 on the bottom surface.

[0139] As an example of the etching method in step S108, if the thickness of the first barrier metal layer 61 on the sidewall is relatively thinner than the thickness of the first barrier metal layer 61 on the bottom, a method can be selected in which the first barrier metal layer 61 on the sidewall is removed and the first barrier metal layer on the bottom remains. Another example is a method in which the first barrier metal layer on the bottom is converted into a silicide layer 63 by performing an annealing treatment after the formation of the first barrier metal layer 61, and the first barrier metal layer on the sidewall is selectively removed by utilizing the difference in etching rates between the first barrier metal layer 61 and the silicide layer 63, or a method in which conditions are adopted in wet etching to etch the interlayer insulating film and lift off the first barrier metal layer 61 on the sidewall by etching the interlayer insulating film on the sidewall. Step S108 may also be omitted.

[0140] In step S110, a second barrier metal layer 62 is formed above the first barrier metal layer 61. The second barrier metal layer 62 may be formed by laminating it on the first barrier metal layer 61 at the bottom and side walls of the contact hole 54. In this example, the second barrier metal layer 62 is a TiN film formed by sputtering or CVD (Chemical Vapor Deposition).

[0141] In step S112, the semiconductor substrate 10 is annealed in a nitrogen atmosphere. The annealing temperature may be 300 degrees Celsius or higher and 1100 degrees Celsius or lower. The atmosphere during the annealing process may also be an atmosphere containing oxygen, a pressurized atmosphere, a vacuum atmosphere, etc. In this example, the annealing is performed after the formation of the second barrier metal layer 62. In this example, the annealing may also be performed before the formation of the second barrier metal layer 62. By undergoing annealing in step S112, the portion of the first barrier metal layer 61 in contact with the semiconductor substrate 10 is silicided, and the silicide layer 63 is formed.

[0142] In step S114, a plug layer 64 is formed. In this example, The plug layer 64 is Tungsten is used to fill the inside of the contact hole 54 using the CVD method. in The barrier layer 60 may function as a metal diffusion prevention layer when forming the plug layer 64. By covering the side walls and bottom surface of the contact hole 54 with the barrier layer 60, it is possible to prevent the material gas of the plug layer 64 from entering the semiconductor substrate 10 when the plug layer 64 is formed by CVD. In addition, the plug layer 64 may be made of a material such as molybdenum, or a manufacturing method such as sputtering or vapor deposition may be employed.

[0143] In step S116, the plug layer 64 is etched back. This may remove any unwanted tungsten film outside the contact hole 54. Etching back may be performed by dry etching or CMP (Chemical Mechanical Polishing). When the tungsten film is removed, the first barrier metal layer 61 and the second barrier metal layer 62 on the interlayer insulating film 38 may also be removed. The first barrier metal layer 61 and the second barrier metal layer 62 on the interlayer insulating film 38 may be removed in a separate process from the etching back of the plug layer 64. Etching back of the barrier layer 60 and the plug layer 64 may be omitted.

[0144] Figure 6A shows an example of a manufacturing method for the semiconductor device 100. In this example, a cross-section near the contact hole 54 is shown, following the manufacturing method flowchart shown in Figure 5.

[0145] In step S104, a contact hole is formed by etching the interlayer insulating film 38. In this example, the interlayer insulating film 38 has a first interlayer insulating film 381 and a second interlayer insulating film 382. The first interlayer insulating film 381 and the second interlayer insulating film 382 may be formed from different materials. When the first interlayer insulating film 381 and the second interlayer insulating film 382 are formed from different materials, or when they are made of the same type of material but have different composition ratios or film quality, a stepped portion 39 is formed on the side wall of the contact hole 54 by employing etching methods and etching conditions with different etching rates. Furthermore, after the formation of the stepped portion 39, the height h of the stepped portion 39 may be reduced or the stepped portion 39 may be removed by applying an etching means to which the etching rate on the side with a narrower opening width is relatively faster for multiple interlayer insulating films 38, or, as an example, an inverse sputtering method using argon.

[0146] In step S106, the first barrier metal layer 61 is formed on the side wall of the interlayer insulating film 38 and on the upper surface of the semiconductor substrate 10. In this example, the first barrier metal layer 61 is formed on the upper surface of the front surface 21. The first barrier metal layer 61 may also be formed on the upper surface of the interlayer insulating film 38.

[0147] The first barrier metal layer 61 is formed by sputtering. Therefore, the thickness of the first barrier metal layer 61 is formed thicker near the step portion 39 than in other areas. If the second barrier metal layer 62 is formed by sputtering in this state, the second barrier metal layer 62 may not be formed to a sufficient thickness below the step portion 39 due to the influence of the first barrier metal layer 61 which is formed thicker near the step portion 39.

[0148] Therefore, in step S108, the thickness of the first barrier metal layer 61 near the step portion 39 is reduced by etching the first region 161 of the first barrier metal layer 61. The etching may be wet etching or dry etching such as reverse sputtering using argon.

[0149] In the subsequent step S110, a second barrier metal layer 62 is formed above the first barrier metal layer 61. In this example, the second barrier metal layer 62 is a TiN film formed by sputtering. In this example, since the thickened first barrier metal layer 61 near the step portion 39 is removed in S108, the second barrier metal layer 62 is formed with sufficient thickness even below the step portion 39.

[0150] Specifically, when T is the maximum thickness of the barrier layer 60 in the first region 161 which is in contact with the stepped portion 39, and t is the minimum thickness of the barrier layer 60 in the second region 162 which is below the first region 161 and is in contact with the side wall of the contact hole 54, then 0.3T ≤ t ≤ 0.95T and 0.5T ≤ t ≤ 0.9T may be true.

[0151] Figure 6B shows an example of a manufacturing method for the semiconductor device 100. In this example, a cross-section near the contact hole 54 is shown in a modified version of the manufacturing method flowchart shown in Figure 5.

[0152] Figure 6B shows a manufacturing method that does not include step S108 for etching the first barrier metal layer 61. In this case, as mentioned above, the thickness of the first barrier metal layer 61 is formed thicker near the step portion 39 than in other areas. Therefore, when the second barrier metal layer 62 is formed by sputtering, there is a risk that the second barrier metal layer 62 will not be sufficiently formed below the step portion 39.

[0153] In step S110, the second barrier metal layer 62 is formed by the CVD method. By forming the second barrier metal layer 62 by the CVD method, the second barrier metal layer 62 can be formed so as to wrap around to the underside of the first barrier metal layer 61 which has thickened near the step portion 39, and the thickness of the barrier layer 60 can be formed uniformly.

[0154] Figure 6C shows an example of a manufacturing method for the semiconductor device 100. In this example, a cross-section near the contact hole 54 is shown in a further modified version of the manufacturing method flowchart shown in Figure 5.

[0155] Figure 6C shows a manufacturing method that does not include step S108 of etching the first barrier metal layer 61. Here, the thickness of the first barrier metal layer 61 is different in the embodiment of Figure 6C compared to the embodiment of Figure 6A. Here, the thickness of the first barrier metal layer 61 refers to the thickness of the first barrier metal layer 61 measured in a direction perpendicular to the tangential direction of the side wall of the contact hole 54.

[0156] The thickness of the first barrier metal layer 61 formed in step S106' in Figure 6C is thinner than the thickness of the first barrier metal layer 61 formed in step S106 in Figure 6A. Specifically, the thickness of the first barrier metal layer 61 formed in step S106 is 5 nm or more and 30 nm or less, while the thickness of the first barrier metal layer 61 formed in S106' is 2.5 nm or more and 20 nm or less.

[0157] In the embodiment shown in Figure 6C, the thickness of the first barrier metal layer 61 formed in step S106' is thin, so the thickness of the first barrier metal layer 61 near the step portion 39 is thinner compared to the case of step S106 in Figure 6A. As a result, even if step S108, in which the first barrier metal layer 61 is etched, the second barrier metal layer 62 can be formed uniformly enough.

[0158] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0159] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order. [Explanation of symbols]

[0160] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 17...Well region, 18...Drift region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 30...Dummy trench portion, 31...Extended portion 32...Dummy insulating film, 33...Connection part, 34...Dummy conductive part, 38...Interlayer insulating film, 39...Stepped part, 40...Gate trench part, 41...Extended part, 42...Gate insulating film, 43...Connection part, 44...Gate conductive part, 50...Gate metal layer, 52...Emitter electrode, 53...Front side metal layer, 54...Contact hole, 5 5...Contact hole, 56...Contact hole, 60...Barrier layer, 61...First barrier metal layer, 62...Second barrier metal layer, 63...Silicide layer, 64...Plug layer, 65...Contact section, 70...Transistor section, 71...Mesa section, 80...Diode section, 81...Mesa section, 82...Cathode region, 85...Extended region, 90...Boundary region, 91...Mesa region, 100...Semiconductor device, 102...Edge, 112...Gate pad, 120...Active region, 130...Gate wiring, 131...Gate wiring between active regions, 140...Edge termination structure, 161...First region, 162...Second region, 163...Third region, 381...First interlayer insulating film, 382...Second interlayer insulating film

Claims

1. Semiconductor substrate and An interlayer insulating film is provided above the semiconductor substrate, and has a contact hole with a stepped portion on its side wall, A contact portion provided in the aforementioned contact hole, Equipped with, The aforementioned contact portion is A barrier layer provided on the side wall and bottom surface of the contact hole, It has, The aforementioned barrier layer is The first region in contact with the stepped portion, In the region below the first region, there is a second region that is in contact with the side wall of the contact hole, It has, When the film thickness of the thickest part of the first region is T and the film thickness of the thinnest part of the second region is t, The following conditions must be met: 0.3T ≤ t ≤ 0.95T Semiconductor equipment.

2. The interlayer insulating film is A first interlayer insulating film is provided in contact with the front surface of the semiconductor substrate, A second interlayer insulating film is provided above the first interlayer insulating film, It has, The semiconductor device according to claim 1, wherein the stepped portion is formed at the boundary between the first interlayer insulating film and the second interlayer insulating film.

3. The semiconductor device according to claim 1, wherein the contact portion is a trench contact portion extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

4. The barrier layer In the aforementioned contact hole, a first barrier metal layer is provided on the side wall, In the aforementioned contact hole, a second barrier metal layer laminated on the first barrier metal layer, A semiconductor device according to claim 1, having the following features.

5. The semiconductor device according to claim 4, wherein above the stepped portion, the thickness of the second barrier metal layer is thicker than the thickness of the first barrier metal layer.

6. The semiconductor device according to claim 4, wherein below the stepped portion, the thickness of the second barrier metal layer is thinner than the thickness of the first barrier metal layer.

7. The semiconductor device according to claim 1, wherein the film thickness T of the thickest part of the first region is 3 nm or more and 120 nm or less, and the film thickness t of the thinnest part of the second region is 1 nm or more and 114 nm or less.

8. The semiconductor device according to claim 4, wherein the thickness of the first barrier metal layer in the first region is 2 nm or more and 119 nm or less.

9. The semiconductor device according to claim 4, wherein the first barrier metal layer comprises one of Ti, TiN, Ta, and TaN.

10. The semiconductor device according to claim 4, wherein the second barrier metal layer comprises one of TiN and TaN.

11. The semiconductor device according to claim 1, wherein the contact hole is provided with a plug layer located inside the barrier layer.

12. The semiconductor device according to claim 11, wherein at least one or both of the barrier layer and the plug layer are provided above the interlayer insulating film.

13. The semiconductor device according to claim 11, wherein the plug layer comprises one of tungsten and molybdenum.

14. The semiconductor device according to claim 1, wherein the side wall of the contact hole has a forward taper.

15. The semiconductor device according to claim 1, wherein the side wall of the contact hole has a reverse taper.

16. The semiconductor device according to claim 1, wherein the height of the stepped portion in a direction perpendicular to the tangential direction of the side wall of the contact hole is 15% or less of the opening width of the contact hole on the upper surface of the interlayer insulating film.

17. The thickness of the barrier layer is Above the aforementioned stepped portion, the wavelength is 1 nm or more and 115 nm or less. Below the aforementioned stepped portion, the wavelength is between 1 nm and 114 nm. The semiconductor device according to any one of claims 1 to 16.

18. The steps include forming an interlayer insulating film on top of a semiconductor substrate, having contact holes with stepped portions on their side walls, The steps include providing a barrier layer on the side walls and bottom surface of the contact hole, The steps include providing a plug layer inside the barrier layer in the contact hole, Equipped with, The aforementioned barrier layer is The first region in contact with the stepped portion, In the region below the first region, there is a second region that is in contact with the side wall of the contact hole, It has, When the film thickness of the thickest part of the first region is T and the film thickness of the thinnest part of the second region is t, The following conditions must be met: 0.3T ≤ t ≤ 0.95T A method for manufacturing a semiconductor device.

19. The step of providing the barrier layer is, The steps include providing a first barrier metal layer on the side wall and the bottom surface of the contact hole, The steps include providing a second barrier metal layer in the contact hole so as to be laminated on the first barrier metal layer, A method for manufacturing a semiconductor device according to claim 18, comprising:

20. A method for manufacturing a semiconductor device according to claim 19, comprising the step of etching the first region after the step of providing the first barrier metal layer and before the step of providing the second barrier metal layer.

21. The method for manufacturing a semiconductor device according to claim 19, wherein the thickness of the first barrier metal layer in the first region is 2 nm or more and 119 nm or less.

22. The barrier layer is formed by sputtering, according to the method for manufacturing a semiconductor device according to any one of claims 18 to 21.

23. The method for manufacturing a semiconductor device according to claim 18, wherein the plug layer is formed by a CVD method.

24. The method for manufacturing a semiconductor device according to claim 19, wherein the second barrier metal layer is formed by a CVD method.

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