Semiconductor substrates, template substrates, methods and equipment for manufacturing semiconductor substrates, methods and equipment for manufacturing semiconductor devices, semiconductor devices

Abstract

To provide a semiconductor substrate in which a base substrate and a base semiconductor portion can be easily separated.SOLUTION: A semiconductor substrate 10 includes a base substrate BS, a mask pattern 6 having an opening K and a mask portion 5 including a first portion B1 and a second portion B2 thicker than the first portion B1, and a base semiconductor portion 8 including a nitride semiconductor and located above the opening K and the second portion B2.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor substrate and the like.

Background Art

[0002] Patent Document 1 discloses a method of forming a GaN-based semiconductor layer on a base substrate such as a GaN-based substrate or a different substrate using the ELO (Epitaxial Lateral Overgrowth) method.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the method of Patent Document 1, it is not easy to separate the grown semiconductor layer from the base substrate.

Means for Solving the Problems

[0005] The semiconductor substrate according to the present disclosure includes a base substrate, a mask pattern including a mask portion having a first portion and a second portion thicker than the first portion, and an opening, and a base semiconductor portion including a nitride semiconductor and located on the opening and the second portion.

Effects of the Invention

[0006] In the semiconductor substrate, it becomes easier to separate the base substrate and the base semiconductor portion.

Brief Description of the Drawings

[0007] [Figure 1] It is a cross-sectional view showing the configuration of the semiconductor substrate according to the present embodiment. [Figure 2]This is a plan view showing the configuration of the semiconductor substrate according to this embodiment. [Figure 3] This is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. [Figure 4] This is a cross-sectional view showing the configuration of the template substrate according to this embodiment. [Figure 5] This is a cross-sectional view showing another configuration of the template substrate according to this embodiment. [Figure 6] This flowchart shows the method for manufacturing a semiconductor substrate according to this embodiment. [Figure 7] This is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to this embodiment. [Figure 8] This is a block diagram of a semiconductor substrate manufacturing apparatus according to this embodiment. [Figure 9] This flowchart shows a method for manufacturing a semiconductor device according to this embodiment. [Figure 10] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to this embodiment. [Figure 11] This is a block diagram of a semiconductor device manufacturing apparatus according to this embodiment. [Figure 12] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to this embodiment. [Figure 13] This is a plan view showing a method for manufacturing a semiconductor device according to this embodiment. [Figure 14] This is a cross-sectional view showing another method for manufacturing the semiconductor device according to this embodiment. [Figure 15] This is a cross-sectional view showing another method for manufacturing the semiconductor device according to this embodiment. [Figure 16] This flowchart shows another method for manufacturing the semiconductor device according to this embodiment. [Figure 17] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to this embodiment. [Figure 18] This is a cross-sectional view showing another method for manufacturing the semiconductor device according to this embodiment. [Figure 19] This is a cross-sectional view showing an example of the configuration of a semiconductor device (laser body) according to this embodiment. [Figure 20] It is a cross-sectional view showing a configuration example of a base substrate. [Figure 21] It is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1. [Figure 22] It is a plan view showing a method for manufacturing a semiconductor device according to Example 2. [Figure 23] It is a flowchart showing a method for manufacturing a semiconductor device according to Example 2. [Figure 24] It is a perspective view showing a configuration example of a semiconductor device (laser array substrate) according to Example 2. [Embodiments for Carrying Out the Invention]

[0008] (Semiconductor Substrate) FIG. 1 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 2 is a plan view showing the configuration of the semiconductor substrate according to the present embodiment. As shown in FIGS. 1 and 2, the semiconductor substrate 10 according to the present embodiment includes a base substrate BS, a mask pattern 6 including a mask portion 5 having a first portion B1 and a second portion B2 thicker than the first portion B1, and an opening K, and a base semiconductor portion 8 including a nitride semiconductor and located on the opening K and the second portion B2 (overlapping the second portion B2 in plan view). Regarding the upper surface of the first portion B1, all or a part thereof may be in an exposed state (a state where the base semiconductor portion 8 does not exist above). The base semiconductor portion 8 may be a base semiconductor layer or a nitride semiconductor layer (for example, a nitride semiconductor crystal).

[0009] According to the semiconductor substrate 10, the interface between the mask portion 5 and the base substrate BS (the interface between the second portion B2 and the base substrate BS) is easily etched, so that the separation between the base semiconductor portion 8 and the base substrate BS becomes easy.

[0010] The base semiconductor portion 8 contains a nitride semiconductor as its main material. Nitride semiconductors can be expressed as, for example, AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0011] The base semiconductor portion 8 may be doped (e.g., n-type including a donor) or undoped. The term "semiconductor substrate" refers to a substrate containing a nitride semiconductor, and the base substrate BS may contain semiconductors other than nitride semiconductors (e.g., silicon-based semiconductors) or non-semiconductors. The base substrate BS and the mask pattern 6 together are sometimes referred to as the template substrate TS.

[0012] The base semiconductor portion 8 can be formed by the ELO (Epitaxial Lateral Overgrowth) method, starting from the seed region S (the region exposed from the opening K on the upper surface of the base substrate BS). The seed region S may also be the region that serves as the starting point for the growth of the base semiconductor portion 8. The thickness direction of the base semiconductor portion 8 is the c-axis direction ( <0001> The direction may be (or directional). The opening K is longitudinal, and its width direction may be the a-axis direction (<11-20> direction) of the base semiconductor portion 8. In the semiconductor substrate 10, the direction from the base substrate BS to the base semiconductor portion 8 is defined as "upward". Viewing an object with a line of sight parallel to the normal direction of the semiconductor substrate 10 (including perspective views) is sometimes called a "planar view".

[0013] The mask pattern 6 is formed on the base substrate BS. The openings K of the mask pattern 6 have the function of growth initiation holes that expose a part of the upper surface (seed region S) of the base substrate BS and initiate the growth of the base semiconductor portion 8, and the mask portion 5 has the function of selective growth mask (growth suppression region) that causes the base semiconductor portion 8 to grow laterally. In the mask pattern 6, multiple openings K may be arranged in the <11-20> direction (a-axis direction: X direction) of the base semiconductor portion 8.

[0014] The first part B1 and the second part B2 of the mask portion 5 may include the first film F1. The second part B2 may include a second film F2 on the first film F1, which has a different constituent material from the first film F1. The first part B1 may have a portion in which the first film F1 is exposed.

[0015] The first film F1 may have a higher etching rate to a predetermined etchant than the second film F2. The first film F1 and the second film F2 may be inorganic insulating films, and the predetermined etchant may be an etchant used in inorganic insulating films, such as hydrofluoric acid (HF). The second film F2 may have a higher density than the first film F1. The second film F2 may have a lower reactivity to nitride semiconductors than the first film F1. The second film F2 may have a lower surface roughness than the first film F1. The light reflectance of the first film F1 and the light reflectance of the second film F2 may be different. The first film F1 may be thinner than the second film F2.

[0016] The second part B2 of the mask part 5 may be adjacent to the opening K in a plan view. The mask part 5 has a first film F1 and a third part B3 which is located on the first film F1 and has the same constituent material as the second film F2, and the first part B1 may be located between the second part B2 and the third part B3. The base semiconductor part 8 may be ridged. The semiconductor substrate 10 includes an adjacent semiconductor part 8A (included in a plurality of base semiconductor parts 8) which is adjacent to the base semiconductor part 8 and overlaps with the third part B3 of the mask part 5, and the first part B1 may be located below the gap G between the base semiconductor part 8 and the adjacent semiconductor part 8A.

[0017] As shown in Figure 2, the mask portion 5 and the opening K have a longitudinal shape in plan view, and the first portion B1 may be narrower than the second portion B2. The mask portion 5 and the opening K have a longitudinal shape in plan view, and the first portion B1 may be wider than the opening K. In plan view, the base semiconductor portion 8 does not have to overlap with the first portion B1.

[0018] The lower surface of the first film F1 may be in contact with the base substrate BS, the edge E of the first film F1 may be in contact with the base semiconductor portion 8, and the upper surface of the first film F1 may be in contact with the second film F2. The base semiconductor portion 8 may have a lower thread-through dislocation density in the portion located on the second portion B2 than in the portion located on the opening K.

[0019] The base substrate BS includes a silicon substrate and a seed crystal, the constituent material of the first film F1 is silicon oxide (SiOx), the constituent material of the second film F2 is silicon nitride (SiNx), and the nitride semiconductor included in the base semiconductor portion 8 may be a GaN-based semiconductor. In Figures 1 and 2, the first portion B1 is composed of a single layer of silicon oxide film, the second portion B2 and the third portion B3 are composed of laminated films of silicon oxide film and silicon nitride film, and the base semiconductor portion 8 may be a GaN crystal.

[0020] Figure 3 is a cross-sectional view showing an alternative configuration of the semiconductor substrate according to this embodiment. As shown in Figure 3, the constituent materials of the first part B1, the second part B2, and the third part B3 of the mask portion 5 may be the same. For example, the first part B1, the second part B2, and the third part B3 may be formed of a single layer film F, with the first part B1 being a thin film portion of the single layer film F and the second part B2 and the third part B3 being thick film portions of the single layer film F. Silicon nitride (SiNx) may be used as the constituent material (common to B1, B2, and B3) of the single layer film F. (Template board) Figure 4 is a cross-sectional view showing the configuration of a template substrate according to this embodiment. The template substrate TS in Figure 4 comprises a base substrate BS and a mask pattern 6 including a mask portion 5 which includes a first portion B1 and a second portion which is thicker than the first portion B1, and an opening K. The first portion B1 is composed of a first film F1, and the second portion B2 is composed of the first film F1 and the second film F2. Figure 5 is a cross-sectional view showing an alternative configuration of the template substrate according to this embodiment. As shown in Figure 5, the first portion B1 and the second portion B2 of the mask portion 5 may be composed of the same material, or the first portion B1 may be composed of a thin film portion of a single-layer film F, and the second portion B2 may be composed of a thick film portion of a single-layer film F.

[0021] (Method of manufacturing semiconductor substrates) Figure 6 is a flowchart showing a method for manufacturing a semiconductor substrate according to this embodiment. Figure 7 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to this embodiment. The method for manufacturing a semiconductor substrate shown in Figures 6 and 7 includes the steps of: preparing a template substrate TS comprising a base substrate BS and a mask pattern 6 having a mask portion 5 including a first portion B1 and a second portion B2 thicker than the first portion B1, and an opening K; and forming a base semiconductor portion 8 containing a nitride semiconductor and located on the opening K and the second portion B2 (S20).

[0022] The first part B1 may consist of a first film F1, and the second part B2 may consist of the first film F1 and the second film F2. For patterning the second film F2 (silicon nitride) formed on top of the first film F1 (e.g., silicon oxide), lift-off method, dry etching, or wet etching can be used. By limiting the growth range of the base semiconductor portion 8 on the mask portion 5 to the second part B2, dislocations (crystal defects) in the base semiconductor portion 8 can be reduced.

[0023] Figure 8 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 in Figure 8 comprises apparatus A10 that performs the process in S10, apparatus A20 that performs the process in S20, and apparatus A30 that controls apparatus A10 and apparatus A20.

[0024] (Manufacturing methods for semiconductor devices) Figure 9 is a flowchart showing a method for manufacturing a semiconductor device according to this embodiment. Figure 10 is a cross-sectional view showing a method for manufacturing a semiconductor device according to this embodiment. The method for manufacturing a semiconductor device shown in Figures 9 and 10 includes a step (S30) of preparing a semiconductor substrate 10 comprising a base substrate BS, a mask pattern 6 including a mask portion 5 with a first portion B1 and a second portion B2 thicker than the first portion B1, and an opening K, and a base semiconductor portion 8 containing a nitride semiconductor and located on the opening K and the second portion B2, and a step (S40) of etching the mask portion 5 in the order from the first portion B1 to the second portion B2. By proceeding with the etching of the mask portion 5 in the order from the first portion B1 to the second portion B2, the interface between the mask portion 5 and the base substrate BS (the interface between the second portion B2 and the base substrate BS) is made easier to remove. This makes it easier to separate the base semiconductor portion 8 and the base substrate BS.

[0025] Figure 11 is a block diagram showing a semiconductor device manufacturing apparatus according to this embodiment. The semiconductor device manufacturing apparatus 70 in Figure 11 includes apparatus A30 that performs process S30, apparatus A40 that performs process S40, and apparatus A50 that controls apparatus A30 and apparatus A40.

[0026] Figure 12 is a cross-sectional view showing a method for manufacturing a semiconductor device according to this embodiment. Figure 13 is a plan view showing a method for manufacturing a semiconductor device according to this embodiment. As shown in Figures 12 and 13, the first part B1 and the second part B2 include a first film F1, and in the second part B2, a second film F2 made of a different constituent material from the first film F1 is located on the first film F1, and the first film F1 is exposed in the second part B2, and the first film F1 has a higher etching rate to a predetermined etchant than the second film F2. Therefore, in etching of the mask part 5 (e.g., wet etching), the lower first film F1 is quickly removed, and a gap can be created between the base substrate BS and the base semiconductor part 8. The base substrate BS includes a silicon substrate and a seed crystal, the first film F1 includes silicon oxide, the second film F2 includes silicon nitride, and the nitride semiconductor included in the base semiconductor part 8 may be a GaN-based semiconductor (e.g., GaN).

[0027] While silicon nitride is preferable as the surface material for the mask portion because it makes it difficult for dislocations to enter the ELO formation layer (base semiconductor portion), there is a problem in that removing the mask portion before the base semiconductor portion is removed is time-consuming because the etching rate of silicon nitride is very small. There is also a risk that insulating films other than the mask (e.g., silicon oxide film) may be removed at the same time.

[0028] In this embodiment, a mask pattern 6 is formed in a laminated film of a first film F1 (e.g., silicon oxide) and a second film F2 (e.g., silicon nitride) in which a portion of the second film F2 is penetrated and the first film F1 is exposed. By performing ELO of a nitride semiconductor (e.g., GaN-based semiconductor) using such a mask pattern 6, a portion (first part B1) is created in which the first film F1 is exposed below the gap G of adjacent base semiconductor portions 8 (e.g., ridge-shaped). Therefore, when a wet etchant (e.g., hydrofluoric acid) is immersed in the gap G, the first film F1 is quickly removed.

[0029] The upper second film F2 may be lifted off by removing the first film F1, or at least a portion of the second film F2 may be left on the lower surface of the base semiconductor portion 8 as a protective film ZF. Leaving the protective film ZF prevents cracking of the base semiconductor portion 8 that may occur when the base semiconductor portion 8 is peeled off from the base substrate BS. If an insulating film other than the mask is present, it should be protected with a resist or the like before etching the mask portion 5. A material resistant to hydrofluoric acid (HF) (e.g., ZrO2) may be used for the insulating film other than the mask.

[0030] As shown in Figures 12 and 13, a laminate JT including the base semiconductor portion 8 and the upper layer portion M may be formed before etching the mask portion 5. Before etching the mask portion 5, the laminate JT, with the Y direction as the longitudinal direction, may be divided so that a cross section parallel to the short direction (X direction) is obtained. After etching the mask portion 5, the base semiconductor portion 8 and the base substrate BS may be separated while the base semiconductor portion 8 is held in place by the support substrate TK.

[0031] Figure 14 is a cross-sectional view showing another method for manufacturing the semiconductor device according to this embodiment. As shown in Figure 14, the constituent materials of the first part B1 and the second part B2 may be the same. For example, the first part B1 may be composed of a thin film portion of a single layer film F, and the second part B2 may be composed of a thick film portion of a single layer film F, and silicon nitride may be used as the constituent material for the first part B1 and the second part B2 (single layer film F). By removing the thin first part B1, the side surface of the second part B2 is exposed, making it easier to remove the interface between the mask portion 5 and the base substrate BS (the interface between the second part B2 and the base substrate BS). This makes it easier to separate the base semiconductor portion 8 from the base substrate BS.

[0032] Figure 15 is a cross-sectional view showing another method for manufacturing the semiconductor device according to this embodiment. As shown in Figure 15, if the laminate JT includes an insulating film PU covering the ridge side surface, the first film F1 may be removed following the dry etching of the insulating film PU (by dry etching using the same etching mask).

[0033] Figure 16 is a flowchart showing another method for manufacturing a semiconductor device according to this embodiment. Figure 17 is a cross-sectional view showing a method for manufacturing a semiconductor device according to this embodiment. The method for manufacturing a semiconductor device shown in Figures 16 and 17 includes the steps of: preparing a semiconductor substrate 10 comprising a base substrate, a mask pattern including a mask portion and an opening, and a base semiconductor portion 8 containing a nitride semiconductor and located on the opening K and the mask portion 5 (S50); forming a first portion B1 on the mask portion 5 that does not overlap with the base semiconductor portion 8, thinner than a second portion B2 that overlaps with the base semiconductor portion 8 (S60); and etching the mask portion 5 in the order from the first portion B1 to the second portion B2 (S70). By etching the mask portion 5 in the order from the first portion B1 to the second portion B2, the interface between the mask portion 5 and the base substrate BS (the interface between the second portion B2 and the base substrate BS) is easily removed. This facilitates the separation of the base semiconductor portion 8 and the base substrate BS.

[0034] Figure 18 is a cross-sectional view showing another method for manufacturing the semiconductor device according to this embodiment. As shown in Figure 18, if the laminate JT includes an insulating film PU covering the ridge side surface, the second film F2 may be removed following the dry etching of the insulating film PU (by dry etching using the same etching mask). The first film F1 can be removed by wet etching. The insulating film PU and the second film F2 may be made of the same material.

[0035] Figure 19 is a cross-sectional view showing an example of the configuration of a semiconductor device according to this embodiment. As shown in Figure 19, the laser body LT (semiconductor device) comprises a base semiconductor portion 8 containing a nitride semiconductor, an upper layer portion M located on the base semiconductor portion 8, and a protective film ZF in contact with the lower surface of the base semiconductor portion 8. The upper layer portion M has a functional semiconductor portion 9 (including an active portion and a ridge 9R) located on the base semiconductor portion 8, an anode E1 and a cathode E2 located above the functional semiconductor portion 9, and an insulating film PU located on the side of the ridge 9R.

[0036] The upper surface of the base semiconductor portion 8 may include a first region A1 that overlaps with the protective film ZF in a plan view, and a second region A2 that does not overlap with the protective film ZF in a plan view and has a higher threading dislocation density than the first region A1. The protective film ZF may be an insulating film (for example, a silicon nitride film).

[0037] Figure 20 is a cross-sectional view showing an example of the base substrate configuration. The base substrate BS may have a main substrate 1 which is a different type of substrate with a different lattice constant from the base semiconductor portion 8. The base semiconductor portion 8 may contain a GaN-based semiconductor, and the main substrate 1, which is a different type of substrate, may be a silicon substrate. Examples of different types of substrates include a sapphire (Al2O3) substrate and a silicon carbide (SiC) substrate. The plane orientation of the main substrate 1 is, for example, the (111) plane of a silicon substrate, the (0001) plane of a sapphire substrate, and the 6H-SiC(0001) plane of a SiC substrate. These are examples, and any substrate and plane orientation that can grow the base semiconductor portion 8 by the ELO method is acceptable.

[0038] The base substrate BS includes a main substrate 1 and a base portion 4 on the main substrate 1, and the base semiconductor portion 8 may grow from the upper surface (seed region S) of the base portion 4 exposed to the opening K. The base portion 4 may contain a nitride semiconductor. The base portion 4 may contain at least one of a buffer portion and a seed portion. That is, the base portion 4 may consist of a seed portion, or the base portion 4 may consist of a buffer portion (main substrate side) and a seed portion (base semiconductor portion side). GaN-based semiconductors, AlN, SiC, etc. can be used as the buffer portion. Nitride semiconductors (e.g., GaN-based semiconductors) can be used as the seed portion. The base substrate BS may be composed of a self-supporting single-crystal substrate such as GaN or SiC (e.g., a wafer cut from a bulk crystal), and a mask pattern 6 may be arranged on the single-crystal substrate.

[0039] (Example 1) Figure 21 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1. In Figure 21, a mask pattern 6 including a plurality of stripe-shaped mask portions 5 is provided on the base substrate BS. The mask portion 5 is made of, for example, a multilayer insulating film (SiOx / SiNx) with a width of 52 μm, and the longitudinal direction is the m-axis direction of the base semiconductor portion 8. The pitch of the stripes of the mask portion 5 is 55 μm. The base semiconductor portion 8 (nitride semiconductor portion) is grown on the mask pattern 6 by metal-organic vapor deposition (MOCVD) using, for example, trimethylgallium (TMG) and ammonia (NH3) (ELO method).

[0040] The initial growth layer 8p serves as the starting point for lateral growth of the base semiconductor layer 8. The initial growth layer 8p can be formed to a thickness of, for example, 30 nm to 1000 nm, 50 nm to 400 nm, or 70 nm to 350 nm. By allowing lateral growth from a state where the initial growth layer 8p slightly protrudes from the mask layer 5, growth of the base semiconductor layer 8 in the c-axis direction (thickness direction) is suppressed, enabling high-speed and highly crystallinity lateral growth of the base semiconductor layer 8, while also reducing raw material consumption. This makes it possible to form a thin, wide, low-defect base semiconductor layer 8 (crystalline nitride semiconductor such as GaN) at low cost.

[0041] The base semiconductor portions 8, which grow laterally in opposite directions from two adjacent openings K, do not come into contact (meet) on the mask portion 5, and instead have a gap G between them, thereby reducing the internal stress of the base semiconductor portions 8. This reduces the occurrence of cracks and defects (dislocations) in the base semiconductor portions 8. This effect is particularly effective when the main substrate 1 is a different type of substrate. The width of the gap G can be, for example, 10 μm or less, 5 μm or less, 3 μm or less, or 2 μm or less. Of the base semiconductor portion 8, the portion located on the initial growth portion 8p becomes a dislocation inheritance portion with many through-dislocations, while the portion on the mask portion 5 (wing portion) becomes a low-defect portion YS (first region A1 in Figure 19) where the through-dislocation density is 1 / 10 or less compared to the dislocation inheritance portion. A through-dislocation is a dislocation that travels through the base semiconductor portion 8 in its c-axis direction ( <0001> These are dislocations (defects) that extend in the direction. The penetration dislocation density of the low-defect area YS is, for example, 5 × 10⁻⁶. 6 [pcs / cm 2 The following is possible. As described later, when an active portion (active layer) including a light-emitting portion is formed above the base semiconductor portion 8, the light-emitting portion can be positioned above the low-defect portion YS (so as to overlap the low-defect portion YS in a plan view).

[0042] For the low-defect portion YS, the ratio of the size W1 in the a-axis direction to the thickness d1 (W1 / d1) can be set to, for example, 2.0 or more. Using the method of Example 1, W1 / d1 can be set to 1.5 or more, 2.0 or more, 4.0 or more, 5.0 or more, 7.0 or more, or 10.0 or more. It has been found that setting W1 / d1 to 1.5 or more facilitates the subsequent process of dividing the base semiconductor portion 8 (for example, a dividing process where the cross-section becomes the m-plane). In addition, the internal stress of the base semiconductor portion 8 is reduced, and the warping of the semiconductor substrate 10 is reduced.

[0043] The aspect ratio of the base semiconductor portion 8 (ratio of size in the X direction to thickness = WL / d1) can be 3.5 or greater, 5.0 or greater, 6.0 or greater, 8.0 or greater, 10 or greater, 15 or greater, 20 or greater, 30 or greater, or 50 or greater. Furthermore, by using the method of Example 1, the ratio of the size WL of the base semiconductor portion 8 in the X direction to the width WK of the aperture K (WL / WK) can be 3.5 or greater, 5.0 or greater, 6.0 or greater, 8.0 or greater, 10 or greater, 15 or greater, 20 or greater, 30 or greater, or 50 or greater, thereby increasing the ratio of low-defect areas. The base semiconductor portion 8 (including the initial growth portion 8p) shown in Figure 21 can be a nitride semiconductor crystal (for example, a GaN crystal, an AlGaN crystal, an InGaN crystal, or an InAlGaN crystal).

[0044] (Example 2) Figure 22 is a plan view showing a method for manufacturing a semiconductor device according to Example 2. Figure 23 is a flowchart showing a method for manufacturing a semiconductor device according to Example 2. Figure 24 is a perspective view showing an example of the structure of a semiconductor device (laser array substrate) according to Example 2. The method for manufacturing a conductive device shown in Figures 22 to 24 may include the steps of: preparing a semiconductor substrate 10 having a mask pattern 6 having a mask portion 5 including a first portion B1 and a second portion B2, and a base semiconductor portion 8 located on the mask pattern 6; forming a laminate JT including the base semiconductor portion 8 and a functional semiconductor portion 9 (see, for example, Figure 15); dividing the laminate JT on the base substrate BS, with the Y direction as the longitudinal direction, so that a cross section parallel to the short direction (X direction) is obtained; etching the mask portion 5 in the order from the first portion B1 to the second portion B2; separating the base semiconductor portion 8 and the base substrate BS while the base semiconductor portion 8 is held by the support substrate TK; and dividing the support substrate TK.

[0045] Multiple laser bodies (laser chips, semiconductor devices) LT may be formed by dividing the laminate JT on the base substrate BS. The resonator end face (e.g., m-plane) of the laser body LT may be formed by cleavage (m-plane cleavage) of the laminate JT.

[0046] The base semiconductor portion 8 may be an n-type semiconductor crystal (for example, n-type GaN). The functional semiconductor portion 9 of the laminate JT (see, for example, Figure 15) may include a GaN-based semiconductor. The functional semiconductor portion 9 may include an active portion (for example, an active layer such as a quantum well structure) and a p-type semiconductor portion, and may include an n-type semiconductor portion (for example, a regrowth layer, an n-type contact layer) below the active portion. If the active portion of the functional semiconductor portion 9 includes a light-emitting portion, the light-emitting portion can be positioned above the low-defect portion of the base semiconductor portion 8 (the portion overlapping with the second portion B2), that is, so as to overlap with the low-defect portion in a plan view. This can increase the luminescence efficiency.

[0047] As shown in Figure 24, multiple laser bodies LT may be arranged in a two-dimensional manner on the laser array substrate 20. First and second electrode pads P1 and P2 may be provided on the support substrate TK, and the first and second electrode pads P1 and P2 may be connected to the anode and cathode of the laser bodies LT.

[0048] As shown in Figure 22, the laser array substrate 20 may be divided into bar shapes (together with the support substrate TK) to form a laser array substrate 21 (one-dimensional arrangement type) in which multiple laser bodies LT are arranged in one dimension. A reflective mirror film RF may be coated on the resonator end face of each laser body LT on the laser array substrate 21. The laser array substrate 21 may be further divided to form laser elements 22 (semiconductor devices). In Figures 22 and 23, the laminate JT is divided on the base substrate BS, but the method is not limited to this. For example, the laminate JT may be transferred to a tape or the like one or more times, and then the laminate JT may be divided on the tape (e.g., by cleavage) to form multiple laser bodies.

[0049] (Additional items) The foregoing disclosures are for illustrative and explanatory purposes only, and not for limitation. Many variations will be obvious to those skilled in the art based on these examples and descriptions, and therefore, these variations are also included in the embodiments. [Explanation of Symbols]

[0050] 1 Main board 4. Substrate 5 Mask section 6 Mask Patterns 8 Base semiconductor section 10 Semiconductor substrates 20 21 Laser array substrate (semiconductor device) 22. Laser elements (semiconductor devices) LT laser body (semiconductor device) BS base board TS template substrate TK support board K opening G Gap F1 First Membrane F2 Second Membrane B1 Part 1 B2 Part 2

Claims

1. Base board and A mask pattern having a mask portion including a first part and a second part that is thicker than the first part, and an opening, A semiconductor substrate comprising a base semiconductor portion containing a nitride semiconductor and located on the opening and the second portion.

2. The first and second parts include the first membrane, The second part includes a second film on the first film, the second film having a different constituent material from the first film. The semiconductor substrate according to claim 1, wherein the first part has a portion in which the first film is exposed.

3. The semiconductor substrate according to claim 2, wherein the first film has a higher etching rate to a predetermined etchant than the second film.

4. The semiconductor substrate according to claim 2, wherein the second film has a higher density than the first film.

5. The semiconductor substrate according to claim 2, wherein the second film has lower reactivity with respect to the nitride semiconductor than the first film.

6. The semiconductor substrate according to claim 2, wherein the second film has a surface roughness smaller than that of the first film.

7. The second part is the semiconductor substrate according to claim 1, adjacent to the opening in a plan view.

8. The semiconductor substrate according to claim 2, wherein the first film is thinner than the second film.

9. The mask portion includes the first film and a third portion which is located on the first film and has the same constituent material as the second film. The semiconductor substrate according to claim 2, wherein the first part is located between the second part and the third part.

10. The mask portion and the opening are longitudinal in a plan view. The semiconductor substrate according to claim 1, wherein the first part is narrower in width than the second part.

11. The mask portion and the opening are elongated in shape. The semiconductor substrate according to claim 1, wherein the first part is wider than the opening.

12. It includes an adjacent semiconductor portion that is adjacent to the base semiconductor portion and overlaps with the third portion, The semiconductor substrate according to claim 9, wherein the first portion is located below the gap between the base semiconductor portion and the adjacent semiconductor portion.

13. The semiconductor substrate according to claim 2, wherein the lower surface of the first film is in contact with the base substrate, the edge of the first film is in contact with the base semiconductor portion, and the upper surface of the first film is in contact with the second film.

14. The semiconductor substrate according to claim 1, wherein the constituent materials of the first and second parts are the same.

15. The semiconductor substrate according to claim 1, wherein the base semiconductor portion has a smaller threading dislocation density in the portion located above the second portion than in the portion located above the opening.

16. The base substrate includes a silicon substrate and a seed crystal. The first film contains silicon oxide, The second film contains silicon nitride, The semiconductor substrate according to claim 2, wherein the nitride semiconductor is a GaN-based semiconductor.

17. Base board and A template substrate comprising a mask portion including a first part and a second part thicker than the first part, and a mask pattern including an opening.

18. A step of preparing a template substrate comprising a base substrate and a mask pattern having a mask portion including a first portion and a second portion thicker than the first portion, and an opening, A method for manufacturing a semiconductor substrate, comprising the step of forming a base semiconductor portion that includes a nitride semiconductor and is located on the opening and the second portion.

19. A step of preparing a semiconductor substrate comprising a base substrate, a mask pattern including a mask portion and an opening, which includes a first portion and a second portion that is thicker than the first portion, and a base semiconductor portion which includes a nitride semiconductor and is located on the opening and the second portion, A method for manufacturing a semiconductor device, comprising the step of proceeding with etching the mask portion in the order from the first portion to the second portion.

20. A step of preparing a semiconductor substrate comprising a base substrate, a mask pattern including a mask portion and an opening, and a base semiconductor portion including a nitride semiconductor that overlaps with the mask portion, The process of forming a first portion on the mask portion that is thinner than the second portion that overlaps with the base semiconductor portion and does not overlap with the base semiconductor portion, A method for manufacturing a semiconductor device, comprising the step of proceeding with etching the mask portion in the order from the first portion to the second portion.

21. A method for manufacturing a semiconductor device according to claim 19 or 20, wherein the etching creates a gap between the base substrate and the base semiconductor portion.

22. The second part and the first part include the first film, In the second part, a second film with a different constituent material from the first film is located on the first film, and in the first part, the first film is exposed. The first film has a higher etching rate to a predetermined etchant than the second film. A method for manufacturing a semiconductor device according to claim 19 or 20, wherein the first film is removed in the etching process.

23. A method for manufacturing a semiconductor device according to claim 22, wherein at least a portion of the second film remains after the first film is removed.

24. A method for manufacturing a semiconductor device according to claim 19 or 20, comprising the step of forming a laminate including the base semiconductor portion and the functional semiconductor portion before the etching.

25. The laminate has a longitudinal shape, A method for manufacturing a semiconductor device according to claim 24, comprising the step of dividing the laminate on the base substrate such that a cross section parallel to the short direction is obtained.

26. A method for manufacturing a semiconductor device according to claim 19 or 20, wherein, after etching, the base semiconductor portion is held on the support substrate and the base semiconductor portion is separated from the base substrate.

27. The base substrate includes a silicon substrate and a seed crystal. The first film contains silicon oxide, The second film contains silicon nitride, The method for manufacturing a semiconductor device according to claim 22, wherein the nitride semiconductor is a GaN-based semiconductor.

28. A semiconductor device manufacturing apparatus that performs each of the steps described in claim 19 or 20.

29. A base semiconductor portion containing a nitride semiconductor, A functional semiconductor section located above the base semiconductor section, An anode located above the functional semiconductor section, A semiconductor device comprising a protective film in contact with the lower surface of the base semiconductor portion.

30. The semiconductor device according to claim 29, wherein the upper surface of the base semiconductor portion includes a first region that overlaps with the protective film in a plan view, and a second region that does not overlap with the protective film in a plan view and has a greater threading dislocation density than the first region.

Images