Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device capable of suppressing a temperature change of a diode characteristic, and provide a manufacturing method of the silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device 200 includes: a silicon carbide substrate 100; a first electrode 61; a second electrode 62; a first main surface 1; a second main surface 2; a first impurity region 10; a second impurity region 20; and a third impurity region 30. The first electrode is contacted to the second and third impurity regions in the first main surface. The second electrode is contacted to the first impurity region in the second main surface. The second impurity region contains: a first region 21, and a second region 22 that is existed to between the first region and the second main surface, and is contacted to the first region. An impurity density of the first region is 6×1016 cm-3 or more.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. This application claims priority based on Japanese Patent Application No. 2019-196257, a Japanese patent application filed on October 29, 2019. All the descriptions contained in the Japanese patent application are incorporated herein by reference.

Background Art

[0002] Kazuto Takao, et al., "High-Frequency Drive High-Power Conversion Device Using a Hybrid Pair of SiC-PiN Diode and Si-IEGT," Toshiba Review, Vol. 66, No. 5, 2011 (Non-Patent Document 1) describes the IV characteristics of SiC-PiN diodes.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

[0004] The silicon carbide semiconductor device according to this disclosure comprises a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface, provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be separated from the first impurity region and having a first conductivity type. The first electrode is in contact with the second impurity region and the third impurity region on the first main surface. The second electrode is in contact with the first impurity region on the second main surface. The second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region. The impurity concentration of the first region is 6 × 10⁻⁶ 16 cm -3 That's all.

[0005] The silicon carbide semiconductor device according to this disclosure comprises a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface, provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be separated from the first impurity region and having a first conductivity type. The first electrode is in contact with the second impurity region and the third impurity region, respectively, on the first main surface. The second electrode is in contact with the first impurity region on the second main surface. The second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region. The point defect density of the first region is 6 × 10⁻⁶ 12 cm -3 That's all.

[0006] A silicon carbide semiconductor device manufacturing method according to this disclosure comprises the following steps: A silicon carbide substrate is prepared having a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface, provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be separated from the first impurity region and having a first conductivity type. A first electrode is formed on the first main surface, in contact with the second impurity region and the third impurity region, respectively. A second electrode is formed on the second main surface, in contact with the first impurity region. The second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region. The impurity concentration of the first region is 6 × 10⁻⁶ 16 cm -3 That concludes the explanation. The first region is formed by ion implantation. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view along the line II-II in Figure 1. [Figure 3] Figure 3 is an enlarged schematic diagram of region III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the second embodiment. [Figure 5] Figure 5 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the third embodiment. [Figure 6] Figure 6 is a schematic flowchart showing the manufacturing method of a silicon carbide semiconductor device according to this embodiment. [Figure 7] Figure 7 is a schematic flowchart showing the steps for preparing the silicon carbide substrate in the silicon carbide semiconductor device manufacturing method according to this embodiment. [Figure 8] Figure 8 is a schematic cross-sectional view showing the first step of the method for manufacturing a silicon carbide semiconductor device according to this embodiment. [Figure 9] Figure 9 is a schematic cross-sectional view showing the second step of the silicon carbide semiconductor device manufacturing method according to this embodiment. [Figure 10] Figure 10 is a schematic cross-sectional view showing the third step of the method for manufacturing a silicon carbide semiconductor device according to this embodiment. [Figure 11] Figure 11 is a schematic cross-sectional view showing the fourth step of the method for manufacturing a silicon carbide semiconductor device according to this embodiment. [Figure 12] Figure 12 is a schematic cross-sectional view showing the fifth step of the silicon carbide semiconductor device manufacturing method according to this embodiment. [Figure 13] Figure 13 is a schematic cross-sectional view showing the sixth step of the silicon carbide semiconductor device manufacturing method according to this embodiment. [Figure 14] Figure 14 is a schematic cross-sectional view showing the seventh step of the silicon carbide semiconductor device manufacturing method according to this embodiment. [Figure 15] Figure 15 is a schematic cross-sectional view showing the eighth step of the silicon carbide semiconductor device manufacturing method according to this embodiment. [Figure 16] This figure shows the relationship between drain current density and drain voltage in a silicon carbide semiconductor device related to Sample 1. [Figure 17] This figure shows the relationship between drain current density and drain voltage in the silicon carbide semiconductor device related to Sample 2. [Modes for carrying out the invention]

[0008] [Issues this disclosure aims to address] The object of this disclosure is to provide a silicon carbide semiconductor device capable of suppressing temperature changes in diode characteristics and a method for manufacturing a silicon carbide semiconductor device. [Effects of this disclosure] According to this disclosure, it is possible to provide a silicon carbide semiconductor device capable of suppressing temperature changes in diode characteristics and a method for manufacturing a silicon carbide semiconductor device. [Description of Embodiments in this Disclosure] First, embodiments of the present disclosure will be enumerated and described. In the crystallographic description of this specification, individual orientations are indicated by [], collective orientations are indicated by <>, individual planes are indicated by (), and collective planes are indicated by {}. A negative crystallographic index is usually expressed by attaching "-" (bar) above the number, but in this specification, a negative crystallographic index is expressed by attaching a negative sign before the number.

[0009] (1) The silicon carbide semiconductor device 200 according to the present disclosure includes a silicon carbide substrate 100, a first electrode 61, and a second electrode 62. The silicon carbide substrate 100 includes a first main surface 1, a second main surface 2 opposite to the first main surface 1, a first impurity region 10 that constitutes at least a part of the second main surface 2 and has a first conductivity type, a second impurity region 20 that constitutes at least a part of the first main surface 1, is provided in contact with the first impurity region 10, and has a second conductivity type different from the first conductivity type, and a third impurity region 30 that is provided in contact with the second impurity region 20 so as to be separated from the first impurity region 10 and has the first conductivity type. The first electrode 61 is in contact with each of the second impurity region 20 and the third impurity region 30 on the first main surface 1. The second electrode 62 is in contact with the first impurity region 10 on the second main surface 2. The second impurity region 20 includes a first region 21 and a second region 22 that is between the first region 21 and the second main surface 2 and is in contact with the first region 21. The impurity concentration of the first region 21 is 6×10 16 cm -3 or more.

[0010] (2) According to the silicon carbide semiconductor device 200 according to (1) above, the impurity concentration of the second region 22 may be 6×10 16 cm -3 or more.

[0011] (3) The silicon carbide semiconductor device 200 according to the present disclosure comprises a silicon carbide substrate 100, a first electrode 61, and a second electrode 62. The silicon carbide substrate 100 has a first main surface 1, a second main surface 2 opposite to the first main surface 1, a first impurity region 10 constituting at least a part of the second main surface 2 and having a first conductivity type, a second impurity region 20 constituting at least a part of the first main surface 1, provided in contact with the first impurity region 10 and having a second conductivity type different from the first conductivity type, and a third impurity region 30 provided in contact with the second impurity region 20 so as to be separated from the first impurity region 10 and having a first conductivity type. The first electrode 61 is in contact with the second impurity region 20 and the third impurity region 30, respectively, on the first main surface 1. The second electrode 62 is in contact with the first impurity region 10 on the second main surface 2. The second impurity region 20 includes a first region 21 and a second region 22 that is located between the first region 21 and the second main surface 2 and is in contact with the first region 21. 2nd area 22 The point defect density is 6 × 10⁻⁶ 12 cm -3 That's all.

[0012] (4) According to the silicon carbide semiconductor device 200 described in (3) above, 2nd area 22 The point defect density is 1 × 10⁻⁶ 14 cm -3 The following is also acceptable.

[0013] (5) In the case of a silicon carbide semiconductor device 200 according to any of (1) to (4) above, the silicon carbide semiconductor device 200 may be of the planar type.

[0014] (6) In the silicon carbide semiconductor device 200 according to any of (1) to (4) above, a trench 5 may be provided in the silicon carbide substrate 100. The trench 5 may have a side surface 3 that is in contact with each of the first impurity region 10, the second impurity region 20, and the third impurity region 30, and a bottom surface 4 that is connected to the side surface 3 and is in contact with the first impurity region 10.

[0015] (7) In the silicon carbide semiconductor device 200 described in (6) above, the shape of the trench 5 in a cross section perpendicular to the first main surface 1 may be U-shaped.

[0016] (8) In the silicon carbide semiconductor device 200 described in (6) above, the shape of the trench 5 in a cross section perpendicular to the first main surface 1 may be V-shaped.

[0017] (9) In the silicon carbide semiconductor device 200 according to any of (1) to (8) above, the first main surface 1 may be the (000-1) surface or a surface inclined at an angle of 8° or less with respect to the (000-1) surface.

[0018] (10) In the silicon carbide semiconductor device 200 according to any of (1) to (9) above, the impurity concentration in the first region 21 may be higher than the impurity concentration in the second region 22.

[0019] (11) According to the silicon carbide semiconductor device 200 described in (10) above, the impurity concentration in the first region 21 is 1 × 10 19 cm -3 The following is also acceptable.

[0020] (12) A method for manufacturing the silicon carbide semiconductor device 200 according to the present disclosure comprises the following steps: A silicon carbide substrate 100 is prepared, having a first main surface 1, a second main surface 2 opposite to the first main surface 1, a first impurity region 10 constituting at least a part of the second main surface 2 and having a first conductivity type, a second impurity region 20 constituting at least a part of the first main surface 1, provided in contact with the first impurity region 10 and having a second conductivity type different from the first conductivity type, and a third impurity region 30 provided in contact with the second impurity region 20 so as to be separated from the first impurity region 10 and having a first conductivity type. A first electrode 61 is formed on the first main surface 1, in contact with the second impurity region 20 and the third impurity region 30, respectively. A second electrode 62 is formed on the second main surface 2, in contact with the first impurity region 10. The second impurity region 20 includes the first region 21 and the second region 22, which is located between the first region 21 and the second main surface 2 and is in contact with the first region 21. The impurity concentration of the first region 21 is 6 × 10⁻⁶. 16 cm -3 That concludes the explanation. The first region 21 is formed by ion implantation.

[0021] (13) According to the method for manufacturing the silicon carbide semiconductor device 200 described in (12) above, the second region 22 may be formed by ion implantation.

[0022] (14) According to the method for manufacturing the silicon carbide semiconductor device 200 described in (12) or (13) above, the first impurity region 10 may be formed by epitaxial growth at a temperature of 1500°C or more and 1750°C or less.

[0023] (15) According to the method for manufacturing a silicon carbide semiconductor device 200 according to any of (12) to (14) above, the step of preparing the silicon carbide substrate 100 may include an activation annealing step. The activation annealing step may be carried out at a temperature of 1600°C or more and 1850°C or less. [Details of the embodiments of this disclosure] The embodiments of this disclosure are described below in detail. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description of them is not repeated.

[0024] (First Embodiment) First, the configuration of the silicon carbide semiconductor device 200 according to the first embodiment will be described. Figure 1 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device 200 according to the first embodiment.

[0025] As shown in Figure 1, the silicon carbide semiconductor device 200 according to the first embodiment is a trench-type MOSFET and mainly comprises a silicon carbide substrate 100, a gate electrode 63, a gate insulating film 51, a isolation insulating film 52, a first electrode 61, and a second electrode 62. The silicon carbide substrate 100 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1.

[0026] The first principal surface 1 is, for example, the {0001} plane or a plane that is 8° or less off-center from the {0001} plane. Specifically, the first principal surface 1 is, for example, the (000-1) plane or a plane that is inclined at an angle of 8° or less with respect to the (000-1) plane. The first principal surface 1 may also be, for example, the (0001) plane or a plane that is inclined at an angle of 8° or less with respect to the (0001) plane.

[0027] As shown in Figure 1, the silicon carbide substrate 100 includes a first impurity region 10, a second impurity region 20, and a third impurity region 30. The first impurity region 10 contains n-type impurities that can impart n-type properties, such as N (nitrogen). The first impurity region 10 has, for example, an n-type (first conductivity type). The first impurity region 10 constitutes at least a part of the second main surface 2. In other words, the first impurity region 10 may constitute the entire second main surface 2 or a part of the second main surface 2.

[0028] The first impurity region 10 includes a silicon carbide single crystal substrate 15, a buffer layer 11, a first superjunction region 12, a first joint region 13, and a current spreading region 14. The silicon carbide single crystal substrate 15 constitutes the second main surface 2. The silicon carbide single crystal substrate 15 is made of, for example, polytype 4H hexagonal silicon carbide. The buffer layer 11 is provided on the silicon carbide single crystal substrate 15. The buffer layer 11 is in contact with the silicon carbide single crystal substrate 15.

[0029] The first superjunction region 12 is provided on the buffer layer 11. The first superjunction region 12 is in contact with the buffer layer 11. In the first direction 101, the width of the first superjunction region 12 is smaller than the width of the buffer layer 11. The height of the first superjunction region 12 in the third direction 103 may be larger than the width of the first superjunction region 12 in the first direction 101. The concentration of n-type impurities in the first superjunction region 12 may be lower than the concentration of n-type impurities in the buffer layer 11.

[0030] The first joint region 13 is located on the first superjunction region 12. The first joint region 13 is in contact with the first superjunction region 12. The first joint region 13 may be narrowed such that the width in the center is smaller than the widths of the upper and lower sections. The current spreading region 14 is located on the first joint region 13. The current spreading region 14 is in contact with the first joint region 13. The current spreading region 14 is in contact with the bottom surface 4 and the side surface 3 of the trench 5.

[0031] The impurity concentration in the first impurity region 10 is, for example, 6 × 10⁻⁶ 16 cm -3 That concludes the explanation. Specifically, the concentration of n-type impurities in the first superjunction region 12 of the first impurity region 10 is, for example, 6 × 10⁻⁶. 16 cm -3 That concludes the explanation. The concentration of n-type impurities in the first superjunction region 12 of the first impurity region 10 is, for example, 8 × 10⁻⁶. 16 cm -3 More than that is also acceptable, or 10 x 10 16 cm -3 That's fine too.

[0032] The concentration of n-type impurities in the first joint region 13 of the first impurity region 10 is, for example, 6 × 10⁻⁶ 16 cm -3 That concludes the explanation. The concentration of n-type impurities in the current spreading region 14 of the first impurity region 10 is, for example, 6 × 10⁻⁶. 16 cm -3 That concludes the explanation. The concentrations of n-type impurities in the first superjunction region 12, the first joint region 13, and the current spreading region 14 are, for example, 6 × 10⁻⁶. 16 cm -3 That's fine too.

[0033] The second impurity region 20 contains p-type impurities, such as Al (aluminum), which can impart p-type properties. The second impurity region 20 has a p-type (second conductivity type) that is different from the n-type. The second impurity region 20 is provided in contact with the first impurity region 10. The second impurity region 20 and the first impurity region 10 constitute a PN diode. The second impurity region 20 constitutes at least a part of the first main surface 1. In other words, the second impurity region 20 may constitute the entire first main surface 1 or a part of the first main surface 1.

[0034] The second impurity region 20 has a first region 21 and a second region 22. The second region 22 is located between the first region 21 and the second main surface 2. The second region 22 is in contact with the first region 21. The first region 21 constitutes at least a part of the first main surface 1. The first region 21 may have, for example, a first portion 41 and a second portion 42. The first portion 41 is on the second portion 42. The second portion 42 is in contact with the first portion 41. The concentration of p-type impurities in the first portion 41 may be higher than the concentration of p-type impurities in the second portion 42. The second portion 42 is, for example, a channel layer. The first region 21 does not have to have the first portion 41. The second region 22 may be in contact with the buffer layer 11.

[0035] The second region 22 includes a second superjunction region 25, a second joint region 24, and a third joint region 23. The second superjunction region 25 is provided on the buffer layer 11. The second superjunction region 25 is in contact with the buffer layer 11. In the first direction 101, the width of the second superjunction region 25 is smaller than the width of the buffer layer 11. The height of the second superjunction region 25 in the third direction 103 may be larger than the width of the second superjunction region 25 in the first direction 101.

[0036] The first superjunction region 12 and the second superjunction region 25 constitute a superjunction. The first superjunction region 12 is in contact with the second superjunction region 25. In the first direction 101, the first superjunction region 12 and the second superjunction region 25 are arranged alternately. The concentration of p-type impurities in the second superjunction region 25 may be approximately the same as the concentration of n-type impurities in the first superjunction region 12. In the first direction 101, the width of the second superjunction region 25 may be approximately the same as the width of the first superjunction region 12.

[0037] The second joint region 24 is located on the second superjunction region 25. The second joint region 24 is in contact with the second superjunction region 25. The second joint region 24 may be extended such that the width of its center is greater than the widths of its upper and lower sections. In the first direction 101, the maximum width of the second joint region 24 may be greater than the width of the second superjunction region 25. The second joint region 24 is in contact with the first joint region 13. In the first direction 101, the second joint region 24 and the first joint region 13 are arranged alternately.

[0038] The third joint region 23 is located on the second joint region 24. The third joint region 23 is in contact with both the second joint region 24 and the first region 21. In the third direction 103, the third joint region 23 is located between the second joint region 24 and the first region 21. In the first direction 101, the third joint region 23 is in contact with the current spreading region 14.

[0039] The impurity concentration in region 22 is 6 × 10⁻⁶. 16 cm -3 That concludes the explanation. Specifically, the concentration of p-type impurities in the second superjunction region 25 of the second region 22 is 6 × 10⁻⁶. 16 cm -3That concludes the explanation. The concentration of p-type impurities in the second superjunction region 25 of the second region 22 is 8 × 10⁻⁶. 16 cm -3 More than that is also acceptable, or 10 x 10 16 cm -3 The above is also acceptable. The upper limit of the concentration of p-type impurities in the second superjunction region 25 of the second region 22 is not particularly limited, but for example, 6 × 10 18 cm -3 The following is also acceptable.

[0040] The concentration of p-type impurities in the second joint region 24 of the second region 22 is, for example, 6 × 10⁻⁶. 16 cm -3 That concludes the explanation. The concentration of p-type impurities in the third joint region 23 of the second region 22 is, for example, 6 × 10⁻⁶. 16 cm -3 That concludes the explanation. The concentrations of p-type impurities in the second superjunction region 25, the second joint region 24, and the third joint region 23 are, for example, 6 × 10⁻⁶. 16 cm -3 That's fine too.

[0041] The third impurity region 30 is provided adjacent to the second impurity region 20 so as to be separated from the first impurity region 10. The third impurity region 30 contains n-type impurities that can impart n-type properties, such as P (phosphorus). The third impurity region 30 has, for example, an n-type property. The third impurity region 30 is, for example, a source region. The third impurity region 30 may constitute a part of the first main surface 1. The concentration of n-type impurities contained in the third impurity region 30 may be higher than the concentration of p-type impurities contained in the second part 42.

[0042] The impurity concentration in region 1, 21, is 6 × 10⁻⁶. 16 cm -3 That concludes the explanation. Specifically, the concentration of p-type impurities in the first region 21 is 6 × 10⁻⁶. 16 cm -3That is all. The impurity concentration in the first region 21 may be higher than the impurity concentration in the second region 22. Specifically, the concentration of p-type impurities in the second part 42 of the first region 21 may be higher than the concentration of p-type impurities in the second region 22. The impurity concentration in the first region 21 is 1 × 10⁻⁶. 19 cm -3 The following may also be the case. Specifically, the concentration of p-type impurities in the second part 42 of the first region 21 is 1 × 10⁻⁶. 19 cm -3 The following may also be true: The concentration of p-type impurities in the second part 42 of the first region 21 is 8 × 10 18 cm -3 The following is also acceptable, or 6 x 10 18 cm -3 The following is also possible: The lower limit of the concentration of p-type impurities in the second part 42 of the first region 21 is not particularly limited, but for example, 6 × 10 17 cm -3 That's fine too.

[0043] A trench 5 is provided in the silicon carbide substrate 100. The trench 5 opens into the first main surface 1. The trench 5 has a side surface 3 and a bottom surface 4. The bottom surface 4 is connected to the side surface 3. The side surface 3 is in contact with each of the first impurity region 10, the second impurity region 20, and the third impurity region 30. Specifically, the side surface 3 is in contact with each of the current spreading region 14, the second portion 42, and the third impurity region 30. The bottom surface 4 is in contact with the first impurity region 10. Specifically, the bottom surface 4 is in contact with the current spreading region 14.

[0044] In a cross-section perpendicular to the first main surface 1, the shape of the trench 5 may be V-shaped. A trench 5 is considered V-shaped if the angle θ between the side surface 3 of the trench 5 and the first main surface 1 is greater than 90° and less than 180°. The angle θ may be, for example, 115° or more and 135° or less.

[0045] The gate insulating film 51 is made of, for example, silicon dioxide. The gate insulating film 51 is located inside the trench 5. The gate insulating film 51 is in contact with the first impurity region 10, the second impurity region 20, and the third impurity region 30 on the side surface 3 of the trench 5. The gate insulating film 51 is in contact with the current spreading region 14 on the bottom surface 4 of the trench 5. A channel can be formed in the second portion 42 of the second impurity region 20 that is in contact with the gate insulating film 51. The gate insulating film 51 is in contact with the third impurity region 30 on the first main surface 1. The thickness of the gate insulating film 51 is, for example, 40 nm or more and 150 nm or less.

[0046] The gate electrode 63 is provided on the gate insulating film 51. It is positioned in contact with the gate insulating film 51. At least a portion of the gate electrode 63 is located inside the trench 5. The gate electrode 63 is made of a conductor, such as polysilicon doped with impurities.

[0047] The isolation insulating film 52 is provided so as to cover the gate electrode 63. The isolation insulating film 52 is in contact with both the gate electrode 63 and the gate insulating film 51. The isolation insulating film 52 is made of, for example, an NSG (None-doped Silicate Glass) film or a PSG (Phosphorus Silicate Glass) film. The isolation insulating film 52 electrically insulates the gate electrode 63 from the first electrode 61.

[0048] The first electrode 61 is provided on the first main surface 1. The first electrode 61 is, for example, a source electrode. The first electrode 61 has an electrode layer 60 and a wiring layer 64. The electrode layer 60 is made of a material containing, for example, Ti (titanium), Al (aluminum), and Si (silicon). The electrode layer 60 may also contain Ni (nickel). The wiring layer 64 is made of a material containing, for example, Al.

[0049] The first electrode 61 is in contact with the second impurity region 20 and the third impurity region 30 on the first main surface 1. Specifically, the electrode layer 60 is in contact with the first portion 41 and the third impurity region 30 on the first main surface 1. The first electrode 61 may be positioned to straddle the trench 5. The first electrode 61 may cover the isolation insulating film 52. The first electrode 61 is electrically connected to the second impurity region 20. The first electrode 61 is electrically connected to the third impurity region 30. When the first impurity region 10 is n-type and the second impurity region 20 is p-type, the first electrode 61 functions as an anode electrode.

[0050] The second electrode 62 is provided on the second main surface 2. The second electrode 62 is, for example, a drain electrode. The second electrode 62 is in contact with the first impurity region 10 on the second main surface 2. Specifically, the second electrode 62 is in contact with the silicon carbide single crystal substrate 15 on the second main surface 2. The second electrode 62 is electrically connected to the first impurity region 10. When the first impurity region 10 is n-type and the second impurity region 20 is p-type, the second electrode 62 functions as a cathode electrode. The second electrode 62 is made of a material that can be ohmic bonded to the n-type silicon carbide single crystal substrate 15, such as NiSi (nickel silicide).

[0051] In the silicon carbide semiconductor device 200 according to the first embodiment, the breakdown voltage in the reverse direction is, for example, 600V or more, preferably 1100V or more.

[0052] Next, we will explain how to measure the concentrations of p-type and n-type impurities in each impurity region.

[0053] The concentrations of p-type and n-type impurities in each impurity region can be measured using SIMS (Secondary Ion Mass Spectrometry). The measuring instrument is, for example, a Cameca secondary ion mass spectrometer. The measurement pitch is, for example, 0.01 μm. When the n-type impurity to be detected is nitrogen, the primary ion beam is cesium (Cs). The primary ion energy is 14.5 keV. The secondary ion polarity is negative. When the p-type impurity to be detected is aluminum or boron, the primary ion beam is oxygen (O2). The primary ion energy is 8 keV. The secondary ion polarity is positive.

[0054] Next, we will explain how to distinguish between p-type and n-type regions. Scanning Capacitance Microscope (SCM) is used to distinguish between p-type and n-type regions. The measuring device is, for example, the NanoScope IV manufactured by Bruker AXS. SCM is a method for visualizing the carrier concentration distribution in a semiconductor. Specifically, a metal-coated silicon probe is used to scan the surface of the sample. During this process, a high-frequency voltage is applied to the sample. This excites the majority carriers and modulates the capacitance of the system. The frequency of the high-frequency voltage applied to the sample is 100 kHz, and the voltage is 4.0 V.

[0055] Figure 2 is a schematic cross-sectional view along the line II-II in Figure 1. As shown in Figure 2, when viewed perpendicular to the second main surface 2, the second superjunction region 25 extends, for example, along the second direction 102. In other words, the longitudinal direction of the second superjunction region 25 is, for example, the second direction 102. The short direction of the second superjunction region 25 is, for example, the first direction 101. When viewed perpendicular to the second main surface 2, the second superjunction region 25 may be substantially rectangular. When viewed perpendicular to the second main surface 2, the first superjunction region 12 may surround the second superjunction region 25.

[0056] Each of the first direction 101 and the second direction 102 is parallel to the second principal plane 2. The third direction 103 is perpendicular to the second principal plane 2. The first direction 101 is, for example, the <11-20> direction. The second direction 102 is, for example, the <1-100> direction. The third direction 103 is, for example <0001> This is a direction. The first direction 101 may be, for example, the direction obtained by projecting the <11-20> direction onto the first principal plane 1. The second direction 102 may be, for example, the direction obtained by projecting the <1-100> direction onto the first principal plane 1. The third direction 103 may be, for example <0001> The direction may be inclined with respect to the direction.

[0057] Figure 3 is an enlarged schematic diagram of region III in Figure 2. As shown in Figure 3, the second region 22 has a point defect 9. The energy level of point defect 9 is more than 0.5 eV deeper than Ec (energy at the bottom of the conduction band) and more than 0.4 eV higher than Ev (energy at the top of the valence band). Point defect 9 is Z 1 / 2 The first defect, called the center, 7, and EH 6 / 7 It may have a second defect 8 called a center. 1 / 2 The energy level of the center is Ec (energy of the bottom of the conduction band) -0.65 eV. 6 / 7The energy level of the center is Ec(energy of the bottom of the conduction band)-1.55eV. The second region 22 may have both the first defect 7 and the second defect 8, or it may have only the first defect 7, or it may have only the second defect 8.

[0058] The point defect density in the second region 22 is 6 × 10⁻¹⁰ 12 cm -3 That concludes the explanation. The point defect density in the second region 22 is, for example, 8 × 10⁻⁶. 12 cm -3 More than that is also acceptable, or 10 x 10 12 cm -3 The above may also be the case. The point defect density of the second region 22 is, for example, 1 × 10⁻⁶. 14 cm -3 The following may also apply: The point defect density of the second region 22 is, for example, 0.8 × 10⁻⁶. 14 cm -3 The following is also acceptable, or 0.6 × 10 14 cm -3 The following is also acceptable. If the second region 22 has the first defect 7 and the second defect 8, the point defect density of the second region 22 is the sum of the point defect density of the first defect 7 and the second defect 8.

[0059] Next, we will explain the method for measuring point defect density. Point defect density can be measured by DLTS (Deep Level Transient Spectroscopy) and / or ICTS (Isothermal Capacitance Transient Spectroscopy). In the DLTS method, the time evolution of junction capacitance is obtained by varying the temperature while keeping the pulse width constant. In the ICTS method, the time evolution of junction capacitance is obtained by varying the pulse width while keeping the temperature constant. Point defect information can be obtained by either the DLTS or ICTS method, but more accurate information can be obtained by performing both methods. As a measurement device, for example, the Phystech FT1230 can be used. The sample temperature is in the range of 77K to 773K, and the time evolution of junction capacitance is obtained by applying a pulse voltage. A pulse voltage of +20V to -20V is used, and a pulse width of 1μs to 60s is used. Point defect density and its energy levels can be obtained by performing a Fourier transform or Laplace transform on the transient change of junction capacitance.

[0060] (Second Embodiment) Next, the configuration of the silicon carbide semiconductor device 200 according to the second embodiment will be described. The silicon carbide semiconductor device 200 according to the second embodiment differs from the silicon carbide semiconductor device 200 according to the first embodiment in that the shape of the trench 5 is U-shaped, but the other configurations are the same as those of the silicon carbide semiconductor device 200 according to the first embodiment. The following description will focus on the configurations that differ from the silicon carbide semiconductor device 200 according to the first embodiment.

[0061] Figure 4 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device 200 according to the second embodiment. As shown in Figure 4, in a cross-section perpendicular to the first main surface 1, the shape of the trench 5 is U-shaped. Specifically, the trench 5 has a side surface 3 and a bottom surface 4. The angle θ between the first main surface 1 and the side surface 3 is 90°. The side surface 3 extends almost perpendicular to the first main surface 1. The bottom surface 4 extends almost parallel to the first main surface 1. The boundary between the side surface 3 and the bottom surface 4 may be rounded.

[0062] (Third embodiment) Next, the configuration of the silicon carbide semiconductor device 200 according to the third embodiment will be described. The silicon carbide semiconductor device 200 according to the third embodiment differs from the silicon carbide semiconductor device 200 according to the first embodiment in that it has a planar configuration, but the other configurations are the same as those of the silicon carbide semiconductor device 200 according to the first embodiment. The following description will focus on the configurations that differ from the silicon carbide semiconductor device 200 according to the first embodiment.

[0063] Figure 5 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device 200 according to the third embodiment. As shown in Figure 5, the silicon carbide semiconductor device 200 according to the third embodiment is of the planar type. The gate insulating film 51 is provided on the first main surface 1. The gate insulating film 51 may be in contact with each of the third impurity region 30, the second portion 42, and the current spreading region 14 on the first main surface 1. The second portion 42 may constitute a part of the first main surface 1. The current spreading region 14 may constitute a part of the first main surface 1. The gate electrode 63 may face each of the third impurity region 30, the second portion 42, and the current spreading region 14.

[0064] (Manufacturing method for silicon carbide semiconductor devices) Next, a method for manufacturing a silicon carbide semiconductor device according to this embodiment will be described.

[0065] As shown in Figure 6, the manufacturing method of the silicon carbide semiconductor device 200 according to this embodiment mainly comprises a step of preparing a silicon carbide substrate (S10: Figure 6), a step of forming a first electrode (S20: Figure 6), and a step of forming a second electrode (S30: Figure 6). As shown in Figure 7, the step of preparing a silicon carbide substrate (S10: Figure 6) mainly comprises a step of preparing a silicon carbide single crystal substrate (S11: Figure 7), a step of forming a second region (S12: Figure 7), and an activation annealing step (S13: Figure 7).

[0066] First, a step (S11: Figure 7) is performed to prepare a silicon carbide single crystal substrate. For example, a silicon carbide ingot (not shown) manufactured by sublimation is sliced ​​to prepare a silicon carbide single crystal substrate 15. As shown in Figure 8, the silicon carbide single crystal substrate 15 has a third principal surface 6 and a second principal surface 2. The second principal surface 2 is on the opposite side of the third principal surface 6. The polytype of silicon carbide constituting the silicon carbide single crystal substrate 15 is, for example, 4H. The polytype may also be 6H, 15R, or 3C. 6H is hexagonal. 15H is rhombohedral. 3C is cubic.

[0067] Next, a buffer layer 11 is formed. For example, a buffer layer 11 is formed on a silicon carbide single crystal substrate 15 by a CVD (Chemical Vapor Deposition) method using a mixed gas of silane (SiH4) and propane (C3H8) as the raw material gas and hydrogen (H2) as the carrier gas (see Figure 9). During epitaxial growth, n-type impurities such as nitrogen are introduced into the buffer layer 11.

[0068] Next, a step to form the second region 22 (S12: Figure 7) is carried out. For example, a mixed gas of silane and propane is used as the raw material gas, and hydrogen is used as the carrier gas by a CVD method to form the first epitaxial layer 70 on the buffer layer 11 (see Figure 10). During epitaxial growth, n-type impurities such as nitrogen are introduced into the first epitaxial layer 70. The first epitaxial layer 70 has an n-type conductivity. The concentration of n-type impurities in the first epitaxial layer 70 may be lower than the concentration of n-type impurities in the buffer layer 11.

[0069] Next, a mask layer (not shown) having an opening is formed on the first epitaxial layer 70. Then, p-type impurity ions capable of imparting p-type properties, such as aluminum ions, are implanted into the first epitaxial layer 70. This forms the first p-type region 251 (see Figure 11). In the first epitaxial layer 70, the region where the first p-type region 251 is not formed becomes the first n-type region 121. The first p-type region 251 is in contact with the first n-type region 121. The first p-type region 251 becomes part of the second region 22.

[0070] Next, the second epitaxial layer 71 is formed. For example, the second epitaxial layer 71 is formed on the first epitaxial layer 70 by a CVD method using a mixed gas of silane and propane as the raw material gas and hydrogen as the carrier gas (see Figure 12). During epitaxial growth, n-type impurities such as nitrogen are introduced into the second epitaxial layer 71. The second epitaxial layer 71 has an n-type conductivity.

[0071] Next, a step of implanting p-type impurity ions is performed. For example, a mask layer (not shown) having an opening is formed on the second epitaxial layer 71. Then, p-type impurity ions capable of imparting p-type properties, such as aluminum ions, are implanted into the second epitaxial layer 71. This forms a second p-type region 252. The second p-type region 252 is formed to connect with the first p-type region 251 (see Figure 13). The second p-type region 252 becomes part of the second region 22. In the second epitaxial layer 71, the region where the second p-type region 252 is not formed becomes the second n-type region 122.

[0072] As described above, the process of forming an n-type epitaxial layer and the process of ion implanting p-type impurities are performed alternately. This forms a superjunction structure having a first superjunction region 12 and a second superjunction region 25. A first joint region 13, a second joint region 24, a third joint region 23, and a current spreading region 14 are formed by a similar method.

[0073] The second superjunction region 25, the second joint region 24, and the third joint region 23 constitute the second region 22. The second region 22 is formed by ion implantation. The impurity concentration of the second region 22 is 6 × 10⁻⁶. 16 cm -3 That concludes the explanation. Specifically, the second superjunction region 25 is formed by ion implantation. The second joint region 24 may also be formed by ion implantation. The third joint region 23 may also be formed by ion implantation. By forming p-type impurities by ion implantation, the point defect density of the second region 22 is increased.

[0074] Next, an n-type epitaxial layer is formed on the current spreading region 14 and the third joint region 23. For the n-type epitaxial layer, p-type impurity ions that can impart p-type properties, such as aluminum ions, are implanted into the entire surface of the n-type epitaxial layer. This forms the second portion 42 of the first region 21.

[0075] The current spreading region 14, the first joint region 13, and the first superjunction region 12 constitute the first impurity region 10. The first impurity region 10 is formed by epitaxial growth, for example, under temperature conditions of 1500°C to 1750°C. The temperature for epitaxial growth of the first impurity region 10 may be, for example, 1550°C or higher, or 1600°C or higher. The temperature for epitaxial growth of the first impurity region 10 may be, for example, 1725°C or lower, or 1700°C or lower. Performing epitaxial growth at high temperatures increases the point defect density of the second region 22.

[0076] Next, n-type impurities, such as phosphorus (P), are ion-implanted into the entire surface of the epitaxial layer. This forms a third impurity region 30. Next, a mask layer (not shown) having an opening is formed on the region where the first portion 41 of the first region 21 is formed. Next, p-type impurity ions, such as aluminum ions, which can impart p-type properties, are implanted into the third impurity region 30. This forms a first portion 41 that is in contact with the third impurity region 30. Thus, a first region 21 having a first portion 41 and a second portion 42 is formed. The first region 21 may be formed by ion implantation. Specifically, the first portion 41 may be formed by ion implantation. Similarly, the second portion 42 may be formed by ion implantation.

[0077] Next, an activation annealing process (S13: Figure 7) is performed. The activation annealing process may be carried out at a temperature of 1600°C to 1850°C. The temperature of the activation annealing process may be 1650°C or higher, or 1700°C or higher. The temperature of the activation annealing process may be 1800°C or lower, or 1750°C or lower. Performing activation annealing at a high temperature increases the point defect density of the second region 22. The activation annealing time is, for example, about 30 minutes. The atmosphere for activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

[0078] As described above, the silicon carbide substrate 100 is prepared. The silicon carbide substrate 100 has a first main surface 1, a second main surface 2, a first impurity region 10, a second impurity region 20, and a third impurity region 30. The second main surface 2 is on the opposite side from the first main surface 1. The first impurity region 10 constitutes at least a part of the second main surface 2 and has a first conductivity type. The second impurity region 20 constitutes at least a part of the first main surface 1, is provided in contact with the first impurity region 10, and has a second conductivity type different from the first conductivity type. The third impurity region 30 is provided in contact with the second impurity region 20 so as to be separated from the first impurity region 10, and has a first conductivity type. The second impurity region 20 includes a first region 21 and a second region 22. The second region 22 is located between the first region 21 and the second main surface 2 and is in contact with the first region 21 (see Figure 14).

[0079] Next, a step of forming the trench 5 is carried out. For example, a mask (not shown) is formed on the first main surface 1, which consists of a third impurity region 30 and a first portion 41. Using the mask, a portion of the third impurity region 30, a portion of the second portion 42, and a portion of the current spreading region 14 are removed by etching. As an etching method, for example, reactive ion etching, in particular inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF6) or a mixed gas of SF6 and oxygen (O2) as the reaction gas can be used. By etching, a recess is formed in the region where the trench 5 is to be formed, having a side portion that is substantially perpendicular to the first main surface 1 and a bottom portion that is continuous with the side portion and substantially parallel to the first main surface 1.

[0080] Next, thermal etching is performed in the recesses. Thermal etching can be performed by heating in an atmosphere containing a reactive gas having at least one type of halogen atom, with a mask formed on the first main surface 1. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere may contain, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, a mixed gas of chlorine gas and oxygen gas may be used as the reaction gas, and thermal etching may be performed at a heat treatment temperature of, for example, 800°C to 900°C. The reaction gas may also contain a carrier gas in addition to the chlorine gas and oxygen gas mentioned above. As the carrier gas, for example, nitrogen gas, argon gas, or helium gas can be used.

[0081] The above thermal etching forms a trench 5 on the first main surface 1 of the silicon carbide substrate 100 (see Figure 15). The trench 5 has a side surface 3 and a bottom surface 4. The side surface 3 is composed of a third impurity region 30, a second portion 42, and a current spreading region 14. The bottom surface 4 is composed of the current spreading region 14. The angle θ between the first main surface 1 and the side surface 3 is, for example, 115° to 135°. Next, the mask is removed from the first main surface 1.

[0082] Next, a step of forming the gate insulating film 51 is carried out. For example, by thermal oxidation of the silicon carbide substrate 100, a gate insulating film 51 is formed that is in contact with the third impurity region 30, the second portion 42, the current spreading region 14, and the first portion 41. Specifically, the silicon carbide substrate 100 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300°C to 1400°C. This forms the gate insulating film 51 that is in contact with the first main surface 1, the side surface 3, and the bottom surface 4.

[0083] Next, the silicon carbide substrate 100 may be subjected to heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In NO annealing, the silicon carbide substrate 100 is held for about 1 hour under conditions of, for example, 1100°C to 1400°C. This introduces nitrogen atoms into the interface region between the gate insulating film 51 and the second portion 42. As a result, the formation of interface states in the interface region is suppressed, thereby improving channel mobility.

[0084] After NO annealing, Ar annealing may be performed using argon (Ar) as the ambient gas. The heating temperature for Ar annealing is, for example, higher than the heating temperature for NO annealing. The Ar annealing time is, for example, about 1 hour. This further suppresses the formation of interface states in the interface region between the gate insulating film 51 and the second portion 42. Note that other inert gases such as nitrogen gas may be used as the ambient gas instead of Ar gas.

[0085] Next, a step is performed to form the gate electrode 63. The gate electrode 63 is formed on the gate insulating film 51. The gate electrode 63 is formed, for example, by the LP-CVD (Low Pressure Chemical Vapor Deposition) method. The gate electrode 63 is formed so as to face the third impurity region 30, the second portion 42, and the current spreading region 14, respectively.

[0086] Next, a process for forming the isolation insulating film 52 is carried out. Specifically, the isolation insulating film 52 is formed to cover the gate electrode 63 and to be in contact with the gate insulating film 51. The isolation insulating film 52 is formed, for example, by the CVD method. The isolation insulating film 52 is made of a material containing, for example, silicon dioxide. A portion of the isolation insulating film 52 may be formed inside the trench 5.

[0087] Next, a step to form the first electrode (S20: Figure 6) is performed. For example, etching is performed so that an opening is formed in the separation insulating film 52 and the gate insulating film 51, thereby exposing the third impurity region 30 and the first portion 41 from the separation insulating film 52 and the gate insulating film 51 at the opening. Next, an electrode layer 60 is formed on the first main surface 1 that is in contact with the third impurity region 30 and the first portion 41. The electrode layer 60 is formed, for example, by a sputtering method. The electrode layer 60 is composed of a material containing, for example, Ti, Al, and Si.

[0088] Next, alloying annealing is performed. The electrode layer 60 in contact with the third impurity region 30 and the first portion 41 is held at a temperature of, for example, 900°C to 1100°C for about 5 minutes. As a result, at least a portion of the electrode layer 60 reacts with the silicon contained in the silicon carbide substrate 100 and becomes silicided. This forms an electrode layer 60 that is ohmic bonded with the third impurity region 30. The electrode layer 60 may also be ohmic bonded with the first portion 41. As a result, a first electrode 61 is formed on the first main surface 1, in contact with the second impurity region 20 and the third impurity region 30, respectively.

[0089] Next, a step to form the second electrode (S30: Figure 6) is performed. For example, the second electrode 62 is formed on the second main surface 2 by sputtering. The second electrode 62 is, for example, a drain electrode. The second electrode 62 is in contact with the first impurity region 10 on the second main surface 2. The second electrode 62 is made of a material containing, for example, NiSi or TiAlSi. With the above steps, the MOSFET 200 (Figure 1) according to the first embodiment is completed.

[0090] In the above description, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, p-type impurities are to be read as n-type impurities and n-type impurities are to be read as p-type impurities. Also, in the above description, a MOSFET was used as an example to explain the silicon carbide semiconductor device 200 according to this disclosure, but the silicon carbide semiconductor device 200 according to this disclosure is not limited to a MOSFET. The silicon carbide semiconductor device 200 according to this disclosure may be, for example, a PN diode, an IGBT (Insulated Gate Bipolar Transistor), etc. [Examples]

[0091] (Sample preparation) Next, the embodiments will be described. First, a silicon carbide semiconductor device 200 according to Sample 1 and a silicon carbide semiconductor device 200 according to Sample 2 were prepared. The silicon carbide semiconductor device 200 according to Sample 1 was a V-type trench MOSFET having a superjunction structure. Specifically, the silicon carbide semiconductor device 200 according to Sample 1 was a V-type trench MOSFET according to the first embodiment. In the silicon carbide semiconductor device 200 according to Sample 1, the concentration of p-type impurities in the second superjunction region 25 was 1 × 10⁻⁶ 17 cm -3 And the concentration of p-type impurities in the channel region (second part 42) is 2 × 10 18 cm -3 The silicon carbide semiconductor device 200 related to Sample 1 had a characteristic on-resistance of 0.63 mΩcm. 2 The breakdown voltage was 1170V. The silicon carbide semiconductor device 200 for Sample 2 was a V-type trench MOSFET without a superjunction structure. In the silicon carbide semiconductor device 200 for Sample 2, the concentration of p-type impurities in the channel region (second part 42) was 1 × 10⁻⁶ 16 cm -3 That's what I decided.

[0092] (Evaluation method) Next, the diode characteristics between the drain electrode (second electrode 62) and the source electrode (first electrode 61) were measured. Specifically, the drain current density was measured while varying the drain voltage under several temperature conditions. For the silicon carbide semiconductor device 200 of Sample 1, the temperature conditions were 25°C, 50°C, 75°C, 100°C, 125°C, 150°C, and 175°C. For the silicon carbide semiconductor device 200 of Sample 2, the temperature conditions were 25°C, 93°C, 122°C, and 162°C.

[0093] (Evaluation results) Figure 16 shows the relationship between drain current density and drain voltage in the silicon carbide semiconductor device 200 of Sample 1. Figure 17 shows the relationship between drain current density and drain voltage in the silicon carbide semiconductor device 200 of Sample 2. As shown in Figure 17, in the silicon carbide semiconductor device 200 of Sample 2, the slope of drain current density with respect to drain voltage increased as the temperature rose. On the other hand, as shown in Figure 16, in the silicon carbide semiconductor device 200 of Sample 1, the slope of drain current density with respect to drain voltage did not change much even when the temperature rose. In other words, it was confirmed that the silicon carbide semiconductor device 200 of Sample 1 can suppress temperature changes in diode characteristics compared to the silicon carbide semiconductor device 200 of Sample 2.

[0094] Furthermore, basal plane dislocations present in the silicon carbide substrate 100 can become stacking faults due to the energy of recombination between minority carriers. If stacking faults are present in the silicon carbide semiconductor device 200, the breakdown voltage of the silicon carbide semiconductor device 200 will decrease significantly. To prevent recombination between minority carriers, it is desirable to reduce the number of minority carriers. The fact that the temperature change of the diode characteristics is small (i.e., the temperature change of the resistance is small), as in the silicon carbide semiconductor device 200 of Sample 1, means that conductivity modulation is hardly occurring. Therefore, it is considered that the silicon carbide semiconductor device 200 of Sample 1 has a very small number of minority carriers. Consequently, in a silicon carbide semiconductor device 200 like the one of Sample 1, the secondary effect of suppressing the occurrence of stacking faults and suppressing the decrease in breakdown voltage can be expected.

[0095] The embodiments and examples disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the claims rather than by the foregoing description, and all modifications within the scope of the claims are intended to be included in the meaning of equivalents and within the scope. [Explanation of symbols]

[0096] 1 First main surface, 2 Second main surface, 3 Side surface, 4 Bottom surface, 5 Trench, 6 Third main surface, 7 First defect, 8 Second defect, 9 Point defect, 10 First impurity region, 11 Buffer layer, 12 First superjunction region, 13 First joint region, 14 Current spreading region, 15 Single crystal substrate, 20 Second impurity region, 21 First region, 22 Second region, 23 Third joint region, 24 Second joint region, 25 Second superjunction region, 30 Third impurity region, 41 First part, 42 Second part, 51 Gate insulating film, 52 Separation insulating film, 60 Electrode layer, 61 First electrode, 62 Second electrode, 63 Gate electrode, 64 Wiring layer, 70 First epitaxial layer, 71 Second epitaxial layer, 100 Silicon carbide substrate, 101 First direction, 102 Second direction, 103 3rd direction, 121 first n-type region, 122 second n-type region, 200 silicon carbide semiconductor device (MOSFET), 251 first p-type region, 252 second p-type region.

Claims

1. A silicon carbide substrate having a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface and provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be separated from the first impurity region and having the first conductivity type, A first electrode in the first main surface that is in contact with the second impurity region and the third impurity region, The second main surface comprises a second electrode in contact with the first impurity region, The second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region. The impurity concentration in the first region is 6 × 10 16 cm -3 That's all. A silicon carbide semiconductor device wherein, when the forward characteristics of the body diode between the second electrode and the first electrode are measured under temperature conditions from 25°C to 175°C, the slope of the drain current density with respect to the drain voltage decreases as the temperature increases.

2. The impurity concentration in the second region is 6 × 10 16 cm -3 The silicon carbide semiconductor device described in claim 1 is as described above.

3. A silicon carbide substrate having a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface and provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be separated from the first impurity region and having the first conductivity type, A first electrode in the first main surface that is in contact with the second impurity region and the third impurity region, The second main surface comprises a second electrode in contact with the first impurity region, The second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region. The point defect density in the second region is 6 × 10 12 cm -3 That's all. A silicon carbide semiconductor device wherein, when the forward characteristics of the body diode between the second electrode and the first electrode are measured under temperature conditions from 25°C to 175°C, the slope of the drain current density with respect to the drain voltage decreases as the temperature increases.

4. The point defect density in the second region is 1 × 10⁻⁶ 14 cm -3 The silicon carbide semiconductor device according to claim 3, which is as follows:

5. The silicon carbide semiconductor device is of the planar type, as described in any one of claims 1 to 4.

6. The silicon carbide substrate is provided with trenches. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the trench has a side surface that is in contact with each of the first impurity region, the second impurity region, and the third impurity region, and a bottom surface that is continuous with the side surface and is in contact with the first impurity region.

7. The silicon carbide semiconductor device according to claim 6, wherein the shape of the trench in a cross section perpendicular to the first main surface is U-shaped.

8. The silicon carbide semiconductor device according to claim 6, wherein the shape of the trench in a cross section perpendicular to the first main surface is V-shaped.

9. The silicon carbide semiconductor device according to any one of claims 1 to 8, wherein the first main surface is the (000-1) surface or a surface inclined at an angle of 8° or less with respect to the (000-1) surface.

10. The silicon carbide semiconductor device according to any one of claims 1 to 9, wherein the impurity concentration in the first region is higher than the impurity concentration in the second region.

11. The impurity concentration of the first region is 1 × 10 19 cm -3 or less. The silicon carbide semiconductor device according to claim 10.

12. When the temperature rises from 25°C to 175°C, the change in the slope of the drain current density with respect to the drain voltage is 20 A / cm². 2 A silicon carbide semiconductor device according to any one of claims 1 to 11, wherein the xV is less than or equal to ×V.

13. A step of preparing a silicon carbide substrate having a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface and provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region so as to be separated from the first impurity region and having a first conductivity type, A step of forming a first electrode in the first main surface that is in contact with the second impurity region and the third impurity region, The process includes the step of forming a second electrode in contact with the first impurity region on the second main surface, The second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region. The impurity concentration in the first region is 6 × 10 16 cm -3 That's all. The first region is formed by ion implantation, A method for manufacturing a silicon carbide semiconductor device, wherein, when the forward characteristics of the body diode between the second electrode and the first electrode are measured under temperature conditions from 25°C to 175°C, the slope of the drain current density with respect to the drain voltage decreases as the temperature increases.

14. The method for manufacturing a silicon carbide semiconductor device according to claim 13, wherein the second region is formed by ion implantation.

15. The method for manufacturing a silicon carbide semiconductor device according to claim 13 or claim 14, wherein the first impurity region is formed by epitaxial growth under temperature conditions of 1500°C to 1750°C.

16. The process of preparing the silicon carbide substrate includes an activation annealing step, The method for manufacturing a silicon carbide semiconductor device according to any one of claims 13 to 15, wherein the activation annealing step is performed under temperature conditions of 1600°C to 1850°C.

17. When the temperature rises from 25°C to 175°C, the change in the slope of the drain current density with respect to the drain voltage is 20 A / cm². 2 A method for manufacturing a silicon carbide semiconductor device according to any one of claims 13 to 16, wherein the xV is less than or equal to ×V.

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