Charge pump circuit, chip, and communication terminal

Abstract

A charge pump circuit, a chip, and a communication terminal are provided. [Solution] The charge pump circuit includes a phase clock generation module, an acceleration response control module, and multiple sub-charge pump modules. The phase clock generation module generates multiple clock signals with a certain phase difference, and controls the multiple sub-charge pump modules to generate output voltages accordingly. The acceleration response control module detects the output voltage of each sub-charge pump module and outputs logic signals to the phase clock generation module and each sub-charge pump module, respectively, to change the frequency of the clock signal output by the phase clock generation module, thereby shortening the charging and discharging time of the capacitance in each sub-charge pump module. This effectively reduces the peak current drawn by the charge pump circuit from the input power supply and reduces ripple interference generated by the charge pump circuit in the input power supply and output voltage signals.

Description

Technical Field

[0001] The present invention relates to a charge pump circuit, an integrated circuit chip including the charge pump circuit, and a corresponding communication terminal, and belongs to the field of analog integrated circuits.

Background Art

[0002] Conventional charge pump circuits rely on an external power supply that can be realized using a low dropout linear regulator or a DC-DC power supply. As shown in FIG. 1, when using a low dropout linear regulator to supply power to a charge pump circuit and a high-precision circuit simultaneously, due to the characteristics of the charge pump circuit itself, a large transient peak current often accompanies the switching of its internal switch. If this peak current is too large, it will not only affect the power supply stability of the power supply system but also the accuracy of other high-precision circuits. For example, it will affect the effective bit number of a high-precision digital-to-analog converter and the output offset voltage of a precision operational amplifier.

[0003] With the increasing high integration of integrated circuits, the integration of charge pump circuits into chips is progressing more and more. However, since the charge pump circuit has high requirements for the power supply, in order to reduce the ripple interference of the power supply in the charge pump circuit, it is common to add an off-chip capacitor to its power port. This not only increases the cost of the power supply system but also means a decrease in the overall reliability of the system.

[0004] Chinese invention patent ZL201810049855.1 discloses a charge pump circuit. The operating principle of this circuit is to divide the charge pump into N stages of sub-charge pump circuits, then use delays to sequentially delay the clock signal, providing a clock signal corresponding to the N stages of sub-charge pumps, and detect the magnitude of the charge pump output voltage ripple through a control unit, adjusting the delay to reduce the charge pump output voltage ripple. However, in order to reduce the voltage ripple output from the charge pump circuit, the number of sub-charge pump circuits increases, which not only complicates the circuit but also increases the peak current of the input power supply. [Overview of the project] [Problems that the invention aims to solve]

[0005] The main technical problem that this invention aims to solve is to provide a charge pump circuit.

[0006] Another technical problem that the present invention aims to solve is to provide an integrated circuit chip and a communication terminal equipped with the above-described charge pump circuit.

[0007] To achieve the above objective, the present invention employs the following technical approach.

[0008] According to a first embodiment of the present invention, a charge pump circuit is provided comprising a phase clock generation module, an acceleration response control module, and a plurality of subcharge pump modules. multiple Output terminal each teeth, handle The clock control terminal of each of the plurality of subcharge pump modules is connected, the plurality of subcharge pump modules are connected in parallel and the input power terminal and output voltage terminal are connected, the output voltage terminal is connected to the input terminal of the acceleration response control module, and the output terminal of the acceleration response control module is connected to the input terminal of the phase clock generation module and each of the plurality of subcharge pump modules.

[0009] The aforementioned phase clock generation module is The system comprises multiple phase clock subcircuits and a first inverter, each of which consists of a first NMOS transistor, a first capacitor, a second capacitor, an output node, and a second inverter, the second inverter comprising a first PMOS transistor and a second NMOS transistor, the gates and drains of the first PMOS transistor and the second NMOS transistor being connected to each other, the source of the first PMOS transistor being connected to the power supply, and the source of the second NMOS transistor being grounded. .

[0010] The input terminal of the first inverter is connected to the output terminal of the acceleration response control module, and the plurality of phase clock subcircuits The output terminal of the first inverter is the first NMOS transistor Each gate is connected to the first NMOS transistor Each drain and The aforementioned Output node each Between them is the first capacity each Connected in series, the first NMOS transistor Each source is grounded, and the output node each is the corresponding The aforementioned multiple Subcharge pump module each It is connected to the output node each and Grand to Between them is the second capacity Each Connected in series, each of the second inverters is Ka Scade connection, The output terminal of the final stage second inverter among these cascaded second inverters and the input terminal of the first stage second inverter These are connected to form a ring oscillator.

[0011] The phase clock generation module generates multiple clock signals having a constant phase difference using the ring oscillator and controls the multiple subcharge pump modules to generate an output voltage. The acceleration response control module detects the output voltage and outputs a logic signal corresponding to the detection result to the phase clock generation module and each of the multiple subcharge pump modules. If the state of the logic signal indicates that the output voltage has not reached the target value, the phase clock generation module changes the oscillation frequency of the ring oscillator to generate an acceleration clock signal and controls each of the multiple subcharge pump modules to rapidly generate the output voltage based on the acceleration clock signal and the logic signal. If the state of the logic signal indicates that the output voltage has reached the target value, the phase clock generation module reduces the frequency of the clock signal output to each of the multiple subcharge pump modules and controls each of the multiple subcharge pump modules to maintain a normal output voltage based on the clock signal and the logic signal and suppress ripple generated in the output voltage. .

[0012] The aforementioned phase clock generation module This is the acceleration response control module twist Output to the aforementioned phase clock generation module The above Based on the state of the logic signal, the phase clock generation module Each of the above multiple output terminals By changing the magnitude of the load capacity in By , having a constant phase difference generated by the ring oscillator The aforementioned Adjust the amplitude of the oscillation frequencies of multiple clock signals.

[0013] Preferably, the acceleration response control module twist Output to the aforementioned phase clock generation module The aforementioned Based on the state of the logic signal, the second inverter Constitutes Each switching transistor By changing the aspect ratio of Further means of making changes

[0014] In order to make it possible Preferably, each of the plurality of sub - charge pump modules supplies a voltage output higher than the input power supply In order to make it possible and the sub - charge pump module includes a third NMOS transistor a fourth NMOS transistor a second PMOS transistor a third PMOS transistor a fourth PMOS transistor a fifth PMOS transistor a first selection switch, a second selection switch, a third selection switch, a fourth selection switch, and a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and an eighth capacitor. Each of the selection switches comprises two stationary ends and one movable end that is selectively connected to either of these two stationary ends, as well as a clock control end that receives the clock signal output from the phase clock generation module and a response control end that receives the logic signal output from the acceleration response control module. The substrate terminal and source of the third NMOS transistor and the substrate terminal and source of the fourth NMOS transistor are respectively connected to the input power supply, and the gate of the third NMOS transistor is respectively connected to the drain of the fourth NMOS transistor one plate of the fourth capacitor, and the drain of the second PMOS transistor The drain of the third NMOS transistor is respectively connected to the gate of the fourth NMOS transistor one plate of the third capacitor, and the drain of the third PMOS transistor The substrate terminal and source of the second PMOS transistor the substrate terminal and source of the third PMOS transistor the substrate terminal and source of the fourth PMOS transistor and the substrate terminal and source of the fifth PMOS transistor are respectively connected to the output voltage terminal and one end of the eighth capacitor, the other end of the eighth capacitor is grounded, and the gate of the second PMOS transistor is one plate of the sixth capacitor, the fourth PMOS transistor The drain and the fifth PMOS transistor Each of the gates is connected to the third PMOS transistor The gate of the fifth capacitor is one of the plates of the fifth PMOS transistor The drain and the fourth PMOS transistor Each is connected to the gate, and the other plates of the third capacitance, the fourth capacitance, the fifth capacitance and the sixth capacitance are, These capacities handle The aforementioned Selection switch The aforementioned It is connected to a movable end, and the movable end is The aforementioned selection switch Each The aforementioned Connected to the clock control terminal, these The clock control terminal of the phase clock generation module A specific one output terminal out of the aforementioned plurality of output terminals Connected to the selection switch In each case , The two stationary ends One stationary end is connected to the power supply, and the other stationary end is connected to ground, and the selection switch each of The aforementioned The response control terminal is connected to the output terminal of the acceleration response control module, and the input terminal of the acceleration response control module is connected to the output voltage terminal.

[0015] Preferably, the phase clock generation module From each of the plurality of output terminals of the plurality clock signal By outputting a time-division first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, , The aforementioned Selection switch each on / off Fu control So , The aforementioned The first clock signal and The aforementioned The third clock signal, The aforementioned The second clock signal and The aforementioned The fourth clock signal is The rising and falling edges of these signals Non-overlapping clock signals That The non-overlapping time is Tnov1, and the first clock signal and the second clock signal, the third clock signal and the fourth clock signal are The rising and falling edges of those signals Non-overlapping clock signals ThatThese non-overlapping time periods are Tnov3 and Tnov2, respectively, and these non-overlapping time periods satisfy the relationship Tnov2 = 2 * Tnov1 + Tnov3.

[0016] Preferably, each of the multiple subcharge pump modules supplies a voltage output below the ground voltage. In order to make it possible , the third NMOS in the subcharge pump module transistor and the aforementioned fourth NMOS transistor , The 6th PMOS transistor and the 7th PMOS transistor Replacement picture, The second PMOS transistor , the third PMOS transistor , the fourth PMOS transistor and the fifth PMOS The transistors are converted to a 5th NMOS transistor, a 6th NMOS transistor, a 9th NMOS transistor, and a 10th NMOS transistor. Replacement El .

[0017] Preferably, each of the selection switches is a 10th PMOS transistor , the 7th NMOS transistor , OR gate, AND gate, third inverter and at least one 11th PMOS transistor and at least one eighth NMOS transistor It is equipped with. In each of the aforementioned selection switches, The 10th PMOS Transistors and The seventh NMOS transistor gate Allies The phase clock generation module Each of the aforementioned plurality of output terminals For connecting The aforementioned The 10th PMOS is connected to function as a clock control terminal. Transistors and The seventh NMOS transistor The gate is the OR gate and the aforementioned AND One side of each gate Input terminal to The 10th PMOS Transistors and The seventh NMOS transistor drain and the above 11th PMOS Transistors and handle The aforementioned 8th NMOS transistor drain TogaThey are connected to each other, and are selector switches. Each handle The aforementioned Capacity The aforementioned others direction Connect the plates Functions as the movable end for the purpose of The 10th PMOS transistor and The aforementioned 11th PMOS transistor Each source is connected to a power supply, and the seventh NMOS transistor and The aforementioned 8th NMOS transistor Each source is grounded. The aforementioned 11th PMOS transistor The gate is the OR gate It is connected to the output terminal, The aforementioned 8th NMOS transistor The gate is the AND gate. gate It is connected to the output terminal of the OR gate In addition direction The input terminal of is connected to the output terminal of the third inverter, and the AND gate In addition direction The input terminal of the third inverter is connected to the input terminal of the acceleration response control module and the output terminal of the acceleration response control module.

[0018] Preferably, the acceleration response control module comprises a first resistor, a second resistor, and a hysteresis comparator. One end of the first resistor is connected to the multiple Each is connected to the output voltage terminal of the subcharge pump module, the other end of the first resistor is connected to one end of the second resistor and the inverting input terminal of the hysteresis comparator, the other end of the second resistor is grounded, the positive-sequence input terminal of the hysteresis comparator is connected to a reference voltage, and the output terminal of the hysteresis comparator is connected to the input terminal of the first inverter and the multiple In the subcharge pump module The aforementioned They are connected to the input terminals of the third inverter.

[0019] A second embodiment of the present invention provides an integrated circuit chip equipped with the above-described charge pump circuit.

[0020] A third embodiment of the present invention provides a communication terminal equipped with the above-described charge pump circuit. [Effects of the Invention]

[0021] The charge pump circuit provided by the embodiment of the present invention controls multiple sub-charge pump modules to generate output voltages by generating multiple clock signals with a constant phase difference in a phase clock generation module. Furthermore, the acceleration response control module detects the output voltage of each sub-charge pump module and outputs logic signals to the phase clock generation module and each sub-charge pump module, respectively, thereby changing the frequency of the clock signal output by the phase clock generation module and shortening the charge and discharge time of the capacitance in each sub-charge pump module. The present invention effectively reduces the peak current drawn by the charge pump circuit from the input power supply and mitigates ripple interference generated in the input power supply and output voltage signals by the charge pump circuit, thereby reducing the input power supply's dependence on off-chip capacitors. [Brief explanation of the drawing]

[0022] [Figure 1] This is a typical application block diagram of a conventional charge pump circuit. [Figure 2] This is a block diagram showing the configuration of a charge pump circuit provided by an embodiment of the present invention. [Figure 3] This is a circuit diagram of the phase clock generation module in a charge pump circuit provided by an embodiment of the present invention. [Figure 4] This is a circuit diagram illustrating the principle of each sub-charge pump module in a charge pump circuit provided according to an embodiment of the present invention. [Figure 5] This is a schematic diagram showing the timing of a charge pump circuit provided by an embodiment of the present invention. [Figure 6]This is a diagram illustrating the principle of another circuit for each sub-charge pump module in a charge pump circuit provided by an embodiment of the present invention. [Figure 7] This is a circuit diagram illustrating the principle of the selection switch for each sub-charge pump module in a charge pump circuit provided according to an embodiment of the present invention. [Figure 8] This is a circuit diagram of the acceleration response control module in a charge pump circuit provided by an embodiment of the present invention. [Modes for carrying out the invention]

[0023] The technical details of the present invention will be described in more detail below with reference to the attached drawings and specific embodiments.

[0024] The objective is to generate a stable and high-speed charge pump output voltage in order to reduce the large ripple interference and noise that the charge pump circuit imposes on the input power supply, reduce the input power supply's reliance on off-chip capacitors, lower the cost of the power supply system, and improve system reliability. As shown in Figure 2, embodiments of the present invention first include a phase clock generation module 101, an acceleration response control module 105, and a plurality of sub-charge pump modules (for example, Figure 2 The present invention provides a charge pump circuit consisting of multiple subcharge pump modules (102, 103, 104, etc.) as shown. The output terminal of the phase clock generation module 101 is connected to the clock control terminal of each subcharge pump module, and multiple subcharge pump modules are connected in parallel, corresponding to the input power terminal VIN and the output voltage terminal VOUT. The output voltage terminal VOUT is connected to the input terminal of the acceleration response control module 105, and the output terminal of the acceleration response control module 105 is connected to the input terminals of the phase clock generation module 101 and each subcharge pump module.

[0025] The phase clock generation module 101 generates multiple clock signals with a constant phase difference to control the output voltages generated by the multiple subcharge pump modules. The acceleration response control module 105 detects the output voltage of each subcharge pump module and outputs logic signals to the phase clock generation module 101 and each subcharge pump module, respectively. Therefore, if the output voltages of the multiple subcharge pump modules have not reached the target value, the phase clock generation module 101 generates an acceleration clock signal to control each subcharge pump module to quickly generate an output voltage. Furthermore, once the output voltages of the multiple subcharge pump modules have reached the target value, the phase clock generation module 101 controls each subcharge pump module to maintain a normal output voltage.

[0026] In other embodiments of the present invention, the phase differences may be 45 degrees, 60 degrees, 90 degrees, 120 degrees, or 180 degrees, and the number of corresponding sub-charge pump modules may be 8, 6, 4, 3, or 2, respectively. The number of sub-charge pump modules can be flexibly adjusted to ensure that the rising and falling edges of clock signals with a certain phase difference, received simultaneously by each sub-charge pump module, do not overlap. For example, for the three-way sub-charge pump modules 102, 103, and 104 shown in Figure 1, the corresponding phase difference is 360 degrees / 3 = 120 degrees.

[0027] As shown in Figure 3, the phase clock generation module 101 comprises a plurality of phase clock subcircuits consisting of a first NMOS tube (e.g., first NMOS tubes MN4 to MN6), a first capacitor (e.g., capacitors C11 to C31), a second capacitor (e.g., capacitors C1 to C3), an output node, and a second inverter 1010, as well as a first inverter INV1. Here, the input terminal of the first inverter INV1 is connected to the output terminal of the acceleration response control module 105, and the output terminal of the first inverter INV1 is connected to the gate of each first NMOS tube, respectively. The drains of each first NMOS tube and their corresponding output nodes (output nodes PH1, PH2, and PH3) are connected in series with a first capacitance. The sources of each first NMOS tube are grounded, and a subcharge pump module corresponding to each output node is connected. In addition, a second capacitance is connected in series between each output node and ground. Each second inverter 1010 is cascaded and connected to the power supply VDD, grounded, and then its ends are connected to form a ring oscillator. Here, the number of second inverters 1010 (which is similar to adjusting the number of subcharge pump modules and therefore omitted here) can be flexibly adjusted to ensure that the rising and falling edges of each clock signal with a constant phase difference generated by the second inverter 1010 do not overlap.

[0028] As shown in Figure 3, the phase clock generation module 101 generates a clock signal with a phase difference of 120 degrees, for example, between three phases. This phase clock generation module 101 comprises a first inverter INV1, three first NMOS tubes MN4 to MN6, three first capacitors C11 to C31, three second capacitors C1 to C3, three output nodes PH1, PH2 and PH3, and three second inverters 1010. Here, the input terminal of the first inverter INV1 is connected to the output terminal of the acceleration response control module 105, and the output terminal of the first inverter INV1 is connected to the gates of the three first NMOS tubes MN4 to MN6, respectively. A first capacitor C11 is connected in series between the first NMOS tube MN4 and output node PH1, a first capacitor C21 is connected in series between the first NMOS tube MN5 and output node PH2, and a first capacitor C31 is connected in series between the first NMOS tube MN6 and output node PH3. The sources of the three first NMOS tubes MN4 to MN6 are grounded, and the three output nodes PH1, PH2, and PH3 are connected to the corresponding subcharge pump modules. A second capacitor C1 is connected in series between output node PH1 and ground, a second capacitor C2 is connected in series between output node PH2 and ground, and a second capacitor C3 is connected in series between output node PH3 and ground. Each second inverter 1010 is cascaded and connected to the power supply VDD and ground accordingly, and then the ends are connected to form a ring oscillator.

[0029] Each second inverter comprises a first PMOS tube and a second NMOS tube, with the gates and drains of the first PMOS tube and the second NMOS tube connected in correspondence. The source of the first PMOS tube is connected to the power supply, and the source of the second NMOS tube is grounded. As shown in Figure 3, taking the case where the phase clock generation module 101 has three second inverters as an example, the first PMOS tube MP1 and the second NMOS tube MN1, the first PMOS tube MP2 and the second NMOS tube MN2, and the first PMOS tube MP3 and the second NMOS tube MN3 each constitute one stage of the second inverter, thereby obtaining three stages of the second inverter. Here, the ends of the cascaded second inverter are connected, meaning that the first PMOS tube MP3 in the third stage second inverter is connected to the drain of the second NMOS tube MN3, and then to the gates of the first PMOS tube MP1 and the second NMOS tube MN1 in the first stage second inverter.

[0030] Here, the output nodes PH1 to PH3 of the phase clock generation module 101 are the corresponding output nodes of the second inverter 1010, the first capacitors C11 to C31 and the second capacitors C1 to C3 are the load capacitances of each output node of the second inverter 1010, the gate voltages of the first NMOS tubes MN4 to MN6 are the outputs of the first inverter INV1, and the first inverter INV receives the logic signal output by the acceleration response control module 105. The oscillation frequency f of the ring oscillator consisting of the second inverter 1010 has the following relationship.

number

[0031] Here, R on This represents the equivalent resistance of the second inverter 1010, and C L This represents the load capacity of the output node of the second inverter 1010. When the logic signal fast_en output by the acceleration response control module 105 is at a high level, the gate voltages of the first NMOS tubes MN4 to MN6 become low, and the first NMOS tubes MN4 to MN6 enter an interrupted state. At this time, the load capacity of each output node of the second inverter 1010 is the second capacity C1 to C3, that is, the load capacity of output node PH1 is the second capacity C1, the load capacity of output node PH2 is the second capacity C2, and the load capacity of output node PH3 is the second capacity C3. When the logic signal fast_en output by the acceleration response control module 105 is at a low level, the gate voltages of the first NMOS tubes MN4 to MN6 become high, and the first NMOS tubes MN4 to MN6 are turned on. At this time, the load capacity of each output node of the second inverter 1010 is the second capacity C1 to C3 and the first capacity C11 to C31. That is, the load equivalent capacity of output node PH1 is the capacity of the second capacity C1 and the first capacity C11 connected in parallel, the load equivalent capacity of output node PH2 is the capacity of the second capacity C2 and the first capacity C21 connected in parallel, and the load equivalent capacity of output node PH3 is the capacity of the second capacity C3 and the first capacity C31 connected in parallel.

[0032] As can be seen from the above, when the logic signal output by the acceleration response control module 105 is at a high level compared to when the logic signal output by the acceleration response control module 105 is at a low level, the load capacity of each output node of the second inverter 1010 decreases, which increases the oscillation frequency of the clock signal output by the ring oscillator. If the output voltages of the multiple subcharge pump modules have not reached the target value, the phase clock generation module 101 generates an acceleration clock signal and controls each subcharge pump module to generate an output voltage quickly. Conversely, when the logic signal output by the acceleration response control module 105 is at a low level compared to when the logic signal output by the acceleration response control module 105 is at a high level, the load capacity of each output node of the second inverter 1010 increases, which reduces the oscillation frequency of the clock signal output by the ring oscillator. When the output voltages of the multiple subcharge pump modules reach the target value, the phase clock generation module 101 controls each subcharge pump module to maintain a normal output voltage.

[0033] Therefore, based on the state of the logic signal output by the acceleration response control module 105, the magnitude of the oscillation frequency of multiple clock signals with a constant phase difference generated by the ring oscillator is adjusted by changing the magnitude of the load capacity of the output node in each second inverter 1010. Based on the fact that the phase difference of the clock signal output by the phase clock generation module 101 is 120 degrees, not only is each subcharge pump module controlled to generate an output voltage, but at the same time, the input power supply reduces the number of charge capacities for each subcharge pump module. Therefore, each subcharge pump module simultaneously extracts current from the input power supply in a time-division manner, reducing the peak current drawn by each subcharge pump module from the input power supply and thereby reducing input power supply ripple caused by excessive peak current in the input power supply.

[0034] Furthermore, based on the state of the logic signal output by the acceleration response control module 105, the ratio of the width to the length (abbreviated as the aspect ratio) of the conductive channels of the switching tubes (i.e., the first PMOS tube and the second NMOS tube) in each second inverter 1010 is changed, thereby changing the equivalent resistance of the second inverter 1010 and adjusting the magnitude of the oscillation frequencies of multiple clock signals having a constant phase difference generated by the ring oscillator. However, this will not be explained in detail here.

[0035] When each subcharge pump module supplies a voltage output higher than the input power supply Vin, as shown in Figure 4, each subcharge pump module comprises a third NMOS tube MN7, a fourth NMOS tube MN8, a second PMOS tube MP4, a third PMOS tube MP5, a fourth PMOS tube MP6, a fifth PMOS tube MP7, a first selector switch SW1, a second selector switch SW2, a third selector switch SW3, a fourth selector switch SW4, and a third capacitor C4, a fourth capacitor C5, a fifth capacitor C6, a sixth capacitor C7, and an eighth capacitor C8. The connections between each part of each subcharge pump module are as follows: The substrate terminal and source of the third NMOS tube MN7, and the substrate terminal and source of the fourth NMOS tube MN8 are each connected to the input power supply Vin. The gate of the third NMOS tube MN7 is connected to the drain of the fourth NMOS tube MN8, one plate A of the third capacitor C5, and the drain of the second PMOS tube MP4. The drain of the third NMOS tube MN7 is connected to the gate of the fourth NMOS tube MN8, one plate B of the third capacitor C4, and the drain of the third PMOS tube MP5. The substrate terminal and source of the second PMOS tube MP4, the substrate terminal and source of the third PMOS tube MP5, the substrate terminal and source of the fourth PMOS tube MP6, and the substrate terminal and source of the fifth PMOS tube MP7 are each connected to the output voltage terminal VOUT and one end of the eighth capacitor C8. The other end of the eighth capacitor C8 is grounded, and the gate of the second PMOS tube MP4 is connected to one plate D of the sixth capacitor C7, the drain of the fourth PMOS tube MP6, and the gate of the fifth PMOS tube MP7, respectively. The gate of the third PMOS tube MP5 is connected to one plate C of the fifth capacitor C6, the drain of the fifth PMOS tube MP7, and the gate of the fourth PMOS tube MP6, respectively. The other plate of the third capacitor C4 is connected to the movable end of the first selector switch SW1, and the other plate of the fourth capacitor C5 is connected to the movable end of the second selector switch SW2. The other plate of the fifth capacitor C6 is connected to the movable end of the third selector switch SW3, and the other plate of the sixth capacitor C7 is connected to the movable end of the fourth selector switch SW4. The movable ends of the first selector switch SW1, the second selector switch SW2, the third selector switch SW3, and the fourth selector switch SW4 are each connected to their respective clock control ends. The clock control ends of the first selector switch SW1, the second selector switch SW2, the third selector switch SW3, and the fourth selector switch SW4 are each connected to the same output node of the phase clock generation module 101. The first, second, third, and fourth selector switches SW1, SW2, SW3, and SW4 each have one stationary terminal connected to the power supply VDD and the other stationary terminal connected to the ground terminal GND. The response control terminals of the first, second, third, and fourth selector switches SW4 are connected to the output terminal of the acceleration response control module 105, and the input terminal of the acceleration response control module 105 is connected to the output voltage terminal VOUT.

[0036] When the phase clock generation module 101 supplies a clock signal with a phase difference of 120 degrees to each subcharge pump module, the first selection switch SW1, the second selection switch SW2, the third selection switch SW3, and the fourth selection switch SW4 in each subcharge pump module receive the clock signal from the same output node in the phase clock generation module 101 in a time-division manner. That is, the first selection switch SW1 receives the first clock signal Φ1 via the clock control terminal, the second selection switch SW2 receives the second clock signal Φ2 via the clock control terminal, the third selection switch SW3 receives the third clock signal Φ3 via the clock control terminal, and the fourth selection switch SW4 receives the fourth clock signal Φ4 via the clock control terminal. Therefore, the selection switches SW1 to SW4 are controlled by the clock signals Φ1 to Φ4 output from the same output node in the phase clock generation module 101, and charge and discharge capacitors C4 to C7 in a time-division manner. The third NMOS tube MN7, the fourth NMOS tube MN8, the second PMOS tube MP4, the third PMOS tube MP5, the fourth PMOS tube MP6, and the fifth PMOS tube MP7, which are used as switches, are switched on and off to transfer the charge from capacitors C4 to C7 to the eighth capacitor C8. By controlling the selection switches SW1 to SW4 with the clock signals Φ1 to Φ4 and performing time-division charge and discharge of capacitors C4 to C7, the number of capacitors that the input power supply simultaneously charges each sub-charge pump module is reduced, input power supply ripple caused by excessively large peak current is reduced, and the input power supply's dependence on off-chip capacitors is decreased.

[0037] As shown in Figure 5, when controlling the on / off state of selection switches SW1 to SW4 via clock signals Φ1 to Φ4 output by the same output node in the phase clock generation module 101, the clock signals Φ1 to Φ4 must satisfy the condition that the first clock signal Φ1 and the third clock signal Φ3, and the second clock signal Φ2 and the fourth clock signal Φ4 are non-overlapping clock signals, with the non-overlapping time being Tnov1. Similarly, the first clock signal Φ1 and the second clock signal Φ2, and the third clock signal Φ3 and the fourth clock signal Φ4 are non-overlapping clock signals, with the non-overlapping times being Tnov3 and Tnov2, respectively, and the non-overlapping times of clock signals Φ1 to Φ4 must satisfy the relationship Tnov2 = 2 * Tnov1 + Tnov3.

[0038] Based on the control of the non-overlapping clock signals described above, capacitors C4 to C7 are all charged in time division, thus reducing the charge capacity of the input power supply Vin at the same time, and further reducing the charging current of the input power supply to capacitors C4 to C7 and the resulting input power supply ripple. Specifically, in the initial state, all clock signals Φ1 to Φ4 are at a low level, so the movable ends of the selection switches SW1 to SW4 are connected to the ground end GND via the clock control end, and plates A and B of the fourth capacitor C5 and the third capacitor C4 are charged to the Vin potential by the body diodes of the third NMOS tube MN7 and the fourth NMOS tube MN8, respectively, and similarly the initial potentials of the output voltage end VOUT and plates C and D of the fifth capacitor C6 and the sixth capacitor C7 are all the input power supply Vin. Assuming C4=C5=C6=C7=C, capacitors C4 to C7 all initially have an accumulated charge of CVin.

[0039] When clock signals Φ2 and Φ3 are at a low level, the fourth capacitor C5 and the fifth capacitor C6 are charged by connecting the plates connected to the second selector switch SW2 and the third selector switch SW3, respectively, to the power supply VDD. The voltages across plates A and C of the fourth capacitor C5 and the fifth capacitor C6 are equal to the input power supply Vin + power supply VDD. Simultaneously, when clock signals Φ1 and Φ4 are at a high level, the first selector switch SW1 and the fourth selector switch SW4 short-circuit the plates connected to the third capacitor C4 and the sixth capacitor C7 to the ground terminal GND. The third capacitor C4 and the sixth capacitor C7 are held, and the voltages across plates B and D of the third capacitor C4 and the sixth capacitor C7 are equal to the input power supply Vin. At this time, the third NMOS tube MN7 turns on, the fourth NMOS tube MN8 turns off, the second PMOS tube MP4 and the fifth PMOS tube MP7 turn on, and the third PMOS tube MP5 and the fourth PMOS tube MP6 turn off. As a result, the charge in the fifth capacitor C6 and the fourth capacitor C5 is transferred to the eighth capacitor C8, which is then charged, while the third capacitor C4 and the sixth capacitor C7 remain in a held state.

[0040] After the clock signals Φ2 and Φ3 jump from low to high levels, the plates of the fourth capacitor C5 and the fifth capacitor C6, which are connected to the second selector switch SW2 and the third selector switch SW3, are short-circuited to ground. As a result, the capacitance voltage cannot change rapidly, and therefore the voltage difference between the fourth capacitor C5 and the fifth capacitor C6 is still equal to the input power supply Vin. Consequently, the voltages across plates A and C of the fourth capacitor C5 and the fifth capacitor C6 are equal to the input power supply Vin. At this time, the clock signals Φ1 and Φ4 jump from high level to low level, and the plates of the third capacitor C4 and the sixth capacitor C7, which are connected to the first selector switch SW1 and the fourth selector switch SW4 respectively, are connected to the power supply VDD. Therefore, the voltages of plates B and D of the third capacitor C4 and the sixth capacitor C7 are the input power supply Vin + power supply VDD, respectively. Therefore, the third NMOS tube MN7 turns off, the fourth NMOS tube MN8 turns on, the second PMOS tube MP4 and the fifth PMOS tube MP7 turn off, the fourth PMOS tube MP6 and the third PMOS tube MP5 turn on, the charges in the third capacitor C4 and the sixth capacitor C7 are transferred to the eighth capacitor C8, respectively, to charge the eighth capacitor C8, and the fourth capacitor C5 and the fifth capacitor C6 remain in a held state.

[0041] Therefore, based on the selection switches SW1-SW4 controlled by non-overlapping clocks, the third capacitor C4 and the sixth capacitor C7, and the fourth capacitor C5 and the fifth capacitor C6 do not simultaneously draw current from the power supply VDD, resulting in a significantly smaller peak current for this power supply VDD. However, during the charge transmission process, the third capacitor C4 and the sixth capacitor C7, or the fourth capacitor C5 and the fifth capacitor C6, together provide the charge to the eighth capacitor C8. At the point when the clock reverses, only one capacitor state is switched each time, so that the ripple of the output voltage VOUT of each subcharge pump module is also significantly reduced. Through several clock cycles, VOUT eventually reaches Vin + VDD, thereby enabling each subcharge pump module to reach a steady output and output a voltage higher than the input power supply. For example, assuming that the fourth capacitor C5 and the fifth capacitor C6 are supplying transmission charge to the eighth capacitor C8, and the third capacitor C4 and the sixth capacitor C7 are in a charged state, at the time the clock inverts, the fourth capacitor C5 can be switched from the transmission state to the charged state first. Then, the fifth capacitor C6 is switched from the transmission state to the charged state, the third capacitor C4 is switched from the charged state to the transmission state, and finally, the fourth capacitor C5 is switched from the charged state to the transmission state.

[0042] Each subcharge pump module can provide a voltage output higher than the input power supply Vin, as well as a voltage output lower than the ground voltage VSS. As shown in Figure 6, if it is necessary to provide a voltage output lower than the ground voltage VSS, the third NMOS tube MN7 and the fourth NMOS tube MN8 in each subcharge pump module are replaced with the sixth PMOS tube MP8 and the seventh PMOS tube MP9, and the second PMOS tube MP4, the third PMOS tube MP5, the fourth PMOS tube MP6, and the fifth PMOS tube MP7 are replaced with the fifth NMOS tube MN9, the sixth NMOS tube MN10, the ninth NMOS tube MN13, and the tenth NMOS tube MN14. This implementation process is the reverse of the process by which each subcharge pump module provides a voltage output higher than the input power supply Vin, and will not be explained in detail here.

[0043] To enable rapid generation of output voltage, the selection switches SW1 to SW4 can be optimized, meaning that the selection switches SW1 to SW4 become accelerated selection switches. As shown in Figure 7, each selection switch comprises a 10th PMOS tube MP12, a 7th NMOS tube MN11, an OR gate OR1, an AND gate AND1, a 3rd inverter INV2, and at least one 11th PMOS tube MP13 and an 8th NMOS tube MN12. The connections of each part of this selection switch are as follows: The gates of the 10th PMOS tube MP12 and the 7th NMOS tube MN11 are connected together as the clock control terminals of the selection switch to connect to one of the output nodes of the phase clock generation module 101, and receive the clock signal Φi (one of the clock signals Φ1 to Φ4) output by the phase clock generation module 101. Furthermore, the gates of the 10th PMOS tube MP12 and the 7th NMOS tube MN11 are connected to one input terminal of the OR gate OR1 and the AND gate AND1. The drains of the 10th PMOS tube MP12 and the 7th NMOS tube MN11, and the drain of the 11th PMOS tube MP13 and its corresponding 8th NMOS tube MN12 are connected to each other, and the corresponding capacitance (one of the capacitances C4 to C7) is connected to the other plate as the movable terminal of the selector switch. The sources of the 10th PMOS tube MP12 and the 11th PMOS tube MP13 are each connected to the power supply VDD, and the sources of the 7th NMOS tube MN11 and each of the 8th NMOS tubes MN12 are each grounded. The gate of the 11th PMOS tube MP13 is connected to the output terminal of the OR gate OR1, and the gate of the 8th NMOS tube MN12 is connected to the output terminal of the AND gate. The other input terminal of the OR gate OR1 is connected to the output terminal of the third inverter INV2, and the other input terminal of the AND gate AND1 is connected to the input terminal of the third inverter INV2 and the output terminal of the acceleration response control module 105.

[0044] When the acceleration response control module 105 detects that the output voltage of each subcharge pump module has not reached the target value, the acceleration response control module 105 outputs a high-level logic signal fast_en to the third inverter INV2. When the clock signal Φi is high, the output of the AND gate AND1 becomes high, the seventh NMOS tube MN11 and at least one eighth NMOS tube MN12 are connected in parallel, and the pull-down resistance corresponding to each subcharge pump module decreases. That is, the discharge current of the eighth capacitor C8 connected to the output voltage terminal of each subcharge pump module increases, and the on-resistance on the discharge path decreases. Similarly, when the clock signal Φi is low level, the output of the OR gate OR11 is also low level, so the pull-up resistor of the output voltage VOUT becomes the impedance of the 10th PMOS tube MP12 and at least one 11th PMOS tube MP13 connected in parallel, resulting in a smaller pull-up resistor for each subcharge pump module. That is, the charging current of the 8th capacitor C8 connected to the output voltage terminal of each subcharge pump module is increased, and the on-resistance on the charging path is reduced.

[0045] When the frequency of the clock signal Φi is high, reducing the on-resistance of the third inverter INV2 increases the charging speed for C4~C7 of each sub-charge pump module under the control of the high-frequency clock signal, thereby shortening the rise time of the output voltage of each sub-charge pump module. At the same time, when the output voltage of each sub-charge pump module reaches a steady state, the logic signal is 0, and when the clock signal Φi is low or high, the on-resistance of the third inverter INV2 is determined by the on-resistances of the 10th PMOS tube MP12 and the 7th NMOS tube MN11, respectively. At this point, it is sufficient that the charging performance of each sub-charge pump module is not affected even if the frequency of the clock signal Φi decreases and the pull-up / pull-down resistors of the selector switches increase. Therefore, after the output voltage of each sub-charge pump module reaches a steady state, the increase in the pull-up / pull-down resistors of the selector switches slows down the rate at which capacitors C4~C7 draw current from the power supply, further reducing the peak current of the input power supply during operation of the charge pump circuit.

[0046] As shown in Figure 8, the acceleration response control module 105 comprises a first resistor R1, a second resistor R0, and a hysteresis comparator Comp. One end of the first resistor R1 is connected to the output voltage terminal VOUT of each subcharge pump module, and the other end is connected to one end of the second resistor R0 and the inverting input terminal of the hysteresis comparator Comp, respectively. The other end of the second resistor R0 is grounded, the positive-sequence input terminal of the hysteresis comparator Comp is connected to a reference voltage VREF, and the output terminal of the hysteresis comparator Comp is connected to the input terminal of the first inverter INV1 of the phase clock generation module 101 and the input terminal of the third inverter INV2 in each subcharge pump module.

[0047] The acceleration response detection module 105 detects the output voltage of each subcharge pump module. If the output voltage of each subcharge pump module does not reach the target value, the logic signal fast_en output by the hysteresis comparator Comp becomes high level and is output to the phase clock generation module 101 and each subcharge pump module. In the phase clock generation module, the oscillation frequency of the ring oscillator is changed, and in each subcharge pump module, the charge / discharge rate of the capacitance is adjusted so that each subcharge pump module generates an output voltage quickly. When the output voltage of each subcharge pump module reaches the target value, the logic signal fast_en output by the hysteresis comparator Comp becomes low level, and the charge pump circuit operates in a low peak current, low power state. Here, to easily determine whether the output voltage of each subcharge pump module has reached the target value, a threshold inversion voltage can be set in the hysteresis comparator Comp. This threshold inversion voltage is VREF(1+R1 / R0). The threshold inversion voltage can be set by adjusting the ratio of the first resistor R1 and the second resistor R0, and when the output voltage of each subcharge pump module reaches the threshold inversion voltage, it is considered that the output voltage of each subcharge pump module has reached the target value.

[0048] Furthermore, the charge pump circuit provided according to the embodiment of the present invention can be used in an analog integrated circuit chip. The specific configuration of the charge pump circuit in this analog integrated circuit chip will not be described in detail here.

[0049] The charge pump circuit described above can also be used in various communication terminals as an important component of an analog integrated circuit. The communication terminals referred to here are computer devices usable in mobile environments that support various communication methods such as GSM, EDGE, TDD_LTE, FDD_LTE, and 5G NR, including mobile phones, laptop computers, tablet PCs, and in-car computers. Furthermore, the technical solutions provided by this invention can also be applied to other analog integrated circuit applications, such as communication base stations.

[0050] Compared to conventional technology, the charge pump circuit provided by the present invention generates multiple clock signals with a constant phase difference via a phase clock generation module in order to control the output voltages generated by multiple sub-charge pump modules in correspondence. The acceleration response control module detects the output voltage of each sub-charge pump module, changes the frequency of the clock signal output by the phase clock generation module, and outputs logic signals to the phase clock generation module and each sub-charge pump module, respectively, in order to shorten the charge and discharge time of the capacity in each sub-charge pump module. The present invention effectively reduces the peak current drawn by the charge pump circuit from the input power supply and mitigates ripple interference that the charge pump circuit imposes on the input power supply and output voltage signals, thereby reducing the input power supply's dependence on off-chip capacitors.

[0051] The charge pump circuit, chip, and communication terminal provided by embodiments of the present invention have been described in detail above. For those skilled in the art, any obvious modifications made thereto without departing from the substantial content of the present invention will all fall within the scope of the patent protection of the present invention.

Claims

1. A charge pump circuit, It comprises a phase clock generation module, an acceleration response control module, and multiple subcharge pump modules. Each of the multiple output terminals of the phase clock generation module is connected to the clock control terminal of each of the corresponding multiple subcharge pump modules, the multiple subcharge pump modules are connected in parallel and connected corresponding to the input power terminal and output voltage terminal, the output voltage terminal is connected to the input terminal of the acceleration response control module, and the output terminal of the acceleration response control module is connected to the input terminals of the phase clock generation module and each of the multiple subcharge pump modules. The phase clock generation module comprises a plurality of phase clock subcircuits and a first inverter, each of which consists of a first NMOS transistor, a first capacitor, a second capacitor, an output node, and a second inverter. The second inverter comprises a first PMOS transistor and a second NMOS transistor, the gates and drains of the first PMOS transistor and the second NMOS transistor are connected to each other, the source of the first PMOS transistor is connected to the power supply, and the source of the second NMOS transistor is grounded. The input terminal of the first inverter is connected to the output terminal of the acceleration response control module, the output terminal of the first inverter is connected to the gate of each of the first NMOS transistors of the plurality of phase clock subcircuits, each of the first capacitors is connected in series between the drain of each of the first NMOS transistors and each of the output nodes, the source of each of the first NMOS transistors is grounded, each of the output nodes is connected to the corresponding plurality of subcharge pump modules, and each of the second capacitors is connected in series between each of the output nodes and ground, each of the second inverters is cascaded, and the output terminal of the final stage second inverter of these cascaded second inverters is connected to the input terminal of the first stage second inverter to form a ring oscillator. A charge pump circuit characterized in that the phase clock generation module generates a plurality of clock signals having a constant phase difference using the ring oscillator and controls the plurality of subcharge pump modules to generate an output voltage, the acceleration response control module detects the output voltage and outputs a logic signal corresponding to the detection result to the phase clock generation module and the plurality of subcharge pump modules, respectively, if the state of the logic signal corresponds to the output voltage not reaching a target value, the phase clock generation module changes the oscillation frequency of the ring oscillator to generate an acceleration clock signal and controls each of the plurality of subcharge pump modules to rapidly generate the output voltage based on the acceleration clock signal and the logic signal, and if the state of the logic signal corresponds to the output voltage reaching a target value, the phase clock generation module reduces the frequency of the clock signal output to each of the plurality of subcharge pump modules and controls each of the plurality of subcharge pump modules to maintain a normal output voltage based on the clock signal and the logic signal and suppress ripple generated in the output voltage.

2. The charge pump circuit according to claim 1, wherein the phase clock generation module adjusts the magnitude of the oscillation frequencies of the plurality of clock signals having a constant phase difference generated by the ring oscillator by changing the magnitude of the load capacitance at each of the plurality of output terminals of the phase clock generation module based on the state of the logic signal output from the acceleration response control module to the phase clock generation module.

3. The charge pump circuit according to claim 1, further comprising means for changing the aspect ratio of each switching transistor constituting the second inverter based on the state of the logic signal output from the acceleration response control module to the phase clock generation module, and characterized in that the magnitude of the oscillation frequencies of a plurality of clock signals having a constant phase difference generated by the ring oscillator is adjusted by changing the equivalent resistance of the second inverter.

4. In order to enable each of the plurality of sub-charge pump modules to supply a voltage output higher than the input power supply, the sub-charge pump module comprises a third NMOS transistor, a fourth NMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first selector switch, a second selector switch, a third selector switch, a fourth selector switch, and a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and an eighth capacitor. Each of the selection switches comprises two stationary ends and one movable end that is selectively connected to either of these two stationary ends, and also comprises a clock control end that receives the clock signal output from the phase clock generation module and a response control end that receives the logic signal output from the acceleration response control module. The substrate terminal and source of the third NMOS transistor and the substrate terminal and source of the fourth NMOS transistor are each connected to the input power supply, the gate of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, one plate of the fourth capacitor and the drain of the second PMOS transistor, the drain of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, one plate of the third capacitor and the drain of the third PMOS transistor, the substrate terminal and source of the second PMOS transistor, the substrate terminal and source of the third PMOS transistor, the substrate terminal and source of the fourth PMOS transistor and the substrate terminal and source of the fifth PMOS transistor are each connected to the output voltage terminal and one end of the eighth capacitor, the other end of the eighth capacitor is grounded, the gate of the second PMOS transistor is connected to one plate of the sixth capacitor and the drain of the fourth PMOS transistor and The charge pump circuit according to claim 1, characterized in that the gates of the fifth PMOS transistors are each connected to the gates of the fifth PMOS transistors, the gate of the third PMOS transistor is connected to one plate of the fifth capacitor, the drain of the fifth PMOS transistor and the gate of the fourth PMOS transistor, the other plate of the third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor are each connected to the movable ends of the selector switches corresponding to these capacitors, the movable ends are each connected to the clock control ends of the selector switches, these clock control ends are each connected to a specific output end of the plurality of output ends of the phase clock generation module, in each of the selector switches, one of the two stationary ends is connected to the power supply and the other stationary end is connected to ground, the response control end of each of the selector switches is each connected to the output end of the acceleration response control module, and the input end of the acceleration response control module is each connected to the output voltage end.

5. Each of the selection switches comprises a 10th PMOS transistor, a 7th NMOS transistor, an OR gate, an AND gate, a 3rd inverter, and at least one 11th PMOS transistor and at least one 8th NMOS transistor. In each of the selection switches, the gates of the 10th PMOS transistor and the 7th NMOS transistor are connected to each other so as to function as the clock control terminal for connecting each of the multiple output terminals of the phase clock generation module, the gates of the 10th PMOS transistor and the 7th NMOS transistor are connected to one input terminal of the OR gate and the AND gate, respectively, and the drains of the 10th PMOS transistor and the 7th NMOS transistor and the 11th PMOS transistor and the corresponding 8th NMOS transistor are connected so as to function as the movable terminal for connecting the other electrode of the capacitance corresponding to each of the selection switches The charge pump circuit according to claim 4, characterized in that the drains of the transistors are connected to each other, the sources of the 10th PMOS transistor and the 11th PMOS transistor are each connected to a power supply, the sources of the 7th NMOS transistor and the 8th NMOS transistor are each grounded, the gate of the 11th PMOS transistor is connected to the output terminal of the OR gate, the gate of the 8th NMOS transistor is connected to the output terminal of the AND gate, the other input terminal of the OR gate is connected to the output terminal of the 3rd inverter, and the other input terminal of the AND gate is connected to the input terminal of the 3rd inverter and the output terminal of the acceleration response control module.

6. The charge pump circuit according to claim 4, characterized in that the on / off state of each of the selection switches is controlled by outputting a time-divided first clock signal, a second clock signal, a third clock signal, and a fourth clock signal as the plurality of clock signals from each of the plurality of output terminals of the phase clock generation module, the first clock signal and the third clock signal, and the second clock signal and the fourth clock signal are clock signals whose rising and falling edges do not overlap, and the time during which they do not overlap is Tnov1, and the first clock signal and the second clock signal, and the third clock signal and the fourth clock signal are clock signals whose rising and falling edges do not overlap, and the time during which they do not overlap is Tnov3 and Tnov2, respectively, and these time periods during which they do not overlap satisfy the relationship Tnov2 = 2 * Tnov1 + Tnov3.

7. The charge pump circuit according to claim 4, characterized in that, in order to enable each of the plurality of subcharge pump modules to supply a voltage output below the ground voltage, the third NMOS transistor and the fourth NMOS transistor in the subcharge pump module are replaced with a sixth PMOS transistor and a seventh PMOS transistor, and the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor are replaced with a fifth NMOS transistor, a sixth NMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor.

8. The acceleration response control module comprises a first resistor, a second resistor, and a hysteresis comparator. The charge pump circuit according to claim 5, characterized in that one end of the first resistor is connected to the output voltage terminals of the plurality of subcharge pump modules, the other end of the first resistor is connected to one end of the second resistor and the inverting input terminal of the hysteresis comparator, the other end of the second resistor is grounded, the positive-sequence input terminal of the hysteresis comparator is connected to a reference voltage, and the output terminal of the hysteresis comparator is connected to the input terminal of the first inverter and the input terminal of the third inverter in the plurality of subcharge pump modules, respectively.

9. An integrated circuit chip characterized by comprising a charge pump circuit according to any one of claims 1 to 8.

10. A communication terminal characterized by comprising a charge pump circuit as described in any one of claims 1 to 8.

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