Delayed Locked Loop Offset Calibration and Correction

Abstract

A clock circuit is provided using a master delay-locked loop (DLL) and a slave DLL. The master DLL code indicates the delay adjustment made in the master DLL. The delay of the slave DLL is adjusted based on the master DLL code. A replica phase detector in the slave DLL is temporarily enabled during interface idle periods. The slave DLL code is determined, and a configuration value for the master DLL code is determined based on the slave DLL code. The replica phase detector is then disabled.

Description

Background Art

[0001] For a memory controller such as a dynamic random-access memory (DRAM) controller to correctly acquire the data sent from the DRAM, the DRAM controller usually uses a delay-locked loop (DLL) circuit to adjust the read clock or strobe signal from the DRAM so that it can be used to correctly latch the input data (DQ) signal. For the same reason, the DRAM controller uses the DLL circuit to concentrate the outgoing data at the transition of the memory write clock.

[0002] The DLL locks to a reference clock signal and keeps the delay of the DLL output signal substantially constant against process, voltage, and temperature variations. Some DLLs continuously maintain lock to the reference signal, while others intermittently lock to the reference signal while continuously using the voltage of the loop filter to set their delays because this voltage changes slowly.

[0003] In some DRAM systems such as the graphics double data rate (GDDR) system, the read clock is configured as a strobe and is activated only to achieve a read command, and otherwise goes into an idle state to save power on the DRAM interface. The DLL is usually used in the receiver of each data lane to provide a consistent clock signal based on the received read clock. When the read clock signal is not received during the idle period, the DLL usually does not operate, and thus the voltage and temperature conditions of the receiver's DLL may drift significantly from their original values without being compensated. Such drift makes it more time-consuming and difficult to maintain lock in the DLL.

Brief Description of the Drawings

[0004] [Figure 1] This is a block diagram of a delayed-locked-loop (DLL) clock circuit based on prior art. [Figure 2] This is a block diagram of a DLL clock circuit 200 according to several embodiments. [Figure 3] These are schematic and block diagrams of DLL clock circuits according to several embodiments. [Figure 4] This is a flowchart of the process for operating a DLL clock circuit according to several embodiments. [Figure 5] This is a partial block diagram of a data processing system 500 according to several embodiments. [Modes for carrying out the invention]

[0005] In the following description, the use of the same reference numeral in different drawings indicates similar or identical items. Unless otherwise specified, the word “coupled” and its associated verb forms include both direct and indirect electrical connections by means known in the art, and unless otherwise specified, any description of a direct connection also means an alternative embodiment using a preferred form of indirect electrical connection.

[0006] The clock circuit for the communication link includes a master delay-locked loop (DLL) circuit, a slave DLL circuit, and an arbiter circuit. The master DLL circuit includes a plurality of delay elements arranged in series between its input and output, and a phase detector circuit coupled to its input and output for detecting phase offsets and providing master DLL code for adjusting the delay elements of the master DLL. The slave DLL circuit provides an oscillator signal to the receiver of the communication link. The slave DLL includes a plurality of delay elements arranged in series between its input and output, and a replica phase detector circuit for detecting phase offsets and providing slave DLL code for adjusting the delay elements of the slave DLL. The arbiter circuit is operable to temporarily enable the replica phase detector of the slave DLL during idle periods of the communication link to update configuration values ​​based on the master DLL code and the slave DLL code, and to adjust the delay elements of the slave DLL during active periods of the communication link based on the configuration values ​​and the master DLL code.

[0007] A method for operating an interface circuit is provided. This method includes providing a master DLL lock value indicating the delay adjustment made in the master delay-locked loop (DLL). This method includes adjusting the delay of the slave DLL based on the master DLL code. This method includes temporarily enabling a replica phase detector in the slave DLL during an interface idle period, determining the slave DLL code, obtaining a configuration value for the master DLL code based on the slave DLL code, and then disabling the replica phase detector.

[0008] The data processing system includes a data processor, memory coupled to the data processor by a communication link, and a clock circuit for the communication link. The clock circuit includes a master DLL circuit, a slave DLL circuit, and an arbiter circuit. The master DLL circuit includes a plurality of delay elements arranged in series between its input and output, and a phase detector circuit coupled to its input and output for detecting phase offsets and providing master DLL code for adjusting the delay elements of the master DLL. The slave DLL circuit provides an oscillator signal to the receiver of the communication link. The slave DLL includes a plurality of delay elements arranged in series between its input and output, and a replica phase detector circuit for detecting phase offsets and providing slave DLL code for adjusting the delay elements of the slave DLL. The arbiter circuit is operable to temporarily enable the replica phase detector of the slave DLL during idle periods of the communication link to update configuration values ​​based on the master DLL code and the slave DLL code, and to adjust the delay elements of the slave DLL during active periods of the communication link based on the configuration values ​​and the master DLL code.

[0009] Figure 1 is a block diagram of a prior art delayed-locked-loop (DLL) clock circuit 100. The DLL clock circuit 100 includes a primary or master DLL 110, a phase detector 115, and a secondary or slave DLL 120.

[0010] Generally, a slave DLL 120 has an input to receive a strobe clock, such as a GDDR read clock (RCK), an input to receive a lock code from a phase detector 115, and an output to provide a phase-shifted or multi-phase version of the strobe clock. A master DLL 110 has an input to receive a reference clock, typically set to the expected frequency of the strobe clock, an input to receive a lock code from a phase detector 115, and an output connected to the input of the phase detector 115. The phase detector 115 detects the phase difference between the input and output of the master DLL 110 and provides a phase lock code to control one or more delay elements within the master DLL 110 to stabilize the phase of the master DLL 110. This phase lock code is then used to stabilize the slave DLL 120 without requiring a phase detector. Generally, multiple slave DLLs are located near the master DLL 110 and connected to the phase detector 115 to receive the phase lock code. This architecture allows each of the multiple slave DLLs to provide a clock signal to local circuitry, generally a receiver circuitry, without having a phase detector circuitry.

[0011] The DLL clock circuit 100 is often used in communication interfaces such as memory interfaces where the read or write clock operates in burst mode or strobe mode to improve power efficiency. Specifically, to improve power efficiency, the clock is turned off in low-power states or idle modes where there is no data transmission or reception. However, the slave DLL clock must be turned on as quickly as possible during the transition from idle to active mode. Fast turn-on of the clock to active mode at the end of idle mode is one of the major design challenges of burst mode systems. In the illustrated conventional slave DLL implementation, the slave DLL 120 operates as an open-loop circuit by using a lock code from the master DLL in both active and idle modes. As a result, conventional implementations of open-loop slave DLLs may have a significant offset between the master DLL and the slave DLL, which can lead to timing errors or clock integrity problems due to factors such as random device mismatches, supply / ground voltage differences, and thermal gradient differences. These factors can change over time as the circuit operates.

[0012] Figure 2 is a block diagram of a DLL clock circuit 200 according to several embodiments. The DLL clock circuit 200 includes a primary or master DLL 110, a phase detector 215, a secondary or slave DLL 220, and a replica phase detector and arbiter circuit 230. The DLL clock circuit 200 is generally implemented in the physical layer (PHY) of an integrated circuit such as a system-on-a-chip, data processor, or graphics processor to provide a clock signal to an interface circuit such as a memory bus interface.

[0013] The master DLL 210 has an input that receives a reference clock labeled "reference Clk", an input that receives a lock code from a phase detector 215, and an output that provides a delayed version of the input signal to the input of the phase detector 215. The phase detector 215 detects the phase difference between the input and output of the master DLL 210 and provides a phase lock code for controlling one or more delay elements within the master DLL 210 to stabilize the phase of the master DLL 210.

[0014] The slave DLL220 has an input that receives a strobe clock labeled "strobe Clk," such as the GDDR read clock (RCK), and an output that provides a phase-shifted or multiphase version of the strobe clock labeled "phase-shifted clock or multiphase strobe clock." The replica phase detector and arbiter circuit 230 includes two inputs connected to the input and output of the slave DLL220, an input that receives a lock code from the phase detector 215, and an output connected to the slave DLL220.

[0015] During operation, the DLL clock circuit 200 activates a duplicate phase detector to temporarily generate a local replica feedback loop for the slave DLL 220 via the phase detector and arbiter circuit 230, and performs offset correction calibration to cancel the offset between the master DLL 210 and the slave DLL 220 to improve performance. The arbiter circuit is operable to temporarily enable the replica phase detector both during initial calibration and during idle periods of the communication link to update the configuration values ​​based on the master DLL lock code and the slave DLL lock code. A reference clock is supplied to the input of the slave DLL 220 to perform initial calibration and update the configuration values. The replica phase detector is then disabled and the reference clock signal is removed. During periods when the communication link is active, if a strobe clock signal is present, the delay element of the slave DLL is adjusted based on the configuration value and the master DLL code.

[0016] Although one slave DLL is shown, typically many slave DLLs exist and are coupled to the master DLL 210 in the same manner to perform such calibrations. The local replica feedback loop of the slave DLL 220 can be continuously on in active mode when an input strobe clock is available, while in idle mode when there is no input clock, the loop can be open. The replica phase detector and the arbiter circuit of the arbiter circuit 230 are used to improve performance by combining information from the offset correction loop of the slave DLL 220 with locked information from the master DLL 210 to reduce or cancel the offset between the two DLLs.

[0017] In some embodiments, the DLL clock circuit 200 can also perform continuous slave DLL offset correction in the active state. The local replica feedback loop via the replica phase detector and arbiter circuit 230 can be continuously on in the active state when the input strobe clock is available, whereas in idle mode when the input strobe clock is not available, the replica loop is disabled. In idle mode, the slave DLL 220 relies on updates of locked information from the master DLL 210, since the feedback loop of the slave DLL 220 is open.

[0018] Figure 3 shows a schematic and block diagram of a DLL clock circuit 300 in several embodiments. The DLL clock circuit 300 includes a primary or master DLL 310, a phase detector 315, a secondary or slave DLL 320, and a phase detector and arbiter circuit 330. The DLL clock circuit 300 is shown coupled to two phase interpolator (PI) blocks 340 and 345 to illustrate how the output signal of the master DLL 310 may be used in some embodiments. The DLL clock circuit 300 is one exemplary embodiment of the circuit 200 in Figure 2 and is embodied on an integrated circuit.

[0019] The master DLL310 includes a first delay line 302, a second delay line 304, a multiplexer 305, two analog bias loop circuits 306 and 308, and a master digital-to-analog converter (DAC) 314. The master DLL310 includes an input to receive a reference clock signal "PLL_ref_clk", an input to receive a range selection signal labeled "range_h", an input to receive a range selection signal labeled "range_l", and an output.

[0020] In this embodiment, the first delay line 302 is an ultra-low voltage threshold (ULVT) delay line containing several delay elements, which are typically a series of complementary metal-oxide-semiconductor (CMOS) inverters constructed with ULVT transistors. The first delay line 302 is used for higher frequency clock signals and has an input that receives an enable signal labeled "range_h". The second delay line 304 is a low voltage threshold (LVT) delay line containing several delay elements constructed with LVT transistors and has an input that receives an enable signal labeled "range_l". The PLL_ref_clk signal is supplied to the inputs of the first delay line 302 and the second delay line 304. The output of each delay line, in this example, five groups of clock signals, each with a different phase, is supplied to a multiplexer 305, which selects which group to pass to the PLL output based on the value of the range_h signal. In this embodiment, two separate delay lines are used for high and low frequencies, but in other embodiments where a narrow range of operation is expected, a single delay line may be used. Furthermore, although two different types of devices (LVT and ULVT) are shown in this embodiment, in other embodiments, the second delay line 304 may be implemented using an ULVT transistor having a channel length longer than the channel length of the first delay line 302.

[0021] The master DAC 314 has an input connected to the master DLL logic 313 and an output connected to the inputs of the analog bias loops 306 and 308. The analog bias loop 306 generates an analog bias voltage supplied to the delay element of the first delay line 302. Similarly, the analog bias loop 308 generates an analog bias voltage supplied to the delay element of the second delay line 304. Separate analog bias voltages are supplied to both the p-type and n-type portions of the delay element to adjust the delay of the delay element.

[0022] The phase detector 315 includes a multiplexer 311, a "bang-bang" (BB) phase detector 312, a master DLL logic circuit 313, and an input that receives an enable signal labeled "master_pd_en". The multiplexer 311 has an input that receives a PLL_ref_clk signal, an input that is coupled to ground or the VSS voltage, and an output that selectively passes either input based on the value of the enable signal master_pd_en. The BB phase detector 312 has an input connected to the output of the multiplexer 311, an input connected to the initial output (phase 0) of the multiplexer 305, and an output that provides an up-down signal labeled "updown_m". The master DLL logic 313 has an input that receives an up-down_m signal and an output connected to the input of the master DAC 314 that provides a master lock code signal labeled "Master_lock_code". The master DLL logic 313 includes a digital circuit configuration for low-pass filtering the updown_m signal and generating a lock code that indicates the DAC input in digital form to generate a lock for the master DLL 310.

[0023] The slave DLL320 includes a first delay line 322, a second delay line 324, a multiplexer 325, two analog bias loop circuits 326 and 328, and a slave digital-to-analog converter (DAC) 334. The slave DLL320 also includes an input for receiving a clock signal or strobe signal "Slave_clk", an input for receiving a range selection signal range_h, an input for receiving a range selection signal range_l, and an output.

[0024] The slave DLL 320 is preferably constructed similarly to the master DLL 310. The first delay line 322 is implemented as a ULVT delay line including several delay elements that are normal CMOS inverters. The first delay line 322 is used for a higher frequency clock signal and has an input that receives an enable signal labeled range_h. The second delay line 324 is a LVT delay line including several delay elements and has an input that receives an enable signal labeled range_l. The Slave_clk signal is supplied to the inputs of the first delay line 322 and the second delay line 324. The outputs of each delay line, in this example, a group of five clock signals with different phases each, are supplied to the multiplexer 325. The multiplexer 325 selects which group to pass to the PLL output based on the value of the range_h signal. As shown on the right side, in this embodiment, the multi-phase output of the slave DLL 320 provides quadrature clock signals to the PI circuit of the DQ receiver in the memory interface PHY circuit. In other embodiments, the output of the slave DLL 320 can supply clock signals to other interface circuits.

[0025] The phase detector and arbiter circuit 330 includes a multiplexer 331, a calibration circuit 332, a slave DLL logic circuit 333, an offset register labeled "offset", a weight register labeled "weight", an input that receives the lock code signal Master_lock_code, an input that receives the Slave_clk signal, an input that receives the PLL_ref_clk signal, and an input that receives an enable signal labeled "slave_pd_en".

[0026] Multiplexer 331 has an input that receives the PLL_ref_clk signal, an input that receives the Slave_clk signal, and an output that selectively passes either input based on the value of the enable signal slave_pd_en. Calibration circuit 332 has an input connected to the output of multiplexer 331, an input connected to the initial output (phase 0) of multiplexer 325, and an output that provides an up-down signal labeled "updown_s". Calibration circuit 332 includes a replica BB phase detector used to perform phase detection using the PLL_ref_clk signal, similar to BB phase detector 312, and generate a calibration value during calibration and calibration updates. In this embodiment, the calibration value is an offset value and is stored in an offset register, as will be further described below. Calibration circuit 332 can also perform continuous closed-loop operation using the Slave_clk signal in situations where open-loop operation is undesirable, i.e., it can allow slave DLL 320 to run as a normal DLL instead of a slave DLL.

[0027] The slave DLL logic circuit 333 has an input for receiving the Master_lock_code, an input for receiving the updown_s signal, an input connected to the offset register, an input connected to the weight register, and an output connected to the input of the master DAC 314. The slave DLL logic 333 includes a digital circuit configuration for generating a lock code that low-pass filters the updown_s signal and indicates in digital form the DAC input for generating the lock of the slave DLL 320 during the calibration and update processes. This circuit configuration is active during closed-loop operation in some embodiments. This circuit configuration measures and stores the difference between the Master_lock_code and the Slave_lock_code in closed-loop operation when the replica slave DLL phase detector is enabled. The slave DLL logic 333 includes a digital circuit configuration for applying the value from the offset register to offset the value of the Master_lock_code to generate the value of the Slave_lock_code for open-loop operation during open-loop operation. In this operation, the value of the offset is added to the value of the Master_lock_code. In some embodiments, the value in the weight register is also used to scale the offset value before addition. The value in the weight register is preferably determined by circuit characterization during manufacturing or an initial training process, but in some embodiments may be updated by a training process during operation.

[0028] The operation of the DLL clock circuit 300 is further described with respect to the flowchart of FIG. 4, which shows a flowchart 400 of a process for operating a DLL clock circuit according to some embodiments. The illustrated process is implemented by a DLL clock circuit or other suitable clock circuit as shown in FIG. 2 or FIG. 3 under the control of a power state controller or initialization controller that controls the initialization of the associated PHY circuit that provides the clock signal. This process is executed during the initialization and operation of the associated PHY circuit.

[0029] In block 402, the process begins initializing and calibrating the master DLL and the slave DLLs controlled by the master DLL. In block 404, the process enables the replica phase detector of each slave DLL for closed-loop mode operation and obtains the slave DLL lock code from the closed-loop mode operation. This calibration is performed with the Slave_clk signal active.

[0030] In block 406, the process calculates an offset between the master DLL lock code and the slave DLL lock code. This offset is stored in an offset register (Figure 3) or in another preferred memory circuit maintained during idle periods of the associated communication link, which in this exemplary embodiment is a DQ receiving circuit configuration. While offset values ​​are shown here, other preferred configuration values, such as a fractional ratio or percentage, can be calculated based on the master and slave DLL lock codes. The offset is specific to each slave DLL. In some embodiments, the process has the ability to generate negative values ​​for the offset to use the lock code used by the master in a bidirectional mode provided by the slave DLL.

[0031] In block 408, weighting coefficients can also be configured, such as those found in the weight register (Figure 3). This operation may involve loading weighting coefficient values ​​from the firmware or calculating such values ​​based on training. Some embodiments may not use weighting coefficients. Since the weighting coefficient values ​​depend on local voltage, temperature, and process variations in and around each slave DLL circuit, it is preferable that they be unique to each slave DLL.

[0032] In block 410, the process disables the replica phase detector of the slave DLL and puts the slave DLL into open-loop mode operation. In block 412, the slave DLL for the RCK signal provided to the PHY's receiver circuit in this example operates in open-loop mode, and DLL adjustment is performed based on the master DLL lock code and the offset and weight values ​​determined during the calibration process. This open-loop mode operation continues until in block 414, when the process enters the idle period for the RCK signal, meaning that no read operations are being performed and the RCK strobe signal is stopped. Although the use with the RCK signal is described here, this process can be used with other interface circuit clock signals as described above.

[0033] When the idle period begins in block 414, the process proceeds to block 420, where the slave DLL does not operate because no RCK signal is provided. In block 420, the process waits for a specified period and then enters a periodic calibration mode (blocks 422-428) in which the offset value of the slave DLL is updated. If the idle period ends while waiting in idle mode, the process in block 421 returns to block 412 for open-loop operation of the slave DLL with the latest offset value. It should be noted that idle times can vary considerably during operation, and therefore thermal and voltage conditions can change significantly during the idle period. The idle period is preferably configured to capture a normal period in which thermal and voltage conditions change.

[0034] After a specified period, the process proceeds to block 422 and begins a configuration update similar to the original configuration of the slave DLL. The replica phase detector is enabled, and the master DLL reference clock (e.g., PLL_ref_clk in Figure 3) is supplied to the slave DLL. This updated value is stored in the offset register. In block 424, the offset between the master DLL lock code and the slave DLL lock code is calculated. In the optional block 426, the weighting coefficients may also be updated. Following the configuration update, the process returns to block 420, waiting for the end of the idle period or the completion of another periodic configuration update.

[0035] Figure 5 is a partial block diagram of a data processing system 500 according to several embodiments. The illustrated portion of the data processing system includes one or more data processors 501, such as a central processing unit (CPU), a graphics processing unit (GPU), or an accelerated processing unit (APU). The data processors 500 access DRAM 540, such as GDDR7 DRAM, via a memory controller 520 and a PHY circuit 530. The PHY circuit 530 includes a master DLL circuit 503, three receiver circuits 504, 506, and 508, and three transmitter circuits 510, 512, and 514, all of which are for specific memory channels. The master DLL circuit 503 can also supply clock signals for one or more additional memory channels. Various other parts of the circuit are not shown to avoid obscuring the clock configuration.

[0036] Each of the receivers 504, 506, and 508 includes four phase interpolators labeled "PI". Slave DLL circuits 505, 507, and 509 supply clock signals to the PIs in their respective receivers. Similarly, in this embodiment, each of the transmitters 510, 512, and 514 includes four phase interpolators labeled "PI". Slave DLL circuits 511, 513, and 515 supply clock signals to the PIs in their respective transmitters.

[0037] The illustrated slave DLL circuits 505, 507, and 509 are constructed according to the slave DLL circuits in Figure 2 or Figure 3. The transmitter slave DLL circuits may be constructed similarly, or they may be constructed to operate only in an open-loop configuration.

[0038] Each of the slave DLL circuits 505, 507, and 509 performs the process shown in Figure 4 to update their calibration during the receiver's idle period when a read clock signal is not present. In some embodiments, control signals for the DLL replicas for the receiver and transmitter slave DLL replica PD may be generated in response to read and write commands dispatched from the memory controller 520, respectively.

[0039] Therefore, a clock circuit, system, and method is described that uses a local arbiter to effectively cancel the offset between the two DLLs by combining information from a local slave DLL offset correction loop with locked information from a master DLL, thereby tracking power supply and temperature drift in idle mode to improve performance. While this exemplary application of the circuit and technology is provided herein, the same technology is applicable to other receiver and transmitter circuits.

[0040] The DLL clock circuit 200, the DLL clock circuit 300, or any part thereof may be described or represented by a computer-accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture an integrated circuit. For example, this data structure may be a behavioral-level description or register-transfer-level (RTL) description of hardware functionality in a high-level design language (HDL) such as VeriLog or VHDL. The description can be read by a synthesis tool that can synthesize the description to generate a netlist containing a list of gates from a synthesis library. The netlist contains a set of gates that also represent the functionality of the hardware, including the integrated circuit. The netlist may then be arranged and routed to generate a dataset describing the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture an integrated circuit. Alternatively, the database on a computer-accessible storage medium may, if desired, be a netlist (with or without a synthesis library) or a dataset, or Graphic Data System (GDS) II data.

[0041] While specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, other communication links that benefit from the slave DLL circuit may employ the circuits and processes described herein. Furthermore, while this circuit is useful for clocking stroved clock signals such as the RCK signal used in various GDDR memory standards, the circuit described herein can be used for unstroved signals such as continuous read clock signals, and gating can be applied to the read clock signal to provide the slave DLL with an idle mode in the PHY.

[0042] Therefore, the attached claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A method for operating an interface circuit, To provide a master DLL code that indicates the delay adjustment performed in the master delay-locked loop (DLL), Adjusting the delay of the slave DLL based on the master DLL code, This includes temporarily enabling the replica phase detector in the slave DLL during the interface idle period, determining the slave DLL code, obtaining configuration values ​​based on the slave DLL code and the master DLL code, and disabling the replica phase detector. method.

2. The above configuration value is based on the offset between the master DLL code and the slave DLL code. The method according to claim 1.

3. When adjusting the delay element of the slave DLL, this includes applying a weighting coefficient to the configuration value. The method according to claim 2.

4. Adjusting the delay of the slave DLL based on the master DLL code includes supplying a bias voltage to the delay element of the slave DLL based on the master DLL code and the configuration value. The method according to claim 1.

5. This includes saving the configuration value in the register settings maintained during the interface idle period, The method according to claim 1.

6. A clock circuit for a communication link, A master delay-locked loop (DLL) circuit comprising a plurality of delay elements and a phase detector circuit for detecting phase offsets and providing a master DLL code for adjusting the delay elements of the master DLL circuit, A slave DLL circuit for providing an oscillator signal to a receiver of the communication link, comprising: a plurality of delay elements; and a replica phase detector circuit for detecting a phase offset and providing a slave DLL code for adjusting the delay elements of the slave DLL circuit; The system includes an arbiter circuit that can operate to temporarily enable the replica phase detector circuit of the slave DLL circuit during idle periods of the communication link in order to update configuration values ​​based on the master DLL code and the slave DLL code. Clock circuit.

7. The arbiter circuit is operable to adjust the delay element of the slave DLL circuit during the active period of the communication link based on the configuration value and the master DLL code. The above configuration value is based on the offset between the master DLL code and the slave DLL code. The clock circuit according to claim 6.

8. The arbiter circuit applies a weighting coefficient to the configuration value when adjusting the delay element of the slave DLL circuit. The clock circuit according to claim 7.

9. The master DLL circuit includes a digital-to-analog converter (DAC) for supplying a bias voltage to its delay element based on the master DLL code. The slave DLL circuit includes a DAC for supplying a bias voltage to its delay element based on the master DLL code and the configuration values. The clock circuit according to claim 7.

10. The replica phase detector is A phase detector that provides an up-down signal indicating whether the delay of the delay element should be increased or decreased, The system includes a digital logic circuit for generating the slave DLL code based on the up / down signals. The clock circuit according to claim 9.

11. The arbiter circuit is operable to enable the replica phase detector circuit and generate the configuration values ​​based on the master DLL code and the slave DLL code, thereby performing an initial calibration process to determine the configuration values ​​in order to store them. The clock circuit according to claim 6.

12. The arbiter circuit is operable to store the configuration values ​​in the register settings maintained during the idle period. The clock circuit according to claim 6.

13. Multiple instances of the aforementioned slave DLL circuit exist, each providing an oscillator signal to the phase interpolator of the respective receiver circuit for each data (DQ) signal of the memory interface. The clock circuit according to claim 6.

14. A data processing system, Data processor, A memory connected to the data processor via a communication link, The system comprises a clock circuit for the aforementioned communication link, The aforementioned clock circuit is A master delay-locked loop (DLL) circuit comprising a plurality of delay elements and a phase detector circuit for detecting phase offsets and providing a master DLL code for adjusting the delay elements of the master DLL circuit, A slave DLL circuit for providing an oscillator signal to a receiver of the communication link, comprising: a plurality of delay elements; and a replica phase detector circuit for detecting a phase offset and providing a slave DLL code for adjusting the delay elements of the slave DLL circuit; The system includes an arbiter circuit that can operate to temporarily enable the replica phase detector circuit of the slave DLL circuit during idle periods of the communication link in order to update configuration values ​​based on the master DLL code and the slave DLL code. Data processing system.

15. The arbiter circuit is operable to adjust the delay element of the slave DLL circuit during the active period of the communication link based on the configuration value and the master DLL code. The above configuration value is based on the offset between the master DLL code and the slave DLL code. The data processing system of claim 14.

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