Improved silicon carbide MOSFET transistor device and corresponding manufacturing process

Abstract

To provide a silicon carbide MOSFET device in which the increase of an electrical field in a gate dielectric region in the central part of a JFET region of a MOSFET is suppressed, and a manufacturing process of the same.SOLUTION: A MOSFET device includes: a functional layer 24 of silicon carbide, the functional layer having a first conductivity type; gate structures 30 formed on a top surface 24a of the functional layer and each comprising a dielectric region 31 and an electrode region 32; body wells 26 having a second conductivity type, and formed within the functional layer while being separated from one another by surface-separation regions 29; and source regions 27 having the first conductivity type and formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions 40 are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified dopant concentration as compared to the dopant concentration of the functional layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This invention relates to a silicon carbide MOSFET transistor device having improved characteristics and a corresponding manufacturing process. [Background technology]

[0002] Electronic semiconductor devices are well known, and in particular, there are MOSFET transistors (metal-oxide-semiconductor field-effect transistors) for electronic power applications, for example, which are manufactured starting from silicon carbide substrates.

[0003] The above-described apparatus demonstrates its advantages thanks to the favorable chemical and physical properties of silicon carbide. For example, silicon carbide typically has a wider band gap than silicon, which is commonly used in electronic devices. As a result, even at relatively small thicknesses, silicon carbide has a higher breakdown voltage than silicon, and therefore can be effectively used in high-voltage, high-power, and high-temperature applications.

[0004] In particular, due to its crystal quality and large-scale availability, silicon carbide having a hexagonal polytype (4H-SiC) can be used for electronic power applications.

[0005] However, the manufacturing of silicon carbide semiconductor devices is affected by several issues. For example, problems with the crystal quality of silicon carbide can hinder the achievement of high manufacturing yields, and the yield for silicon carbide is generally lower than that for similar devices manufactured starting from silicon, which in turn increases manufacturing costs.

[0006] In particular, reliability issues have been found to be linked to the high electric field generated at the interface between silicon oxide (SiO2) and silicon carbide (4H-SiC).

[0007] Figure 1 shows a basic or fundamental structure (so-called cell) of a vertical MOSFET device, specifically an N-channel VDMOS (vertical double-diffusion metal oxide semiconductor), for the power application example shown in reference number 1, which is not shown here (e.g., 10 18 Number of atoms / cm 3 Even higher doping concentrations, for example, N + A substrate made of a semiconductor material (especially silicon carbide 4H-SiC) that is highly doped (by type doping), and a substrate made of a lower dopant concentration (N ― The substrate has the same conductivity type as the substrate and also has an epitaxial layer (referred to as a drift layer) 2 made of silicon carbide located above the substrate. The substrate acts as a drain for the MOSFET device 1, and the epitaxial layer 2 constitutes its surface extension and defines the upper surface 2a.

[0008] Each cell in the MOSFET device 1 consists of a main cell 4 (P-type in the illustrated example) having a conductivity type opposite to that of the epitaxial layer 2, and a substrate cell with the same conductivity type and high dopant concentration (N + The epitaxial layer 2 has a source region 5 located within the main body well 4 on the upper surface 2a. The surface portion of the epitaxial layer 2 located on the upper surface 2a and interposed between adjacent main body wells 4 is usually referred to as the JFET region.

[0009] The apparatus 1 further has a gate structure 6, which is composed of a gate dielectric region 7 made of, for example, silicon oxide, formed on the JFET region and partially superimposed on the main body well 4 and the source region 5, and a gate electrode 8 provided on the gate dielectric region 7.

[0010] For example, a dielectric material region 9 made of field oxide exists on the gate electrode 8, and an electrical contact region 11 is defined through this dielectric material region 9 and is configured to contact the surface portion of the source region 5.

[0011] The source metallization 12 is positioned in contact with the electrical contact region 11, and although not shown, the drain metallization is in contact with the substrate from the back side, and the gate metallization, which is provided within a contact opening via the dielectric material region 9, is in contact with the gate electrode 8.

[0012] The channels of each cell in the MOSFET device 1 are located directly beneath the gate electrode 8 and formed within the corresponding portion of the main body well 4, and their range is defined on one side by a junction between the source region 5 and the main body well 4, and on the opposite side by a junction between the same main body well 4 and the JFET region.

[0013] The gate electrode 8 is capacitively coupled to the channel to adjust its conductivity type, and in particular, the application of an appropriate voltage to the gate electrode 8 makes it possible to cause channel inversion, thereby forming a conductive path for electrons between the source region 5 (the first current-conducting region of the device) and the substrate (the second current-conducting region of the device) via the channel and the drift layer.

[0014] One problem plaguing silicon carbide MOSFET devices is linked to an increase in the electric field, which is thought to be due to crystal defects, and is a tendency for the electric field to increase within the insulating material, particularly in the gate dielectric region 7 in the central part of the JFET region, especially in reverse bias configuration.

[0015] Figure 2 shows the trend of the electric field E within the dielectric material in the region defined above. The increase in the electric field in the central region of the JFET is evident, and what is shown there may reach a level that causes dielectric breakdown and thus jeopardizes the reliability of the MOSFET device.

[0016] Known solutions to address the aforementioned problems involve one or more of the following approaches: increasing the thickness of the epitaxial layer (drift layer), decreasing the doping of the epitaxial layer, and decreasing the width of the JFET region by reducing the distance between adjacent body wells, in an attempt to reduce the electric field at the interface between the silicon carbide and the gate dielectric region. However, it has become clear that such solutions are not entirely satisfactory. This is because they generally undesirably increase the on-resistance of the MOSFET and further have an impact on the cost and efficiency of the manufacturing process that cannot be ignored.

Summary of the Invention

Problems to be Solved by the Invention

[0017] An object of the present invention is to solve the above-described problems.

Means for Solving the Problems

[0018] According to the present invention, as described in the claims, a silicon carbide MOSFET device and a corresponding manufacturing process are provided.

[0019] To better understand the present invention, the preferred embodiments thereof will be described below by way of a purely non-limiting example with reference to the accompanying drawings.

Brief Description of the Drawings

[0020] [Figure 1] A partial cross-sectional view of a known type of MOSFET device. [Figure 2] A graph showing the tendency of the electric field in the JFET region of the MOSFET device of FIG. 1. [Figure 3] A cross-sectional view of a MOSFET device according to one embodiment of the present invention. [Figure 4] A graph showing the tendency of the electric field in the JFET region of the MOSFET device of FIG. 3 as compared to the tendency of the electric field in a known type of MOSFET device. [Figure 5] (A) and (B) are cross-sectional views of the MOSFET device in successive steps of the manufacturing process according to the first embodiment, respectively. [Figure 6] (A) to (C) are cross-sectional views of the MOSFET device in successive steps of the manufacturing process according to different embodiments, respectively. [Figure 7] (A) is a cross-sectional view of a MOSFET device according to a further embodiment of the present invention and (B) is a simplified cross-sectional view of a part of the MOSFET device of (A).

Mode for Carrying Out the Invention

[0021] As will be described in detail below, one aspect of the present invention aims to reduce the electric field in the gate dielectric region, particularly under reverse bias conditions, by introducing a modified doping region into the JFET region of a MOSFET device (especially a 4H-SiC polytype silicon carbide power MOSFET transistor). The modified doping region is a region having a reduced net dopant concentration compared to the concentration of the epitaxial layer in which the JFET region is provided.

[0022] FIG. 3 shows a MOSFET device 20, particularly an N-channel vertical transistor for high-power applications.

[0023] The MOSFET device 20 is provided in a die made of a semiconductor material, particularly silicon carbide (especially 4H-SiC polytype), and has a highly doped (N + type doping) substrate (or structural layer) 22 and is disposed on the substrate 22 with the same conductivity type as the substrate 22 and a lower concentration (e.g., N ―It has a functional layer 24 having a doping type), and the functional layer 24 having an upper surface 24a is grown on the substrate 22 using, for example, an epitaxial technique and, together with the substrate 22, provides the drain of the MOSFET device 20 (i.e., the first current conducting region of the same device). In particular, this functional layer 24 defines the so-called drift layer of the MOSFET device 20. A drain contact (not shown here) made of an appropriate conductive material is coupled to the lower side of the substrate 22 (i.e., on the opposite side of the functional layer 24 along the vertical direction z).

[0024] A plurality of functional units or cells of the MOSFET device 20 are formed within the active region of the functional layer 24, and these cells have, for example, a substantially stripe-shaped extension in the longitudinal axis direction y (a direction orthogonal to the cross-sectional transverse direction x of FIG. 3 and to the aforementioned vertical direction z corresponding to the thickness of the MOSFET device 20).

[0025] Each functional unit has a body well 26 having a conductivity type opposite to that of the functional layer 24 (in the illustrated example, P - type), and a source region 27 which is disposed within the body well 26 on the upper surface 24a and has the same conductivity type as the substrate 22 (and, in the illustrated example, N + type doping with a high concentration) and defines the second current conducting region of the same device. Each body well 26 and source region 27 are shared by two consecutive functional units of the MOSFET device 20 in the illustrated example.

[0026] Furthermore, a drain region 28 having the same conductivity type as the body well 26 and a high doping (in the illustrated example, P + type) is disposed in one or more of the same body wells 26 on the upper surface 24a of the functional layer 24.

[0027] The intercellular region, i.e., the JFET region 29, corresponds to the portion of the functional layer 24 located between two adjacent body wells 26 (in the horizontal direction, i.e., along the transverse direction x in the illustrated example) and between the upper surface 24a of the functional layer 24 and the depth of the body well 26 (in the vertical direction z).

[0028] Each functional unit further has a gate structure 30, which is located on the upper surface 24a and overlaps with the JFET region 29 and partially overlaps with the main body well 26 and the source region 27, in particular, located on the channel region of the main body well 26 (this channel region is defined on one side by the junction between the source region 27 and the main body well 26, and on the opposite side by the junction between the main body well 26 and the JFET region 29). In this example, the gate structure 30 is shared by two adjacent cells of the MOSFET device 20.

[0029] More specifically, for example, a gate structure 30 having a stripe-like shape along the longitudinal axis y includes, for example, a gate dielectric region 31 having silicon oxide (SiO2) and positioned on the front surface 24a of the functional layer 24, and a gate electrode region 32 superimposed on the gate dielectric region 31 and having substantially the same transverse dimensions as the same gate dielectric region 31.

[0030] A passivation layer 35 made of a dielectric material is placed on the gate structure 30, and the source contact opening 36 in the lower source region 27 and the body contact opening 37 in the lower drain region 28 are defined via the same passivation layer 35. An electrical contact region 38 is located within the aforementioned source contact opening 36 and body contact 37, providing ohmic-type electrical contacts to the lower source region 27 and drain region 28, respectively.

[0031] The MOSFET device 20 further has a conformable, or adaptable, type of source metallization layer 39, which includes, for example, aluminum, and is located on the passivation layer 35 in the entire active region, and is provided in particular within the source contact opening 36 and the body contact opening 37 to contact the respective electrical contact regions 38, thus the source region 27 and the drain region 28.

[0032] In embodiments not shown, further electrical contact areas are provided on the front side for electrical connection to the gate electrode 32 extending through the passivation layer 35, and on the back side for electrical connection to the drain contact.

[0033] According to a particular aspect of the present invention, the MOSFET device 20 further has a modified doping region 20 which is located within the surface portion of the functional layer 24 separating adjacent body wells 26, i.e., on the upper surface 24a, below each gate component 30, and in particular below the corresponding gate dielectric region 31, within the JFET region 29.

[0034] In the illustrated embodiment, the modified doping region 40 is centrally located with respect to each JFET region 29. Alternatively, as will be explained and illustrated later, the same modified doping region 40 can extend transversely across the entire width of each JFET region 40 and terminate at the body well 26 of each adjacent cell.

[0035] Furthermore, the modified doping region 40 described above has a smaller thickness in the vertical direction z with respect to the thickness of the main body well 26 (i.e., with respect to the position of the main body joint between the same main body well 26 and the functional layer 24 along the vertical direction z), and the aforementioned thickness of the modified doping region 40 can be between 10% and 50% of the thickness of the main body well 26.

[0036] In detail, the modified doping region 40 has the same conductivity type as the functional layer 24 and has a net dopant concentration that is reduced compared to the concentration in the same functional layer 24. Specifically, the doping concentration of the modified doping region 40 is between 5% and 50%, for example, it is equal to 20% of the doping concentration of the functional layer 24.

[0037] As described below, the modified doping region 40 can be obtained by localizing and partially inactivating the N-type doping of the functional layer 24, particularly through localized injection. This localized injection may have the opposite conductivity type (P-type) or cause localized damage to the functional layer 24, for example, with aluminum atoms or some other suitable substance.

[0038] Alternatively, the modified doping region 40 can be obtained by the specialized growth of an epitaxial layer with appropriate and specific doping on the upper surface 24a of the functional layer 24.

[0039] In either case, the presence of the modified doping region 40 located below the gate structure 30 and within the JFET region 29 makes it possible to reduce the electric field in the corresponding gate dielectric region 31, especially under the reverse bias conditions of the MOSFET device 20.

[0040] In this regard, Figure 4 shows the trend of the electric field along the transverse direction within the gate dielectric region 31 with the modified doping region 40 present as a continuous line, while the trend of the electric field in the same gate dielectric region 31 in the conventional solution without the modified doping region 40, shown as a dotted line for comparison as an example, is evident. Examining these two trends reveals a clear decrease in the electric field in the JFET region 29 (highlighted with a circular box), which is beneficial, as this decrease is sufficient to prevent dielectric breakdown and thus maintain the reliability of the MOSFET device 20.

[0041] It should be noted that the inventors have shown that the beneficial effect of reducing the electric field does not involve any substantial modification of the breakdown characteristics of the MOSFET device 20, and that the values ​​of the breakdown voltage and threshold voltage are not substantially changed. In other words, the reduction in the electric field can be achieved while the breakdown voltage and threshold voltage of the MOSFET device 20 remain unchanged.

[0042] Furthermore, it should be noted that reducing the electric field by only a small amount (e.g., 10% or less) is sufficient to guarantee a significant increase in the reliability of the MOSFET device 20. This is particularly important because an excessive reduction in the electric field will reduce the on-state resistance (R) of the MOSFET device 20. ON This is because it can lead to an undesirable increase in the on-state resistance. Therefore, in either case, it is possible to achieve a good compromise between the beneficial effect of reducing the electric field and the undesirable increase in on-state resistance.

[0043] In particular, regarding the formation of the modified doping region 40 mentioned above, possible processes for manufacturing the MOSFET device 20 are described below.

[0044] In the first embodiment, a modified doping region 40 is obtained by appropriate localized injection performed in the JFET region 29 of the MOSFET device 20 for the purpose of partially deactivating the N-type doping of the functional layer 24 of the same MOSFET device 20.

[0045] As shown in Figure 5(A), the manufacturing process first aims to form body wells 26 within the functional layer 24 by injecting P-type dopant atoms (e.g., aluminum atoms) in a known manner, source regions 27 within the same body wells 26 by injecting N-type dopant atoms (e.g., phosphorus atoms), and drain regions 28 within one or more body wells 26 on the upper surface 24a of the functional layer 24 by injecting P-type dopant atoms with high doping doses.

[0046] Next, in Figure 5(B), based on one aspect of the present invention, a modified doping region 40 is provided in the JFET region 29 between adjacent body wells 26 by P-type injection (for example, with aluminum or boron atoms). Since this injection is performed with dopant atoms having a conductivity type opposite to that of the functional layer 24 (in this case, N-type), counter-doping, and therefore partial inactivation of the doping of the functional layer 24, is performed, thus forming a modified doping region 40 with a reduced net doping concentration.

[0047] Following the thermal activation of the dopant, the process proceeds in a manner known to itself, forming a gate structure 30 on the functional layer 24 (by depositing and subsequently defining dielectric and metal layers for the formation of the gate dielectric region 31 and gate electrode 32, and then by depositing a passivation layer 35). Furthermore, electrical contact regions 38 are formed (on the front and back sides) to provide source, gate, and drain contacts, and then a source metallization layer 39 is formed (thus defining the aforementioned structure with reference to Figure 3).

[0048] One variation of the aforementioned manufacturing process involves forming a modified doping region 40 by damaging and thus inactivating the doping in a region of interest, with the aim of ultimately obtaining a reduced net doping concentration in the same modified doping region 40.

[0049] In a different embodiment, the modified doping region 40 described above is to be formed by epitaxial growth of a surface layer having a desired doping concentration (even lower than the concentration intended for the functional layer 24).

[0050] As shown in Figure 6(A), the above manufacturing process applies a desired conductivity type and a desired doping concentration (in this example, N) to the drift layer of the MOSFET device 20. = The aim is to grow a first epitaxial layer 24' having a specific type on the substrate 22, and it should be noted that this first epitaxial layer 24' has a thickness that is slightly smaller overall than the functional layer 24 of the MOSFET device 20.

[0051] Next, as shown in Figure 6(A), according to one aspect of the present invention, a second thin epitaxial layer 24” is grown on the first epitaxial layer 24' (the thickness of which, when added to the thickness of the first epitaxial layer 24', is such that the desired thickness of the functional layer 24 is obtained). In particular, this second epitaxial layer 24” which is grown in a continuous manner and defines the front surface 24a of the functional layer 24 has an N-type (similar to the functional layer 24) conductivity with a desired doping concentration that is reduced compared to the first epitaxial layer 24' corresponding to the desired net doping concentration for the modified doping region 40, that is, as will be illustrated later, the modified doping region 40 itself is defined in this case by the portion of the second epitaxial layer 24” described above.

[0052] Next, as shown in Figure 6(B), the main body well 26, source region 27, and drain region 28 are formed by ion implantation. In particular, since the aforementioned second epitaxial layer 24'' is present on the front surface 24a, the surface doping density of the implantation region is appropriately adjusted taking into account the doping already present in the same second epitaxial layer 24'' to obtain the desired dopant concentration (this adjustment of the surface doping density is schematically shown in Figure 6(B)).

[0053] It should be noted that, at the end of the ion implantation described above, the modified doping regions 40 remain between the main body wells 26 and are composed of the portion of the second epitaxial layer 24" remaining between the same main body wells 26 (in this case, these modified doping regions 40 extend transversely through the entire width of the JFET region 29 in the transverse direction x until they come into contact with the main body wells 26).

[0054] In this case, the process proceeds in a known manner, forming a gate structure 30 on the functional layer 24, forming an electrical contact region 38 to form a source contact, a gate contact, and a drain contact (in a manner not shown here), and forming a source metallization layer 39, thereby defining the MOSFET device 20 shown in Figure 6(C).

[0055] Next, further embodiments of the present invention will be described with reference to Figures 7(A) and (B).

[0056] In this further embodiment, the modified doping region 40 located within the JFET region 29 of the MOSFET device 20 is composed of a laminate consisting of an upper layer 40a and a bottom layer 40b located below the upper layer 40a.

[0057] The bottom layer 40b of the modified doping region 40 has an even higher doping level, i.e., a higher dopant concentration and the same conductivity type (N-type in this example) as the functional layer 24. In particular, the dopant concentration of the bottom layer 40b is between 1.5 and 50 times that of the functional layer 24.

[0058] Furthermore, the depth level of the bottom layer 40b with respect to the upper surface 24a of the functional layer 24 along the vertical direction z is between 0.5 and 1.2 times the respective depth levels of the main body well 26, which are shown as Db in Figure 7(B) (note that for simplicity, the source and drain regions 27 and 28 of the MOSFET device 20 are not shown) and also shown as D in Figure 7(B).

[0059] The upper layer 40a of the modified doping region 40 has a lower dopant concentration compared to the bottom layer 40b, for example, between 0.1 and 0.5 times the dopant concentration of the same bottom layer 40b. The conductivity type of the upper layer 40a can be the same as or opposite to that of the functional layer 24. The thickness of the upper layer 40a along the vertical z direction is shown as Ta and is between 0.1 and 0.5 times the respective thickness Tb of the bottom layer 40b.

[0060] The width of the bottom layer 40b of the modified doping region 40 (in the horizontal direction, along the transverse direction x in the illustrated example) is shown as Wb in Figure 7(B) and can be smaller than or equal to the width W of the JFET region 29 (in the second case, the bottom layer 40b extends horizontally across the entire JFET region 29). Similarly, the width Wa (in the horizontal direction) of the upper layer 40a of the same modified doping region 40 can be smaller than or equal to the width W of the JFET region 29, independently and uncorrelated with respect to the bottom layer 40b (i.e., the widths Wa and Wb of the upper and bottom layers 40a and 40b can be different, and each can be equal to or smaller than the width of the JFET region 29).

[0061] In this embodiment as well, the modified doping region 40 can be positioned centrally with respect to each JFET region 29 (i.e., symmetrical with respect to a vertical plane that crosses the same JFET region 29 at its center).

[0062] In this embodiment of the modified doping region 40, the presence of the bottom layer 40b improves the conductivity characteristics and reduces the on-state resistance of the MOSFET device 20, while the top layer 40a reduces the electric field within the gate dielectric region of the same MOSFET device 20, as described above. Generally, similar considerations as described above also apply to the manufacturing of this embodiment of the modified doping region 40.

[0063] The bottom layer 40b can be obtained by epitaxial growth in a single step or successive steps relative to the functional layer 24, and it can be obtained by injecting the same type of doping species as the functional layer 24 to enhance its doping. The bottom layer 40b can be formed to the depth described above and reach or be embedded in the upper surface 24a of the functional layer 24.

[0064] The upper layer 40a can be obtained by epitaxial growth in a single step or successive steps with respect to the functional layer 24 and the bottom layer 40b, and it can be obtained by injecting the same type or a different type of doping species as the same functional layer 24. The doping of the upper layer 40a can be adjusted by injecting different species due to a counter-doping effect.

[0065] As described above, the upper layer 40a is formed to a desired depth with respect to the upper surface 24a of the functional layer 24. The same upper layer 40a can be continuous or, for example, divided horizontally in the JFET region 29 by a photomasking process and subsequent injection step before or after forming the main body wells 26 and / or bottom layer 40b. If the width Wa of the upper layer 40a is greater than the distance between the main body wells 26, doping of the same main body wells 26 must take into account doping interference with the same upper layer 40 in the overlapping region.

[0066] The advantages of the present invention are evident from the above description. In all cases, it should be emphasized again that the present invention enables improvements in the performance and reliability of MOSFET transistor devices constructed starting from silicon carbide substrates (particularly 4H-SiC polytype). In particular, the present invention makes it possible to solve reliability problems linked to the high electric field generated at the interface between silicon oxide (SiO2) and silicon carbide (4H-SiC), especially in the center of the JFET region of the MOSFET transistor device. Beneficially, the aforementioned reduction in the electric field is achieved while maintaining the breakdown characteristics of the MOSFET transistor device unchanged.

[0067] Furthermore, embodiments having a modified doping region 40 formed by a laminate of upper and lower layers 40a and 40b offer the advantage of improving the on-resistance and conductivity characteristics of the MOSFET device 20, as well as providing protection against electric fields to the gate dielectric region.

[0068] Therefore, the MOSFET transistor device obtained based on the present invention can be usefully used in various application fields, such as power supplies, uninterruptible power supplies (UPS) with power factor correction (PFC), photovoltaic systems, energy distribution systems, industrial motors, and electric vehicles.

[0069] Finally, it is clear that modifications and variations can be constructed without departing from the scope of the present invention as defined in the claims, in relation to what has been described and illustrated above. In particular, it is emphasized that the invention can be beneficially applied to various silicon carbide MOSFET transistor devices, such as signal or power VDMOS devices for automotive applications, and IGBT (including MOSFET transistors) IP (intelligent power) MOSFETs, in general, both N-channel and P-channel MOSFET transistors.

Claims

1. In a MOSFET transistor device, A functional layer (24) made of silicon carbide having a first conductivity type, A gate structure (30) is formed on the upper surface (24a) of the functional layer (24), and each has a dielectric region (31) and an electrode region (32). The main body wells (26) have a second conductivity type different from the first conductivity type, are formed within the functional layer (24), and are separated from each other by the surface separation regions (29) of the functional layer (24), The first conductivity type is present, and the source region (27) is formed laterally and partially below each gate structure (30) within the main body well (26), It has, and furthermore, Each gate structure (30) has a modified doping region (40) located below the functional layer (24) within the surface separation region (29), wherein the modified doping region (40) has the first conductivity type and a dopant concentration that is reduced compared to the dopant concentration of the functional layer (24). The apparatus is characterized in that the modified doping region (40) extends transversely across the entire width of each surface separation region (29) and terminates in the main body well (26).

2. The apparatus according to claim 1, wherein the modified doping region (40) is located below the dielectric region (31) of each gate structure (30) and is centrally positioned with respect to the surface separation region (29).

3. The apparatus according to claim 1 or 2, wherein the modified doping region (40) is between 5% and 50% of the dopant concentration of the functional layer (24).

4. The apparatus according to claim 3, wherein the modified doping region (40) has a thickness that is even smaller than the thickness of the main body well (26) in the transverse and perpendicular direction (z) with respect to the upper surface (24a), and is between 10% and 50% of the thickness of the main body well (26).

5. In a MOSFET transistor device, A functional layer (24) made of silicon carbide having a first conductivity type, A gate structure (30) is formed on the upper surface (24a) of the functional layer (24), and each has a dielectric region (31) and an electrode region (32). The main body wells (26) have a second conductivity type different from the first conductivity type, are formed within the functional layer (24), and are separated from each other by the surface separation regions (29) of the functional layer (24), The first conductivity type is present, and the source region (27) is formed laterally and partially below each gate structure (30) within the main body well (26), It has, and furthermore, Each gate structure (30) has a modified doping region (40) located below the functional layer (24) within the surface separation region (29), wherein the modified doping region (40) has the first conductivity type and a dopant concentration that is reduced compared to the dopant concentration of the functional layer (24). The apparatus is characterized in that the modified doping region (40) is composed of a laminate consisting of an upper layer (40a) and a lower bottom layer (40b) below the upper layer (40a), wherein the bottom layer (40b) has a higher dopant concentration than the functional layer (24) and the upper layer (40a) has a lower dopant concentration than the bottom layer (40b).

6. The apparatus according to claim 5, wherein the dopant concentration of the bottom layer (40b) is between 1.5 and 50 times the dopant concentration of the functional layer (24), and the dopant concentration of the upper layer (40a) is between 0.1 and 0.5 times the dopant concentration of the bottom layer (40b).

7. The apparatus according to claim 5 or 6, wherein the depth level (Db) of the bottom layer (40b) with respect to the upper surface (24a) of the functional layer (24) is between 0.5 and 1.2 times the respective depth level (D) of the main body well (26), and the thickness (Ta) of the upper layer (40a) is between 0.1 and 0.5 times the respective thickness (Tb) of the bottom layer (40b).

8. The apparatus according to any one of claims 5 to 7, wherein the width (Wa) of the upper layer (40a) and the respective widths (Wb) of the bottom layer (40b) are independent of each other and are smaller than or equal to the respective widths (W) of the surface separation region (29).

9. The apparatus according to any one of claims 1 to 8, wherein the surface isolation region (29) is the JFET region of the MOSFET transistor device (20).

10. In a method for manufacturing a MOSFET transistor device (20), It has a first conductivity type and forms a functional layer (24) made of silicon carbide. Each gate structure (30) having a dielectric region (31) and an electrode region (32) is formed on the upper surface (24a) of the functional layer (24). Body wells (26) having a second conductivity type different from the first conductivity type are formed within the functional layer (24), separated from each other by the surface separation region (29) of the functional layer (24). Source regions (27) having the first conductivity type are formed within the main body well (26) on the lateral and partially downward sides of each gate structure (30). It includes the fact that, furthermore, The method comprises forming a modified doping region (40) by placing it within the surface separation region (29) of the functional layer (24) on the lower side of each gate structure (30), wherein the modified doping region (40) has the first conductivity type and a doping concentration that is reduced compared to the doping concentration of the functional layer (24), and wherein the modified doping region (40) extends transversely across the entire width of each surface separation region (29) and terminates in the main body well (26).

11. The method according to claim 10, wherein forming the modified doping region (40) includes performing localized injection within the surface separation region (29) for the purpose of partially deactivating the doping of the first conductivity type of the functional layer (31).

12. The method according to claim 11, wherein the localized injection comprises injecting atoms of a second conductivity type into the surface separation region (29), the injection providing counter-doping and thus resulting in partial inactivation of the doping of the functional layer (24), and thus forming a modified doping region (40) having a reduced net doping concentration.

13. The method according to claim 11, wherein performing localized injections includes performing injections of aluminum atoms in the surface separation region (29), which damages and thus inactivates the doping in the surface separation region (29), resulting in the formation of a modified doping region (40) having a reduced net doping concentration.

14. A method for manufacturing a MOSFET transistor device (20), It has a first conductivity type and forms a functional layer (24) made of silicon carbide. Each gate structure (30) having a dielectric region (31) and an electrode region (32) is formed on the upper surface (24a) of the functional layer (24). Body wells (26) having a second conductivity type different from the first conductivity type are formed within the functional layer (24), separated from each other by the surface separation region (29) of the functional layer (24). Source regions (27) having the first conductivity type are formed within the main body well (26) on the lateral and partially downward sides of each gate structure (30). It includes the fact that, furthermore, This includes forming a modified doping region (40) by placing it within the surface separation region (29) of the functional layer (24) on the lower side of each gate structure (30), wherein the modified doping region (40) has the first conductivity type and has a doping concentration that is reduced compared to the doping concentration of the functional layer (24), A method comprising forming the functional layer (24) by forming a first epitaxial layer (24') on a substrate (22) having a desired doping concentration for the functional layer (24) and the first conductivity type, and forming the modified doping region (40) by forming a second epitaxial layer (24'') having the modified dopant concentration on the first epitaxial layer (24').

15. The method according to claim 14, wherein forming the main body well (26) and forming the source region (27) includes performing injections on the surface portion of the functional layer and adjusting the concentration of surface doping in the injection region taking into account the doping already present in the second epitaxial layer (24"),

16. The method according to any one of claims 10 to 15, wherein the modified doping region (40) is located below the dielectric region (31) of each gate structure (30) and is centered with respect to the surface isolation region (29).

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