Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device that can be prevented from being deteriorated in characteristics, and a method of manufacturing the semiconductor device.SOLUTION: A semiconductor device comprises: a silicon substrate which has a first surface and a second surface on the opposite side from the first surface, and contains oxygen as impurities; a first electrode provided on the first surface; a second electrode provided on the second surface. The silicon substrate comprises: an n-type drift layer having a higher impurity density toward the second surface side; an n-type first buffer layer provided on the drift layer on the second surface side and including protons as impurities; and a second buffer layer on the first buffer layer on the second surface side.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 contains, N - An insulated gate bipolar transistor (IGBT) is disclosed in which there is at least one location where the impurity concentration in the drift layer is maximum. - The impurity concentration in the drift layer decreases from the point where the impurity concentration is maximum toward the P-base layer and P-collector layer. Furthermore, at least N - The areas in the drift layer where the impurity concentration is maximum contain oxygen atoms and elements lighter than oxygen. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2008-91853 [Overview of the project] [Problems that the invention aims to solve]

[0004] Patent Document 1 uses a Floating Zone (FZ) wafer as the Si wafer. In Patent Document 1, protons are introduced into the Si from the emitter electrode side where the IGBT MOS (Metal-Oxide-Semiconductor) transistor is formed by proton irradiation, forming an impurity profile in the drift layer. As a result, charged particles, which are protons, pass through the MOS transistor region. Consequently, degradation of the MOS transistor characteristics and the gate oxide film characteristics constituting the MOS gate structure may occur.

[0005] The present disclosure has been made to solve the above problems, and an object thereof is to obtain a semiconductor device capable of suppressing deterioration of characteristics and a method for manufacturing the semiconductor device.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure has a first surface and a second surface opposite to the first surface, a silicon substrate containing oxygen as an impurity, a first electrode provided on the first surface, and a second electrode provided on the second surface. The silicon substrate includes an n-type drift layer having an impurity concentration higher on the second surface side, an n-type first buffer layer provided on the second surface side of the drift layer and containing protons as an impurity, and a second buffer layer provided on the second surface side of the first buffer layer. , the oxygen concentration of the drift layer O i [cm -3 ] is the impurity concentration of the drift layer Cn[cm -3 When ], 1.00 × 10 17 ln(C n )-2.84×10 18 ≦O i ≦9.40×10 16 ln(C n )-2.27×10 18 satisfies 。

[0007] The method for manufacturing a semiconductor device according to the present disclosure is manufactured by a magnetic-applied Czochralski (MCZ) method. A semiconductor layer is formed on the first surface side of a silicon wafer having an n-type drift layer, ion implantation is performed on the second surface opposite to the first surface of the silicon wafer, and annealing is performed to form a second buffer layer. After forming the second buffer layer, protons (H + ) are implanted at a position deeper from the second surface than the second buffer layer, and after implanting the protons, annealing is performed on the protons to form a first buffer layer. And the oxygen concentration of the drift layer O i [cm -3 ] is the impurity concentration of the drift layer Cn[cm -3 When ], 1.00 × 10 17 ln(C n )-2.84×10 18 ≦O i ≦9.40×10 16 ln(C n )-2.27×10 18 satisfies . [Effects of the Invention]

[0008] In the semiconductor device and method for manufacturing the semiconductor device described herein, an impurity profile of the drift layer can be formed by combining a silicon substrate containing oxygen as an impurity or a silicon wafer manufactured by the MCZ method with an n-type first buffer layer containing protons as impurities. Therefore, degradation of characteristics such as MOS transistor characteristics can be suppressed. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view of the semiconductor device according to Embodiment 1. [Figure 2A] This is a cross-sectional view of the IGBT according to Embodiment 1. [Figure 2B] This is a cross-sectional view of a diode according to Embodiment 1. [Figure 2C] This is a cross-sectional view showing another example of the diode according to Embodiment 1. [Figure 3A] This figure shows the impurity profile of the drift layer according to Embodiment 1. [Figure 3B] This diagram illustrates the effect of the buffer layer on the impurity profile of the drift layer. [Figure 3C] This is the calculation result of the impurity profile in the depth direction of hydrogen concentration. [Figure 4] This figure shows the relationship between the change in impurity concentration in the drift layer and its resistance to pressure. [Figure 5] This figure shows the relationship between oxygen concentration and impurity concentration in the drift layer of an MCZ wafer. [Figure 6]This figure shows the temperature dependence of the static breakdown voltage of a 3.3kV diode. [Figure 7] This figure shows the prototype results for the safe operating region in the dynamic state of a 3.3kV IGBT and a diode. [Figure 8] This is a diagram showing the waveform of RBSOA. [Figure 9] This is a diagram showing the waveform of SCSOA. [Figure 10] This figure shows the waveform of Recovery SOA. [Figure 11A] This figure shows the impurity profile according to Embodiment 2. [Figure 11B] This figure shows various impurity profiles for the first buffer layer. [Figure 11C] This figure shows the impurity profile of the first buffer layer according to a modified example of Embodiment 2. [Figure 12] This figure shows the waveform when a 1200V diode maintains its withstand voltage. [Figure 13] This figure shows the device characteristics of a 1200V diode. [Figure 14] This is a diagram showing the waveform of RBSOA. [Figure 15] This figure shows the waveform of Recovery SOA. [Figure 16A] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16B] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16C] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16D] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16E] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16F] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16G] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16H] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16I] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16J] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16K] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16L] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 16M] This is a diagram illustrating the method for manufacturing IGBTs according to Embodiment 3. [Figure 17] This is a flowchart showing the method for forming a vertical structure according to Embodiment 3. [Figure 18A] This is a diagram illustrating the method for manufacturing a diode according to Embodiment 4. [Figure 18B] This is a diagram illustrating the method for manufacturing a diode according to Embodiment 4. [Figure 18C] This is a diagram illustrating the method for manufacturing a diode according to Embodiment 4. [Figure 18D] This is a diagram illustrating the method for manufacturing a diode according to Embodiment 4. [Figure 18E] This is a diagram illustrating the method for manufacturing a diode according to Embodiment 4. [Figure 18F] This is a diagram illustrating the method for manufacturing a diode according to Embodiment 4. [Figure 18G] This is a diagram illustrating the method for manufacturing a diode according to Embodiment 4. [Figure 18H] This is a diagram illustrating the method for manufacturing a diode according to Embodiment 4. [Figure 18I] This is a diagram illustrating the method for manufacturing a diode according to Embodiment 4. [Figure 19] This is a flowchart showing the method for forming a vertical structure according to Embodiment 4. [Figure 20] This flowchart shows a method for forming a vertical structure according to a modified example of Embodiment 4. [Figure 21] This is a cross-sectional view showing an example of a semiconductor device according to Embodiment 5. [Figure 22] This is a cross-sectional view showing an example of a semiconductor device according to Embodiment 5. [Figure 23] This is a cross-sectional view showing an example of a semiconductor device according to Embodiment 5. [Figure 24] This is a cross-sectional view showing an example of a semiconductor device according to Embodiment 5. [Figure 25] This is a cross-sectional view showing an example of a semiconductor device according to Embodiment 5. [Figure 26] This is a cross-sectional view showing an example of a semiconductor device according to Embodiment 5. [Figure 27] This is a cross-sectional view showing an example of a semiconductor device according to Embodiment 5. [Figure 28] This is a cross-sectional view showing an example of a semiconductor device according to Embodiment 5. [Modes for carrying out the invention]

[0010] Semiconductor devices and methods for manufacturing semiconductor devices according to each embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repetition of the description may be omitted.

[0011] Embodiment 1. Figure 1 is a plan view of a semiconductor device 100 according to Embodiment 1. The semiconductor device 100 is, for example, a power semiconductor chip. The active cell area 1 is an area that guarantees the basic performance of the power semiconductor chip. The interface area 2 is the area where the active cell area 1 and the edge termination area 3 join. The interface area 2 supports the breakdown withstand capability during dynamic operation of the power semiconductor and supports the inherent performance of the active cell area 1. The edge termination area 3 is provided to maintain breakdown withstand capability in a static state and to guarantee the stability and reliability of the breakdown withstand capability characteristics. The edge termination area 3 further suppresses breakdown withstand capability failures during dynamic operation and supports the inherent performance of the active cell area 1.

[0012] The above areas enable improved total loss performance, improved leakage characteristics during voltage holding at high temperatures, guaranteed reliability, improved controllability during dynamic operation, and guaranteed breakdown tolerance. Total loss includes on-state loss, turn-on loss, and turn-off loss. The semiconductor device 100 further includes a surface gate wiring section 4 and a gate pad section 39. For example, if the semiconductor device 100 is a diode, the surface gate wiring section 4 and gate pad section 39 may not be present.

[0013] Figure 2A is a cross-sectional view of an IGBT 101 according to Embodiment 1. Figure 2B is a cross-sectional view of a diode 102 according to Embodiment 1. Figure 2C is a cross-sectional view showing another example of a diode 103 according to Embodiment 1. The semiconductor device 100 is, for example, an IGBT or a diode as shown in Figures 2A to 2C. Figures 2A to 2C are cross-sectional views obtained by cutting Figure 1 along the line A-A'. Diode 102 has a pin diode structure. Diode 103 has an RFC (Relaxed Field of Cathode) diode structure. The diodes in this embodiment may be power diodes or freewheeling diodes (FWDs).

[0014] The semiconductor device 100 comprises a silicon substrate having a first surface and a second surface opposite to the first surface, a first electrode 5 provided on the first surface, and a second electrode 21 provided on the second surface. The silicon substrate has an impurity concentration that is higher towards the second surface. - It has a drift layer 15 of type n. On the second side of the drift layer 15, an n-type buffer layer 16 containing protons as impurities is provided. On the second side of the buffer layer 16, a buffer layer 17 is provided. Of the two types of buffer layers 16 and 17, only buffer layer 16 is in contact with the drift layer 15. Hereafter, the first side may be referred to as the Front side and the second side as the Back side.

[0015] The drift layer 15 has phosphorus or antimony as a dopant. The drift layer 15 has an impurity concentration of C n- is 1.0 × 10 12 ~5.0×10 14 atoms / cm 3 Formed using silicon wafers manufactured by the MCZ method. Final device thickness t device The diameter is 40-700 μm. Phosphorus or antimony is used as the n-type dopant during MCZ wafer manufacturing. This results in the impurity concentration C in the crystal axis direction of the Si single crystal ingot, which is caused by the segregation phenomenon of the dopant due to the increased diameter. n- This can suppress variations. In particular, antimony has an evaporation rate about three orders of magnitude higher than phosphorus. The evaporation rate of P is 1.6 × 10⁻⁶ -4 The evaporation rate of Sb is 1.3 × 10¹⁶ cm / sec. -1 The rate is cm / sec. By using evaporation control technology that takes advantage of this characteristic to produce Si single crystals, the impurity concentration C in the crystal axis direction of the Si single crystal ingot can be reduced. n- This significantly reduces the variability.

[0016] In diodes 102 and 103, the drift layer 15 is the region from the main junction 12 on the front side to the junction 22 on the back side. In IGBT 101, the drift layer 15 and the semiconductor layer 11 are provided between the main junction 12 and the junction 22. The main junction 12 is the junction where the electric field strength is maximum when the depletion layer extends to the back side to maintain the voltage when a reverse bias is applied in the power semiconductor. The junction 22 is the junction where the depletion layer extending from the main junction 12 to the back side first makes contact when the voltage is maintained, and it is the junction where the electric field strength is second highest when the voltage is maintained.

[0017] Furthermore, buffer layers 16 and 17 are provided on the IGBT 101 and diodes 102 and 103. Buffer layer 16 enables reduced loss during off-state operation and improved controllability and breakdown tolerance during dynamic operation. Buffer layer 17 enables stable voltage maintenance in the off state.

[0018] In the IGBT 101 shown in Figure 2A, an n-type semiconductor layer 11 is provided on the first surface side of the drift layer 15. The semiconductor layer 11 is formed deeper than the base layer 9 on the first surface side of the drift layer 15. The semiconductor layer 11 has the effect of increasing the carrier concentration on the first surface side when the IGBT is in the ON state. This makes it possible to lower the ON voltage of the IGBT. A p-type base layer 9 is provided on the first surface side of the n-type semiconductor layer 11. + emitter layer 7 and p + A semiconductor layer 8 of a certain type is provided.

[0019] A trench 24 is formed on the first surface of the silicon substrate. The trench 24 penetrates the emitter layer 7 and the base layer 9. A gate electrode 14 is provided inside the trench 24. A first electrode 5 is provided on the gate electrode 14 via an interlayer film 6. In the IGBT 101, the first electrode 5 is the emitter electrode. A p-type collector layer 18 is provided on the second surface side of the buffer layer 17. A second electrode 21 is provided in contact with the collector layer 18. In the IGBT 101, the second electrode is the collector electrode.

[0020] In the MOS transistor section, a portion of the trench 24 is at the same potential as the first electrode 5, which is at the emitter potential. The first electrode 5 is, for example, an aluminum wire. This structure enables suppression of the IGBT's saturation current density, suppression of oscillation in no-load short-circuit conditions by controlling the capacitance characteristics, improvement of short-circuit withstand capability, and low ON voltage by improving the carrier concentration on the emitter side.

[0021] In the diode 102 shown in Figure 2B, a p-type anode layer 10 is provided on the first surface side of the drift layer 15. A first electrode 5 is provided on the anode layer 10. In the diode 102, the first electrode 5 is the anode electrode. On the second surface side of the buffer layer 17, n + A cathode layer 19 of a certain type is provided. The cathode layer 19 is in contact with the second electrode 21. In the diode 102, the second electrode 21 is the cathode electrode.

[0022] Diode 103, shown in Figure 2C, differs from diode 102 in that it further includes a p-type cathode layer 20. The cathode layer 20 is provided on the second surface side of the buffer layer 17 and is aligned with the cathode layer 19 in the direction along the second surface. Multiple cathode layers 19 and 20 are provided alternately in the direction along the second surface.

[0023] Examples of parameters for each diffusion layer and trench in IGBT101 are described below. In the following, impurity concentration refers to the concentration of elements other than Si. Elements that form the diffusion layer are called dopants. • p-type base layer 9 Dopant: Boron, Peak impurity concentration: 1.0 × 10⁻⁶ 16 ~1.0×10 18 atoms / cm 3 Depth: Deeper than emitter layer 7 and shallower than semiconductor layer 11 n-type semiconductor layer 11 Dopant: Arsenic or phosphorus, Peak impurity concentration: 1.0 × 10⁻⁶ 15 ~1.0×10 17 atoms / cm 3 Depth: 0.5-1.0 μm deeper than the base layer 9. ·n + Type emitter layer 7 Dopant: Arsenic, Phosphorus; Peak impurity concentration: 1.0 × 10⁻⁶ 18 ~1.0×10 21 atoms / cm 3 Depth: 0.2~1.0μm ·p + Semiconductor layer 8 Dopant: Boron, Surface impurity concentration: 1.0 × 10⁻⁶ 18 ~1.0×10 21 atoms / cm -3 Depth: Same as or deeper than emitter layer 7. n-type buffer layer 16 Dopant: Proton, peak impurity concentration C P,n2n ≤0.01 × C P,n1 , depth X j,nb2 :X j,n1 +20~30μm n-type buffer layer 17 Dopant: Arsenic or phosphorus, peak impurity concentration C p,n1 :1.0×10 15 ~5.0×10 16 atoms / cm 3 , depth X j,n1 : 1.0~30μm p-type collector layer 18 Dopant: Boron, Peak impurity concentration: 1.0 × 10⁻⁶ 16 ~1.0×10 20 atoms / cm 3 Depth: 0.3~0.8μm Trench depth D trench : Depth deeper than the n-type semiconductor layer 11 (2.0 μm)

[0024] Examples of parameters for each diffusion layer of diode 102 are described below. • p-type anode layer 10 Dopant: Boron, Surface impurity concentration: 1.0 × 10⁻⁶ 16 atoms / cm 3 In summary, peak impurity: 2.0 × 10⁻⁶ 16 ~1.0×10 18 atoms / cm 3 Depth: 2.0~10.0 μm n-type buffer layer 16 Dopant: Proton, peak impurity concentration C P,n2n ≤0.01×C P,n1 , depth X j,nb2 : X j,n1 +20 to 30 μm ·n-type buffer layer 17 Dopant: Arsenic or phosphorus, peak impurity concentration C P,n1 : 1.0×10 15 ~5.0×10 16 atoms / cm 3 , depth X j,n1 : 1.0 to 30 μm ·n + -type cathode layer 19 Dopant: Arsenic, phosphorus, peak impurity concentration: 1.0×10 17 ~1.0×10 19 atoms / cm 3 , depth: 0.3 to 0.5 μm

[0025] Examples of the parameters of each diffusion layer of the diode 103 will be described. ·p-type anode layer 10 Dopant: Boron, surface impurity concentration: 1.0×10 16 atoms / cm 3 or more, peak impurity: 2.0×10 16 ~1.0×10 18 atoms / cm 3 , depth: 2.0 to 10.0 μm ·n-type buffer layer 16 Dopant: Proton, peak impurity concentration C P,n2n ≤0.01×C P,n1 , depth X j,nb2 : X j,n1 +20 to 30 μm ·n-type buffer layer 17 Dopant: Arsenic or phosphorus, peak impurity concentration C P,n1 : 1.0×10 15 ~5.0×10<000偶094>atoms / cm 3 , depth X j,n1 : 1.0 to 30 μm ·n + -type cathode layer 19 Dopant: Arsenic, Phosphorus; Peak impurity concentration: 1.0 × 10⁻⁶ 17 ~1.0×10 19 atoms / cm 3 Depth: 0.3~0.5μm p-type cathode layer 20 Dopant: Boron, Peak impurity concentration: 1.0 × 10⁻⁶ 16 ~1.0×10 18 atoms / cm 3 Depth: 0.3~0.5μm

[0026] In the following, the drift layer 15, buffer layers 16 and 17, and collector layer 18 in IGBT101 may be referred to as the vertical structure 38. Similarly, the drift layer 15, buffer layers 16 and 17, and cathode layer 19 in diode 102, and the drift layer 15, buffer layers 16 and 17, and cathode layers 19 and 20 in diode 103 may be referred to as the vertical structure 38.

[0027] In MCZ wafers, impurities such as oxygen and nitrogen are introduced during Si wafer manufacturing. Among these impurities, oxygen atoms cause a thermal donor phenomenon at a specific annealing temperature. The thermal donor phenomenon is a phenomenon in which oxygen atoms in the MCZ wafer become donors in a specific temperature range. In this embodiment, this thermal donor phenomenon is utilized to control the impurity concentration of the drift layer 15 to a characteristic impurity profile that increases from the main junction 12 toward the junction 22. This suppresses adverse effects on the off-state voltage holding ability, i.e., the static breakdown voltage characteristics, and improves the controllability and breakdown withstand capability during dynamic operation.

[0028] The oxygen and nitrogen introduced during the manufacturing of MCZ wafers are present in the interstitial and substitutional positions, respectively, within the Si single crystal. Oxygen concentration O i The nitrogen concentration C is two to three orders of magnitude higher in MCZ wafers than in FZ wafers. sThis is equivalent to that of an FZ wafer in an MCZ wafer. In this embodiment, protons are injected from the back side and diffused from the back side to the front side, utilizing the oxygen-induced thermal donor phenomenon. This makes it possible to form a characteristic impurity profile in which the impurity concentration of the drift layer 15 increases from the main junction 12 toward the junction 22.

[0029] Figures 3A to 3C show the impurity profiles along the C-C' line in Figure 2. Figure 3A is a diagram showing the impurity profile of the drift layer 15 according to Embodiment 1. In Figure 3A, "new structure" shows the impurity profile of this embodiment, and "con. structure" shows the impurity profile of the comparative example. The comparative example differs from this embodiment in that it uses an FZ wafer. The impurity concentration of the drift layer 15 in this embodiment is higher than that of the comparative example, compared to the X of the main junction 12. j,MJ X from joint 22 j、n2n It slopes gently upward toward the end. The impurity concentration in the drift layer 15 may continue to rise from the junction between the drift layer 15 and the layer provided on the first surface side of the drift layer 15 up to the junction between the drift layer 15 and the buffer layer 16.

[0030] Figure 3B illustrates the effect of the buffer layer 16 on the impurity profile of the drift layer 15. Figure 3B shows the impurity profiles for both the new structure and the con. structure, with and without the buffer layer 16. Note that the buffer layer 17 is present in all samples shown in Figure 3B. The horizontal axis of Figures 3A and 3B is the same as the t shown in Figure 2. device It is standardized as follows. In Figure 3B, it can be seen that a profile in which the impurity concentration increases towards the second surface can be obtained by using only the new structure with an MCZ wafer and the buffer layer 16.

[0031] Figure 3C shows the calculated impurity profile in the depth direction of hydrogen concentration. The buffer layer 16 is formed by injecting protons from the back side. critical H + 1 and critical H + 2 represents the critical hydrogen atoms when one and two oxygen atoms diffuse, respectively. + It is the concentration. The hydrogen concentration is the critical level required for oxygen to diffuse. + It's one to three orders of magnitude higher than the concentration.

[0032] Protons have the effect of increasing the rate of oxygen diffusion. Therefore, H + The presence of oxygen promotes the oxygen-induced thermal donor phenomenon. Hydrogen introduced from the back side diffuses to the front side through annealing during the formation of the buffer layer 16, as described later. For this reason, thermal donor formation is more easily promoted on the back side than on the front side. Consequently, the combination of oxygen in the drift layer 15 and protons in the buffer layer 16 can form an impurity profile of hydrogen element in which the concentration decreases gradually towards the front side.

[0033] Figure 4 shows the relationship between the change in impurity concentration of the drift layer 15 and the breakdown voltage. Figure 4 shows the results of a simulation performed with a 6.5kV IGBT. The horizontal axis shows the change in impurity concentration relative to the impurity concentration of the con. structure. 100% represents the impurity concentration of the drift layer 15 in the con. structure in Figure 3A. The vertical axis shows the static breakdown voltage (BV) at 218K. When the change is greater than 20%, or 120% on the horizontal axis, the breakdown voltage at 218K falls below the rated voltage of 6500V. Therefore, it is preferable that the change in impurity concentration of the drift layer 15 is 20% or less relative to the impurity concentration of the drift layer 15 in the con. structure. In other words, it is desirable that the change in impurity concentration in the drift layer 15 be 20% or less.

[0034] Figure 5 shows the oxygen concentration in the MCZ wafer. i and the impurity concentration C of the drift layer 15 n-This figure shows the relationship. When a donor layer is formed by the thermal donor phenomenon in an MCZ wafer, the impurity concentration C n- It rises. Minimum [O i ] and maximum[O i These are expressed by the relationships in equation (1) and equation (2), respectively.

[0035]

number

[0036]

number

[0037] Here, minimum[O i ] utilizes the oxygen-induced thermal donor phenomenon in the MCZ wafer to achieve the minimum [O i The value is maximum[O i ] is due to oxygen-induced thermal donor formation in MCZ wafers. n- Even if the voltage changes, the [O] maintains the power semiconductor's basic performance of holding the off-state voltage. i This is the limit value of ].

[0038] maximum[O i ] and minimum[O i ] Oxygen concentration O i By controlling C n- Even if the oxygen concentration of the drift layer 15 changes, the adverse effects on the power semiconductor's basic performance, which is its off-state voltage holding ability, i.e., its static breakdown voltage characteristics, can be suppressed. i and impurity concentration C n- is minimum[O i ]≦O i ≤maximum[O i It is desirable to satisfy the following conditions.

[0039] Figure 6 shows the static breakdown voltage (BV) of a 3.3kV diode. RThis figure shows the temperature dependence of the measurement. In Figure 6, new device A measures the oxygen concentration at maximum[O i ] and minimum[O i It is a device controlled during ]. new deviceB is [O i ] to maximum[O i This device has a higher concentration than [new device A]. The impurity profiles of the drift layer 15 of new device A and B are both characteristic impurity profiles shown in Figure 3A. However, new device B has a higher impurity concentration C due to the thermal donor phenomenon by oxygen than new device A. n- This is a diode with a large increase in performance.

[0040] As a result, new device A exhibits the same voltage withstand capability as con. device, but new device B cannot maintain the rated voltage of 3300V in the 3.3kV class even at 298K, and its voltage holding capability in the off state is reduced.

[0041] Figure 7 shows the results of a prototype of the safe operating area (SOA) in the dynamic state of a 3.3kV IGBT diode. The impurity profiles of the drift layer 15 of the con. device and the new device in Figure 7 are the same as the impurity profiles of the con. structure and the new structure in Figure 3A, respectively. In the new device, maximum[O i ] and minimum[O i [O i MCZ wafers with controlled [specific properties] are used. FZ wafers are used in con. devices.

[0042] In Figure 7, J C (break) is the maximum break current density during IGBT in L-load switching. Max. power density is the maximum break power density during IGBT turn-off operation or diode recovery operation during L-load switching. WThis is the maximum interruption gate pulse width of the IGBT under no-load short circuit conditions. SC dj / dt is the maximum interruption short-circuit energy of the IGBT under no-load short circuit. A This represents the gradient of the waveform, specifically the maximum gradient at which the signal is cut off.

[0043] The new device, which has the characteristic impurity profile of the drift layer 15 of this embodiment, exhibits an expanded SOA compared to the con. device, in both IGBTs and diodes. This is a result of controlling the interaction between the carrier plasma layer and the electric field strength inside the device under dynamic conditions. The carrier plasma layer is a layer formed by conductivity modulation when electrons and holes are injected into the drift layer 15 when the device is ON. The carrier plasma layer is a neutral layer where n ≈ p, where n is the electron concentration and p is the hole concentration. Controlling this carrier plasma layer is important for improving the performance of power semiconductors such as IGBTs and diodes.

[0044] Figure 8 shows the waveform of RB (Reverse-Bias) SOA. Figure 9 shows the waveform of SC (Short Circuit) SOA. Figure 10 shows the waveform of Recovery SOA. In Figures 8 and 10, it can be seen that the new device can interrupt even under conditions that would cause the con. device to fail, indicating a higher breakdown withstand capability. Figure 9 shows the waveform at maximum interruption in short-circuit mode, and it can be seen that the new device can interrupt under conditions with a longer pulse width than the con. device, indicating a higher breakdown withstand capability in short-circuit mode.

[0045] Thus, according to this embodiment, controllability and breakdown resistance during dynamic operation can be improved without adversely affecting the voltage holding capability in the off state. Furthermore, in this embodiment, by combining a silicon substrate manufactured by the MCZ method containing oxygen as an impurity with a buffer layer 16 containing protons as an impurity, an impurity profile of the drift layer 15 can be formed in which the impurity concentration is higher on the second surface side. Therefore, the impurity profile of the drift layer 15 can be formed without protons passing through the MOS transistor region due to proton irradiation. Consequently, degradation of MOS transistor characteristics and gate oxide film characteristics can be suppressed.

[0046] Furthermore, the concentration of carbon [Cs], another impurity element introduced during the manufacturing process within the MCZ wafer, is 1.0 × 10⁻⁶. 14 ~5.0×10 15 atoms / cm -3 It's an order.

[0047] In this embodiment, an example in which the semiconductor device 100 is an IGBT or a diode has been described, but the semiconductor device 100 may also be an RC (Reverse-Conducting)-IGBT. In other words, the silicon substrate in the semiconductor device 100 may have an IGBT region and a diode region. The IGBT region can employ the structure of IGBT 101. For the diode region, either the diode 102 or 103 structure may be employed.

[0048] The modifications described above can be appropriately applied to the semiconductor device and method for manufacturing the semiconductor device according to the following embodiments. Since the semiconductor device and method for manufacturing the semiconductor device according to the following embodiments have many similarities with Embodiment 1, the differences from Embodiment 1 will be the focus of this explanation.

[0049] Embodiment 2. Figure 11A shows the impurity profile according to Embodiment 2. Figure 11A shows the impurity profile along the C-C' line in Figure 2. In this embodiment, the impurity profile of the buffer layer 16 differs from that of Embodiment 1. The other configurations are the same as in Embodiment 1. The impurity concentration of the buffer layer 16 has multiple peaks in the thickness direction of the silicon substrate. The impurity concentration of the multiple peaks increases as it approaches the buffer layer 17.

[0050] In other words, buffer layer 16 consists of multiple n-type layers n 2n It can also be said that it includes multiple layers n. 2n Peak concentration C p,n2n This is the junction X of buffer layers 16 and 17. j,n1 From the junction X of buffer layer 16 and drift layer 15 j,n2n It decreases in the direction. In the example in Figure 11A, there are n=2 peaks in buffer layer 16. The peak concentration of buffer layer 17 is C p,21 The peak concentrations of buffer layer 16 are measured from C, starting from the one closest to buffer layer 17. p,n21 , C p,n22 Therefore, C p,n22 <C p,n21 <C p,21 This is the result.

[0051] Figure 11B shows the impurity profiles of various buffer layers 16. Figure 11B shows the impurity profile along the B-B' line in Figure 2. The new profile is the impurity profile of this embodiment, and C p,n22 <C p,n21 <C p,21 The results are as follows: In con. profile1, there is only one peak in the impurity concentration of buffer layer 16. In con. profile2, the peak in the impurity concentration of buffer layer 16 decreases as it approaches buffer layer 17. Con. profile3 is a profile of an almost constant impurity concentration in buffer layer 16, with no peaks in the impurity concentration.

[0052] In con. profile1', there is a region 37 in the buffer layer 16 with a lower impurity concentration than that of the drift layer 15. The buffer layer 16 is formed by introducing H + It is formed when it reacts with point defects in Si to form a composite defect, which then becomes a donor layer. Region 37 is H + It does not diffuse in the back side direction, and point defects in Si and H + H required for the reaction + This results in a state where H does not exist. + This is a layer formed due to unreacted point defects in Si.

[0053] H + The behavior of not diffusing in the back side direction is due to the oxygen concentration in the MCZ wafer. i It depends on the oxygen concentration. The higher the oxygen concentration, the more H will be involved in the complex defects caused by oxygen in Si. + H was trapped, + The diffusion of is inhibited. Compound defects include, for example, VO (Vacancy-Oxygen pair), C i O i (Interstitial Carbon-Interstitial Oxygen pair), V2 (di-Vacancy). H + When trapped, VOH, C i O i H n , it becomes V2H2.

[0054] In contrast, in the new profile corresponding to this embodiment, the impurity concentration of the buffer layer 16 has multiple peaks. This structure is achieved by ion implantation using multiple acceleration energies, as will be described later. + This is obtained by introducing H into Si from the back side. At this time, H is used at a high oxygen concentration. + Even if H cannot diffuse in the back side direction, + This compensates for the lack of impurities. As a result, it is possible to prevent the formation of a region 37 with an impurity concentration lower than that of the drift layer 15, as shown in the new profile in Figure 11B.

[0055] Figure 11C shows the impurity profile of the buffer layer 16 according to a modified example of Embodiment 2. As shown in new profiles 1 and 2, the buffer layer 16 may have three or more impurity concentration peaks. As shown in new profile 3, the impurity concentration peaks are on the first surface side of the buffer layer 16 and The They may be provided separately on two sides. device It is standardized.

[0056] Figure 12 shows the waveform of diode 103 during voltage breakdown. Figure 12 shows the waveform of a 1200V diode having the structure of diode 103 during voltage breakdown at 298K. The diode with con. profile 1' has a low concentration region 37. Therefore, the main junction X is connected to region 37. J,MJ A characteristic leakage pattern is observed where the leakage current increases when the depletion layer extending from the source is reached. This results in a decrease in voltage resistance and loss during off-mode = V R ×J R This leads to an increase in leakage current. On the other hand, according to the new profile of this embodiment, there is no sudden increase in leakage current, and the voltage withstand capability can be maintained.

[0057] Figure 13 shows the device characteristics of diode 103. In Figure 13, the device characteristics of a 1200V diode having the structure of diode 103 are shown for con. profiles 2 and 3 and the new profile shown in Figure 11B. In the new profile of this embodiment, the ON voltage V is lower compared to con. profiles 2 and 3. F While achieving this, the leakage current J when maintaining 1200V R It is small. Furthermore, it allows for a wider range of SOA in dynamic conditions.

[0058] In this embodiment, the diode having a new profile of the buffer layer 16 has a depletion layer that is the main junction X during dynamic operation. J、MJThis allows for a gradual expansion of the depletion layer as it reaches the buffer layer 16, while retaining carriers on the back side. This behavior is due to its ability to control the interaction between the carrier plasma layer and the electric field strength during the dynamic operation of the IGBT or diode.

[0059] Furthermore, in snappy mode, the maximum voltage V during recovery operation is snap-off The voltage can be lowered from the rated voltage of 1200V for a 1200V element. In this way, it is possible to suppress damage during dynamic operation and improve controllability, and in the high-current mode SOA, the break current density J during recovery operation A (break) can be increased.

[0060] Figure 14 shows the waveform of the RBSOA. Figure 14 shows the interruption capability under L-load switching conditions for a 3.3kV IGBT with con. profile 1 and the new profile shown in Figure 11B. The IGBT with the new profile of this embodiment has improved interruption capability compared to con. profile 1. In other words, even with IGBTs, the new profile of this embodiment enables dynamic SOA expansion.

[0061] Figure 15 shows the waveform of the Recovery SOA. Figure 15 also shows the cutoff capability under L-load switching conditions for a 3.3kV diode with con. profile 1 and the new profile shown in Figure 11B. The HV (High Voltage) diode with the new profile shows improved cutoff capability compared to con. profile 1.

[0062] Furthermore, the same results as those shown in Figures 13 to 15 can be obtained with the modified impurity profiles of the buffer layer 16 of this embodiment shown in Figure 11C, namely new profiles 1 to 3.

[0063] Furthermore, the new profile of the buffer layer 16 in this embodiment alone has the effect of controlling the interaction between carrier concentration and electric field strength during the dynamic operation of the IGBT or diode. For this reason, the buffer layer 16 of this embodiment, which has multiple peaks in the impurity concentration, may be applied to an FZ wafer.

[0064] Embodiment 3. The manufacturing methods for IGBT101 according to Embodiments 1 and 2 will be described. Figures 16A to 16M illustrate the manufacturing method for IGBT101 according to Embodiment 3. Figures 16A to 16M are cross-sectional views at positions corresponding to the line A-A' in Figure 1. First, a semiconductor layer is formed on the first surface of a silicon wafer having an n-type drift layer 15, manufactured by the MCZ method. Specifically, as shown in Figure 16A, after the formation of the oxide film 23, a base layer 9 and a semiconductor layer 11 are formed on the front side of the drift layer 15 by photolithography, etching, ion implantation, annealing technology, etc. Next, as shown in Figure 15B, an emitter layer 7 is partially formed on the front side by ion implantation and annealing technology.

[0065] Subsequently, as shown in Figure 16C, the trench 24 is formed by etching. Furthermore, the inner walls of the trench are cleaned, smoothed, and rounded using a combination of etching and oxidation techniques. Next, as shown in Figure 16D, a gate oxide film 13 is formed on the inner walls of the trench. Furthermore, the trench 24 is filled with a d-poly Si film that will become the gate electrode 14. The d-poly Si film contains, for example, n-type elements such as As and phosphorus in a 1x10⁻¹⁶ layer. 19 atoms / cm 3 This is a polysilicon film doped to the above high concentration.

[0066] Next, as shown in Figures 16E-H, in order to recover the carrier lifetime of the drift layer 15, a high concentration n is applied to the back surface of the wafer. + A gettering layer is formed consisting of layer 27 and a high crystal defect density layer 28. + Layer 27 has a surface concentration of 1.0 × 10⁻⁶ 20~1.0×10 22 cm -3 The depth is 1.0 to 10 μm. As a result, the carrier lifetime of the drift layer 15 will be greater than or equal to the value calculated by the following equation 3.

[0067]

number

[0068] Here, t N- The thickness (m) of the drift layer 15, τ t is the carrier lifetime (sec) in the drift layer 15 where the effect of carrier lifetime on the IGBT ON voltage disappears. In equation (3), t N- This is t in Figure 2. device This corresponds to the device parameter.

[0069] The ON voltage of the IGBT diode depends on the carrier lifetime of the drift layer 15. Equation (3) is an indicator of the carrier lifetime required to minimize this dependence. The carrier lifetime is calculated using equation (3) τ t By setting the parameters as described above, the impact of carrier lifetime on switching losses can be minimized. Furthermore, since off-loss is also affected by carrier lifetime, this allows for reduced off-loss and suppression of thermal runaway.

[0070] Next, the method for forming the gettering layer will be described in detail. First, as shown in Figure 16E, the d-poly Si film that will become the gate electrode 14, which is formed on the first surface of the wafer, is removed, an oxide film 25 is formed on the surface of the d-poly Si film, and an interlayer film 6 is formed on the first surface of the wafer. Next, as shown in Figure 16F, selective etching is performed only on the back surface of the wafer in order to expose the Si surface on the back surface of the wafer. This removes the gate oxide film 13 and the d-poly Si film on the back surface of the wafer. Hydrofluoric acid or a mixed acid solution is used for etching. The mixed acid is, for example, a mixture of hydrofluoric acid, nitric acid, and acetic acid.

[0071] Next, as shown in Figure 16G, high concentration n + As a source for forming layer 27 and high crystal defect density layer 28, high concentration n + Polysilicon 26 doped with the element forming layer 27 is formed by the LPCVD method. Polysilicon 26 is d-poly Si. High concentration n + As elements that form layer 27, for example, phosphorus, arsenic, antimony, etc., which diffuse into Si + Elements capable of forming layers can be selected. Polysilicon 26 has a layer size of 1 x 10⁻¹⁶. 19 atoms / cm 3 The above is a film doped with high-concentration impurities, and the film thickness is 500 nm or more. With polysilicon 26 doped with high-concentration impurities, the high-concentration impurities diffuse to the Si surface on the back of the wafer during subsequent annealing. As a result, high-concentration n + During the formation of layer 27, high-density dislocations and lattice defects, including a high-crystal defect density layer 28, are introduced.

[0072] Specifically, after depositing polysilicon 26, thermal annealing is performed at 900-1000°C in a nitrogen atmosphere. Next, the temperature is cooled from 900-1000°C to 500-700°C at an arbitrary rate, and thermal annealing is performed in a nitrogen atmosphere at a lower temperature than the previous annealing temperature. As a result, impurities diffuse from d-poly Si into Si on the back surface of the wafer where polysilicon 26 and Si are in direct contact. As a result, as shown in Figure 16H, high concentration n + Layer 27 is formed. Furthermore, high concentration n + When layer 27 is formed, crystal defects, i.e., a high crystal defect density layer 28, are secondarily generated.

[0073] By bringing polysilicon 26 and the Si surface, which have different coefficients of thermal expansion, into direct contact, the interface, i.e., the high concentration of n, is annealed using annealing technology. + Strain occurs in the surface layer of layer 27. As a result, high concentration n +Layer 27, the high-crystal defect density layer 28, and the strained layer present on the surface of polysilicon 26 act as getter sites. With this configuration, heavy metals and contaminating atoms incorporated into the wafer during the wafer process diffuse through the crystal lattice and move to the getter sites during annealing at 500-700°C. As a result, heavy metals and contaminating atoms can be captured.

[0074] This technology improves the τ of the drift layer 15, which had decreased in previous wafer processes. t This allows for the recovery of the carrier lifetime. In other words, as shown in equation (3), a drift layer 15 with a sufficiently long carrier lifetime can be realized without affecting the electrical characteristics of IGBTs of various voltage ratings.

[0075] In addition to polysilicon-26, similar effects can be obtained by forming a high-crystal defect density layer on the back surface of the wafer using laser annealing technology. This laser annealing technology is a localized annealing technique involving rapid heating and cooling using a laser with a wavelength of 500-1000 nm. In this case, the power density of the laser annealing is set to 4 J / cm². 2 This concludes the procedure. After this, annealing is performed in the same manner as the method using polysilicon 26. That is, thermal annealing is performed at 900-1000°C in a nitrogen atmosphere, then the temperature is lowered from 900-1000°C to 500-700°C at an arbitrary cooling rate, and then low-temperature thermal annealing is performed at 500-700°C in a nitrogen atmosphere. This causes heavy metals and contaminating atoms to move to the getter site, resulting in an improvement in carrier lifetime.

[0076] After the gettering layer is formed, the polysilicon 26 formed on the first surface of the wafer is removed, as shown in Figure 16I. Furthermore, as shown in Figure 16J, the interlayer film 6 is selectively removed, and n is applied to the first surface on the front side of the drift layer 15. + Type emitter layer 7 or p +Contact holes are formed to expose the Si surface of the semiconductor layer 8. Next, as shown in Figure 16K, a first electrode 5, which is an aluminum wiring film, is formed on the interlayer film 6 and in the contact holes using sputtering technology. The first electrode 5 has a laminated structure consisting of an aluminum-based metal with Si or Cu added to Al, a barrier metal 40, and a silicide layer 41 formed by the reaction of the exposed Si and the metal. The aluminum-based metal is, for example, AlSi, AlSiCu, or AlCu. The barrier metal 40 is, for example, TiN or TiW. The silicide layer 41 is, for example, TiSi2, PtSi, or CoSi. Next, as shown in Figure 16L, a passivation film 30 is formed on the first electrode 5. Furthermore, polysilicon 26 and high-concentration n + Layer 27 and the high crystal defect density layer 28 are removed by a polishing process and a subsequent wet etching process.

[0077] Next, as shown in Figure 16M, a vertical structure 38 including buffer layers 16 and 17 is formed. Figure 17 is a flowchart showing the method for forming the vertical structure 38 according to Embodiment 3. On the first surface side where the vertical structure 38 is not formed, the MOS transistor structure constituting the IGBT, aluminum wiring, and passivation film 30 are already present. Therefore, when forming the buffer layers 16 and 17 and the collector layer 18 that constitute the vertical structure 38, the temperature on the first surface side is lower than the melting point of the first electrode 5, i.e., the melting point of aluminum, 660°C. In other words, considering the temperature gradient in the device depth direction, laser annealing using a laser with a wavelength that does not transfer heat to the first surface, or annealing in a low-temperature diffusion furnace below the metal melting point is selected.

[0078] Furthermore, buffer layers 16 and 17 have a thickness equal to the device thickness shown in Figure 16L, i.e., t device It is formed after a process that precisely forms particles of 40-700 μm. At this time, high concentration n + Layer 27, the high-crystal defect density layer 28, and the polysilicon 26 are removed. However, the carrier lifetime of the drift layer 15 satisfies equation (3).

[0079] In Figure 17, the front side protective film formation step (S1) corresponds to the passivation film 30 formation step described above. Polishing (S2) and etching (S3) correspond to the steps shown in Figure 16L.

[0080] In the process of this embodiment, the order in which buffer layers 16 and 17 are formed and the setting of the peak position of the acceleration energy when buffer layer 16 is introduced are important. In this embodiment, as shown in Figures 16A to L, after forming a semiconductor layer on the first side of the silicon wafer, ion implantation is performed on the second side of the silicon wafer (S4), and annealing is performed (S5) to form buffer layer 17. After forming buffer layer 17, protons are implanted at a position deeper than buffer layer 17 from the second side (S6), and after implanting the protons, annealing is performed on the protons (S12) to form buffer layer 16. Hereafter, S5 may be referred to as the first annealing step and S12 as the third annealing step. The annealing of buffer layer 16 with respect to protons (S12) is preferably performed at 375 to 425°C for 90 minutes or more.

[0081] Furthermore, after implanting protons (S6) and before annealing the protons (S12), ion implantation is performed on the second surface, and annealing is then performed to form a p-type layer shallower than the buffer layer 17. In the example shown in Figure 17, the collector layer 18 is formed as the p-type layer.

[0082] The annealing process for forming buffer layer 17 is performed at a higher temperature than the annealing process for forming buffer layer 16. Therefore, forming buffer layer 17 after buffer layer 16 may adversely affect the impurity profile of buffer layer 16 after activation and the type of lattice defects introduced to form buffer layer 16. This may adversely affect carriers in the device ON state. For this reason, it is preferable to form buffer layer 16 after forming buffer layer 17.

[0083] The buffer layer 16 of Embodiment 2 can be formed by introducing protons into Si at two or more different acceleration energies and doses after activation annealing (S5) of the buffer layer 17, and then performing annealing (S12). The buffer layers 16 and 17 are formed to satisfy the following relationship: The peak position of the buffer layer 16 is at the junction X of the buffer layers 16 and 17. j,n1 More X j,n2n It is set to be located on the junction side. This prevents the buffer layers 16 and 17 from interfering with each other, allowing the buffer layer 16 to be formed with high precision.

[0084] Buffer layer 17 is formed using As or phosphorus as a dopant. Buffer layer 16 is formed using protons as a dopant. When implanting protons, multiple ion implantations are performed. These multiple ion implantations are performed sequentially, starting with conditions of high acceleration energy, and the dose amount decreases as the acceleration energy increases. In other words, ion implantations are performed sequentially from the drift layer 15 side to the buffer layer 17 side, decreasing the acceleration energy and increasing the dose amount.

[0085] Furthermore, the buffer layer 16 can be formed not only by ion implantation but also by irradiation techniques using a cyclotron.

[0086] When protons are introduced into Si, the vacancies v created during introduction react with impurities in Si such as oxygen and carbon to form composite defects. Hydrogen contained in these composite defects acts as an electron donor. As the density of composite defects increases due to annealing, the donor concentration increases, and this is further accelerated by the thermal donoring phenomenon caused by ion implantation or irradiation processes, leading to an increase in donor concentration. As a result, a buffer layer 16, which is an n-layer formed by donoring, is created with a higher impurity concentration than the drift layer 15.

[0087] In this embodiment, device performance can be improved by utilizing the complex defects formed in the buffer layer 16. On the other hand, some of these complex defects are lifetime killers that reduce the lifetime of carriers. Therefore, the flow of forming the buffer layer 16 after the formation of the buffer layer 17 using ion implantation and annealing techniques is important for controlling the complex defects formed in the buffer layer 16 to remove lifetime killer defects and for stabilizing the profile of the buffer layer 16. Furthermore, the peak position of the buffer layer 16 is set at the junction X of the buffer layers 16 and 17. j,n1 More X j,n2n By positioning it on the junction side, buffer layer 17 and layer n 21 and do not interfere with buffer layer 17. Layer n 21 This layer constitutes the buffer layer 16 and is joined to the buffer layer 17. Therefore, multiple diffusion layers can be formed with high precision.

[0088] After proton implantation (S6), a photolithography process (S7) and an ion implantation process (S8) are performed to form the collector layer 18. Furthermore, after the resist removal process (S9), a second annealing process (S10) is performed to form the collector layer 18. The second annealing process may use the same annealing technique as the first annealing process. Laser annealing or annealing at a low temperature below the metal melting point can be used for the second annealing process.

[0089] Next, the front side protective film is removed (S11), and the third annealing step for protons described above is performed (S12). Next, light etching (S13) is performed, and the metal that forms the second electrode 21 is deposited by sputtering (S14). Next, in the fourth annealing step, an alloy layer or silicide layer is formed at the interface between the Si surface and the metal (S15). The second electrode 21 is a metal that is in contact with the collector layer 18, and is, for example, an AlSi film with a Si content of 1-3% or a multilayer film containing Ni. The fourth annealing step is performed at a lower temperature of 300-400°C than the temperature of the third annealing step.

[0090] According to this embodiment, an MCZ wafer with a high oxygen concentration is used, protons are injected from the back side, and H is injected by annealing. + This diffuses from the back side to the front side. This promotes the oxygen-induced thermal donor phenomenon in Si more on the back side than on the front side, and allows for the formation of a sloped impurity profile in the drift layer 15.

[0091] Embodiment 4. The manufacturing method for the diode 103 in Embodiments 1 and 2 will be described. Figures 18A to 18 I This is a diagram illustrating the manufacturing method of diode 103 according to Embodiment 4. First, as shown in Figures 18A to C, an oxide film 33 is formed on the front side, and photolithography is performed on the oxide film 33. Next, ion implantation is performed from the opening of the oxide film 33, and annealing is performed after the resist used during photolithography is removed, thereby creating the p layer 31 and n layer of the terminal region. + Layer 34 and the anode layer 10 of the active region are formed. Subsequently, an interlayer film 6 of the oxide film system is formed as shown in Figure 18C.

[0092] Next, as shown in Figure 18D, a high concentration n is obtained using the same method as in Embodiment 3. + The strain layer present in layer 27, the high-crystal defect density layer 28, and the surface layer of polysilicon 26 forms a getter site. This allows the carrier lifetime of the drift layer 15 to be set to satisfy equation (3).

[0093] Next, as shown in Figure 18E, the polysilicon 26 is removed while it is present on the front side. Then, the p layer 31, n + Contact holes are formed in the interlayer film 6 for contact with layer 34 and the anode layer 10. Then, as shown in Figures 18F and 18G, the first electrode 5 and passivation films 35 and 36 are formed.

[0094] Figure 19 is a flowchart showing the method for forming the vertical structure 38 according to Embodiment 4. The method for forming the vertical structure 38 is the same as the method for forming the cathode layers 19 and 20 instead of the collector layer 18, except that the cathode layers 19 and 20 are formed instead. As shown in Figure 18H, a passivation film 30 is formed as a front side protective film (S21), and the second surface is polished (S22) and etched (S23). Steps S24 to S26 are the same as steps S4 to S6 in Embodiment 3.

[0095] Next, ion implantation is performed to form the cathode layer 20 (S27). Then, using photolithography technology (S28), ion implantation is performed to form the cathode layer 19 (S29), and the cathode layer 19 is partially formed on the back side. S30 to S36 are the same as S9 to S15 in Embodiment 3. This makes it possible to manufacture a diode 103 as shown in Figure 18I.

[0096] Figure 20 is a flowchart showing a method for forming a vertical structure 38 according to a modified example of Embodiment 4. Figure 20 shows a method for forming a vertical structure 38 in a diode 102. In diode 102, since there is no cathode layer 20, there is no ion implantation step for the cathode layer 20, and no photoengraving step and associated resist removal step for partially forming the cathode layer 19 on the back side. The other steps are the same as the manufacturing steps for diode 103. That is, steps S41 to S46 are the same as steps S21 to S26, and steps S47 to S55 are the same as steps S28 to S36.

[0097] Embodiment 5. In this embodiment, an example in which the semiconductor device 100 is an RC-IGBT will be described. Figures 21 to 28 are cross-sectional views showing an example of the semiconductor device 100 according to Embodiment 5. Figures 21 to 28 are cross-sectional views obtained by cutting Figure 1 along the line A-A'. In the semiconductor device 100 of this embodiment, the silicon substrate has an IGBT region and a diode region.

[0098] The structure of the IGBT region of the semiconductor device 100 shown in Figure 21 is the same as the structure of the IGBT 101 in Embodiment 1. In Figure 21, the diode region comprises an n-type semiconductor layer 11 provided on the first surface side of the drift layer 15 and a p-type anode layer 10 provided on the first surface side of the semiconductor layer 11. Furthermore, the diode region is provided on the first surface side of the anode layer 10 and is an impurity diffusion layer with a higher impurity concentration than the anode layer 10, called a p + The semiconductor layer 8 is of type n. The diode region includes an n-type cathode layer 19 provided on the second surface side of the buffer layer 17. The semiconductor layer 11 is formed deeper than the base layer 9 on the first surface side of the drift layer 15 in the IGBT region, and deeper than the anode layer 10 on the first surface side of the drift layer 15 in the diode region.

[0099] The drift layer 15 shown in Figures 21-28 has a characteristic impurity profile similar to that of Embodiment 1. Impurity concentration C of the drift layer 15 n- is 1.0 × 10 12 ~5.0×10 14 atoms / cm 3 And the final t device The size is 40-700 μm.

[0100] The following are examples of parameters for each diffusion layer and trench that make up the RC-IGBT shown in Figure 21. Note that the anode layer 10 is the same layer as the base layer 9. • p-type base layer 9 Dopant: Boron, Peak impurity concentration: 1.0 × 10⁻⁶ 16 ~1.0×10 18 atoms / cm 3 Depth: Deeper than emitter layer 7 and shallower than semiconductor layer 11 n-type semiconductor layer 11 Dopant: Arsenic, Phosphorus; Peak impurity concentration: 1.0 × 10⁻⁶ 15 ~1.0×10 17 atoms / cm 3 Depth: 0.5-1.0 μm deeper than the base layer 9. ·n + Emitter layer 7 Dopant: Arsenic, Phosphorus; Peak impurity concentration: 1.0 × 10⁻⁶ 18 ~1.0×10 21 atoms / cm 3 Depth: 0.2~1.0μm ·p + Semiconductor layer 8 Dopant: Boron, Surface impurity concentration: 1.0 × 10⁻⁶ 18 ~1.0×10 21 atoms / cm 3 Depth: Same as or deeper than emitter layer 7. Trench depth D trench Depths from 2.0 μm to deeper than semiconductor layer 11 n-type buffer layer 16 Dopant: Proton, peak impurity concentration C P,n2n ≤0.01 × C P,n1 , depth X j、nb2 :X j,n1 +20~30μm n-type buffer layer 17 Dopant: Arsenic, Phosphorus, Peak impurity concentration C P,n1 :1.0×10 15 ~5.0×10 16 atoms / cm 3 , depth X j、n1 : 1.0~30μm p-type collector layer 18 Dopant: Boron, Peak impurity concentration: 1.0 × 10⁻⁶ 16 ~1.0×10 20 atoms / cm 3 Depth: 0.3~0.8μm ·n + Cathode layer 19 Dopant: As, Phosphorus, Peak impurity concentration: 1.0 × 10⁻⁶ 17 ~1.0×10 19 atoms / cm 3 Depth: 0.3~0.5μm

[0101] The semiconductor device 100 in Figure 22 differs from the semiconductor device 100 in Figure 21 in that it lacks the semiconductor layer 8. In other words, the anode layer 10 is in contact with the first electrode 5. The other configurations are the same as those of the semiconductor device 100 in Figure 21. Compared to the semiconductor device 100 in Figure 21, the semiconductor device 100 in Figure 22 can reduce the hole injection efficiency from the base layer 9 when the diode constituting the RC-IGBT is in the ON state.

[0102] Figure 23 shows a configuration in which the structure of the first surface is the same as that of the semiconductor device 100 in Figure 21, and includes a cathode layer 20. The p-type cathode layer 20 is provided on the second surface side of the buffer layer 17 and is aligned with the n-type cathode layer 19 in the direction along the second surface. Figure 24 shows a configuration in which the structure of the first surface is the same as that of the semiconductor device 100 in Figure 22, and includes a cathode layer 20. p-type cathode layer 20 Dopant: Boron, Peak impurity concentration: 1.0 × 10⁻⁶ 16 ~1.0×10 18 atoms / cm 3 Depth: 0.3~0.5μm In the semiconductor devices 100 shown in Figures 23 and 24, the electron injection efficiency from the back side of the ON state of the diode constituting the RC-IGBT can be reduced compared to the semiconductor devices 100 shown in Figures 21 and 22, respectively.

[0103] Furthermore, in the RC-IGBT shown in Figure 22-24, the turn-off loss E in the diode region is REC and ON voltage V F The high-speed performance on the trade-off curve can be achieved without relying on carrier lifetime control using charged particles such as electron beams. High-speed performance refers to low E REC And high V F It exhibits excellent performance. The adverse effects of impurities such as oxygen and carbon in MCZ wafers on diode performance become more pronounced when carrier lifetime control is performed using charged particles. In order to make the most of MCZ wafers, it is important to avoid relying on carrier lifetime control. REC vs. V F The structures shown in Figures 22-24, which can improve performance on the high-speed side of the trade-off curve, are effective.

[0104] The semiconductor devices 100 in Figures 25-28 differ from those in Figures 21-24 in that some of the gate electrodes 14 in the IGBT region are in contact with the first electrode 5. In other words, in some of the trenches 24, the gate electrodes 14 are at the same potential as the emitter potential. Even in RC-IGBTs, using a MOS transistor structure makes it possible to suppress the saturation current density of the IGBT and suppress oscillation in the no-load short-circuit state by controlling the capacitance characteristics. This enables improved short-circuit withstand capability and lower ON voltage by improving the carrier concentration on the emitter side.

[0105] The technical features described in this embodiment may be used in combination as appropriate.

[0106] The various aspects of this disclosure are summarized below as an appendix. (Note 1) A silicon substrate having a first surface and a second surface opposite to the first surface, and containing oxygen as an impurity, The first electrode provided on the first surface, The second electrode provided on the second surface, Equipped with, The aforementioned silicon substrate is An n-type drift layer in which the impurity concentration is higher on the second side, A first buffer layer of n type containing protons as impurities is provided on the second surface side of the drift layer, A second buffer layer provided on the second surface side of the first buffer layer, A semiconductor device characterized by comprising the following features. (Note 2) The semiconductor device according to Appendix 1, characterized in that the impurity concentration of the drift layer continues to rise from the junction between the layer provided on the first surface side of the drift layer and the drift layer to the junction between the drift layer and the first buffer layer. (Note 3) The drift layer contains phosphorus or antimony as an impurity. The semiconductor device according to Appendix 1 or 2, characterized in that the second buffer layer has arsenic or phosphorus as an impurity. (Note 4) Oxygen concentration of the drift layer i When the impurity concentration of the drift layer is Cn, 1.00 × 10 17 ln(C n )-2.84×10 18 ≦O i ≤9.40 × 10 16 ln(C n )-2.27×10 18 A semiconductor device according to any one of the appendices 1 to 3, characterized in that it satisfies the following conditions. (Note 5) The impurity concentration of the first buffer layer has multiple peaks in the thickness direction of the silicon substrate. The semiconductor device according to any one of the appendices 1 to 4, characterized in that the impurity concentrations of the multiple peaks increase as they approach the second buffer layer. (Note 6) A p-type base layer provided on the first surface side of the drift layer, An n-type emitter layer provided on the first surface side of the base layer, A gate electrode is provided inside a trench formed on the first surface of the silicon substrate and penetrating the emitter layer and the base layer, A p-type collector layer provided on the second surface side of the second buffer layer, A semiconductor device according to any one of the appendices 1 to 5, characterized by comprising the above. (Note 7) The semiconductor device according to Appendix 6, further comprising an n-type semiconductor layer formed more deeply than the base layer on the first surface side of the drift layer. (Note 8) A p-type anode layer provided on the first surface side of the drift layer, An n-type cathode layer provided on the second surface side of the second buffer layer, A semiconductor device according to any one of the appendices 1 to 7, characterized by comprising the above. (Note 9) The semiconductor device according to Appendix 8, characterized in that it comprises a p-type cathode layer provided on the second surface side of the second buffer layer and aligned with the n-type cathode layer in a direction along the second surface. (Note 10) The semiconductor device according to any one of the appendices 1 to 5, characterized in that the silicon substrate has an IGBT region and a diode region. (Note 11) The diode region is A p-type anode layer provided on the first surface side of the drift layer, An n-type cathode layer provided on the second surface side of the second buffer layer, An impurity diffusion layer is provided on the first surface side of the anode layer, and has a higher impurity concentration than the anode layer. The semiconductor device according to Appendix 10, characterized by comprising the above. (Note 12) The diode region is A p-type anode layer provided on the first surface side of the drift layer, An n-type cathode layer provided on the second surface side of the second buffer layer, Equipped with, The semiconductor device according to Appendix 10, characterized in that the anode layer is in contact with the first electrode. (Note 13) The diode region is A p-type anode layer provided on the first surface side of the drift layer, An n-type cathode layer provided on the second surface side of the second buffer layer, A p-type cathode layer is provided on the second surface side of the second buffer layer and is aligned with the n-type cathode layer in a direction along the second surface, The semiconductor device according to Appendix 10, characterized by comprising the above. (Note 14) The aforementioned IGBT region is A p-type base layer provided on the first surface side of the drift layer, An n-type emitter layer provided on the first surface side of the base layer, A plurality of gate electrodes provided inside a plurality of trenches formed on the first surface of the silicon substrate and penetrating the emitter layer and the base layer, A p-type collector layer provided on the second surface side of the second buffer layer, Comprising, The semiconductor device according to any one of Appendices 10 to 13, characterized in that a part of the plurality of gate electrodes is in contact with the first electrode. (Appendix 15) The IGBT region is, A p-type base layer provided on the first surface side of the drift layer, An n-type semiconductor layer formed deeper than the base layer on the first surface side of the drift layer, Comprising, The diode region is, A p-type anode layer provided on the first surface side of the drift layer, An n-type semiconductor layer formed deeper than the anode layer on the first surface side of the drift layer, The semiconductor device according to any one of Appendices 10 to 13, characterized in that it comprises. (Appendix 16) Manufactured by the MCZ method, a semiconductor layer is formed on the first surface side of a silicon wafer having an n-type drift layer, Ion implantation is performed on the second surface opposite to the first surface of the silicon wafer, and annealing is performed to form a second buffer layer, After forming the second buffer layer, protons are implanted at a position deeper from the second surface than the second buffer layer, A method for manufacturing a semiconductor device, characterized in that after implanting the protons, annealing is performed on the protons to form a first buffer layer. (Appendix 17) After implanting the protons, before annealing the protons, ion implantation is performed on the second surface and annealing is performed to form at least one of a p-type layer or an n-type layer shallower than the second buffer layer. The method for manufacturing a semiconductor device according to Appendix 16, characterized in that. (Appendix 18) When implanting the aforementioned protons, multiple ion implantations are performed. The method for manufacturing a semiconductor device according to Appendix 16 or 17, characterized in that the multiple ion implantations are performed sequentially starting from conditions with high acceleration energy, and the dose amount decreases as the acceleration energy increases. (Note 19) The method for manufacturing a semiconductor device according to any one of appendices 16 to 18, characterized in that the second buffer layer has arsenic or phosphorus as an impurity. (Note 20) The method for manufacturing a semiconductor device according to any one of appendices 16 to 19, characterized in that the drift layer has antimony as an impurity. (Note 21) The method for manufacturing a semiconductor device according to any one of Appendix 16 to 20, characterized in that the annealing to the proton is carried out at 375 to 425°C for 90 minutes or more. [Explanation of symbols]

[0107] 1 Active cell region, 2 Interface region, 3 Termination region, 4 Surface gate wiring region, 5 First electrode, 6 Interlayer film, 7 Emitter layer, 8 Semiconductor layer, 9 Base layer, 10 Anode layer, 11 Semiconductor layer, 12 Main junction, 13 Gate oxide film, 14 Gate electrode, 15 Drift layer, 16 Buffer layer, 17 Buffer layer, 18 Collector layer, 19 Cathode layer, 20 Cathode layer, 21 Second electrode, 22 Junction, 23 Oxide film, 24 Trench, 25 Oxide film, 26 Polysilicon, 27 High-concentration n + 28. High crystal defect density layer, 30. Passivation film, 31. p layer, 33. Oxide film, 34. n + Layer, 35 Passivation film, 37 Region, 38 Longitudinal structure, 39 Gate pad area, 40 Barrier metal, 41 Silicide layer, 100 Semiconductor device, 101 IGBT, 102, 103 Diode

Claims

1. A silicon substrate having a first surface and a second surface opposite to the first surface, and containing oxygen as an impurity, The first electrode provided on the first surface, The second electrode provided on the second surface, Equipped with, The aforementioned silicon substrate is An n-type drift layer in which the impurity concentration is higher on the second side, A first n-type buffer layer is provided on the second surface side of the drift layer and contains protons as impurities. A second buffer layer provided on the second surface side of the first buffer layer, Equipped with, The oxygen concentration O i [cm⁻³] of the drift layer is given by the impurity concentration Cn [cm⁻³] of the drift layer, 1.00×10 17 ln(C n )-2.84×10 18 ≦O i ≦9.40×10 16 ln(C n )-2.27×10 18 A semiconductor device characterized by satisfying the following conditions.

2. The semiconductor device according to claim 1, characterized in that the impurity concentration of the drift layer continues to rise from the junction between the layer provided on the first surface side of the drift layer and the drift layer to the junction between the drift layer and the first buffer layer.

3. The drift layer contains phosphorus or antimony as an impurity. The semiconductor device according to claim 1 or 2, characterized in that the second buffer layer has arsenic or phosphorus as an impurity.

4. The impurity concentration of the first buffer layer has multiple peaks in the thickness direction of the silicon substrate. The semiconductor device according to claim 1 or 2, characterized in that the impurity concentrations of the plurality of peaks increase as they approach the second buffer layer.

5. A p-type base layer provided on the first surface side of the drift layer, An n-type emitter layer provided on the first surface side of the base layer, A gate electrode is provided inside a trench formed on the first surface of the silicon substrate and penetrating the emitter layer and the base layer, A p-type collector layer provided on the second surface side of the second buffer layer, A semiconductor device according to claim 1 or 2, characterized by comprising the above.

6. The semiconductor device according to claim 5, further comprising an n-type semiconductor layer formed more deeply than the base layer on the first surface side of the drift layer.

7. A p-type anode layer provided on the first surface side of the drift layer, An n-type cathode layer provided on the second surface side of the second buffer layer, A semiconductor device according to claim 1 or 2, characterized by comprising the above.

8. The semiconductor device according to claim 7, characterized in that it comprises a p-type cathode layer provided on the second surface side of the second buffer layer and aligned with the n-type cathode layer in a direction along the second surface.

9. The semiconductor device according to claim 1 or 2, characterized in that the silicon substrate has an IGBT region and a diode region.

10. The diode region is A p-type anode layer provided on the first surface side of the drift layer, An n-type cathode layer provided on the second surface side of the second buffer layer, An impurity diffusion layer is provided on the first surface side of the anode layer, and has a higher impurity concentration than the anode layer. The semiconductor device according to claim 9, characterized by comprising:

11. The diode region is A p-type anode layer provided on the first surface side of the drift layer, An n-type cathode layer provided on the second surface side of the second buffer layer, Equipped with, The semiconductor device according to claim 9, characterized in that the anode layer is in contact with the first electrode.

12. The diode region is A p-type anode layer provided on the first surface side of the drift layer, An n-type cathode layer provided on the second surface side of the second buffer layer, A p-type cathode layer is provided on the second surface side of the second buffer layer and is aligned with the n-type cathode layer in a direction along the second surface, The semiconductor device according to claim 9, characterized by comprising:

13. The aforementioned IGBT region is A p-type base layer provided on the first surface side of the drift layer, An n-type emitter layer provided on the first surface side of the base layer, A plurality of gate electrodes are provided inside a plurality of trenches formed on the first surface of the silicon substrate and penetrating the emitter layer and the base layer, A p-type collector layer provided on the second surface side of the second buffer layer, Equipped with, The semiconductor device according to claim 9, characterized in that a portion of the plurality of gate electrodes is in contact with the first electrode.

14. The aforementioned IGBT region is A p-type base layer provided on the first surface side of the drift layer, An n-type semiconductor layer is formed on the first surface side of the drift layer, deeper than the base layer, Equipped with, The diode region is A p-type anode layer provided on the first surface side of the drift layer, An n-type semiconductor layer is formed on the first surface side of the drift layer, deeper than the anode layer, The semiconductor device according to claim 9, characterized by comprising:

15. A semiconductor layer is formed on the first side of a silicon wafer manufactured by the MCZ method and having an n-type drift layer. Ion implantation is performed on the second surface of the silicon wafer opposite to the first surface, and annealing is performed to form a second buffer layer. After forming the second buffer layer, protons are injected at a position deeper than the second buffer layer from the second surface. After injecting the protons, the protons are annealed to form a first buffer layer. The oxygen concentration O i [cm⁻³] of the drift layer is given by the impurity concentration Cn [cm⁻³] of the drift layer, 1.00×10 17 ln(C n )-2.84×10 18 ≦O i ≦9.40×10 16 ln(C n )-2.27×10 18 A method for manufacturing a semiconductor device, characterized by satisfying the requirements.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that after implanting the protons and before annealing the protons, ion implantation is performed on the second surface and annealing is performed to form at least one of a p-type layer or an n-type layer shallower than the second buffer layer.

17. When implanting the aforementioned protons, multiple ion implantations are performed. The method for manufacturing a semiconductor device according to claim 15 or 16, characterized in that the multiple ion implantations are performed sequentially from conditions with high acceleration energy, and the dose amount decreases as the acceleration energy increases.

18. The method for manufacturing a semiconductor device according to claim 15 or 16, characterized in that the second buffer layer has arsenic or phosphorus as an impurity.

19. The method for manufacturing a semiconductor device according to claim 15 or 16, characterized in that the drift layer contains antimony as an impurity.

20. The method for manufacturing a semiconductor device according to claim 15 or 16, characterized in that the annealing with respect to the proton is carried out at 375 to 425°C for 90 minutes or more.

Images