Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor (1) in which the occurrence of dielectric breakdown is further suppressed. The multilayer ceramic capacitor (1) comprises: a laminate (2) including a plurality of dielectric layers (4) and a plurality of internal electrode layers (10) stacked on one another; and external electrodes (20) provided on a first end surface (62a) and a second end surface (62b). The internal electrode layers (10) comprise first internal electrode layers (10a) and second internal electrode layers (10b), the first internal electrode layers (10a) being led to the first end surface (62a), and the second internal electrode layers (10b) being led to the second end surface (62b). The external electrodes (20) include a first external electrode (20a) connected to the first internal electrode layers (10a) and a second external electrode (20b) connected to the second internal electrode layers (10b). A region that is disposed on the first end surface (62a) side and in which the first internal electrode layers (10a) do not overlap each other in the stacking direction (T), and a region that is disposed on the second end surface (62b) side and in which the second internal electrode layers (10b) do not overlap each other in the stacking direction (T) are defined as L gap regions (51). The L gap regions (51) comprise Si segregation layers (14).

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] As the multilayer ceramic capacitor becomes smaller and has a larger capacitance, dielectric breakdown is likely to occur in the multilayer ceramic capacitor. In Patent Document 1, for the purpose of suppressing this dielectric breakdown, a technique is described in which at least a part of a region near the edge portion of the internal electrode of the dielectric layer is formed of a dielectric porcelain having a higher withstand voltage than other regions.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For the purpose of further miniaturization and higher capacitance, the thickness of the dielectric layer of the multilayer ceramic capacitor has been further reduced. As the thickness of the dielectric layer decreases, the insulation resistance value decreases. Particularly in a region where the internal electrodes connected to the same external electrode overlap on the end face side of the laminate, the internal electrodes are likely to be curved structurally. Therefore, the thickness of the dielectric layer is locally reduced, and dielectric breakdown is more likely to occur. Therefore, an object of the present invention is to provide a multilayer ceramic capacitor in which the occurrence of dielectric breakdown is more suppressed.

Means for Solving the Problems

[0005] The multilayer ceramic capacitor of the present invention includes a plurality of stacked dielectric layers and a plurality of internal electrode layers, and comprises a laminate having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, and external electrodes provided on the first end surface and the second end surface, wherein the internal electrode layer comprises a first internal electrode layer and a second internal electrode layer, the first internal electrode layer being drawn out to the first end surface, the second internal electrode layer being drawn out to the second end surface, and the external electrodes include a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer, and the L gap region is located on the first end surface side and the first internal electrode layers do not overlap in the stacking direction, and the L gap region comprises a Si segregation layer. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the occurrence of dielectric breakdown is further suppressed. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view of the multilayer ceramic capacitor of this embodiment. [Figure 2] This is a cross-sectional view taken along line II in Figure 1. [Figure 3] This is a cross-sectional view taken along line II-II in Figure 1. [Figure 4] This figure shows a portion of the LT cross-section of the multilayer ceramic capacitor of this embodiment. [Figure 5] This figure shows a portion of the WT cross-section of the multilayer ceramic capacitor of this embodiment. [Figure 6] This figure shows a portion of the WT cross-section of another configuration of the multilayer ceramic capacitor of this embodiment. [Figure 7] This is a plan view of the ceramic green sheet in this embodiment. [Figure 8] This is a plan view of a ceramic green sheet with a different configuration according to this embodiment. [Figure 9] (a) and (b) are diagrams showing the LT cross-section of the laminated ceramic green sheets. [Figure 10] This figure shows the results of the high-temperature load reliability test. [Figure 11] This figure shows the results for dielectric constant and mean time of failure. [Modes for carrying out the invention]

[0008] An example of an embodiment of the multilayer ceramic capacitor 1 of the present invention will be described below with reference to the attached drawings.

[0009] (Outer dimensions of a multilayer ceramic capacitor) The external appearance of the multilayer ceramic capacitor 1 will be described based on Figure 1. Figure 1 is a perspective view showing the multilayer ceramic capacitor 1 of this embodiment. The multilayer ceramic capacitor 1 comprises a laminate 2 and external electrodes 20.

[0010] (Definition of direction) The drawings show the L, W, and T directions as appropriate. The L direction is the length L of the multilayer ceramic capacitor 1. The W direction is the width W of the multilayer ceramic capacitor 1. The T direction is the stacking direction T of the multilayer ceramic capacitor 1. Accordingly, the cross-section shown in Figure 2 is called the LT cross-section, and the cross-section shown in Figure 3 is called the WT cross-section. The length L, width W, and stacking direction T do not necessarily have to be orthogonal to each other. The length L, width W, and stacking direction T may intersect to each other.

[0011] (Outer shape of the laminate) The laminate 2 has a substantially rectangular parallelepiped shape. The laminate 2 has two main surfaces 61, two end surfaces 62, and two side surfaces 63. The main surface 61 is a surface facing the lamination direction T. The end surface 62 is a surface facing the length direction L. The side surface 63 is a surface facing the width direction W. One of the two main surfaces 61 is defined as the first main surface 61a, and the other is defined as the second main surface 61b. One of the two end surfaces 62 is defined as the first end surface 62a, and the other is defined as the second end surface 62b. One of the two side surfaces 63 is defined as the first side surface 63a, and the other is defined as the second side surface 63b. The second main surface 61b and the first side surface 63a are shown in FIG. 1.

[0012] It is preferable that the ridge lines and corners of the laminate 2 are rounded. A ridge line is a portion where two surfaces of the laminate 2 intersect. A corner is a portion where three surfaces of the laminate 2 intersect. Note that the size of the laminate 2 is not particularly limited. [[ID=])5

[0013] [[ID=]]7 (Structure of laminate) The laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. Hereinafter, the structure of the laminate 2 will be described while referring to a cross-sectional view of the laminate 2.

[0014] (Internal structure of laminate (LT cross-section)) Based on FIG. 2, the internal structure of the laminate 2 will be described. FIG. 2 is a cross-sectional view taken along line I-I of the laminated ceramic capacitor 1 shown in FIG. 1. FIG. 2 shows the LT cross-section of the laminated ceramic capacitor 1. The laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The plurality of dielectric layers 4 and the plurality of internal electrode layers 10 are laminated on each other in the lamination direction T.

[0015] (Inner layer part and outer layer part) In the lamination direction T, the laminate 2 is divided into an inner layer part 53 and two outer layer parts 54. The outer layer part 54 includes a first outer layer part 54a and a second outer layer part 54b. The first outer layer part 54a and the second outer layer part 54b are located at positions sandwiching the inner layer part 53 in the lamination direction T.

[0016] The inner layer 53 contains multiple dielectric layers 4 and multiple internal electrode layers 10. In the inner layer 53, the multiple internal electrode layers 10 face each other via the dielectric layers 4. As a result, capacitance is formed in the inner layer 53. Therefore, the inner layer 53 is the part of the laminate 2 that functions as a capacitor. For this reason, the inner layer 53 is also called the effective part.

[0017] The first outer layer 54a is the portion of the outer layer 54 located on the side of the first main surface 61a of the laminate 2. The second outer layer 54b is the portion of the outer layer 54 located on the side of the second main surface 61b of the laminate 2. Specifically, the first outer layer 54a is the portion between the internal electrode layer 10 closest to the first main surface 61a and the first main surface 61a. The second outer layer 54b is the portion between the internal electrode layer 10 closest to the second main surface 61b and the second main surface 61b. No internal electrode layers 10 are arranged in the first outer layer 54a and the second outer layer 54b. The dielectric layers 4 remaining from the dielectric layer 4 for the inner layer 53 are arranged in the first outer layer 54a and the second outer layer 54b. The first outer layer 54a and the second outer layer 54b function as protective layers for the inner layer 53.

[0018] (Dielectric layer) The dielectric layer 4 can be classified into a dielectric layer 4 located in the inner layer 53 and a dielectric layer 4 located in the outer layer 54. The dielectric layer 4 located in the inner layer 53 is referred to as the inner dielectric layer 4a. The dielectric layer 4 located in the outer layer 54 is referred to as the outer dielectric layer 4b.

[0019] (Number of dielectric layers) The dielectric layers 4 stacked on the laminate 2 can be, for example, 5 to 2000 layers.

[0020] (Materials for the dielectric layer) For example, dielectric ceramics consisting of main components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3 can be used as the material for the dielectric layer 4. Alternatively, materials in which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds are added to these main components may be used.

[0021] (Thickness of the dielectric layer) The thickness of the dielectric layer 4 can be, for example, 0.3 μm or more and 0.6 μm or less.

[0022] (Internal electrode layer) The internal electrode layer 10 can be classified into a first internal electrode layer 10a and a second internal electrode layer 10b. The first internal electrode layer 10a is the internal electrode layer 10 connected to the first external electrode 20a. The second internal electrode layer 10b is the internal electrode layer 10 connected to the second external electrode 20b. The first internal electrode layer 10a extends from the first end face 62a toward the second end face 62b. The second internal electrode layer 10b extends from the second end face 62b toward the first end face 62a.

[0023] (Opposite section and drawer section) The first internal electrode layer 10a and the second internal electrode layer 10b each have a counter electrode portion 11 and a lead-out electrode portion 12. The opposing electrode portion 11 is the portion in the internal electrode layer 10 where the first internal electrode layer 10a and the second internal electrode layer 10b face each other in the stacking direction T. The drawn-out electrode portion 12 is the portion in the internal electrode layer 10 that is drawn out from the opposing electrode portion 11 to the first end face 62a or the second end face 62b of the laminate 2.

[0024] The opposing electrode portion 11 of the first internal electrode layer 10a is designated as the first opposing electrode portion 11a. The drawn-out electrode portion 12 of the first internal electrode layer 10a is designated as the first drawn-out electrode portion 12a. The first drawn-out electrode portion 12a is the portion drawn out from the first opposing electrode portion 11a to the first end face 62a of the laminate 2.

[0025] Similarly, the opposing electrode portion 11 of the second internal electrode layer 10b is designated as the second opposing electrode portion 11b. The drawn-out electrode portion 12 of the second internal electrode layer 10b is designated as the second drawn-out electrode portion 12b. The second drawn-out electrode portion 12b is the portion drawn out from the second opposing electrode portion 11b to the second end face 62b of the laminate 2.

[0026] (Number of layers in the internal electrode layer) The internal electrode layer 10 can consist of, for example, 10 to 2000 layers. The number of layers in this internal electrode layer 10 includes the number of layers of the first internal electrode layer 10a and the number of layers of the second internal electrode layer 10b.

[0027] (Thickness of the internal electrode layer) The thickness of the internal electrode layer 10 can be, for example, 0.1 μm or more and 5.0 μm or less, preferably 0.2 μm or more and 2.0 μm or less. When the thickness of the internal electrode layer 10 is 0.5 μm or more, the plating film grows more easily when the metal layer of the external electrode 20 is formed by plating.

[0028] (Material of the internal electrode layer) The material of the internal electrode layer 10 can be, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys of Ni and Cu or alloys of Ag and Pd. In addition, the material of the internal electrode layer 10 may also contain dielectric particles of the same composition as the ceramic contained in the dielectric layer 4.

[0029] (electrode facing part) The division of the laminate 2 in the longitudinal direction L will now be described. The laminate 2 can be divided in the longitudinal direction L into an electrode-facing portion 50 and an L-gap (L-gap region) 51. The electrode-facing portion 50 in the division in the longitudinal direction L will be called the L-facing portion 50a. The L-gap 51 includes a first L-gap 51a and a second L-gap 51b.

[0030] The L-opposing portion 50a corresponds to the portion where the first internal electrode layer 10a and the second internal electrode layer 10b face each other in the stacking direction T. A capacitance is formed in the L-opposing portion 50a. For this reason, the L-opposing portion 50a is also called the effective portion.

[0031] (L gap) The L gap 51 is the portion in the longitudinal direction L of the laminate 2 where the first internal electrode layer 10a and the second internal electrode layer 10b do not face each other in the lamination direction T. Of the L gap 51, the first L gap 51a is between the L-facing portion 50a and the first end face 62a. The second L gap 51b is between the L-facing portion 50a and the second end face 62b.

[0032] In the first L gap 51a, the first internal electrode layer 10a is positioned in the stacking direction T, but the second internal electrode layer 10b is not positioned. In the second L gap 51b, the second internal electrode layer 10b is positioned in the stacking direction T, but the first internal electrode layer 10a is not positioned.

[0033] The first L-gap 51a functions as a lead-out portion to the first end face 62a of the first opposing electrode portion 11a. The second L-gap 51b functions as a lead-out portion to the second end face 62b of the second opposing electrode portion 11b.

[0034] The length L of the L gap 51 in the longitudinal direction can be, for example, 10% to 30% of the length L of the laminate 2 in the longitudinal direction. Alternatively, the length L of the L gap 51 in the longitudinal direction can be, for example, 5 μm to 30 μm.

[0035] (external electrode) The external electrode 20 includes a first external electrode 20a and a second external electrode 20b. (First external electrode) The first external electrode 20a is an external electrode 20 positioned on the first end face 62a of the laminate 2. The first external electrode 20a is electrically connected to the first internal electrode layer 10a. (Second external electrode) The second external electrode 20b is an external electrode 20 positioned on the second end face 62b of the laminate 2. The second external electrode 20b is electrically connected to the second internal electrode layer 10b.

[0036] (External electrodes on each surface) The external electrode 20 extends from one end face 62 to a portion of the two main faces 61 and to a portion of the two side faces 63.

[0037] (Layer configuration of external electrodes) The layer configuration of the external electrode 20 will be described based on Figure 2. The external electrode 20 includes a base electrode layer 21 and a plating layer 23. The plating layer 23 includes an inner plating layer 24 and a surface plating layer 25. These layers are arranged in the order of base electrode layer 21, inner plating layer 24, and surface plating layer 25 from the end face 62 of the laminate 2. Specifically, the first external electrode 20a includes a first base electrode layer 21a and a first plating layer 23a. Furthermore, the first plating layer 23a includes a first inner plating layer 24a and a first surface plating layer 25a. Similarly, the second external electrode 20b includes a second base electrode layer 21b and a second plating layer 23b. Furthermore, the second plating layer 23b includes a second inner plating layer 24b and a second surface plating layer 25b.

[0038] (base electrode layer) The first base electrode layer 21a is positioned on the first end face 62a of the laminate 2 and covers the first end face 62a. The first base electrode layer 21a extends from the first end face 62a to a portion of the first main surface 61a, a portion of the second main surface 61b, a portion of the first side surface 63a, and a portion of the second side surface 63b.

[0039] Similarly, the second base electrode layer 21b is positioned on and covers the second end face 62b of the laminate 2. The second base electrode layer 21b extends from the second end face 62b to a portion of the first main surface 61a, a portion of the second main surface 61b, a portion of the first side surface 63a, and a portion of the second side surface 63b.

[0040] (Baked layer) The first base electrode layer 21a and the second base electrode layer 21b are configured as a baking layer. The baking layer contains a glass component and a metal. The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baking layer may consist of multiple layers.

[0041] (Plating layer) The plating layer 23 on the base electrode layer 21 will now be described. As mentioned above, in this embodiment, the plating layer 23 includes an inner plating layer 24 and a surface plating layer 25. When the plating layer 23 consists of two layers, it is preferable that the layers be in the order of Ni plating layer and Sn plating layer from the bottom. That is, the inner plating layer 24 becomes the Ni plating layer and the surface plating layer 25 becomes the Sn plating layer.

[0042] The Ni plating layer prevents the underlying electrode layer 21 from being corroded by the solder used when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder used when mounting the multilayer ceramic capacitor 1, making mounting easier. Therefore, by making the surface plating layer 25 a Sn plating layer, the wettability of the solder to the external electrode 20 can be improved. The thickness of each plating layer is preferably 3 μm to 9 μm.

[0043] (Internal structure of the laminate (WT cross-section)) The internal structure of the laminate 2 will be explained based on Figure 3. Figure 3 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 shown in Figure 1. The laminate 2 is divided in the width direction W into an electrode opposing portion 50 and a W gap 52. The electrode opposing portion 50 in the division in the width direction W is referred to as the W opposing portion 50b. The W gap 52 includes a first W gap 52a and a second W gap 52b.

[0044] The W-facing portion 50b is the portion where the internal electrode layers 10 face each other in the stacking direction T. The W-gap 52 is the portion in the width direction W where neither the first internal electrode layer 10a nor the second internal electrode layer 10b is positioned in the stacking direction T.

[0045] Of the W gaps 52, the first W gap 52a is between the W-facing portion 50b and the first side surface 63a in the width direction W of the laminate 2. The second W gap 52b is between the W-facing portion 50b and the second side surface 63b.

[0046] The first W gap 52a and the second W gap 52b are positioned to sandwich the W-facing portion 50b. The first W gap 52a and the second W gap 52b function as protective layers for the internal electrode layer 10.

[0047] The length of the widthwise W of the W gap 52 can be, for example, 20% to 30% of the length of the widthwise W of the laminate 2. Alternatively, the length of the widthwise W of the W gap 52 can be, for example, 5 μm to 50 μm.

[0048] (Size of multilayer ceramic capacitors) The size of the multilayer ceramic capacitor 1 is not particularly limited. The size of the multilayer ceramic capacitor 1 can be, for example, as follows: The length L dimension of the multilayer ceramic capacitor 1 including the laminate 2 and external electrodes 20 is denoted as dimension L. Dimension L is preferably 0.25 mm or more and 1.0 mm or less. The dimension T dimension of the multilayer ceramic capacitor 1 including the laminate 2 and external electrodes 20 in the stacking direction is denoted as dimension T. Dimension T is preferably 0.125 mm or more and 0.5 mm or less. The width W dimension of the multilayer ceramic capacitor 1 including the laminate 2 and external electrodes 20 is denoted as dimension W. Dimension W is preferably 0.125 mm or more and 0.5 mm or less. The lengths of each part of the laminate 2 and external electrodes 20 can be measured with a micrometer or an optical microscope.

[0049] (Terminal configuration) In this embodiment, the multilayer ceramic capacitor 1 was described as a two-terminal multilayer ceramic capacitor. However, the multilayer ceramic capacitor 1 is not limited to a two-terminal multilayer ceramic capacitor, and can also be a multi-terminal multilayer ceramic capacitor with three or more terminals.

[0050] (Si segregation layer) The multilayer ceramic capacitor 1 of this embodiment is equipped with a Si segregation layer 14 in the L gap 51. The Si segregation layer 14 refers to a Si layer formed on the surface of the internal electrode layer 10 or the like.

[0051] The Si segregation layer 14 will be described based on Figure 4. Figure 4 is a diagram showing a part of the LT cross-section of the multilayer ceramic capacitor 1 of this embodiment. Figure 4 corresponds to an enlarged view of the region R1 shown by the dashed line in Figure 2. Figure 4 shows the first L gap 51a and its vicinity.

[0052] In the first L gap 51a and its vicinity, a Si segregation layer 14 is formed on the surface of the internal electrode layer 10. (First internal electrode layer) Regarding the first internal electrode layer 10a, a Si segregation layer 14 is formed on the entire surface of the first extraction electrode portion 12a and on at least a portion of the surface of the first counter electrode portion 11a. The at least portion of the first counter electrode portion 11a corresponds to the portion of the first counter electrode portion 11a that is close to the first L gap 51a.

[0053] (Second internal electrode layer) Regarding the second internal electrode layer 10b, a Si segregation layer 14 is formed on at least a portion of the surface of the second counter electrode portion 11b. The portion of the second counter electrode portion 11b corresponds to the portion of the second counter electrode portion 11b that is close to the first L gap 51a.

[0054] With respect to the first internal electrode layer 10a and the second internal electrode layer 10b, the portion close to the first L gap 51a refers to a portion of approximately 50 μm in the direction of the L opposing portion 50a from the boundary between the first L gap 51a and the L opposing portion 50a.

[0055] The end of the internal electrode layer 10 is defined as the electrode end 10e. The end of the internal electrode layer 10 refers to the end face parallel to the stacking direction T of the internal electrode layer 10. Figure 4 shows the electrode end 10e of the second internal electrode layer 10b. In the configuration shown in Figure 4, a Si segregation layer 14 is formed on this electrode end 10e over its entire length in a direction parallel to the stacking direction T.

[0056] As described above, the Si segregation layer 14 is formed not only on the plane parallel to the longitudinal direction L of the internal electrode layer 10, but also on the plane parallel to the stacking direction T at the electrode end 10e. In this way, the Si segregation layer 14 is formed on the surface of the internal electrode layer 10 in the first L gap 51a and its vicinity.

[0057] (Floating island electrode) In the example shown in Figure 4, a floating island electrode 13 is formed in the first L gap 51a. A Si segregation layer 14 is also formed on the surface of this floating island electrode 13. The floating island electrode 13 can be intentionally formed when forming the internal electrode layer 10. Alternatively, it may be formed unintentionally when forming the internal electrode layer 10.

[0058] (Second L gap) The Si segregation layer 14 has been described above using the first L gap 51a as an example. However, the second L gap 51b has a similar configuration. That is, the second extraction electrode portion 12b and the first counter electrode portion 11a of the second L gap 51b also have a Si segregation layer 14 similar to that of the first extraction electrode portion 12a and the second counter electrode portion 11b of the first L gap 51a.

[0059] (Electrode ends in the width direction) Based on Figure 5, the electrode ends 10e in the width direction W of the internal electrode layer 10 will be described. Figure 5 is a diagram showing a part of the WT cross-section of a multilayer ceramic capacitor 1 according to an embodiment of the present invention. Note that Figure 5 is a schematic diagram. Therefore, the number of patterns, etc., may not be consistent with other drawings.

[0060] As shown in Figure 5, the Si segregation layer 14 is also formed on the electrode end 10e in the width direction W. More specifically, the Si segregation layer 14 is formed over the entire length of the electrode end 10e in the width direction W, parallel to the stacking direction T. The Si segregation layer 14 is also formed on the surface of the internal electrode layer 10 parallel to the width direction W. However, the Si segregation layer 14 is not formed to completely cover the surface parallel to the width direction W. The Si segregation layer 14 is formed on the surface parallel to the width direction W for a predetermined distance from the electrode end 10e. This predetermined distance is shown as distance d1 in Figure 5. Distance d1 can be, for example, 1 μm or more and 50 μm or less.

[0061] (Other compositions of the Si segregation layer) Figure 6 shows an alternative configuration for region R2 in Figure 5. The configuration shown in Figure 5 and the configuration shown in Figure 6 differ in the position where the Si segregation layer 14 is formed on the surface of the internal electrode layer 10. In the configuration shown in Figure 5, as shown in region R2, the Si segregation layer 14 was formed over the entire stacking direction T at the electrode end 10e of the internal electrode layer 10. In contrast, in the configuration example shown in Figure 6, the Si segregation layer 14 is not formed over the entire stacking direction T at the electrode end 10e. The Si segregation layer 14 is formed at both ends of the electrode end 10e in the stacking direction T. On the other hand, the Si segregation layer 14 is not formed in the central part of the electrode end 10e in the stacking direction T. Therefore, the internal electrode layer 10 is exposed from the central part of the electrode end 10e in the stacking direction T.

[0062] As shown in Figures 5 and 6, the Si segregation layer 14 may be formed over the entire length of the stacking direction T at the electrode end 10e in the width direction W of the internal electrode layer 10, or it may be formed over a portion of the stacking direction T.

[0063] (Thickness of the Si segregation layer) The thickness of the Si segregation layer 14 can be, for example, 0.01 μm or more and 0.30 μm or less. The thickness of the Si segregation layer 14 can be determined by exposing the cross-section of the laminate 2, distinguishing between dielectric particles and the Si segregation layer using a scanning electron microscope (SEM), and then performing elemental analysis of its surface using energy-dispersive X-ray spectroscopy (EDX).

[0064] (Manufacturing method for multilayer ceramic capacitors) The manufacturing method for the multilayer ceramic capacitor 1 will be explained based on Figure 7 and other figures. (Fabrication of laminated blocks) Prepare a ceramic green sheet 30, an electrode paste 31 for the internal electrode layer 10, and a step paste 32 for the step layer 5.

[0065] (step layer) First, let's explain the stepped layer 5. It is preferable that the length of the stacking direction T of the laminate 2 differs little between the electrode-facing portion 50 and the L gap 51. However, in the inner layer portion 53, the length of the stacking direction T tends to differ between the electrode-facing portion 50 and the L gap 51. The dielectric layer 4 and the internal electrode layer 10 are stacked in the electrode-facing portion 50. In contrast, the dielectric layer 4 and only the internal electrode layer 10 connected to one of the external electrodes 20 are stacked in the L gap 51. Therefore, the length of the stacking direction T tends to differ between the electrode-facing portion 50 and the L gap 51.

[0066] Therefore, in order to reduce the difference in length T in the stacking direction between the L gap 51 and the electrode opposing portion 50, an additional dielectric layer 4 is placed in the L gap 51. This additional dielectric layer 4 is designated as a step layer 5. Preferably, the step layer 5 has the same components as the dielectric layer 4. However, the components of the dielectric layer 4 are not limited to this.

[0067] Figure 4 shows the stepped layer 5. As shown in Figure 4, the stepped layer 5 is positioned between two first opposing electrode portions 11a facing each other in the stacking direction T at the first L gap 51a. By the stepped layer 5 supplementing the thickness of the second internal electrode layer 10b, the difference in length in the stacking direction T between the first L gap 51a and the L opposing portion 50a can be reduced.

[0068] In this embodiment, a Si component is added to the stepped paste 32. This Si component later forms the Si segregation layer 14. Adding a Si component to the stepped paste 32 is one example of a method for forming the Si segregation layer 14.

[0069] (Application of paste) The general outline of the lamination of the ceramic green sheet 30 when forming the stepped layer 5 will be described below. The shapes of the patterns of the electrode paste 31 and the stepped paste 32 will be described later. First, the aforementioned electrode paste 31 and stepped paste 32 are applied to the ceramic green sheet 30 in a desired pattern. The application of each paste to the ceramic green sheet 30 can be done by methods such as screen printing or gravure printing. The electrode paste 31 and stepped paste 32 are printed on the ceramic green sheet 30 in a predetermined pattern using any printing method. This gives rise to a ceramic green sheet 30 for the inner layer 53 with the paste printed on it.

[0070] (Laminated) A predetermined number of ceramic green sheets 30, which do not have the pattern of the internal electrode layer 10 printed on them, are stacked. This creates a portion corresponding to the outer layer 54. On top of this, ceramic green sheets 30 for the inner layer 53, to which paste has been applied, are stacked sequentially. This creates a portion corresponding to the inner layer 53. Furthermore, a predetermined number of ceramic green sheets 30 for the other outer layer 54 are stacked on top of that. This creates a laminated sheet. The laminated sheet is pressed in the stacking direction by means of a hydrostatic press or the like to create a laminated block.

[0071] (pattern) Figure 7 is a plan view of a ceramic green sheet 30 to which electrode paste 31 and step paste 32 have been applied. Figure 7 is a view of the ceramic green sheet 30 from the stacking direction T. 701 and 702 in Figure 7 each show a single ceramic green sheet 30. A stacked sheet can be obtained by stacking these ceramic green sheets 30. In the example shown in Figure 7, 10 electrode patterns are formed on the ceramic green sheet 30 using electrode paste 31. The electrode patterns are arranged in two rows in the length direction L and five rows in the width direction W. Step paste 32 is applied between two electrode patterns aligned in the length direction L. The two ceramic green sheets 30 shown in Figure 7, 701 and 702, are coated with electrode paste 31 and step paste 32 in the same pattern.

[0072] (Laminated) When stacking the two ceramic green sheets 30 shown in Figure 7, 701 and 702, they are stacked with a vertical offset L. The offset distance is shown as distance d2 in Figure 7. By stacking the two ceramic green sheets 30 with a vertical offset, a multilayer ceramic capacitor 1 can be easily fabricated in which a Si segregation layer 14 is formed in both the first L gap 51a and the second L gap 51b. This will be explained later.

[0073] (Fabrication of multilayer chips) The laminated block is cut to the specified size, and the laminated chips are cut out. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0074] (Firing) Next, the laminated chips are fired to produce the laminated body 2. The firing temperature depends on the materials of the ceramic layer 4 and the internal electrode layer 10, but it is preferably between 900°C and 1400°C.

[0075] (external electrode) Next, the external electrode 20 is formed. (base electrode layer) A conductive paste to form the base electrode layer 21 is applied to two end faces 62 of the laminate 2. To form the baked layer, a conductive paste containing glass components and metal is applied by a method such as dipping. Then, a baking treatment is performed to form the base electrode layer 21. The baking treatment temperature is preferably 500°C to 900°C. The baking treatment time is preferably 30 minutes to 2 hours. The atmosphere for the baking treatment is preferably a reducing atmosphere containing, for example, H2O or H2.

[0076] Next, a plating layer 23 is formed on the surface of the base electrode layer 21. In this embodiment, a Ni plating layer is formed on the baked layer. This Ni plating layer becomes the inner plating layer 24. Next, a Sn plating layer is formed on the Ni plating layer. This Sn plating layer becomes the outer plating layer 25. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by a barrel plating method. In this way, a multilayer ceramic capacitor 1 is obtained.

[0077] (Lamination and cutting) Based on Figures 8 and 9, the lamination and cutting processes in the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be explained in more detail. Figure 8 is a plan view of a ceramic green sheet 30 to which electrode paste 31 and step paste 32 have been applied. The shapes of the patterns of the electrode paste 31 and step paste 32 applied to the ceramic green sheet 30 differ between Figure 7 and Figure 8. In the configuration shown in Figure 7, the electrode patterns were arranged in two columns in the length direction L and five rows in the width direction W. The step paste 32 was applied between two electrode patterns aligned in the length direction L. In contrast, in the configuration shown in Figure 8, the electrode patterns are arranged in four columns in the length direction L and five rows in the width direction W. The step paste 32 is applied between the first and second electrode patterns, and between the third and fourth electrode patterns, in the four electrode patterns aligned in the length direction L. In this way, electrode paste 31 and step paste 32 can be applied to the ceramic green sheet 30 in various patterns depending on the type of multilayer ceramic capacitor 1 to be manufactured.

[0078] (Laminated) In Figure 8, the ceramic green sheet 30 shown as 801 is designated as the first ceramic green sheet 30a. In Figure 8, the ceramic green sheet 30 shown as 802 is designated as the second ceramic green sheet 30b. The first ceramic green sheet 30a and the second ceramic green sheet 30b are stacked with an offset, similar to the configuration shown in Figure 7. Specifically, they are stacked with a offset of d2 in the length direction L.

[0079] (Cut) The cutting of the laminated ceramic green sheets 30 will be explained based on Figure 9. Figures 9(a) and 9(b) show the LT cross-section of the laminated ceramic green sheets 30. In Figures 9(a) and 9(b), a state in which only two ceramic green sheets 30 are laminated is shown as an example in order to simplify the structure. This laminate of two ceramic green sheets 30 will be referred to as the laminate 40 in the following explanation. Lines L1 and L2 shown in Figure 9(a) indicate the cutting lines. These lines L1 and L2 correspond to lines L1 and L2 shown in Figure 8. Figure 9(a) shows the laminate 40 before cutting. Figure 9(b) shows the laminate 40 after cutting along lines L1 and L2.

[0080] (line L1) As shown in Figure 9(a), the first ceramic green sheet 30a and the second ceramic green sheet 30b in the laminate 40 are stacked with a staggered alignment in the longitudinal direction L. Therefore, the longitudinal end 31b of the electrode paste 31 pattern in the second ceramic green sheet 30b is aligned with the longitudinal central part 32a of the stepped paste 32 pattern in the first ceramic green sheet 30a at the position in the longitudinal direction L. In other words, both the end 31b of the electrode paste 31 pattern and the central part 32a of the stepped paste 32 pattern are located on line L1.

[0081] (line L2) Similarly, the central portion 32b of the stepped paste 32 pattern in the second ceramic green sheet 30b aligns with the end portion 31a of the electrode paste 31 pattern in the first ceramic green sheet 30a in the longitudinal direction L at the same position in the longitudinal direction L. That is, both the central portion 32b of the stepped paste 32 pattern and the end portion 31a of the electrode paste 31 pattern are located on line L2.

[0082] (after cutting) Figure 9(b) shows the laminated material 40 after cutting. The laminated material 40 cut along lines L1 and L2 has a stepped layer 5 formed in the L gap 51. This is because the ceramic green sheets 30 are stacked with a staggered arrangement so that the pattern applied to the first ceramic green sheet 30a and the pattern applied to the second ceramic green sheet 30b are in the aforementioned positional relationship.

[0083] (cut surface) The cut surface resulting from cutting along line L1 is designated as the first cut surface 41. The cut surface resulting from cutting along line L2 is designated as the second cut surface 42. The first cut surface 41 corresponds to the first end face 62a of the laminate 2. The second cut surface 42 corresponds to the second end face 62b of the laminate 2. Here, "corresponds" means the part of the laminate 2 that corresponds when the laminate 40 is fired to become the laminate 2.

[0084] From the first cross-section 41 of the laminate 40, the first green sheet 30a corresponding to the inner dielectric layer 4a, the step paste 32 corresponding to the step layer 5, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the electrode paste 31 corresponding to the first internal electrode layer 10a are exposed in order along the stacking direction T. Similarly, from the second cross-section 42 of the laminate 40, the first green sheet 30a corresponding to the inner dielectric layer 4a, the electrode paste 31 corresponding to the second internal electrode layer 10b, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the step paste 32 corresponding to the step layer 5 are exposed in order along the stacking direction T. In the length direction L, the portions where the step paste 32 is located become the first L gap 51a and the second L gap 51b, respectively.

[0085] (Formation of Si segregation layer) As mentioned above, the stepped paste 32 contains a Si component for forming the Si segregation layer 14. This Si component migrates within the stepped paste 32 and adheres to the internal electrode layer 10. The Si component is a liquid-phase component. Therefore, the Si component can move over the dielectric material and towards the internal electrode layer. Specifically, the Si component adheres to the surface of the extraction electrode portion 12 and at least a portion of the ends and surfaces of the opposing electrode portion 11. The Si components that adhere to each of these internal electrode layers 10 form the Si segregation layer 14.

[0086] (Other methods for forming Si segregation layers) The method for forming the Si segregation layer 14 is not limited to the method of mixing the Si component into the stepped paste 32 described above. Another method for forming the Si segregation layer 14 is to apply the Si component to the L gap 51. In this method, the Si component is applied by printing or other means to the application pattern of the electrode paste 31 corresponding to the area where the Si segregation layer 14 is to be formed. Other methods for forming the Si segregation layer 14 include impregnating the Si component from the WT end face of the laminated chip before firing, i.e., the surface corresponding to the end face 62 of the laminated body 2.

[0087] (Effect of Si segregation layer) In this embodiment, the multilayer ceramic capacitor 1 is provided with a Si segregation layer 14 in the L gap 51. Therefore, the reliability of the multilayer ceramic capacitor 1 can be improved. This is because the Si segregation layer 14 has high IR (Insulation Resistance).

[0088] The following shows the evaluation results of the characteristics of multilayer ceramic capacitor 1. (High-temperature load reliability test) The results of the high-temperature load reliability test will be explained based on Figure 10. Figure 10 shows the results of the high-temperature load reliability test for the comparative example and the example. The method for the high-temperature load reliability test is as follows. 100 samples were prepared for each of the comparative example and Examples 1 to 8. These samples were mounted on a glass epoxy substrate using eutectic solder. The thickness of the dielectric layer in each sample was 0.5 μm. First, the initial insulation resistance value of each sample was measured. Next, the glass epoxy substrate was placed in a high-temperature chamber, and a voltage of 6.3 V was applied to each sample under conditions of 150 °C. Subsequently, the insulation resistance value was measured after 200 hours and after 500 hours. The initial insulation resistance value was compared with the insulation resistance value after time, and samples whose insulation resistance value decreased by more than one order of magnitude were considered defective. As shown in Figure 10, no defects occurred in the samples with a Si segregation layer at 200 hours. Furthermore, even at 500 hours, the number of defects was kept below 5.

[0089] In particular, in Examples 2 to 6, where the thickness of the Si segregation layer was between 0.03 μm and 0.15 μm, no defects occurred not only after 200 hours but also after 500 hours.

[0090] (Dielectric constant and mean time to failure) Based on Figure 11, the evaluation results for dielectric constant and mean time of failure will be explained. Figure 11 shows the evaluation results for dielectric constant and mean time of failure for comparative examples and examples. The dielectric layer thickness in the samples was set to four different values, from 0.3 μm to 0.6 μm. By varying the dielectric layer thickness, samples with different device thicknesses were fabricated. In addition, the Si segregation layer thickness was set to 0.07 μm and 0.08 μm.

[0091] Si has a low dielectric constant. Therefore, a decrease in dielectric constant was observed in samples with a Si segregation layer formed. In addition, an improvement in MTTF (Mean Time To Failure) was observed in samples with a Si segregation layer formed.

[0092] In particular, in Examples B and C, where the dielectric layer thickness was between 0.4 μm and 0.5 μm, a significant improvement in MTTF was observed.

[0093] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and variations are possible.

[0094] <1> It includes multiple stacked dielectric layers and multiple internal electrode layers, A laminate comprising a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, External electrodes provided on the first and second end faces, Equipped with, The internal electrode layer comprises a first internal electrode layer and a second internal electrode layer. The first internal electrode layer is drawn out to the first end face, The second internal electrode layer is drawn out to the second end face, The external electrode includes a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer. The region located on the first end face side where the first internal electrode layers do not overlap in the stacking direction, and the region located on the second end face side where the second internal electrode layers do not overlap in the stacking direction, are defined as the L-gap region. The L gap region is characterized by comprising a Si segregation layer. Multilayer ceramic capacitor.

[0095] <2> The thickness of the Si segregation layer is 0.03 μm or more and 0.15 μm or less. <1> The multilayer ceramic capacitor described above.

[0096] <3> The Si segregation layer is present at the widthwise end of the first internal electrode layer and at the widthwise end of the second internal electrode. <1> or <2> The multilayer ceramic capacitor described above.

[0097] <4> The thickness of the dielectric layer is 0.4 μm or more and 0.5 μm or less. <1> from <3> A multilayer ceramic capacitor as described in one of the following: [Explanation of symbols]

[0098] 1. Multilayer ceramic capacitor 2 Laminate 4. Dielectric layer 5 step layer 10 Internal electrode layer 11 Counter electrode section 12. Drawer electrode section 13. Floating island electrodes 14 Si segregation layer 20 External electrode 21 Base electrode layer 23 Plating layer 24 Inner plating layer 25 Surface plating layer 30 Ceramic Green Sheets 31 Electrode Paste 32-step paste 40 Laminates 41 First cross-section 42 Second cross-section 50 Electrode facing part 51 L-gap (L-gap region) 52 W gap 53 Inner layer 54 Outer layer 61 Main surface 62 End face 63 Side view R1 area R2 area T Stacking direction L (Length direction) W (width direction)

Claims

1. It includes multiple stacked dielectric layers and multiple internal electrode layers, A laminate comprising a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, External electrodes provided on the first and second end faces, Equipped with, The internal electrode layer comprises a first internal electrode layer and a second internal electrode layer. The first internal electrode layer is drawn out to the first end face, The second internal electrode layer is drawn out to the second end face, The external electrode includes a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer. The region located on the first end face side where the first internal electrode layers do not overlap in the stacking direction, and the region located on the second end face side where the second internal electrode layers do not overlap in the stacking direction, are defined as the L-gap region. The L gap region comprises a Si segregation layer, The thickness of the Si segregation layer is 0.03 μm or more and 0.15 μm or less. In the aforementioned L-gap region, island-shaped electrodes are formed. The Si segregation layer is formed on the surface of the floating island electrode, Multilayer ceramic capacitor.

2. The Si segregation layer is present at the end of the first internal electrode layer in the width direction and at the end of the second internal electrode layer in the width direction. The multilayer ceramic capacitor according to claim 1.

3. The thickness of the dielectric layer is 0.4 μm or more and 0.5 μm or less. The multilayer ceramic capacitor according to claim 1 or 2.

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