semiconductor devices and memory devices

Abstract

To provide a memory device which includes a gain-cell memory cell formed using an n-channel transistor and in which a potential lower than a potential applied to a bit line is not necessary.SOLUTION: Memory cells included in the memory device are arranged in a matrix, and each of the memory cells is connected to a write word line, a write bit line, a read word line, and a read bit line. The write word line is arranged in parallel to one of directions of a row and a column of memory cells arranged in a matrix, and the write bit line is arranged in parallel to the other of the directions of the row and the column. The read word line is arranged in parallel to the one of the directions of the row and the column of the memory cells arranged in a matrix, and the read bit line is arranged in parallel to the other of the directions of the row and the column.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a memory device, and more particularly to a memory device that can function by utilizing semiconductor properties.

[0002] Furthermore, one embodiment of the present invention relates to a semiconductor device. In this specification, a semiconductor device refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, electronic components with chips housed in a package, and electronic devices equipped with integrated circuits are examples of semiconductor devices.

[0003] Furthermore, one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to a product, method, or method of manufacture. Alternatively, one embodiment of the present invention relates to a process, machine, manufacture, or composition of matter. [Background technology]

[0004] Oxide semiconductors have recently attracted attention as semiconductors applicable to transistors. Transistors using oxide semiconductors (also called oxide semiconductor transistors or OS transistors) are thin-film transistors that can be stacked. For example, a first circuit can be constructed using Si transistors formed on a single-crystal silicon substrate, and a second circuit using OS transistors can be stacked on top of it. Furthermore, OS transistors have the characteristic of having very low leakage current (also called off-current) in the off state.

[0005] Patent Document 1 discloses a semiconductor device having multiple memory cells using OS transistors on a semiconductor substrate on which peripheral circuits such as drive circuits and control circuits are formed, and an example in which OS transistors are applied to the memory cells of a DRAM (Dynamic Random Access Memory). For example, by configuring peripheral circuits using Si transistors formed on a single-crystal silicon substrate and stacking memory cells using OS transistors on top of them, the chip area can be reduced.

[0006] Patent Document 2 discloses a semiconductor device having multiple memory cells using an OS transistor and other transistors (e.g., Si transistors), and an example in which an OS transistor is applied to a gain cell type memory cell composed of two transistors and one capacitance element (the capacitance element may be omitted). A gain cell type memory cell can function as a memory even when the capacitance of the capacitance element is small, by amplifying the stored charge with the nearest transistor. By using an OS transistor, which has the characteristic of having a very small off-current, in a gain cell type memory cell, the stored charge can be retained for a long period of time.

[0007] In this specification, a semiconductor device composed of gain-cell type memory cells using OS transistors is referred to as "NOSRAM (registered trademark, Nonvolatile Oxide Semiconductor Random Access Memory)". Furthermore, a semiconductor device having memory cells, NOSRAM, and a semiconductor device having peripheral circuits and multiple memory cells will hereafter be referred to as a storage device or memory.

[0008] On the other hand, regarding oxide semiconductors, not only oxides of monocrystalline metals, such as indium oxide and zinc oxide, but also oxides of multicrystalline metals are known. Among the oxides of multicrystalline metals, research on In-Ga-Zn oxide (also known as IGZO) is particularly active.

[0009] Research on IGZO has revealed that in oxide semiconductors, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 to 3).

[0010] Non-Patent Documents 1 and 2 disclose techniques for fabricating transistors using oxide semiconductors having a CAAC structure. Furthermore, Non-Patent Documents 4 and 5 show that even oxide semiconductors with lower crystallinity than the CAAC structure and the nc structure have minute crystals.

[0011] Non-Patent Document 6 reports that the off-current of a transistor using an oxide semiconductor is extremely small, and Non-Patent Documents 7 and 8 report LSIs and displays that utilize the property of an extremely small off-current.

Prior Art Documents

Patent Documents

[0012]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0013]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

[0014] As shown in Patent Document 2, when a memory cell is constructed using OS transistors and transistors other than OS transistors, for example, when a memory cell is constructed using Si transistors formed on a single-crystal silicon substrate and OS transistors stacked above them, peripheral circuits could not be constructed on the single-crystal silicon substrate located below the memory cell, as shown in Patent Document 1. More precisely, in order to construct peripheral circuits on the single-crystal silicon substrate located below the memory cell, it was necessary to provide a region for constructing peripheral circuits between the memory cells.

[0015] Alternatively, as in Patent Document 1, in order to stack memory cells using OS transistors on a semiconductor substrate on which peripheral circuits are formed, it was necessary to use only OS transistors as the transistors constituting the memory cells. Since OS transistors are n-channel transistors, if the gain cell type memory cell shown in Patent Document 2 is composed only of n-channel transistors, it was necessary to apply a potential lower than the potential applied to the bit line to the word line. For example, if the lowest potential applied to the bit line is set to GND, it was necessary to apply a potential lower than GND, i.e., a negative potential, to the word line.

[0016] One embodiment of the present invention aims to provide a memory device having a gain cell type memory cell, wherein the memory cell using OS transistors is stacked on a semiconductor substrate on which peripheral circuits are formed, and there is no need to apply a negative potential. Alternatively, one embodiment of the present invention aims to provide a memory device having a gain cell type memory cell, having a small chip area, and not requiring the application of a negative potential. Alternatively, one embodiment of the present invention aims to provide an electronic device having a memory device having a gain cell type memory cell, having a small chip area, and not requiring the application of a negative potential.

[0017] Furthermore, one embodiment of the present invention does not necessarily need to solve all of the above-mentioned problems; it is sufficient if it can solve at least one of them. Also, the description of the above-mentioned problems does not preclude the existence of other problems. Other problems will naturally become clear from the description in the specification, claims, drawings, etc., and it is possible to extract other problems from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0018] One embodiment of the present invention is a memory device having a memory cell array and peripheral circuits. The memory cell array has m × n memory cells (where m and n are integers of 1 or more), n first wirings, n second wirings, m third wirings, and m fourth wirings. The m × n memory cells are arranged in a matrix, and each memory cell is electrically connected to the first to fourth wirings, and each memory cell has a first transistor and a second transistor. One of the sources or drains of the first transistor is electrically connected to the first wiring, the other of the source or drain is electrically connected to the gate of the second transistor, and the gate of the first transistor is electrically connected to the third wiring. One of the sources or drains of the second transistor is electrically connected to the second wiring, and the other of the source or drain is electrically connected to the fourth wiring. The first and second transistors are n-channel transistors, and the first and second transistors have a metal oxide in the channel forming region. The peripheral circuit comprises a first circuit, a second circuit, and a controller. The first circuit is electrically connected to the first and second wirings and has the function of writing data to the memory cell and reading data from the memory cell. The second circuit is electrically connected to the third and fourth wirings and has the function of driving the third and fourth wirings. The controller has the function of controlling the first and second circuits.

[0019] Furthermore, one embodiment of the present invention is a memory device having a memory cell array and peripheral circuits. The memory cell array has m × n memory cells (where m and n are integers of 1 or more), n first wirings, n second wirings, m third wirings, and m fourth wirings. The m × n memory cells are arranged in a matrix, and each memory cell is electrically connected to the first to fourth wirings, and each memory cell has a first transistor and a second transistor. One of the sources or drains of the first transistor is electrically connected to the first wiring, the other of the source or drain is electrically connected to the gate of the second transistor, and the gate of the first transistor is electrically connected to the third wiring. One of the sources or drains of the second transistor is electrically connected to the second wiring, and the other of the source or drain is electrically connected to the fourth wiring. The first and second transistors are n-channel transistors, and the first and second transistors have a metal oxide in the channel forming region. The peripheral circuit comprises a first circuit, a second circuit, and a controller. The first circuit is electrically connected to the first and second wirings and has the function of writing data to and reading data from the memory cell. The second circuit is electrically connected to the third and fourth wirings and has the function of driving the third and fourth wirings. The controller has the function of controlling the first and second circuits and has the function of a serial peripheral interface.

[0020] Furthermore, one embodiment of the present invention is a memory device having a memory cell array and peripheral circuits. The memory cell array has m × n memory cells (where m and n are integers of 1 or more), n first wirings, n second wirings, m third wirings, and m fourth wirings. The m × n memory cells are arranged in a matrix, and each memory cell is electrically connected to the first to fourth wirings, and each memory cell has a first transistor and a second transistor. One of the sources or drains of the first transistor is electrically connected to the first wiring, the other of the source or drain is electrically connected to the gate of the second transistor, and the gate of the first transistor is electrically connected to the third wiring. One of the sources or drains of the second transistor is electrically connected to the second wiring, and the other of the source or drain is electrically connected to the fourth wiring. The first and second transistors are n-channel transistors, and the first and second transistors have a metal oxide in the channel forming region. The peripheral circuit comprises a first circuit, a second circuit, a controller, and a page buffer. The first circuit is electrically connected to the first and second wirings. The page buffer has the function of temporarily storing data. The controller has the function of writing data to the page buffer and reading data from the page buffer. The first circuit has the function of writing data read from the page buffer to a memory cell and writing data read from the memory cell to the page buffer. The second circuit is electrically connected to the third and fourth wirings and has the function of driving the third and fourth wirings. The controller has the function of controlling the first and second circuits and has the function of a serial peripheral interface.

[0021] Furthermore, in the above configuration, each memory cell has a capacitive element, one electrode of the capacitive element is electrically connected to the gate of the second transistor, and the other electrode of the capacitive element is electrically connected to wiring to which a predetermined potential is supplied.

[0022] Furthermore, in the above configuration, the first circuit supplies the first potential or the second potential to the first and second wiring. The second circuit supplies the first potential or the second potential to the fourth wiring, and supplies the first potential or the third potential to the third wiring.

[0023] Furthermore, in the above embodiment, the first circuit and the second circuit each have transistors formed on a semiconductor substrate, and the first transistor and the second transistor are formed by stacking them on top of the semiconductor substrate. [Effects of the Invention]

[0024] According to one embodiment of the present invention, a memory device having a gain cell type memory cell can be provided in which memory cells using OS transistors are stacked on a semiconductor substrate on which peripheral circuits are formed, and there is no need to apply a negative potential. Alternatively, according to one embodiment of the present invention, a memory device having a gain cell type memory cell, having a small chip area, and not requiring the application of a negative potential can be provided. Alternatively, according to one embodiment of the present invention, an electronic device having a memory device having a gain cell type memory cell, having a small chip area, and not requiring the application of a negative potential can be provided.

[0025] Furthermore, the description of these effects does not preclude the existence of other effects. Also, one embodiment of the present invention does not necessarily have to possess all of these effects. Other effects will naturally become clear from the description in the specification, claims, drawings, etc., and it is possible to extract other effects from the description in the specification, claims, drawings, etc. [Brief explanation of the drawing]

[0026] [Figure 1] Figure 1 is a schematic perspective view showing an example of a storage device configuration. [Figure 2] Figure 2 is a schematic diagram showing the relationship between Vgs and Ids of a transistor. [Figure 3] Figure 3 is a block diagram showing an example of a storage device configuration. [Figure 4]Figure 4(A) is a diagram illustrating a memory cell array, and Figures 4(B) and (C) are circuit diagrams showing examples of memory cell configurations. [Figure 5] Figures 5(A), (B), (C), (D), (E), and (F) are circuit diagrams showing examples of memory cell configurations. [Figure 6] Figure 6 illustrates the circuitry that constitutes the bit line driver circuit. [Figure 7] Figure 7 is a timing chart illustrating an example of memory cell operation. [Figure 8] Figure 8 is a block diagram showing an example of a storage device configuration. [Figure 9] Figure 9 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 10] Figures 10(A), (B), and (C) are cross-sectional views showing examples of transistor structures. [Figure 11] Figure 11(A) is a top view showing an example of transistor structure, and Figures 11(B) and (C) are cross-sectional views showing an example of transistor structure. [Figure 12] Figure 12(A) is a top view showing an example of transistor structure, and Figures 12(B) and (C) are cross-sectional views showing an example of transistor structure. [Figure 13] Figure 13(A) is a top view showing an example of transistor structure, and Figures 13(B) and (C) are cross-sectional views showing an example of transistor structure. [Figure 14] Figure 14(A) is a top view showing an example of transistor structure, and Figures 14(B) and (C) are cross-sectional views showing an example of transistor structure. [Figure 15] Figure 15(A) is a top view showing an example of transistor structure, and Figures 15(B) and (C) are cross-sectional views showing an example of transistor structure. [Figure 16] Figure 16(A) is a top view showing an example of transistor structure, and Figure 16(B) is a perspective view showing an example of transistor structure. [Figure 17] Figures 17(A) and (B) are cross-sectional views showing examples of transistor structures. [Figure 18] Figure 18 is a diagram illustrating the product image. [Figure 19] Figures 19(A), (B), (C), (D), (E1), and (E2) show examples of electronic device configurations. [Figure 20] Figures 20(A) and (B) show examples of the configuration of electronic equipment. [Figure 21] Figures 21(A), (B), and (C) show examples of the configuration of electronic devices. [Figure 22] Figures 22(A) and (B) show examples of the configuration of electronic equipment. [Modes for carrying out the invention]

[0027] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different forms, and that their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0028] Furthermore, the multiple embodiments shown below can be combined as appropriate. Also, if multiple configuration examples are shown within a single embodiment, these configuration examples can be combined as appropriate.

[0029] In the drawings attached to this specification, the components are classified by function and shown as independent blocks in block diagrams. However, in reality, it is difficult to completely separate the components by function, and one component may be involved in multiple functions.

[0030] Furthermore, in drawings, dimensions, layer thickness, and area may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0031] Furthermore, in drawings and other documents, the same reference numeral may be used for identical elements, elements with similar functions, elements made of the same material, or elements formed simultaneously, and repeated explanations may be omitted.

[0032] Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer."

[0033] Furthermore, in this specification, terms indicating arrangement, such as "above" or "below," do not limit the positional relationship of the components to "directly above" or "directly below." For example, the expression "gate electrode on the gate insulating layer" does not exclude components that include other components between the gate insulating layer and the gate electrode.

[0034] Furthermore, in this specification, ordinal numbers such as "1st," "2nd," and "3rd" are used to avoid confusion of constituent elements and do not imply any numerical limitation.

[0035] Furthermore, in this specification, "electrically connected" includes cases where connections are made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical function" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitive elements, and other elements with various functions.

[0036] Furthermore, in this specification and other documents, "voltage" often refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage and potential difference can be used interchangeably.

[0037] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It has a channel-forming region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0038] Furthermore, the functions of the source and drain may be reversed when transistors with different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification.

[0039] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the gate voltage Vgs relative to the source is lower than the threshold voltage Vth, and in a p-channel transistor where the gate voltage Vgs relative to the source is higher than the threshold voltage Vth. In other words, the off-current of an n-channel transistor may refer to the drain current when the gate voltage Vgs relative to the source is lower than the threshold voltage Vth.

[0040] In the above explanation of off-current, drain may be read as source. In other words, off-current sometimes refers to the source current when the transistor is in the off state. Also, sometimes the term leakage current is used interchangeably with off-current. Furthermore, in this specification, off-current sometimes refers to the current that flows between the source and drain when the transistor is in the off state.

[0041] Furthermore, in this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors), and so on.

[0042] For example, when a metal oxide is used in the channel formation region of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, if a metal oxide has at least one of the following properties: amplification, rectification, and switching, it can be called a metal oxide semiconductor. That is, a transistor having a metal oxide in its channel formation region can be called an "oxide semiconductor transistor" or "OS transistor." Similarly, the "transistor using an oxide semiconductor" mentioned above is also a transistor having a metal oxide in its channel formation region.

[0043] Furthermore, in this specification, metal oxides containing nitrogen may also be referred to as metal oxides. Alternatively, metal oxides containing nitrogen may be referred to as metal oxynitrides. Details regarding metal oxides will be described later.

[0044] (Embodiment 1) This embodiment describes an example of the configuration of a memory device according to one embodiment of the present invention. The memory device according to one embodiment of the present invention is a memory device that can function by utilizing semiconductor properties, and is also called a memory. Furthermore, the memory device according to one embodiment of the present invention has a structure in which memory cells, which are composed of OS transistors, are stacked on a semiconductor substrate on which peripheral circuits are formed.

[0045] <Schematic diagram of a memory device in perspective> Figure 1 is a schematic perspective view showing an example of the configuration of a storage device 100 according to one embodiment of the present invention.

[0046] The memory device 100 has a structure in which layer 101 and layer 201 are stacked on top of layer 101. Each layer 101 and layer 201 is provided with circuits that can function by utilizing semiconductor properties, with peripheral circuits 110 provided on layer 101 and a memory cell array 210 provided on layer 201. In the drawings described herein, the main signal flow is shown by arrows or lines, and power lines and the like may be omitted.

[0047] The peripheral circuit 110 includes a row decoder 121, a word line driver circuit 122, a column decoder 131, a bit line driver circuit 132, an output circuit 140, and a control logic circuit 160. The peripheral circuit 110 also functions as a drive circuit and control circuit for the memory cell array 210.

[0048] The peripheral circuit 110 is constructed using transistors formed on a semiconductor substrate SUB. The semiconductor substrate SUB is not particularly limited as long as it is possible to form the channel region of the transistor. For example, single-crystal silicon substrates, single-crystal germanium substrates, compound semiconductor substrates (SiC substrates, GaN substrates, etc.), SOI (Silicon on Insulator) substrates, etc., can be used.

[0049] Furthermore, as SOI substrates, SIMOX (Separation by Implanted Oxygen) substrates may be used, which are formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface while eliminating defects in the surface layer. Other SOI substrates may be used that are formed using methods such as the smart cut method, which utilizes the growth of minute voids formed by hydrogen ion implantation through heat treatment to cleave the semiconductor substrate, or the ELTRAN method (registered trademark: Epitaxial Layer Transfer). Transistors formed using a single-crystal substrate have a single-crystal semiconductor in the channel formation region.

[0050] This embodiment describes the case where a single-crystal silicon substrate is used as the semiconductor substrate SUB. Furthermore, a transistor formed on a single-crystal silicon substrate is referred to as a Si transistor. The peripheral circuit 110, configured using Si transistors, is capable of high-speed operation.

[0051] The memory cell array 210 has multiple memory cells 211, and each memory cell 211 is constructed using OS transistors. Since OS transistors are thin-film transistors, the memory cell array 210 can be stacked on a semiconductor substrate SUB.

[0052] Here, since the band gap of the oxide semiconductor is 2.5 eV or more, preferably 3.0 eV or more, the OS transistor has a small leakage current due to thermal excitation and a very small off-current. Off-current refers to the current that flows between the source and drain when the transistor is in the off state.

[0053] The metal oxide used in the channel formation region of an OS transistor is preferably an oxide semiconductor containing at least one of indium (In) and zinc (Zn). Typical examples of such oxide semiconductors include In-M-Zn oxide (where element M is, for example, Al, Ga, Y, or Sn). By reducing impurities such as water and hydrogen, which act as electron donors, and by also reducing oxygen vacancies, the oxide semiconductor can be made i-type (intrinsic) or substantially i-type. Such an oxide semiconductor can be called a highly purified oxide semiconductor. Further details of the OS transistor will be described in Embodiment 4.

[0054] The memory cell 211 has the function of storing data by accumulating and holding electric charge. The memory cell 211 may have the function of storing binary data (high level or low level), or it may have the function of storing four or more levels of data, or it may have the function of storing analog data.

[0055] OS transistors are suitable for use in memory cells 211 because they have a very low off-current. For example, OS transistors can achieve off-currents of 100 zA / μm or less, 10 zA / μm or less, 1 zA / μm or less, or 10 yA / μm or less per 1 μm channel width. By using OS transistors in memory cells 211, data stored in memory cells 211 can be retained for a long period of time.

[0056] Because OS transistors do not experience a significant increase in off-current even at high temperatures, data stored in the memory cell 211 is less likely to be lost even at high temperatures caused by heat generation from the peripheral circuitry 110. Using OS transistors enhances the reliability of the memory device 100.

[0057] Figure 2 also shows the relationship between Vgs and Ids of an OS transistor. Figure 2 is a schematic diagram showing the relationship between the gate voltage Vgs relative to the source and the current Ids flowing between the source and drain of an OS transistor when a constant voltage is applied between the source and drain.

[0058] As shown in Figure 2, OS transistors have the property that as the temperature increases, the threshold voltage shifts to the negative, and the current flowing between the source and drain when the transistor is in the ON state (also called the ON current) increases. In other words, the memory cell 211 can operate at high speed even at high temperatures.

[0059] As shown in Figure 1, in the memory cell array 210, the memory cells 211 are arranged in a matrix (also called a matrix), and each memory cell 211 is connected to wiring WL and wiring BL. A memory cell 211 is selected by the potential applied to wiring WL, and data is written to the selected memory cell 211 via wiring BL. Alternatively, a memory cell 211 is selected by the potential applied to wiring WL, and data is read from the selected memory cell 211 via wiring BL.

[0060] In other words, wiring WL functions as a word line for memory cell 211, and wiring BL functions as a bit line for memory cell 211. Although not shown in Figure 1, wiring WL is composed of word line wwl and word line rwl, and wiring BL is composed of bit line wbl and bit line rbl (see Figure 3).

[0061] <Block diagram of storage device> Figure 3 is a block diagram showing an example configuration of the storage device 100.

[0062] The storage device 100 includes peripheral circuits 110 and a memory cell array 210. The peripheral circuits 110 include a raw decoder 121, a word line driver circuit 122, a column decoder 131, a bit line driver circuit 132, an output circuit 140, and a control logic circuit 160. The memory cell array 210 includes memory cells 211, word lines wwl, word lines rwl, bit lines wbl, and bit lines rbl.

[0063] The storage device 100 receives the potentials Vss, Vdd, Vdh, and reference potential Vref as inputs. The potential Vdh is the high power supply potential of the word line wwl.

[0064] The storage device 100 receives the clock signal CLK, chip enable signal CE, global write enable signal GW, byte write enable signal BW, address signal ADDR, and data signal WDATA as inputs, and outputs the data signal RDATA. These signals are digital signals that can be represented as high or low levels (High or Low, H or L, 1 or 0, etc.).

[0065] Here, the byte write enable signal BW, the address signal ADDR, the data signal WDATA, and the data signal RDATA are signals that have multiple bits.

[0066] In this specification, for signals having multiple bits, for example, if the byte write enable signal BW has 4 bits, it will be written as byte write enable signal BW[3:0]. This means that the byte write enable signal has bits BW[0] through BW[3], and if it is necessary to specify a single bit, it will be written as, for example, byte write enable signal BW[0]. Also, when referred to as byte write enable signal BW, it refers to any bit.

[0067] For example, the byte write enable signal BW can be 4 bits, and the data signal WDATA and data signal RDATA can be 32 bits. That is, the byte write enable signal BW, data signal WDATA, and data signal RDATA can be denoted as byte write enable signal BW[3:0], data signal WDATA[31:0], and data signal RDATA[31:0], respectively.

[0068] In the storage device 100, the aforementioned circuits, signals, and potentials can be appropriately selected or omitted as needed. Alternatively, other circuits, signals, or potentials may be added.

[0069] The control logic circuit 160 processes the chip enable signal CE and the global write enable signal GW to generate control signals for the low decoder 121 and the column decoder 131. For example, when the chip enable signal CE is high and the global write enable signal GW is low, the low decoder 121 and the column decoder 131 perform a read operation; when the chip enable signal CE is high and the global write enable signal GW is high, the low decoder 121 and the column decoder 131 perform a write operation; and when the chip enable signal CE is low, the low decoder 121 and the column decoder 131 can operate in standby mode regardless of whether the global write enable signal GW is high or low. The signals processed by the control logic circuit 160 are not limited to these, and other signals may be input as needed.

[0070] Furthermore, the control logic circuit 160 processes the byte write enable signal BW[3:0] to control the write operation. Specifically, when the byte write enable signal BW[0] is high, the low decoder 121 and column decoder 131 perform a write operation of the data signal WDATA[7:0]. Similarly, when the byte write enable signal BW[1] is high, a write operation of the data signal WDATA[15:8] is performed; when the byte write enable signal BW[2] is high, a write operation of the data signal WDATA[23:16] is performed; and when the byte write enable signal BW[3] is high, a write operation of the data signal WDATA[31:24] is performed.

[0071] In addition to the control signals generated by the control logic circuit 160 described above, the address signal ADDR is input to the row decoder 121 and the column decoder 131.

[0072] The raw decoder 121 decodes the address signal ADDR and generates a control signal for the word line driver circuit 122. The word line driver circuit 122 has the function of driving word lines wwl and word lines rwl. Based on the control signal from the raw decoder 121, the word line driver circuit 122 selects either word line wwl or word line rwl for the row to be accessed.

[0073] Furthermore, if the memory cell array 210 is divided into multiple blocks, a pre-decoder 123 may be provided. The pre-decoder 123 has the function of decoding the address signal ADDR to determine the block to be accessed.

[0074] The column decoder 131 and bit line driver circuit 132 have functions such as writing data input by the data signal WDATA to the memory cell array 210, reading data from the memory cell array 210, amplifying the read data, and outputting it to the output circuit 140.

[0075] The output circuit 140 outputs the data read from the memory cell array 210 by the column decoder 131 and the bit line driver circuit 132 as a data signal RDATA.

[0076] In the example shown in Figure 3, the bit line driver circuit 132 includes a pre-charge circuit 133, a sense amplifier circuit 134, an output MUX (multiplexer) circuit 135, and a write driver circuit 136. The pre-charge circuit 133, sense amplifier circuit 134, output MUX circuit 135, and write driver circuit 136 will be described later.

[0077] <Memory cell array> Figure 4(A) shows an example of the configuration of the memory cell array 210. The memory cell array 210 has m (where m is an integer greater than or equal to 1) memory cells 211 in each column and n (where n is an integer greater than or equal to 1) in each row, for a total of m × n memory cells 211, which are arranged in a matrix.

[0078] In Figure 4(A), the addresses of memory cells 211 are also shown, with [1,1], [i,1], [m,1], [1,j], [i,j], [m,j], [1,n], [i,n], and [m,n] (where i is an integer between 1 and m, and j is an integer between 1 and n) being the addresses of memory cells 211. For example, the memory cell 211 labeled [i,j] is the memory cell 211 at row i and column j.

[0079] Furthermore, the memory cell array 210 has n bit lines wbl (wbl(1) to wbl(n)), n bit lines rbl (rbl(1) to rbl(n)), m word lines wwl (wwl(1) to wwl(m)), and m word lines rwl (rwl(1) to rwl(m)).

[0080] Each memory cell 211 is connected to a bit line wbl, a bit line rbl, a word line wwl, and a word line rwl. As shown in Figure 4(A), the memory cell 211 with address [i,j] is electrically connected to the word line driver circuit 122 via the word line wwl(i) and word line rwl(i), and is electrically connected to the bit line driver circuit 132 via the bit line wbl(j) and bit line rbl(j).

[0081] <membrane> Figure 4(B) is a circuit diagram showing an example configuration of the memory cell 211.

[0082] The memory cell 211 has a transistor M11 and a transistor M12. One source or drain of transistor M11 is electrically connected to the gate of transistor M12, the other source or drain of transistor M11 is connected to the bit line wbl, and the gate of transistor M11 is connected to the word line wwl. Also, one source or drain of transistor M12 is connected to the bit line rbl, and the other source or drain of transistor M12 is connected to the word line rwl. Here, the gate of transistor M12 is referred to as node N11.

[0083] Furthermore, the memory cell 211 may have a capacitive element C11. An example configuration in which the memory cell 211 has a capacitive element C11 is shown in Figure 4(C). The first terminal of the capacitive element C11 is electrically connected to node N11, and the second terminal of the capacitive element C11 is connected to wiring CAL. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element C11.

[0084] Bit line wbl functions as a write bit line, bit line rbl functions as a read bit line, word line wwl functions as a write word line, and word line rwl functions as a read word line. Transistor M11 functions as a switch to make node N11 and bit line wbl conduct or not conduct.

[0085] Data is written by applying a high-level potential to the word line wwl, causing transistor M11 to conduct, and electrically connecting node N11 and bit line wbl. Specifically, when transistor M11 is conducting, a potential corresponding to the data to be written is applied to bit line wbl, and this potential is written to node N11. Subsequently, a low-level potential is applied to the word line wwl, causing transistor M11 to deconduct, thereby maintaining the potential of node N11.

[0086] Data is read by applying a predetermined potential to the bit line rbl, then making the bit line rbl electrically floating, and applying a low-level potential to the word line rwl. Hereafter, applying a predetermined potential to the bit line rbl and then making the bit line rbl floating will be referred to as precharging the bit line rbl.

[0087] For example, by precharging the bit line rbl with a potential Vdd, transistor M12 has a potential difference between its source and drain, and the current flowing between the source and drain of transistor M12 is determined by the potential held at node N11. Therefore, by reading the potential change of the bit line rbl when it is floating, the potential held at node N11 can be read.

[0088] Furthermore, rows containing memory cells 211 for writing data are selected by a word line wwl to which a high-level potential is applied, and rows containing memory cells 211 for reading data are selected by a word line rwl to which a low-level potential is applied. Conversely, rows containing memory cells 211 that do not write data can be deselected by applying a low-level potential to the word line wwl, and rows containing memory cells 211 that do not read data can be deselected by applying the same potential to the word line rwl as the potential used to precharge the bit line rbl.

[0089] Here, transistors M11 and M12 can be transistors having a metal oxide in the channel formation region (OS transistors). For example, the channel formation region of transistors M11 and M12 can be made of a metal oxide having one of the following: indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), or zinc. In particular, a metal oxide consisting of indium, gallium, and zinc is preferred.

[0090] Because OS transistors have a very low off-current, using an OS transistor for transistor M11 allows the potential written to node N11 to be retained for a long time. In other words, the data written to memory cell 211 can be retained for a long time.

[0091] The transistor used for transistor M12 is not particularly limited. An OS transistor, a Si transistor, or other transistor may be used for transistor M12, but it is preferable to use OS transistors for transistors M12 and M11 so that the memory cell array 210 can be stacked on the peripheral circuit 110.

[0092] Furthermore, because the OS transistor has a very small off-current, the memory cell 211 can be configured without a capacitive element C11. If the memory cell 211 does not have a capacitive element C11, the potential written to node N11 is maintained by the gate capacitance of transistor M12, etc.

[0093] Memory cell 211 is a gain cell type memory cell composed of two transistors or two transistors with one capacitance element. Gain cell type memory cells can function as memory even when their charge storage capacity is small, by amplifying the stored charge with the nearest transistor. Memory cell 211 is the NOSRAM described above.

[0094] Furthermore, the memory cell 211 may be constructed using transistors M13 and M14, each having a back gate. Figure 5(A) is a circuit diagram showing an example configuration of the memory cell 212. The memory cell 212 has transistors M13 and M14. Transistors M13 and M14 have a front gate and a back gate.

[0095] One source or drain of transistor M13 is electrically connected to the front gate and back gate of transistor M14, the other source or drain of transistor M13 is connected to the bit line wbl, and the front gate and back gate of transistor M13 are connected to the word line wwl. Also, one source or drain of transistor M14 is connected to the bit line rbl, and the other source or drain of transistor M14 is connected to the word line rwl. Here, the front gate and back gate of transistor M14 are referred to as node N12.

[0096] Transistors M13 and M14 can increase their on-current by having back gates. That is, the memory cell 212 can operate at high speed.

[0097] Figure 5(B) is a circuit diagram showing an example configuration of the memory cell 213. The memory cell 213 includes transistor M13 and transistor M14.

[0098] One source or drain of transistor M13 is electrically connected to the front gate of transistor M14, the other source or drain of transistor M13 is connected to the bit line wbl, and the front gate of transistor M13 is connected to the word line wwl. Also, one source or drain of transistor M14 is connected to the bit line rbl, and the other source or drain of transistor M14 is connected to the word line rwl. The back gates of transistors M13 and M14 are connected to wiring VBG. Wiring VBG functions as wiring to apply a predetermined potential to the back gates of transistors M13 and M14. Here, the front gate of transistor M14 is referred to as node N13.

[0099] By applying a predetermined potential to the back gates of transistors M13 and M14 via the wiring VBG, the threshold voltages of transistors M13 and M14 can be increased or decreased. Specifically, increasing the potential applied to the back gates of transistors M13 and M14 shifts the threshold voltage to the negative, and decreasing the potential applied to the back gates of transistors M13 and M14 shifts the threshold voltage to the positive. Shifting the threshold voltage to the negative increases the on-current of the transistors, allowing the memory cell 213 to operate at high speed. Shifting the threshold voltage to the positive reduces the off-current of the transistors, allowing the memory cell 213 to retain data for a longer period of time.

[0100] In the memory cell 213 shown in Figure 5(B), the back gates of transistors M13 and M14 are connected to wiring VBG. However, the back gates of transistor M13 and transistor M14 may be connected to different wirings. For example, the back gate of transistor M13 may be connected to wiring VBG1, and the back gate of transistor M14 may be connected to wiring VBG2. By lowering the potential applied to wiring VBG1, the off-current of transistor M13 can be reduced, and by increasing the potential applied to wiring VBG2, the on-current of transistor M14 can be increased. Transistors M13 and M14 can be configured to suit their respective purposes.

[0101] Figure 5(C) is a circuit diagram showing an example configuration of the memory cell 214. The memory cell 214 has transistors M13 and M14 and is connected to the bit line wbl, bit line rbl, word line wwl, word line rwl, and wiring VBG, in addition to the word line rwlb.

[0102] One of the sources or drains of transistor M13 is electrically connected to the front gate of transistor M14, the other source or drain of transistor M13 is connected to the bit line wbl, and the front gate of transistor M13 is connected to the word line wwl. Also, one of the sources or drains of transistor M14 is connected to the bit line rbl, and the other source or drain of transistor M14 is connected to the word line rwl. The back gate of transistor M14 is connected to the word line rwlb, and the back gate of transistor M13 is connected to wiring VBG. Wiring VBG functions as wiring to apply a predetermined potential to the back gate of transistor M13, and the front gate of transistor M14 is referred to as node N14.

[0103] For wiring VBG, refer to the explanation for memory cell 213. Also, transistor M13 may be replaced with a transistor without a back gate.

[0104] The word line rwlb, like the word line wwl and word line rwl, is driven by the word line driver circuit 122. The word line driver circuit 122 can increase the on-current of transistor M14 during read operation by increasing the potential applied to the word line rwlb of the row to be read. Conversely, by applying a low potential to the word lines rwlb of rows other than the row to be read, the off-current of transistor M14 that is not performing read operations can be reduced.

[0105] Furthermore, memory cells 212, 213, and 214 may each have capacitive elements C12, C13, and C14, respectively. An example configuration where memory cell 212 has a capacitive element C12 is shown in Figure 5(D), an example configuration where memory cell 213 has a capacitive element C13 is shown in Figure 5(E), and an example configuration where memory cell 214 has a capacitive element C14 is shown in Figure 5(F). Note that the configuration of memory cell 211 is the same as the example where memory cell 211 has a capacitive element C11, so the explanation for memory cell 211 will be used.

[0106] <Example of bit line driver circuit configuration> The bit line driver circuit 132 is provided with a circuit 137, as shown in Figure 6, for each column. Figure 6 is a circuit diagram showing an example of the configuration of circuit 137. In this embodiment, the memory cell array 210 is assumed to have 128 memory cells 211 in each row (n=128).

[0107] Circuit 137 includes transistors M21 to M26, a sense amplifier circuit 31, an AND circuit 32, an analog switch 33, and an analog switch 34.

[0108] Circuit 137 operates according to the signals SEN[3:0], SEP[3:0], PRE, RSEL[3:0], WSEL, GRSEL[3:0], and GWSEL[15:0]. Note that one bit of the 4-bit signal SEN[3:0] is input to each circuit 137. The same applies to other signals with multiple bits (such as SEP[3:0]).

[0109] The bit line driver circuit 132 writes the data DIN[31:0] to the memory cell array 210 and reads the data DOUT[31:0] from the memory cell array 210. One circuit 137 has the function of writing any one bit of the 32-bit data DIN[31:0] to the memory cell array 210 and reading any one bit of the 32-bit data DOUT[31:0] from the memory cell array 210.

[0110] Note that data DIN[31:0] and data DOUT[31:0] are internal signals, corresponding to data signals WDATA and RDATA, respectively.

[0111] <<Pre-charge circuit>> Transistor M21 constitutes the precharge circuit 133. Transistor M21 precharges the bit line rbl to potential Vdd. The signal PRE is the precharge signal, and the conduction state of transistor M21 is controlled by the signal PRE.

[0112] <<Sense Amplifier Circuit>> The sense amplifier circuit 31 constitutes the sense amplifier circuit 134. During read operations, the sense amplifier circuit 31 determines whether the data input to the bit line rbl is high or low level. During write operations, the sense amplifier circuit 31 functions as a latch circuit that temporarily holds the data DIN input from the write driver circuit 136.

[0113] The sense amplifier circuit 31 shown in Figure 6 is a latch-type sense amplifier. The sense amplifier circuit 31 has two inverter circuits, and the input node of one inverter circuit is connected to the output node of the other inverter circuit. If the input node of one inverter circuit is node NS and the output node is node NSB, complementary data is held at node NS and node NSB.

[0114] Signals SEN and SEP are sense amplifier enable signals for activating the sense amplifier circuit 31, and the reference potential Vref is the readout determination potential. The sense amplifier circuit 31 determines whether the potential of node NSB at the time of activation is high level or low level, based on the reference potential Vref.

[0115] The AND circuit 32 controls the conduction state between node NS and bit line wbl. Additionally, analog switch 33 controls the conduction state between node NSB and bit line rbl, and analog switch 34 controls the conduction state between node NS and the wiring supplying the reference potential Vref.

[0116] The signal WSEL is a write selection signal that controls the AND circuit 32. The signal RSEL[3:0] is a read selection signal that controls the analog switches 33 and 34.

[0117] <<Output MUX Circuit>> Transistors M22 and M23 constitute the output MUX circuit 135. The signal GRSEL[3:0] is a global readout selection signal that controls the output MUX circuit 135. The output MUX circuit 135 has the function of selecting 32 bit lines rbl from 128 bit lines rbl to read data. The output MUX circuit 135 functions as a 128-input, 32-output multiplexer.

[0118] The output MUX circuit 135 reads the data DOUT[31:0] from the sense amplifier circuit 134 and outputs it to the output circuit 140.

[0119] <<Writing driver circuit>> Transistors M24 through M26 constitute the write driver circuit 136. The signal GWSEL[15:0] is a global write selection signal that controls the write driver circuit 136. The write driver circuit 136 has the function of writing the data DIN[31:0] to the sense amplifier circuit 134.

[0120] The write driver circuit 136 has the function of selecting the column to which to write data DIN[31:0]. The write driver circuit 136 writes data in byte units, half-word units, or whole-word units according to the signal GWSEL[15:0].

[0121] Circuit 137 is electrically connected to data DIN[k] (where k is an integer between 0 and 31) every four columns. Additionally, circuit 137 is electrically connected to data DOUT[k] every four columns.

[0122] <Example of memory cell operation> Figure 7 is a timing chart illustrating an example of memory cell 211 operation. Figure 7 explains the potential relationships between word line wwl, word line rwl, bit line wbl, and bit line rbl during the write and read operations of memory cell 211. The word line rwlb, to which memory cell 214 is connected, will be explained later.

[0123] In Figure 7, the period Twrite is the period during which write operations are performed, and the period Tread is the period during which read operations are performed. Also, the high level of the word line rwl, the bit line wbl, and the bit line rbl is at potential Vdd, and the low level is at potential Vss. The high level of the word line wwl is at potential Vdh, and the low level of the word line wwl is at potential Vss.

[0124] <<Writing operation>> During the Twrite period, a potential Vdata corresponding to the data to be written is applied to the bit line wbl. With the potential Vdata corresponding to the data to be written applied to the bit line wbl, when a potential Vdh is applied to the word line wwl of the row where the memory cell 211 to be written is located, the transistor M11 becomes conductive, and the potential Vdata corresponding to the data to be written is written to node N11.

[0125] Furthermore, during the Twrite period, the potential Vdd is applied to the bit line rbl and the word line rwl.

[0126] <<Read operation>> During the Tread period, the bit line rbl is precharged with a potential Vdd. When the bit line rbl is floating and a potential Vss is applied to the word line rwl of the row where the memory cell 211 for reading data is located, if the data written to node N11 is at a high level, transistor M12 becomes conductive and the potential of the bit line rbl begins to decrease.

[0127] When the potential of the bit line rbl drops by ΔV1 and becomes lower than the reference potential Vref, the sense amplifier circuit 31 determines that the bit line rbl is at a low level.

[0128] Furthermore, even if the bit line rbl is floating and a potential Vss is applied to the word line rwl of the row where the memory cell 211 for reading data is located, if the data written to node N11 is at a low level, the transistor M12 will not become conductive, and therefore the potential of the bit line rbl will not change. In this case, the sense amplifier circuit 31 determines that the bit line rbl is at a high level.

[0129] During the Tread period, a potential Vss is applied to the bit line wbl and the word line wwl.

[0130] Furthermore, regarding the word line rwlb to which the memory cell 214 is connected, for example, the high level of the word line rwlb can be set to potential Vdh, and the low level of the word line rwlb can be set to potential Vss.

[0131] During the Twrite period, a potential Vss is applied to the word line rwlb, and during the Tread period, a potential Vdh is applied to the word line rwlb of the row where the memory cell 214 from which data is read is located.

[0132] Applying a potential Vdh to the word line rwlb increases the on-current of transistor M14 in the memory cell 214 that reads data. Conversely, applying a potential Vss to the word line rwlb reduces the off-current of transistor M14.

[0133] As described above, the memory device 100 has a gain cell type memory cell composed of n-channel transistors, and the word line wwl, word line rwl, bit line wbl, and bit line rbl are represented as high or low levels by three types of potentials Vss, Vdd, and Vdh. In other words, a potential lower than the low-level potential Vss applied to the bit line wbl and bit line rbl is not required, and the memory device 100 can be operated with fewer power supplies. This reduces the cost of electronic devices that incorporate the memory device 100.

[0134] Furthermore, by using OS transistors for all the transistors constituting the memory cell 211, the memory cell array 210 can be stacked on the peripheral circuit 110. This allows for a reduction in the chip area of ​​the storage device 100.

[0135] This embodiment can be implemented in appropriate combination with other embodiments described herein.

[0136] (Embodiment 2) This embodiment describes an example in which the storage device described in the above embodiment has a Serial Peripheral Interface (SPI). The Serial Peripheral Interface is a type of serial interface used for communication between semiconductor devices that input and output digital signals, and has the characteristic of reducing the number of terminals required for signal input and output. For example, it is used for communication between a CPU (Central Processing Unit) and a storage device.

[0137] <Block diagram of storage device> Figure 8 is a block diagram showing an example configuration of the storage device 105. The storage device 105 has peripheral circuits 115 and a memory cell array 210. Similar to the storage device 100 described in the above embodiment, in the storage device 105, the peripheral circuits 115 are configured using Si transistors, the memory cell array 210 has a plurality of memory cells 211, and the memory cells 211 are configured using OS transistors.

[0138] The peripheral circuit 115 includes a row decoder 121, a word line driver circuit 122, a column decoder 131, a bit line driver circuit 132, a page buffer 138, a potential generation circuit 150, an SPI controller 161, and a status register 168. The memory cell array 210 includes a memory cell 211, a word line wwl, a word line rwl, a bit line wbl, and a bit line rbl.

[0139] Note that the memory cell array 210, row decoder 121, word line driver circuit 122, column decoder 131, and bit line driver circuit 132 are the same as in the above embodiment and therefore will not be described.

[0140] The storage device 105 receives the potentials Vss and Vdh as inputs. It also receives the clock signal SCLK, the chip select signal CS, the data input signal SI, the data output signal SO, the hold signal HOLD, and the write protection signal WP.

[0141] The potential generation circuit 150 includes a regulator 151, a regulator 152, and a power switch 153. From the potentials Vss and Vdh input to the storage device 105, the regulator 151 generates a potential Vdd, the regulator 152 generates a reference potential Vref, and the power switch 153 can control the output of the potential Vdh.

[0142] The potential generation circuit 150 has the function of supplying potentials Vdh, Vdd, and Vss to the peripheral circuit 115. For example, potential Vdh can be set to 3.3V, potential Vdd to 1.2V, and potential Vss to 0V (GND).

[0143] Furthermore, if the memory cell 211 is configured using a transistor with a back gate, the potential generation circuit 150 may have the function of generating and supplying a potential to be applied to the back gate.

[0144] The SPI controller 161 includes a serial-to-parallel converter 162, an instruction decoder circuit 163, a page address generation circuit 164, a command generation circuit 165, a byte address generation circuit 166, and a parallel-to-serial converter 167.

[0145] The SPI controller 161 processes the signals input to the storage device 105 and outputs the chip enable signal CE and the global write enable signal GW to the row decoder 121 and the column decoder 131.

[0146] For example, when the chip enable signal CE is high and the global write enable signal GW is low, the low decoder 121 and column decoder 131 perform a read operation; when the chip enable signal CE is high and the global write enable signal GW is high, the low decoder 121 and column decoder 131 perform a write operation; and when the chip enable signal CE is low, regardless of whether the global write enable signal GW is high or low, the low decoder 121 and column decoder 131 can be in standby mode.

[0147] The SPI controller 161 processes the signals input to the storage device 105 and outputs the write data signal WDATA to the page buffer 138. The page buffer 138 outputs the read data signal RDATA, which has been read from the memory cell array 210, to the SPI controller 161.

[0148] Furthermore, the page address generation circuit 164 outputs a low address signal RADR to the low decoder 121, and the byte address generation circuit 166 outputs a column address signal CADR to the column decoder 131. The memory cell 211 to be read from or written to is determined by the low address signal RADR and the column address signal CADR.

[0149] The page buffer 138 has the function of temporarily storing data signals to be read or written, and the status register 168 is a memory that stores the operating mode of the SPI controller 161.

[0150] For example, by setting the storage capacity of the page buffer 138 to 256 bytes (2048 bits) and the memory cell array 210 to have 2048 memory cells 211 in one row and 1024 memory cells 211 in one column, the storage device 105 can be made into a storage device with a capacity of 256 KBytes.

[0151] Furthermore, the write protection signal WP is a signal that prevents writing to the status register 168, and the hold signal HOLD is a signal that temporarily suspends the operation of the storage device 105.

[0152] The signals processed by the SPI controller 161 are not limited to those described above; other signals may be input or output as needed.

[0153] This embodiment can be implemented in appropriate combination with other embodiments described herein.

[0154] (Embodiment 3) This embodiment describes an example configuration of a Si transistor applicable to the peripheral circuit 110 described in the above embodiment, and an OS transistor applicable to the memory cell 211. In this embodiment, the Si transistor and the OS transistor together are referred to as a semiconductor device.

[0155] <Example of semiconductor device configuration> The semiconductor device shown in Figure 9 includes a transistor 300, a transistor 500, and a capacitive element 600. Figure 10(A) is a cross-sectional view of transistor 500 in the channel length direction, Figure 10(B) is a cross-sectional view of transistor 500 in the channel width direction, and Figure 10(C) is a cross-sectional view of transistor 300 in the channel width direction.

[0156] Transistor 500 is an OS transistor (OS transistor) that has a metal oxide in its channel formation region. Because transistor 500 has a low off-current, it can be used in semiconductor devices to retain memory content for long periods of time. Alternatively, it can reduce the capacitance required to store charge.

[0157] The semiconductor device described in this embodiment has a transistor 300, a transistor 500, and a capacitive element 600, as shown in Figure 9. Transistor 500 is located above transistor 300, and the capacitive element 600 is located above both transistor 300 and transistor 500.

[0158] The transistor 300 is provided on a substrate 311 and has a conductor 316, an insulator 315, a semiconductor region 313 consisting of a part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region.

[0159] As shown in Figure 10(C), the transistor 300 has its semiconductor region 313's top surface and side surface in the channel width direction covered by a conductor 316 via an insulator 315. By making the transistor 300 a Fin type in this way, the effective channel width can be increased, thereby improving the on-characteristics of the transistor 300. In addition, the contribution of the gate electrode's electric field can be increased, thus improving the off-characteristics of the transistor 300.

[0160] Note that transistor 300 can be either a p-channel or n-channel type.

[0161] In the low-resistance region 314a and low-resistance region 314b, which are the channel-forming region of the semiconductor region 313, the region near it, the source region, or the drain region, it is preferable that a semiconductor such as a silicon-based semiconductor is included, and it is preferable that single-crystal silicon is included. Alternatively, it may be formed from a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing is also possible. Alternatively, the transistor 300 may be made into a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, etc.

[0162] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0163] The conductor 316, which functions as the gate electrode, can be made of a conductive material such as silicon, a semiconductor material, a metallic material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0164] Furthermore, since the work function is determined by the material of the conductor, the Vth of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use a laminate of metallic materials such as tungsten or aluminum as the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0165] Note that the transistor 300 shown in Figure 9 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration and driving method.

[0166] The transistor 300 is covered by an insulator 320, an insulator 322, an insulator 324, and an insulator 326, which are stacked in that order.

[0167] For insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, etc. may be used.

[0168] The insulator 322 may also function as a planarizing film that flattens any steps caused by the transistor 300 or other components located below it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0169] Furthermore, it is preferable to use a film for the insulator 324 that has barrier properties to prevent hydrogen and impurities from diffusing from the substrate 311 or the transistor 300 to the region where the transistor 500 is provided.

[0170] As an example of a film having barrier properties against hydrogen, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the properties of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0171] The amount of hydrogen desorption can be analyzed using methods such as thermal desorption spectroscopy (TDS). For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm 2 The following is acceptable.

[0172] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, than that of the relative permittivity of the insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0173] Furthermore, insulators 320, 322, 324, and 326 have embedded conductors 328 and 330, which connect to the capacitive element 600 or the transistor 500. Conductors 328 and 330 function as plugs or wires. Conductors that function as plugs or wires may be grouped together and assigned the same reference numeral. In this specification, the wire and the plug connected to the wire may be an integrated unit. That is, a part of the conductor may function as a wire, and a part of the conductor may function as a plug.

[0174] The plugs and wiring (conductors 328 and 330, etc.) can be made from conductive materials such as metals, alloys, metal nitrides, or metal oxides, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and conductivity, with tungsten being preferable. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0175] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 9, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as a plug or wiring for connecting to the transistor 300. Conductors 356 can be provided using the same material as conductors 328 and 330.

[0176] For example, it is preferable that the insulator 350, like the insulator 324, be an insulator that has barrier properties against hydrogen. It is also preferable that the conductor 356 includes a conductor that has barrier properties against hydrogen. In particular, a conductor that has barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 350. With this configuration, transistor 300 and transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0177] For example, tantalum nitride may be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0178] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in Figure 9, insulators 360, 362, and 364 are stacked in order. Conductors 366 are formed on insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductor 366 can be provided using the same material as conductors 328 and 330.

[0179] For example, it is preferable that the insulator 360, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 366 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 360. With this configuration, transistor 300 and transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0180] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in Figure 9, insulators 370, 372, and 374 are stacked in order. Conductors 376 are formed on insulators 370, 372, and 374. Conductors 376 function as a plug or wiring. Conductors 376 can be provided using the same material as conductors 328 and 330.

[0181] For example, it is preferable that the insulator 370, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 376 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 370. With this configuration, transistor 300 and transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0182] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in Figure 9, insulators 380, 382, ​​and 384 are stacked in order. Furthermore, a conductor 386 is formed on insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be provided using the same material as the conductors 328 and 330.

[0183] For example, it is preferable that the insulator 380, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 386 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 380. With this configuration, transistor 300 and transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0184] In the above, wiring layers including conductor 356, wiring layers including conductor 366, wiring layers including conductor 376, and wiring layers including conductor 386 have been described, but the semiconductor device according to this embodiment is not limited thereto. Three or fewer wiring layers similar to the wiring layer including conductor 356 may be used, or five or more wiring layers similar to the wiring layer including conductor 356 may be used.

[0185] Insulators 510, 512, 514, and 516 are arranged in order on the insulator 384. It is preferable that one of the insulators 510, 512, 514, and 516 is made of a material that has barrier properties against oxygen and hydrogen.

[0186] For example, it is preferable to use a film for insulators 510 and 514 that has barrier properties to prevent hydrogen and impurities from diffusing from, for example, the substrate 311 or the region where the transistor 300 is installed to the region where the transistor 500 is installed. Therefore, the same material as for insulator 324 can be used.

[0187] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0188] Furthermore, as a film having barrier properties against hydrogen, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for insulators 510 and 514.

[0189] In particular, aluminum oxide exhibits a high barrier effect, preventing the penetration of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0190] Furthermore, for example, the same materials as insulator 320 can be used for insulators 512 and 516. Also, by using a material with a relatively low dielectric constant as the interlayer film, parasitic capacitance between wiring can be reduced. For example, silicon oxide films or silicon oxynitride films can be used as insulators 512 and 516.

[0191] Furthermore, insulators 510, 512, 514, and 516 have conductors 518 embedded within them. The conductor 518 functions as a plug or wiring for connecting to the capacitive element 600 or the transistor 300. The conductor 518 can be provided using the same material as conductors 328 and 330.

[0192] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, transistor 300 and transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0193] A transistor 500 is provided above the insulator 516.

[0194] As shown in Figures 10(A) and (B), the transistor 500 comprises an insulator 520 placed on an insulator 516, an insulator 522 placed on an insulator 520, an insulator 524 placed on an insulator 522, an oxide 530a placed on an oxide 530a, and conductors 542a and 542b placed spaced apart from each other on the oxide 530b, and conductors 542a and conductors The device comprises an insulator 580 arranged on the electric body 542b and superimposed between the conductors 542a and 542b to form an opening, a conductor 560 arranged in the opening, an insulator 550 arranged between oxide 530b, conductor 542a, conductor 542b, insulator 580, and conductor 560, and oxide 530c arranged between oxide 530b, conductor 542a, conductor 542b, insulator 580, and insulator 550.

[0195] Furthermore, as shown in Figures 10(A) and (B), it is preferable that an insulator 544 is placed between the oxide 530a, oxide 530b, conductor 542a, and conductor 542b and the insulator 580. Also, as shown in Figures 10(A) and (B), it is preferable that the conductor 560 has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. Furthermore, as shown in Figures 10(A) and (B), it is preferable that an insulator 574 is placed on top of the insulator 580, conductor 560, and insulator 550.

[0196] In the following, oxides 530a, 530b, and 530c may be collectively referred to as oxide 530. Also, conductors 542a and 542b may be collectively referred to as conductor 542.

[0197] In the transistor 500, a configuration is shown in which three layers of oxide 530a, oxide 530b, and oxide 530c are stacked in the region where the channel is formed and in its vicinity. However, the present invention is not limited to this configuration. For example, a single layer of oxide 530b, a two-layer structure of oxide 530b and oxide 530a, a two-layer structure of oxide 530b and oxide 530c, or a stacked structure of four or more layers may be provided. Also, in the transistor 500, the conductor 560 is shown as a two-layer stacked structure. However, the present invention is not limited to this configuration. For example, the conductor 560 may be a single-layer structure or a stacked structure of three or more layers. Furthermore, the transistor 500 shown in Figures 9 and 10(A)(B) is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method.

[0198] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode or drain electrode, respectively. As described above, the conductor 560 is formed to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-alignment manner with respect to the opening of the insulator 580. In other words, in the transistor 500, the gate electrode can be positioned in a self-alignment manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing an alignment margin, the occupied area of ​​the transistor 500 can be reduced. This enables miniaturization and high integration of semiconductor devices.

[0199] Furthermore, since the conductor 560 is self-alignedly formed in the region between the conductors 542a and 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560, the conductor 542a, and the conductor 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be achieved.

[0200] The insulator 550 functions as a gate insulating film.

[0201] Here, it is preferable to use an insulator containing more oxygen than oxygen that satisfies the stoichiometric composition for the insulator 524 in contact with the oxide 530. That is, it is preferable that an excess oxygen region is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, the oxygen deficiency in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved.

[0202] Specifically, as the insulator having an excess oxygen region, it is preferable to use an oxide material in which some oxygen desorbs upon heating. The oxide that desorbs oxygen upon heating means that, in TDS analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more, and it is an oxide film. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0203] Also when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate).

[0204] The insulator 522 has a function of suppressing the diffusion of oxygen and impurities, so the oxygen contained in the oxide 530 does not diffuse towards the insulator 520, which is preferable.

[0205] The insulator 522 preferably uses a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0206] In particular, it is preferable to use an insulator containing oxides of one or both aluminum and hafnium, which are insulating materials that have the function of suppressing the diffusion of impurities and oxygen (the above-mentioned oxygen is less permeable). As an insulator containing oxides of one or both aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When an insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the periphery of the transistor 500 into the oxide 530.

[0207] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated onto the above insulators.

[0208] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Also, by combining a high-k material insulator with silicon oxide or silicon oxynitride, an insulator 520 with a thermally stable and high dielectric constant laminated structure can be obtained.

[0209] Furthermore, the insulators 520, 522, and 524 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, but may be made of different materials.

[0210] In transistor 500, it is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, In-Ga oxide or In-Zn oxide may be used as the oxide 530.

[0211] In oxide 530, it is preferable to use a metal oxide that functions as a channel-forming region and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0212] By having oxide 530a below oxide 530b, the diffusion of impurities from structures formed below oxide 530a to oxide 530b can be suppressed. Furthermore, by having oxide 530c above oxide 530b, the diffusion of impurities from structures formed above oxide 530c to oxide 530b can be suppressed.

[0213] Furthermore, it is preferable that oxide 530 has a layered structure made up of oxides with different atomic ratios of each metal atom. Specifically, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M in the constituent elements is greater than the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 530b. Also, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, in the metal oxide used for oxide 530b, it is preferable that the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a. In addition, oxide 530c can be any metal oxide that can be used for oxide 530a or oxide 530b.

[0214] Furthermore, it is preferable that the energy at the lower end of the conduction band of oxide 530a and oxide 530c is higher than the energy at the lower end of the conduction band of oxide 530b. In other words, it is preferable that the electron affinity of oxide 530a and oxide 530c is smaller than the electron affinity of oxide 530b.

[0215] Here, at the junctions of oxide 530a, oxide 530b, and oxide 530c, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junctions of oxide 530a, oxide 530b, and oxide 530c can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 530a and oxide 530b, and at the interface between oxide 530b and oxide 530c.

[0216] Specifically, a mixed layer with a low defect level density can be formed if oxide 530a and oxide 530b, and oxide 530b and oxide 530c, have a common element other than oxygen (as the main component). For example, if oxide 530b is In-Ga-Zn oxide, then In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc., can be used as oxide 530a and oxide 530c.

[0217] In this case, the primary carrier pathway is oxide 530b. By configuring oxides 530a and 530c as described above, the defect level density at the interface between oxide 530a and oxide 530b, and at the interface between oxide 530b and oxide 530c, can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 500 can obtain a high on-current.

[0218] A conductor 542 (conductor 542a and conductor 542b) that functions as a source electrode and a drain electrode is provided on the oxide 530b. As the conductor 542, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0219] Furthermore, as shown in Figure 10(A), a low-resistance region, region 543 (regions 543a and 543b), may be formed at and near the interface of the oxide 530 with the conductor 542. In this case, region 543a functions as either a source region or a drain region, and region 543b functions as either a source region or a drain region. In addition, a channel-forming region is formed in the region sandwiched between regions 543a and 543b.

[0220] By providing the conductor 542 in contact with the oxide 530, the oxygen concentration in region 543 may be reduced. In addition, a metal compound layer containing the metal contained in the conductor 542 and the components of the oxide 530 may be formed in region 543. In such cases, the carrier density in region 543 increases, and region 543 becomes a low-resistance region.

[0221] The insulator 544 is provided so as to cover the conductor 542 and suppress the oxidation of the conductor 542. In this case, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and be in contact with the insulator 524.

[0222] As the insulator 544, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0223] In particular, it is preferable to use an insulator 544 that contains an oxide of either aluminum or hafnium, or both, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is especially preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in subsequent processes. However, if the conductor 542 is made of an oxidation-resistant material, or if its conductivity does not significantly decrease even when it absorbs oxygen, the insulator 544 is not an essential component. It should be designed appropriately according to the desired transistor characteristics.

[0224] The insulator 550 functions as a gate insulating film. It is preferable that the insulator 550 is placed in contact with the inside (top and side) of the oxide 530c. It is preferable that the insulator 550 is formed using an insulator that releases oxygen upon heating. For example, if the amount of oxygen released in terms of oxygen atoms is 1.0 × 10¹⁶ in thermal desorption gas analysis (TDS analysis), 18 atoms / cm 3 Preferably 1.0 × 10 19 atoms / cm 3 More preferably 2.0 × 10 19 atoms / cm 3 Above, or 3.0 × 10 20 atoms / cm 3 The oxide film is as described above. Furthermore, the surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C.

[0225] Specifically, silicon oxide with excess oxygen, silicon oxide nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies can be used. Silicon oxide and silicon oxide nitride are particularly preferred because they are stable to heat.

[0226] By providing an insulator 550, which releases oxygen upon heating, in contact with the upper surface of oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel-forming region of oxide 530b through oxide 530c. Furthermore, similar to the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 is preferably between 1 nm and 20 nm.

[0227] Furthermore, in order to efficiently supply excess oxygen from the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. It is preferable that the metal oxide suppresses the diffusion of oxygen from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, the reduction in the amount of excess oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, any material that can be used for the insulator 544 may be used.

[0228] The conductor 560, which functions as a gate electrode, is shown as a two-layer structure in Figures 10(A) and (B), but it may also be a single-layer structure or a stacked structure of three or more layers.

[0229] It is preferable to use a conductive material for the conductor 560a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules). By having the function of suppressing the diffusion of oxygen in the conductor 560a, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 550 and the decrease in conductivity. As a conductive material that has the function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0230] Furthermore, it is preferable that the conductor 560b is made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 560b functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 560b may also be in a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive material.

[0231] The insulator 580 is provided on the conductor 542 via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and porous silicon oxide are particularly preferred because they can easily form an excess oxygen region in a later process.

[0232] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580, which releases oxygen upon heating, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

[0233] The opening in the insulator 580 is formed superimposed on the region between the conductors 542a and 542b. As a result, the conductor 560 is formed to be embedded in the opening in the insulator 580 and in the region sandwiched between the conductors 542a and 542b.

[0234] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may take on a shape with a high aspect ratio. In this embodiment, since the conductor 560 is embedded in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, it can be formed without the conductor 560 collapsing during the manufacturing process.

[0235] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. By depositing the insulator 574 by sputtering, an excess oxygen region can be created on the insulator 550 and the insulator 580. This allows oxygen to be supplied to the oxide 530 from the excess oxygen region.

[0236] For example, as the insulator 574, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0237] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in thin films between 0.5 nm and 3.0 nm in thickness. Therefore, aluminum oxide deposited by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0238] Furthermore, it is preferable to provide an insulator 581 that functions as an interlayer film on top of the insulator 574. Similar to the insulator 524, it is preferable that the insulator 581 has a reduced concentration of impurities such as water or hydrogen in the film.

[0239] Furthermore, conductors 540a and 540b are placed in the openings formed in insulators 581, 574, 580, and 544. Conductors 540a and 540b are provided facing each other with conductor 560 in between. Conductors 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0240] An insulator 582 is provided on the insulator 581. It is preferable that the insulator 582 be made of a material that has barrier properties against oxygen and hydrogen. Therefore, the same material as that used for the insulator 514 can be used for the insulator 582. For example, it is preferable that the insulator 582 be made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0241] In particular, aluminum oxide exhibits a high barrier effect, preventing the penetration of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0242] Furthermore, an insulator 586 is provided on the insulator 582. The insulator 586 can be made of the same material as the insulator 320. In addition, by using a material with a relatively low dielectric constant as the interlayer film, parasitic capacitance occurring between the wiring can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used as the insulator 586.

[0243] Furthermore, insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586 have conductors 546 and 548 embedded in them.

[0244] Conductors 546 and 548 function as plugs or wires for connecting to the capacitive element 600, transistor 500, or transistor 300. Conductors 546 and 548 can be provided using the same materials as conductors 328 and 330.

[0245] Subsequently, a capacitive element 600 is provided above the transistor 500. The capacitive element 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0246] Also, a conductor 612 may be provided on the conductor 546 and the conductor 548. The conductor 612 functions as a plug connected to the transistor 500 or as a wiring. The conductor 610 functions as an electrode of the capacitive element 600. Note that the conductor 612 and the conductor 610 can be formed simultaneously.

[0247] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can also be applied.

[0248] In FIG. 9, the conductor 612 and the conductor 610 are shown in a single-layer structure, but the present invention is not limited to this configuration, and a laminated structure of two or more layers may be used. For example, between a conductor having barrier properties and a conductor having high conductivity, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed.

[0249] A conductor 620 is provided so as to overlap with a conductor 610 via an insulator 630. Note that the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. Further, when forming simultaneously with other structures such as conductors, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used.

[0250] An insulator 650 is provided on the conductor 620 and the insulator 630. The insulator 650 can be provided using the same material as the insulator 320. Further, the insulator 650 may function as a planarization film that covers the uneven shape below it.

[0251] By using this structure, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor having an oxide semiconductor with a large on-current can be provided. Alternatively, a transistor having an oxide semiconductor with a small off-current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved.

[0252] <Structural example of a transistor> Note that the transistor 500 of the semiconductor device shown in this embodiment is not limited to the above structure. Hereinafter, structural examples that can be used for the transistor 500 will be described.

[0253] <Structural example 1 of a transistor> The structure of transistor 510A is explained using Figures 11(A), (B), and (C). Figure 11(A) is a top view of transistor 510A. Figure 11(B) is a cross-sectional view of the area indicated by the dashed-dotted line L1-L2 in Figure 11(A). Figure 11(C) is a cross-sectional view of the area indicated by the dashed-dotted line W1-W2 in Figure 11(A). Note that in the top view of Figure 11(A), some elements have been omitted for clarity.

[0254] Figures 11(A), (B), and (C) show the transistor 510A and the insulators 511, 512, 514, 516, 580, 582, and 584, which function as interlayer films. Also shown are the conductors 546 (conductors 546a and 546b), which are electrically connected to the transistor 510A and function as contact plugs.

[0255] The transistor 510A includes a conductor 560 (conductor 560a and conductor 560b) that functions as a gate electrode, an insulator 550 that functions as a gate insulating film, an oxide 530 (oxide 530a, oxide 530b and oxide 530c) having a region in which a channel is formed, a conductor 542a that functions as either a source or a drain, a conductor 542b that functions as the other source or drain, and an insulator 574.

[0256] Furthermore, in the transistor 510A shown in Figure 11, the oxide 530c, insulator 550, and conductor 560 are arranged in an opening provided in the insulator 580, via an insulator 574. In addition, the oxide 530c, insulator 550, and conductor 560 are arranged between conductors 542a and 542b.

[0257] Insulators 511 and 512 function as interlayer films.

[0258] As the interlayer film, insulators such as silicon oxide, silicon oxide nitride, silicon oxide nitride, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used in single or multilayer layers. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxide nitride, or silicon nitride may be used in a multilayer layer on top of the above insulators.

[0259] For example, the insulator 511 preferably functions as a barrier film that suppresses the ingress of impurities such as water or hydrogen from the substrate side into the transistor 510A. Therefore, it is preferable to use an insulating material for the insulator 511 that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (i.e., the above impurities do not easily permeate it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (i.e., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen does not easily permeate it). Furthermore, for example, aluminum oxide or silicon nitride may be used as the insulator 511. With this configuration, it is possible to suppress the diffusion of impurities such as hydrogen and water from the substrate side to the transistor 510A side beyond the insulator 511.

[0260] For example, it is preferable that the dielectric constant of the insulator 512 is lower than that of the insulator 511. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between the wiring can be reduced.

[0261] In transistor 510A, the conductor 560 may function as a gate electrode.

[0262] Insulators 514 and 516 function as interlayer films, similar to insulators 511 or 512. For example, insulator 514 preferably functions as a barrier film that suppresses the ingress of impurities such as water or hydrogen from the substrate side into the transistor 510A. This configuration suppresses the diffusion of impurities such as hydrogen and water from the substrate side to the transistor 510A side beyond the insulator 514. Furthermore, for example, insulator 516 preferably has a lower dielectric constant than insulator 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wiring can be reduced.

[0263] Furthermore, it is preferable that the insulator 522 has barrier properties. The barrier properties of the insulator 522 allow it to function as a layer that suppresses the ingress of impurities such as hydrogen from the periphery of the transistor 510A into the transistor 510A.

[0264] The insulator 522 preferably uses a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0265] For example, the insulator 521 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k material insulator with silicon oxide or silicon oxynitride, an insulator 521 with a thermally stable and high dielectric constant laminated structure can be obtained.

[0266] The oxide 530 having a region that functions as a channel formation region includes an oxide 530a, an oxide 530b on the oxide 530a, and an oxide 530c on the oxide 530b. By having the oxide 530a under the oxide 530b, diffusion of impurities from a structure formed below the oxide 530a into the oxide 530b can be suppressed. Also, by having the oxide 530c on the oxide 530b, diffusion of impurities from a structure formed above the oxide 530c into the oxide 530b can be suppressed. As the oxide 530, an oxide semiconductor which is one kind of the above-described metal oxides can be used.

[0267] Note that the oxide 530c is preferably provided in an opening provided in the insulator 580 via the insulator 574. When the insulator 574 has barrier properties, diffusion of impurities from the insulator 580 into the oxide 530 can be suppressed.

[0268] One side of the conductor 542 functions as a source electrode and the other side functions as a drain electrode.

[0269] As the conductor 542a and the conductor 542b, metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or alloys mainly composed of these can be used. In particular, metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen or oxygen and high oxidation resistance.

[0270] Also, although a single-layer structure is shown in FIG. 11, a stacked structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be stacked. Also, a titanium film and an aluminum film may be stacked. Also, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0271] Furthermore, there are three-layer structures such as a titanium film or titanium nitride film, an aluminum film or copper film laminated on top of the titanium film or titanium nitride film, and a titanium film or titanium nitride film formed on top of that; and a molybdenum film or molybdenum nitride film, an aluminum film or copper film laminated on top of the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film formed on top of that. Transparent conductive materials containing indium oxide, tin oxide, or zinc oxide may also be used.

[0272] Furthermore, a barrier layer may be provided on the conductor 542. It is preferable that the barrier layer be made of a material that has barrier properties against oxygen or hydrogen. This configuration makes it possible to suppress the oxidation of the conductor 542 when the insulator 574 is formed.

[0273] For the barrier layer, for example, a metal oxide can be used. In particular, it is preferable to use an insulating film that has barrier properties against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, or gallium oxide. Alternatively, silicon nitride formed by CVD may be used.

[0274] The presence of a barrier layer broadens the range of materials that can be selected for the conductor 542. For example, materials with low oxidation resistance but high conductivity, such as tungsten or aluminum, can be used for the conductor 542. In addition, for example, conductors that are easy to deposit or process can be used.

[0275] The insulator 550 functions as a gate insulating film. Preferably, the insulator 550 is provided in an opening in the insulator 580 via oxide 530c and insulator 574.

[0276] As transistors become smaller and more highly integrated, thinning of the gate insulating film can lead to problems such as leakage current. In such cases, the insulator 550 may be in a multilayer structure. By using a multilayer structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a multilayer structure that is thermally stable and has a high dielectric constant can be achieved.

[0277] The conductor 560, which functions as a gate electrode, has a conductor 560a and a conductor 560b on the conductor 560a. It is preferable that the conductor 560a is made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms or oxygen molecules). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of one or all of the above-mentioned impurities or oxygen.

[0278] The conductor 560a has the function of suppressing oxygen diffusion, thereby improving the material selectivity of the conductor 560b. In other words, the presence of conductor 560a suppresses the oxidation of conductor 560b and prevents a decrease in conductivity.

[0279] As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. In addition, an oxide semiconductor that can be used as oxide 530 can be used as the conductor 560a. In that case, the electrical resistance of the conductor 560a can be reduced by depositing the conductor 560b by sputtering, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0280] The conductor 560b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, since the conductor 560 functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 560b may also be in a laminated structure, for example, a laminate of titanium, titanium nitride, and the above conductive material.

[0281] An insulator 574 is placed between the insulator 580 and the transistor 510A. The insulator 574 should be made of an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, aluminum oxide or hafnium oxide is preferred. In addition, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride, or silicon nitride can also be used.

[0282] The presence of the insulator 574 suppresses the diffusion of impurities such as water and hydrogen present in the insulator 580 to the oxide 530b via the oxide 530c and insulator 550. Furthermore, it suppresses the oxidation of the conductor 560 due to excess oxygen present in the insulator 580.

[0283] Insulators 580, 582, and 584 function as interlayer films.

[0284] The insulator 582, like the insulator 514, preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 510A from the outside.

[0285] Furthermore, it is preferable that insulators 580 and 584 have a lower dielectric constant than insulator 582, similar to insulator 516. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0286] Furthermore, transistor 510A may be electrically connected to other structures via plugs or wiring, such as conductors 546 embedded in insulators 580, 582, and 584.

[0287] Furthermore, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used as the material for the conductor 546, either in a single layer or in a laminated form. For example, it is preferable to use high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and conductivity. Alternatively, it is preferable to form it with low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce the wiring resistance.

[0288] For example, by using a laminated structure of tantalum nitride, which is a conductor with barrier properties against hydrogen and oxygen, and tungsten, which has high conductivity, the diffusion of impurities from the outside can be suppressed while maintaining conductivity as a wiring.

[0289] By having the above structure, it is possible to provide a semiconductor device having a transistor with an oxide semiconductor having a large on-current. Alternatively, it is possible to provide a semiconductor device having a transistor with an oxide semiconductor having a small off-current. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

[0290] <Example of transistor structure 2> The structure of transistor 510B is illustrated using Figures 12(A), (B), and (C). Figure 12(A) is a top view of transistor 510B. Figure 12(B) is a cross-sectional view of the area indicated by the dashed-dotted line L1-L2 in Figure 12(A). Figure 12(C) is a cross-sectional view of the area indicated by the dashed-dotted line W1-W2 in Figure 12(A). Note that in the top view of Figure 12(A), some elements have been omitted for clarity.

[0291] Transistor 510B is a modified version of transistor 510A. Therefore, to avoid repetition, we will mainly explain the differences between transistor 510B and transistor 510A.

[0292] Transistor 510B has a region where conductor 542 (conductor 542a and conductor 542b), oxide 530c, insulator 550, and conductor 560 are superimposed. This structure makes it possible to provide a transistor with high on-current. It also makes it possible to provide a transistor with high controllability.

[0293] The conductor 560, which functions as a gate electrode, has a conductor 560a and a conductor 560b on the conductor 560a. It is preferable that the conductor 560a is made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0294] The conductor 560a has the function of suppressing oxygen diffusion, thereby improving the material selectivity of the conductor 560b. In other words, the presence of conductor 560a suppresses the oxidation of conductor 560b and prevents a decrease in conductivity.

[0295] Furthermore, it is preferable to provide an insulator 574 so as to cover the top and sides of the conductor 560, the sides of the insulator 550, and the sides of the oxide 530c. The insulator 574 should be made of an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, other materials such as metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride, or silicon nitride can also be used.

[0296] By providing the insulator 574, oxidation of the conductor 560 can be suppressed. Furthermore, the presence of the insulator 574 can suppress the diffusion of water and other impurities such as hydrogen present in the insulator 580 to the transistor 510B.

[0297] Alternatively, a barrier insulator 576 (insulator 576a and insulator 576b) may be placed between the conductor 546 and the insulator 580. By providing the insulator 576, it is possible to suppress the reaction of oxygen in the insulator 580 with the conductor 546 and the oxidation of the conductor 546.

[0298] Furthermore, by providing the barrier-type insulator 576, the range of materials that can be selected for the conductors used in plugs and wiring can be broadened. For example, by using a metal material that has the property of absorbing oxygen while having high conductivity for the conductor 546, a semiconductor device with low power consumption can be provided. Specifically, materials such as tungsten or aluminum, which have low oxidation resistance but high conductivity, can be used. In addition, for example, conductors that are easy to deposit or process can be used.

[0299] <Example of transistor structure 3> The structure of transistor 510C is explained using Figures 13(A), (B), and (C). Figure 13(A) is a top view of transistor 510C. Figure 13(B) is a cross-sectional view of the area indicated by the dashed-dotted line L1-L2 in Figure 13(A). Figure 13(C) is a cross-sectional view of the area indicated by the dashed-dotted line W1-W2 in Figure 13(A). Note that in the top view of Figure 13(A), some elements have been omitted for clarity.

[0300] Transistor 510C is a modified version of transistor 510A. Therefore, to avoid repetition, we will mainly explain the differences between transistor 510C and transistor 510A.

[0301] In the transistor 510C shown in Figure 13, a conductor 547a is positioned between a conductor 542a and an oxide 530b, and a conductor 547b is positioned between a conductor 542b and an oxide 530b. Here, the conductor 542a (conductor 542b) extends beyond the upper surface and the side surface on the conductor 560 side of the conductor 547a (conductor 547b), and has a region that contacts the upper surface of the oxide 530b. Here, the conductor 547 may be any conductor that can be used for conductor 542. Furthermore, it is preferable that the film thickness of the conductor 547 is at least thicker than that of the conductor 542.

[0302] The transistor 510C shown in Figure 13, having the above-described configuration, allows the conductor 542 to be brought closer to the conductor 560 than in transistor 510A. Alternatively, the ends of conductor 542a and conductor 542b can be overlapped with the conductor 560. This shortens the effective channel length of transistor 510C, improving on-current and frequency characteristics.

[0303] Furthermore, it is preferable that the conductor 547a (conductor 547b) is provided superimposed on the conductor 542a (conductor 542b). With this configuration, in etching to form an opening for embedding the conductor 546a (conductor 546b), the conductor 547a (conductor 547b) functions as a stopper, preventing the oxide 530b from being over-etched.

[0304] Furthermore, the transistor 510C shown in Figure 13 may be configured such that an insulator 545 is placed in contact with an insulator 544. The insulator 544 preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen, or excess oxygen, into the transistor 510C from the insulator 580 side. As the insulator 545, an insulator that can be used for the insulator 544 can be used. Also, as the insulator 544, a nitride insulator such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon nitride, or silicon nitride oxide may be used.

[0305] <Example of transistor structure 4> The structure of transistor 510D is illustrated using Figures 14(A), (B), and (C). Figure 14(A) is a top view of transistor 510D. Figure 14(B) is a cross-sectional view of the area indicated by the dashed-dotted line L1-L2 in Figure 14(A). Figure 14(C) is a cross-sectional view of the area indicated by the dashed-dotted line W1-W2 in Figure 14(A). Note that in the top view of Figure 14(A), some elements have been omitted for clarity.

[0306] Transistor 510D is a modified version of the above transistor. Therefore, to avoid repetition, we will mainly explain the differences between it and the above transistor.

[0307] In Figures 14(A) to (C), an insulator 550 is present on the oxide 530c, and a metal oxide 552 is present on the insulator 550. Furthermore, a conductor 560 is present on the metal oxide 552, and an insulator 570 is present on the conductor 560. Additionally, an insulator 571 is present on the insulator 570.

[0308] Preferably, the metal oxide 552 has the function of suppressing oxygen diffusion. By providing the metal oxide 552 that suppresses oxygen diffusion between the insulator 550 and the conductor 560, the diffusion of oxygen into the conductor 560 is suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 by oxygen can be suppressed.

[0309] Furthermore, the metal oxide 552 may also function as part of the gate. For example, an oxide semiconductor that can be used as oxide 530 can be used as metal oxide 552. In that case, the electrical resistance of the metal oxide 552 can be reduced by depositing the conductor 560 by sputtering, thereby creating a conductive layer. This can be called an OC electrode.

[0310] Furthermore, the metal oxide 552 may function as part of the gate insulating film. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 550, it is preferable to use a metal oxide 552 that is a high-k material with a high dielectric constant. This layered structure provides thermal stability and a high dielectric constant. As a result, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulating layer that functions as a gate insulating film.

[0311] In transistor 510D, the metal oxide 552 is shown as a single layer, but it may also be a stacked structure of two or more layers. For example, a metal oxide that functions as part of the gate electrode and a metal oxide that functions as part of the gate insulating film may be stacked.

[0312] By having the metal oxide 552, when it functions as a gate electrode, the on-current of the transistor 510D can be improved without weakening the influence of the electric field from the conductor 560. Alternatively, when it functions as a gate insulating film, the physical thickness of the insulator 550 and the metal oxide 552 maintains the distance between the conductor 560 and the oxide 530, thereby suppressing leakage current between the conductor 560 and the oxide 530. Therefore, by providing a laminated structure of the insulator 550 and the metal oxide 552, the physical distance between the conductor 560 and the oxide 530, and the electric field strength applied from the conductor 560 to the oxide 530 can be easily and appropriately adjusted.

[0313] Specifically, as metal oxide 552, an oxide semiconductor that can be used in oxide 530 can be used as metal oxide 552 by reducing its resistance. Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0314] In particular, it is preferable to use an insulating layer containing an oxide of either aluminum or hafnium, or both, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is especially preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in subsequent processes. Note that metal oxide 552 is not an essential component. It can be designed as appropriate depending on the desired transistor characteristics.

[0315] The insulator 570 should be made of an insulating material that has the function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. This makes it possible to suppress the oxidation of the conductor 560 by oxygen from above the insulator 570. In addition, it is possible to suppress the mixing of impurities such as water or hydrogen from above the insulator 570 into the oxide 530 via the conductor 560 and the insulator 550.

[0316] The insulator 571 functions as a hard mask. By providing the insulator 571, when processing the conductor 560, the side surface of the conductor 560 can be made approximately perpendicular, specifically, the angle between the side surface of the conductor 560 and the substrate surface can be made between 75 degrees and 100 degrees, preferably between 80 degrees and 95 degrees.

[0317] Furthermore, the insulator 571 may also function as a barrier layer by using an insulating material that has the function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. In that case, the insulator 570 does not need to be provided.

[0318] By using the insulator 571 as a hard mask, and selectively removing parts of the insulator 570, conductor 560, metal oxide 552, insulator 550, and oxide 530c, these surfaces can be made substantially aligned, and a portion of the oxide 530b surface can be exposed.

[0319] Furthermore, transistor 510D has regions 531a and 531b on a portion of the exposed oxide 530b surface. One of region 531a or region 531b functions as the source region, and the other functions as the drain region.

[0320] The formation of regions 531a and 531b can be achieved, for example, by introducing impurity elements such as phosphorus or boron to the exposed oxide 530b surface using ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. In this embodiment, "impurity element" refers to an element other than the main component element.

[0321] Alternatively, a metal film can be formed after a portion of the oxide 530b surface is exposed, and then a heat treatment can be performed to diffuse elements contained in the metal film into the oxide 530b, thereby forming regions 531a and 531b.

[0322] In the region where the impurity element of oxide 530b is introduced, the electrical resistivity decreases. For this reason, regions 531a and 531b are sometimes referred to as the "impurity region" or "low-resistance region."

[0323] By using the insulator 571 and / or the conductor 560 as a mask, regions 531a and 531b can be formed in a self-aligned manner. Therefore, regions 531a and / or region 531b do not overlap with the conductor 560, and parasitic capacitance can be reduced. In addition, no offset region is formed between the channel formation region and the source-drain region (region 531a or region 531b). By forming regions 531a and 531b in a self-aligned manner, it is possible to increase the on-current, reduce the threshold voltage, and improve the operating frequency.

[0324] Furthermore, to further reduce the off-current, an offset region may be provided between the channel formation region and the source-drain region. The offset region is a region with high electrical resistivity where the aforementioned impurity elements are not introduced. The formation of the offset region can be achieved by introducing the aforementioned impurity elements after the formation of the insulator 575. In this case, the insulator 575 also functions as a mask, similar to the insulator 571. Therefore, impurity elements are not introduced into the region of oxide 530b that overlaps with the insulator 575, and the electrical resistivity of that region can be kept high.

[0325] Furthermore, the transistor 510D has an insulator 570, a conductor 560, a metal oxide 552, an insulator 550, and an insulator 575 on the side surface of the oxide 530c. The insulator 575 is preferably an insulator with a low dielectric constant. For example, it is preferably silicon oxide, silicon oxynitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. In particular, using silicon oxide, silicon oxynitride, silicon oxide nitride, or porous silicon oxide for the insulator 575 is preferable because it allows for easy formation of an excess oxygen region in the insulator 575 in a later process. Also, silicon oxide and silicon oxynitride are preferred because they are thermally stable. Furthermore, it is preferable that the insulator 575 has the function of diffusing oxygen.

[0326] Furthermore, the transistor 510D has an insulator 575 and an insulator 574 on the oxide 530. The insulator 574 is preferably deposited using a sputtering method. By using the sputtering method, an insulator with fewer impurities such as water or hydrogen can be deposited. For example, aluminum oxide may be used as the insulator 574.

[0327] Furthermore, oxide films formed by sputtering may extract hydrogen from the structure to which the film is deposited. Therefore, the hydrogen concentration of oxide 530 and insulator 575 can be reduced by the insulator 574 absorbing hydrogen and water from oxide 530 and insulator 575.

[0328] <Example of transistor structure 5> The structure of transistor 510E will be explained using Figures 15(A) to 15(C). Figure 15(A) is a top view of transistor 510E. Figure 15(B) is a cross-sectional view of the area indicated by the dashed-dotted line L1-L2 in Figure 15(A). Figure 15(C) is a cross-sectional view of the area indicated by the dashed-dotted line W1-W2 in Figure 15(A). Note that in the top view of Figure 15(A), some elements have been omitted for clarity.

[0329] Transistor 510E is a modified version of the above transistor. Therefore, to avoid repetition, we will mainly explain the differences between it and the above transistor.

[0330] In Figures 15(A) to 15(C), without the conductor 542, a portion of the exposed oxide 530b surface has regions 531a and 531b. One of region 531a or region 531b functions as a source region, and the other functions as a drain region. In addition, an insulator 573 is provided between the oxide 530b and the insulator 574.

[0331] As shown in Figure 15, region 531 (regions 531a and 531b) is a region in which the following elements are added to oxide 530b. Region 531 can be formed, for example, by using a dummy gate.

[0332] Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask to add an element that reduces the resistance of the oxide 530b. In other words, the element is added to the region of oxide 530 that does not overlap with the dummy gate, forming region 531. As for the method of adding the element, ion implantation, in which ionized raw material gas is added by mass separation, ion doping, in which ionized raw material gas is added without mass separation, and plasma immersion ion implantation can be used.

[0333] Typical elements used to reduce the resistance of oxide 530 include boron and phosphorus. Hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, and noble gases may also be used. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. The concentration of these elements can be measured using methods such as secondary ion mass spectrometry (SIMS).

[0334] In particular, boron and phosphorus are preferred because they can be manufactured using equipment from amorphous silicon or low-temperature polysilicon production lines. Existing equipment can be repurposed, which helps to reduce capital investment.

[0335] Next, an insulating film that will become an insulator 573 and an insulating film that will become an insulator 574 may be formed on the oxide 530b and the dummy gate. By stacking the insulating film that will become an insulator 573 and the insulating film that will become an insulator 574, a region 531 and a region in which the oxide 530c and the insulator 550 overlap can be provided.

[0336] Specifically, an insulating film that will become insulator 580 is provided on an insulating film that will become insulator 574. Then, by performing a CMP treatment on the insulating film that will become insulator 580, a portion of the insulating film that will become insulator 580 is removed, exposing the dummy gate. Subsequently, when removing the dummy gate, it is preferable to also remove a portion of the insulator 573 that is in contact with the dummy gate. As a result, insulators 574 and 573 are exposed on the side surface of the opening provided in insulator 580, and a portion of the region 531 provided in oxide 530b is exposed on the bottom surface of the opening. Next, an oxide film that will become oxide 530c, an insulating film that will become insulator 550, and a conductive film that will become conductor 560 are sequentially deposited on the opening. Then, by removing a portion of the oxide film that will become oxide 530c, the insulating film that will become insulator 550, and the conductive film that will become conductor 560 through CMP treatment or the like until insulator 580 is exposed, the transistor shown in Figure 15 can be formed.

[0337] Note that insulators 573 and 574 are not essential components. They can be designed as appropriate depending on the desired transistor characteristics.

[0338] The transistor shown in Figure 15 can utilize existing equipment, and furthermore, since it does not require a conductor 542, costs can be reduced.

[0339] <Example of transistor structure 6> Furthermore, while Figures 9 and 10(A) and (B) describe an example structure in which the conductor 560, which functions as a gate, is formed inside the opening of the insulator 580, it is also possible to use a structure in which the insulator is provided above the conductor. Examples of such transistor structures are shown in Figures 16 and 17.

[0340] Figure 16(A) is a top view of the transistor, and Figure 16(B) is a perspective view of the transistor. Furthermore, Figure 17(A) shows a cross-sectional view of X1-X2 in Figure 16(A), and Figure 17(B) shows a cross-sectional view of Y1-Y2.

[0341] The transistors shown in Figures 16(A)(B) and 17(A)(B) comprise an oxide semiconductor S, an insulator FGI functioning as a gate insulating film, a conductor FGE functioning as a front gate, and a conductor WE functioning as wiring. Furthermore, the conductor PE functions as a plug for connecting the conductor WE with the oxide S or the conductor FGE. In this example, the oxide semiconductor S is composed of three layers of oxide S1, S2, and S3.

[0342] This embodiment can be implemented in appropriate combination with other embodiments described herein.

[0343] (Embodiment 4) This embodiment describes the configuration of a metal oxide that can be used in the OS transistor described in the above embodiment.

[0344] <Composition of metal oxides> In this specification, CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite) may be used. Note that CAAC represents an example of a crystal structure, while CAC represents an example of a function or material composition.

[0345] CAC-OS or CAC-metal oxide is a material that possesses conductive properties in some parts, insulating properties in others, and semiconductor properties as a whole. When CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the conductive function is the function of allowing electrons (or holes) to flow, and the insulating function is the function of preventing electrons from flowing. By making the conductive and insulating functions work complementaryly, a switching function (on / off function) can be given to CAC-OS or CAC-metal oxide. By separating each function in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0346] Furthermore, CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the conductive function described above, and the insulating regions have the insulating function described above. In addition, the conductive regions and insulating regions may be separated at the nanoparticle level within the material. Also, the conductive regions and insulating regions may be unevenly distributed within the material. Furthermore, the conductive regions may be observed as blurred around the edges and connected in a cloud-like manner.

[0347] Furthermore, in CAC-OS or CAC-metal oxide, conductive regions and insulating regions may be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0348] Furthermore, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide band gap due to an insulating region and a component with a narrow band gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow band gap. In addition, the component with the narrow band gap acts complementaryly to the component with the wide band gap, and carriers also flow in the component with the wide band gap in conjunction with the component with the narrow band gap. For this reason, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, i.e., a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0349] In other words, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0350] <Structure of metal oxides> Oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0351] It is preferable to use a highly crystalline thin film as the oxide semiconductor used in the semiconductor of a transistor. By using such a thin film, the stability or reliability of the transistor can be improved. Examples of such thin films include thin films of single-crystal oxide semiconductors or thin films of polycrystalline oxide semiconductors. However, forming thin films of single-crystal oxide semiconductors or polycrystalline oxide semiconductors on a substrate requires high-temperature or laser heating processes. Therefore, the manufacturing process costs increase, and throughput also decreases.

[0352] Non-Patent Documents 1 and 2 reported the discovery of an In-Ga-Zn oxide with a CAAC structure (referred to as CAAC-IGZO) in 2009. These documents reported that CAAC-IGZO has c-axis orientation, clearly defined grain boundaries, and can be formed on a substrate at low temperatures. Furthermore, transistors using CAAC-IGZO were reported to possess excellent electrical properties and reliability.

[0353] Furthermore, in 2013, an In-Ga-Zn oxide with an nc structure (called nc-IGZO) was discovered (see Non-Patent Literature 3). It was reported that nc-IGZO has periodicity in the atomic arrangement in minute regions (for example, regions between 1 nm and 3 nm), and that no regularity is observed in the crystal orientation between different such regions.

[0354] Non-patent documents 4 and 5 show the changes in average crystal size of thin films of CAAC-IGZO, nc-IGZO, and low-crystallinity IGZO after electron beam irradiation. In the low-crystallinity IGZO thin film, crystalline IGZO of about 1 nm was observed even before electron beam irradiation. Therefore, it is reported that the existence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, it has been shown that CAAC-IGZO thin films and nc-IGZO thin films have higher stability against electron beam irradiation compared to low-crystallinity IGZO thin films. Therefore, it is preferable to use CAAC-IGZO thin films or nc-IGZO thin films as semiconductors for transistors.

[0355] CAAC-OS has a c-axis orientation and a crystal structure in which multiple nanocrystals are linked in the ab-plane direction, resulting in a strained structure. The strain refers to the region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement, within the region where multiple nanocrystals are linked.

[0356] Nanocrystals are based on a hexagonal structure, but they are not necessarily regular hexagons and may have non-regular hexagonal shapes. Furthermore, under strain, they may have lattice arrangements such as pentagons and heptagons. In CAAC-OS, however, clear grain boundaries (also called crystal grain boundaries) cannot be observed even near strain. This indicates that the formation of crystal grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to factors such as the sparse arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distances due to the substitution of metal elements.

[0357] Furthermore, CAAC-OS tends to have a layered crystalline structure (also called a layered structure) in which layers containing indium and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer) are stacked. Note that indium and element M are mutually substitutable, and when element M in the (M,Zn) layer is substituted with indium, it can also be represented as the (In,M,Zn) layer. Similarly, when indium in the In layer is substituted with element M, it can also be represented as the (In,M) layer.

[0358] CAAC-OS is a highly crystalline oxide semiconductor. Furthermore, because clear grain boundaries cannot be observed in CAAC-OS, it is less susceptible to the reduction in electron mobility caused by grain boundaries. Also, since the crystallinity of oxide semiconductors can decrease due to impurities and defects, CAAC-OS can be considered an oxide semiconductor with fewer impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors containing CAAC-OS have stable physical properties. Consequently, oxide semiconductors containing CAAC-OS are highly heat-resistant and reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0359] nc-OS exhibits periodicity in atomic arrangement within minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). Furthermore, nc-OS lacks regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed across the entire film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors.

[0360] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. In other words, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0361] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may comprise two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0362] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0363] Furthermore, by using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. In addition, highly reliable transistors can be realized.

[0364] Furthermore, transistors using the above oxide semiconductor exhibit extremely low leakage current in the non-conductive state. Specifically, the off-current per 1 μm of channel width of the transistor is yA / μm(10 -24 Non-patent document 6 shows that the order is on the order of A / μm. For example, a low-power CPU that takes advantage of the low leakage current characteristic of transistors using oxide semiconductors has been disclosed (see Non-patent document 7).

[0365] Furthermore, applications of transistors using oxide semiconductors to display devices have been reported, taking advantage of their low leakage current characteristic (see Non-Patent Document 8). In display devices, the displayed image switches dozens of times per second. The number of image switches per second is called the refresh rate. The refresh rate is also sometimes called the drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, is considered to be a cause of eye fatigue. Therefore, it has been proposed to reduce the refresh rate of the display device to reduce the number of image rewrites. In addition, it is possible to reduce the power consumption of the display device by driving with a reduced refresh rate. This driving method is called idling stop (IDS) driving.

[0366] Furthermore, it is preferable to use an oxide semiconductor with a low carrier density for the transistor. To lower the carrier density of an oxide semiconductor, the impurity concentration in the oxide semiconductor should be reduced, thereby lowering the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, an oxide semiconductor with a carrier density of 8 × 10⁻¹⁶ is preferable. 11 / cm 3 Less than 1 × 10 11 / cm 3 Less than 1 × 10 10 / cm 3 It is less than 1 × 10 -9 / cm 3 That should suffice.

[0367] Furthermore, oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic may have a low trap level density due to their low defect level density.

[0368] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0369] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0370] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0371] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration obtained from the silicon or carbon near the interface with the oxide semiconductor (SIMS) are calculated as 2 × 10⁻¹⁰ 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0372] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be reduced to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0373] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier density and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Therefore, it is preferable to reduce the nitrogen content in the oxide semiconductor as much as possible. For example, the nitrogen concentration in the oxide semiconductor is 5 × 10¹⁶ in SIMS. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following applies:

[0374] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons, which act as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Less than.

[0375] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0376] The discovery of CAAC and nc structures has contributed to improving the electrical properties and reliability of transistors using oxide semiconductors with CAAC or nc structures, as well as reducing manufacturing costs and increasing throughput. Furthermore, research is underway on the application of these transistors to display devices and LSIs, taking advantage of their low leakage current characteristics.

[0377] This embodiment can be implemented in appropriate combination with other embodiments described herein.

[0378] (Embodiment 5) This embodiment describes a product image and an example of an electronic device that can use the storage device described in the above embodiment.

[0379] <Product Image> First, Figure 18 shows a product image that can be used in a memory device according to one embodiment of the present invention. Region 701 in Figure 18 represents high temperature characteristics (High T operation), region 702 represents high frequency characteristics (High f operation), region 703 represents low off-mode characteristics (Ioff), and region 704 represents the overlapping region of regions 701, 702, and 703.

[0380] Furthermore, to satisfy region 701, it can be roughly satisfied by using silicon carbide or gallium nitride or other carbides or nitrides as the channel formation region of the transistor. Similarly, to satisfy region 702, it can be roughly satisfied by using single-crystal silicon or crystalline silicon or other silides as the channel formation region of the transistor. Finally, to satisfy region 703, it can be roughly satisfied by using oxide semiconductors or metal oxides as the channel formation region of the transistor.

[0381] A storage device according to one embodiment of the present invention can be suitably used in products within the range shown in area 704, for example.

[0382] In conventional products, it was difficult to satisfy all of regions 701, 702, and 703. However, the transistor in a memory device according to one embodiment of the present invention has crystalline OS in the channel formation region. When crystalline OS is present in the channel formation region, it is possible to provide a memory device and electronic device that satisfy high temperature characteristics, high frequency characteristics, and low off-peak characteristics.

[0383] Products within the scope of area 704 include, for example, electronic devices with low power consumption and high performance CPUs, and automotive electronic devices that require high reliability in high-temperature environments. More specifically, Figures 19(A) to (E2), 20(A)(B), 21(A) to (C), and 22(A)(B) show examples of electronic devices equipped with a memory device according to one embodiment of the present invention.

[0384] <Electronic equipment> A storage device according to one embodiment of the present invention can be used in various electronic devices. In particular, a storage device according to one embodiment of the present invention can be used as memory built into an electronic device. Hereinafter, examples of electronic devices that can use a storage device according to one embodiment of the present invention will be given and described, including information terminals, game consoles, electrical appliances, mobile devices, parallel computers, and systems including servers.

[0385] For example, an information terminal 5500 is shown in Figure 19(A) as an electronic device that can use a storage device according to one embodiment of the present invention. The information terminal 5500 is a mobile phone (smartphone). The information terminal 5500 has a housing 5510 and a display unit 5511, and as an input interface, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0386] For example, as an electronic device that can use a storage device according to one embodiment of the present invention, a desktop information terminal 5300 is shown in Figure 19(B). The desktop information terminal 5300 has an information terminal body 5301, a display 5302, and a keyboard 5303.

[0387] Figures 19(A) and 19(B) illustrate smartphones and desktop information terminals as examples, but the storage device according to one embodiment of the present invention may also be used in other information terminals, such as PDAs (Personal Digital Assistants), notebook computers, and workstations.

[0388] For example, a portable game console 5200 is shown in Figure 19(C) as an electronic device that can use a storage device according to one embodiment of the present invention. The portable game console 5200 has a housing 5201, a display unit 5202, buttons 5203, etc.

[0389] Figure 19(C) illustrates a portable game console as an example, but the memory device according to one embodiment of the present invention may also be used in other game consoles, such as home consoles, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), and pitching machines for batting practice installed in sports facilities.

[0390] For example, an electric refrigerator-freezer 5800 is shown in Figure 19(D) as an electronic device that can use a storage device according to one embodiment of the present invention. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, etc.

[0391] Figure 19(D) illustrates an electric refrigerator as an example, but a storage device according to one embodiment of the present invention may also be used in other electrical appliances, such as vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, audiovisual equipment, digital cameras, digital video cameras, etc.

[0392] For example, an automobile 5700 is shown in Figure 19(E1) as an electronic device that can use a storage device according to one embodiment of the present invention. Figure 19(E2) shows the area around the windshield inside the automobile. In Figure 19(E2), display panels 5701, 5702, and 5703 mounted on the dashboard are shown, as well as a display panel 5704 mounted on the pillar.

[0393] Display panels 5701 to 5703 can provide various information by displaying the speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, and more. Furthermore, the display items and layout on the display panels can be changed as needed to suit the user's preferences, enhancing the design. Display panels 5701 to 5703 can also be used as lighting devices.

[0394] The display panel 5704 can compensate for the blind spot (view obstructed by the pillar) by displaying images from an imaging device (not shown) installed on the vehicle 5700. In other words, by displaying images from an imaging device installed on the outside of the vehicle 5700, the blind spot can be compensated for, and safety can be enhanced. Furthermore, by displaying images that compensate for the parts that are not visible, safety checks can be performed more naturally and without discomfort. The display panel 5704 can also be used as an illumination device.

[0395] Figures 19(E1) and 19(E2) illustrate an automobile and a display panel mounted around the windshield of an automobile as examples, but a memory device according to one embodiment of the present invention may also be used in other moving objects, such as trains, monorails, ships, and aircraft (helicopters, unmanned aerial vehicles (drones), airplanes, rockets, etc.).

[0396] For example, an information terminal 7000 is shown in Figures 20(A) and 20(B) as an electronic device that can use a storage device according to one embodiment of the present invention. The information terminal 7000 has a housing 7010, a monitor unit 7012, a keyboard 7013, a port 7015, etc.

[0397] The keyboard 7013 and port 7015 are located on the chassis 7010. Port 7015 includes, for example, a USB port, a LAN port, and an HDMI (High-Definition Multimedia Interface; HDMI is a registered trademark) port.

[0398] The monitor unit 7012, which is attached to the housing 7010, is openable and closable. Figure 20(A) shows the monitor unit 7012 in the open position, and Figure 20(B) shows the monitor unit 7012 in the closed position. For example, the maximum angle to which the monitor unit 7012 can be opened is approximately 135° (see Figure 20(A)).

[0399] The housing 7010 is provided with an openable and closable cover 7011 (see Figure 20(B)). A storage device 100 according to one embodiment of the present invention is incorporated inside the housing 7010, and the storage device 100 is removable. A device for cooling or dissipating heat from the storage device 100 may be provided inside the housing 7010. Since the storage device 100 can be removed and installed by opening the cover 7011, the information terminal 7000 has high expandability. By incorporating multiple storage devices 100 into the information terminal 7000, advanced graphics processing, scientific and technical calculations, artificial intelligence calculations, etc., can be performed.

[0400] For example, a large parallel computer 5400 is shown in Figure 21(A) as an electronic device that can use a storage device according to one embodiment of the present invention. The parallel computer 5400 has multiple rack-mount type computers 5420 in a rack 5410.

[0401] Figure 21(B) is a schematic perspective view showing an example configuration of computer 5420. Computer 5420 has a motherboard 5430, which has multiple slots 5431. A PC card 5421 is inserted into a slot 5431. The PC card 5421 has connectors 5423, 5424, and 5425, which are each connected to the motherboard 5430.

[0402] Figure 21(C) is a schematic perspective view showing an example configuration of the PC card 5421. The PC card 5421 has a board 5422, on which connection terminals 5423, 5424, 5425, chips 5426, chips 5427, etc.

[0403] Chips 5426, 5427, etc., are equipped with a storage device, CPU, GPU (Graphics Processing Unit), FPGA (Field Programmable Gate Array), etc., according to one embodiment of the present invention. Chips 5426, 5427, etc., have a plurality of terminals (not shown) for inputting and outputting signals, and an electrical connection to the PC card 5421 may be made by inserting these terminals into a socket (not shown) provided on the PC card 5421, or an electrical connection may be made by soldering these terminals to the wiring provided on the PC card 5421, for example, by reflow soldering.

[0404] Terminals 5423, 5424, and 5425 can serve as interfaces for, for example, power supply to the PC card 5421, signal input / output, etc. Examples of standards for terminals 5423, 5424, and 5425 include USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), and, if outputting video signals, HDMI (registered trademark).

[0405] Furthermore, the PC card 5421 has a connector 5428 on board 5422. The connector 5428 is shaped to be inserted into slot 5431 of the motherboard 5430, and functions as an interface for connecting the PC card 5421 and the motherboard 5430. An example of a standard for the connector 5428 is PCI Express (also known as PCIe; PCI Express and PCIe are registered trademarks).

[0406] The parallel computer 5400 can perform large-scale calculations necessary for, for example, large-scale scientific and technical calculations, and artificial intelligence learning and inference.

[0407] For example, Figure 22(A) shows a system including a server 5100 as an electronic device that can use a storage device according to one embodiment of the present invention. Figure 22(A) schematically shows how communication 5110 is performed between the server 5100 and an information terminal 5500 and a desktop information terminal 5300.

[0408] Users can access the server 5100 from information terminals 5500, desktop information terminals 5300, etc. Through communication 5110 over the internet, users can receive services provided by the administrator of the server 5100. Examples of such services include email, SNS (Social Networking Service), online software, cloud storage, navigation systems, translation systems, internet games, online shopping, financial transactions such as stocks, foreign exchange, and bonds, reservation systems for public facilities, commercial facilities, accommodations, hospitals, etc., and viewing of internet programs, lectures, and seminars.

[0409] Furthermore, if the information terminal 5500 or desktop information terminal 5300 at the user's location lacks sufficient processing power for scientific and technical calculations, or calculations necessary for artificial intelligence learning and inference, the user can access the server 5100 via communication 5110 and perform such calculations or operations on the server 5100.

[0410] For example, artificial intelligence can be used in services provided on server 5100. For instance, by introducing artificial intelligence into a navigation system, the system may be able to provide flexible guidance based on road congestion, train operation information, and other relevant factors. For instance, by introducing artificial intelligence into a translation system, the system may be able to appropriately translate unique expressions such as dialects and slang. For instance, by using artificial intelligence in a hospital reservation system, the system may be able to assess the user's symptoms and the severity of their injury and recommend appropriate hospitals or clinics.

[0411] Figure 22(A) shows communication 5110 between the server 5100 and the information terminal 5500 and the desktop information terminal 5300. However, communication 5110 may also be performed between the server 5100 and electronic devices other than information terminals. For example, it may be in the form of IoT (Internet of Things) where electronic devices are connected to the internet.

[0412] Figure 22(B) schematically shows, as an example, how communication 5110 is performed between a server 5100 and electronic devices (electric refrigerator 5800, portable game console 5200, automobile 5700, television equipment 5600).

[0413] In Figure 22(B), each electronic device may utilize artificial intelligence. Calculations necessary for AI learning and inference can be performed on the server 5100. For example, data necessary for calculations is transmitted from one of the electronic devices to the server 5100 via communication 5110, AI calculations are performed on the server 5100, and the output data is transmitted from the server 5100 to one of the electronic devices via communication 5110. This allows the electronic device to utilize the data output by the AI ​​calculations.

[0414] Note that the electronic equipment shown in Figure 22(B) is just an example, and communication 5110 may also be performed between the server 5100 and electronic equipment not shown in Figure 22(B).

[0415] As described above, a storage device according to one embodiment of the present invention can be used in various electronic devices. A storage device according to one embodiment of the present invention can operate with a small number of power supplies, thereby reducing the cost of electronic devices using this storage device. Furthermore, a storage device according to one embodiment of the present invention has a small chip area, which allows for miniaturization of electronic devices, or enables the installation of more storage devices in electronic devices. In addition, a storage device according to one embodiment of the present invention is less prone to data loss even in high-temperature environments and can operate at high speeds. By using a storage device according to one embodiment of the present invention, it is possible to provide highly reliable electronic devices that operate reliably even in high-temperature environments.

[0416] This embodiment can be implemented in appropriate combination with other embodiments described herein. [Explanation of symbols]

[0417] C11: Capacitive element, C12: Capacitive element, C13: Capacitive element, C14: Capacitive element, M11: Transistor, M12: Transistor, M13: Transistor, M14: Transistor, M21: Transistor, M22: Transistor, M23: Transistor, M24: Transistor, M26: Transistor, N11: Node, N12: Node, N13: Node, N14: Node, S1: Oxide, 31: Sense amplifier circuit, 32: AND circuit, 33: Analog switch, 34: Analog switch, 100: Memory device, 101: Layer, 105: Memory device, 110: Peripheral circuit, 115: Peripheral circuit, 121: Raw decoder, 122: Word line driver circuit, 123: Pre-decoder, 131: Column decoder, 132: Bit line driver circuit, 133: Precharge circuit, 134: Sense amplifier circuit, 135: Output MUX circuit, 136: Driver circuit, 137: Circuit, 138: Page buffer, 140: Output circuit, 150: Potential generation circuit, 151: Regulator, 152: Regulator, 153: Power switch, 160: Control logic circuit, 161: SPI controller, 162: Serial-to-parallel converter, 163: Instruction decoder circuit, 164: Page address generation circuit, 165: Command generation circuit, 166: Byte address generation circuit, 167: Parallel-to-serial converter, 168: Status register, 201: Layer, 210: Memory cell array, 211: Memory cell, 212: Memory cell, 213: Memory cell 214: Memory cell, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low-resistance region, 314b: Low-resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 370: Insulator, 372: Insulator, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 500: Transistor, 510: Insulator, 510A: Transistor, 510B: Transistor, 510C: Transistor, 510D: Transistor, 510E: Transistor, 511: Insulator, 512: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator, 521: Insulator, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 530c: Oxide, 531: Region, 531a: Region, 531b: Region, 540a: Conductor, 540b: Conductor, 542: Conductor, 542a: Conductor, 542b: Conductor, 543: Region, 543a: Region, 543b: Region, 544: Insulator, 545: Insulator, 546: Conductor, 546a: Conductor, 546b: Conductor, 547: Conductor, 547a: Conductor, 547b: Conductor, 548: Conductor, 550: Insulator, 552: Metal oxide, 560: Conductor, 560a: Conductor, 560b: Conductor, 570: Insulator, 571: Insulator, 573: Insulator, 574: Insulator, 575: Insulator, 576: Insulator, 576a: Insulator, 576b: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 584: Insulator, 586: Insulator, 600: Capacitive element, 610: Conductor, 612: Conductor, 620: Conductor, 630: Insulator, 650: Insulator, 701: Area, 702: Area, 703: Area, 704: Area, 5100: Server, 5110: Communication, 5200: Portable game console, 5201: Enclosure, 5202: Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main unit, 5302: Display, 5303: Keyboard, 5400: Parallel computer, 5410: Rack, 5420: Computer, 5421: PC card, 5422: Board, 5423: Connection terminal, 5424: Connection terminal, 5425: Connection terminal5426: Chip, 5427: Chip, 5428: Connector, 5430: Motherboard, 5431: Slot, 5500: Information terminal, 5510: Enclosure, 5511: Display unit, 5600: Television equipment, 5700: Automobile, 5701: Display panel, 5702: Display panel, 5703: Display panel, 5704: Display panel, 5800: Electric refrigerator / freezer, 5801: Enclosure, 5802: Refrigerator door, 5803: Freezer door, 7000: Information terminal, 7010: Enclosure, 7011: Cover, 7012: Monitor unit, 7013: Keyboard, 7015: Port

Claims

1. The first to fifth wirings, It has first and second transistors, The second transistor has a front gate and a back gate, Either the source or the drain of the first transistor is electrically connected to the first wiring, The source or drain of the first transistor, the other of which is electrically connected to the front gate of the second transistor, The gate of the first transistor is electrically connected to the third wiring, Either the source or the drain of the second transistor is electrically connected to the second wiring. The source or drain of the second transistor, the other of which is electrically connected to the fourth wiring, The back gate of the second transistor is electrically connected to the fifth wiring, The first and second wirings are arranged parallel to each other. The third, fourth, and fifth wirings are arranged parallel to each other. The first wiring is arranged to intersect with the fourth wiring. The fourth and fifth wirings are each given different potentials. The first and second transistors are n-channel transistors, The first and second transistors are semiconductor devices having a metal oxide in the channel formation region.

2. m × n memory cells (where m and n are integers greater than or equal to 1), n first wires and n second wires and m-number third wiring, m-number fourth wiring, It has m fifth wirings, The aforementioned m × n memory cells are arranged in a matrix, Each of the memory cells is electrically connected to the first to fifth wirings. Each of the aforementioned memory cells has a first and a second transistor, The second transistor has a front gate and a back gate, Either the source or the drain of the first transistor is electrically connected to the first wiring, The source or drain of the first transistor, the other of which is electrically connected to the front gate of the second transistor, The gate of the first transistor is electrically connected to the third wiring, Either the source or the drain of the second transistor is electrically connected to the second wiring. The source or drain of the second transistor, the other of which is electrically connected to the fourth wiring, The back gate of the second transistor is electrically connected to the fifth wiring, The first and second wirings are arranged parallel to each other. The third, fourth, and fifth wirings are arranged parallel to each other. The first wiring is arranged to intersect with the fourth wiring. The fourth and fifth wirings are each given different potentials. The first and second transistors are n-channel transistors, The first and second transistors are memory devices having a metal oxide in the channel formation region.

3. In claim 1 or claim 2, The aforementioned metal oxide is indium oxide, in a memory device.

Images