Semiconductor device and method for manufacturing the same

Abstract

The present invention reduces the influence of dry etching during via forming in a substrate.　A first base body is formed by laminating a first semiconductor substrate and a second semiconductor substrate. A pixel region for executing photoelectric conversion is formed in the first semiconductor substrate. A logic circuit for processing a pixel signal outputted from the pixel region is formed in the second semiconductor substrate. The first base body is provided with a first via that extends from a wiring layer of the logic circuit to the backside of the first base body. A second base body is provided with a connection part and a second via. The connection part is connected, at the surface of the second base body, to the first via of the first base body. The second via is formed such that the connection part and an electrode of a lowermost surface are electrically connected by a conductive material.

Description

Technical Field

[0001] This technology relates to semiconductor devices. More specifically, it relates to a semiconductor device composed of a stacked semiconductor substrate in which multilayer wiring layers between a plurality of semiconductor substrates are electrically connected, and a method for manufacturing the same.

Background Art

[0002] For the purpose of miniaturizing semiconductor devices, a wafer-level CSP (WLCSP: Wafer Level Chip Size Package) in which the semiconductor device is miniaturized to the chip size is used. As a WLCSP of a solid-state imaging device, a surface-type solid-state imaging device on which a color filter and an on-chip lens are formed is bonded with glass in a cavity structure, through holes and rewiring are formed from the silicon substrate side, and a structure for mounting solder balls has been proposed. This can reduce the chip area by extracting the pad electrodes from the back side of the chip, compared to a structure in which the pad electrodes of the semiconductor device are arranged on the outer peripheral part of the circuit and the electrodes are drawn out by wire bonding. For example, a method has been proposed in which vias (TSV: Through Silicon Via) penetrating the silicon of the substrate are formed from the back side of the chip, vias and wiring connected to the pad electrodes inside the chip are formed, and electrodes are formed on the back side of the chip (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when forming vias on a thick substrate such as the silicon substrate layer of a chip, the charge generated during dry etching when opening the vias can affect the characteristics of transistors connected to the pad electrodes inside the chip. This phenomenon is called PID (Plasma Induced Damage) and can lead to threshold fluctuations in transistor characteristics, increased leakage current in the gate insulating film, and reduced yield or malfunction of semiconductor products. It is known that the effect of PID increases as the via depth increases.

[0005] This technology was developed in light of these circumstances and aims to reduce the effects of dry etching when forming vias on a substrate. [Means for solving the problem]

[0006] This technology was developed to solve the aforementioned problems, and its first aspect is a semiconductor device comprising: a first substrate having a first semiconductor substrate on which a pixel region for photoelectric conversion is formed and a second semiconductor substrate having a logic circuit for processing the pixel signal output from the pixel region, with the first via extending from the wiring layer of the logic circuit to the back surface; and a second substrate having a connection portion on the surface that connects to the first via of the first substrate, and a second via electrically connected between the connection portion and the electrode on the bottom surface by a conductive material. By forming the second via on the second substrate separately from the first substrate, the influence on the logic circuit of the first substrate is reduced.

[0007] Furthermore, in this first aspect, it is desirable that the thickness of the second substrate be greater than the depth of the first via. This has the effect of further reducing the influence of the first substrate on the logic circuit.

[0008] Furthermore, in this first aspect, the second substrate may be provided with a plurality of the second vias.

[0009] Furthermore, in this first aspect, the second substrate may include an insulating layer through which the second via opens. In this case, the insulating layer through which the second via opens is assumed to be, for example, a silicon oxide film. On the other hand, in this first aspect, the second substrate may include a silicon layer through which the second via opens.

[0010] Furthermore, in this first aspect, the connecting portion of the second base may be larger than the diameter of the first via. This provides a margin in the connection between the first via and the second via.

[0011] Furthermore, in this first aspect, the second substrate may be provided with a wiring layer in the path that electrically connects the connection portion and the electrode. This provides a degree of freedom in the arrangement of the second via in the second substrate.

[0012] Furthermore, in this first aspect, the second substrate may be provided with a bump that electrically connects to the electrode at its lowest surface.

[0013] Furthermore, the second aspect of this technology is the process of forming a first substrate by stacking a first semiconductor substrate on which a pixel region for photoelectric conversion is formed and a second semiconductor substrate on which a logic circuit for processing the pixel signal output from the pixel region is formed; forming an insulating film on the back surface of the first substrate; forming a first opening by opening up the conductive material inside the first substrate; forming an insulating film sidewall inside the first opening; embedding a conductive material inside the insulating film sidewall; flattening the conductive material; and the above A method for manufacturing a semiconductor device comprising the steps of: forming a second opening by opening a second substrate different from a first substrate; forming an insulating film on the back surface of the second substrate; embedding a conductive material in the second opening; flattening the conductive material; bonding the first substrate and the second substrate together such that the conductive material in the first opening of the first substrate and the conductive material in the second opening of the second substrate are connected; and removing the substrate of the second substrate until a portion of the conductive material inside the second substrate is exposed. This reduces the influence of the first substrate on the logic circuit by forming the second via in the second substrate separately from the first substrate and bonding them together.

[0014] Furthermore, in this second aspect, the first opening may be formed in at least the silicon layer during the process of forming the first opening.

[0015] Furthermore, in this second aspect, the process may further include a step of thinning the film thickness of the upper material of the first substrate after bonding the first substrate and the second substrate together. In this case, the upper material of the first substrate is assumed to be, for example, silicon. [Brief explanation of the drawing]

[0016] [Figure 1] This figure shows an example of the overall configuration of a solid-state imaging device, which is an example of a semiconductor device having an image sensor in an embodiment of this technology. [Figure 2]It is a diagram showing an example of dividing a substrate of a solid-state imaging device in an embodiment of the present technology. [Figure 3] It is a diagram showing an example of a cross-sectional structure of a solid-state imaging device in the first embodiment of the present technology. [Figure 4] It is a diagram showing a first example of a solid-state imaging device in the first embodiment of the present technology. [Figure 5] It is a diagram showing an example of the shape of via 235 of a solid-state imaging device in the first embodiment of the present technology. [Figure 6] It is a diagram showing a second example of a solid-state imaging device in the first embodiment of the present technology. [Figure 7] It is a diagram showing a third example of a solid-state imaging device in the first embodiment of the present technology. [Figure 8] It is a diagram showing a fourth example of a solid-state imaging device in the first embodiment of the present technology. [Figure 9] It is a diagram showing a fifth example of a solid-state imaging device in the first embodiment of the present technology. [Figure 10] It is a diagram showing a fifth example of a solid-state imaging device in the first embodiment of the present technology. [Figure 11] It is a diagram showing a fifth example of a solid-state imaging device in the first embodiment of the present technology. [Figure 12] It is a diagram showing a fifth example of a solid-state imaging device in the first embodiment of the present technology. [Figure 13] It is a diagram showing an example of a procedure for manufacturing the first substrate 100 in the first embodiment of the present technology. [Figure 14] It is a diagram showing an example of a procedure for manufacturing the first substrate 100 in the first embodiment of the present technology. [Figure 15] It is a diagram showing an example of a procedure for manufacturing the second substrate 200 in the first embodiment of the present technology. [Figure 16] It is a diagram showing an example of a procedure for manufacturing the second substrate 200 in the first embodiment of the present technology. [Figure 17] It is a diagram showing an example of a procedure for manufacturing the second substrate 200 in the first embodiment of the present technology. [Figure 18] This figure shows a first modified example of the second substrate 200 in the first embodiment of this technology. [Figure 19] This figure shows a second modified example of the second substrate 200 in the first embodiment of this technology. [Figure 20] This figure shows an example of a procedure for manufacturing a solid-state imaging device according to the first embodiment of this technology. [Figure 21] This figure shows an example of a procedure for manufacturing a solid-state imaging device according to the first embodiment of this technology. [Figure 22] This figure shows an example of a procedure for manufacturing a solid-state imaging device according to the first embodiment of this technology. [Figure 23] This figure shows an example of a procedure for manufacturing a solid-state imaging device according to the first embodiment of this technology. [Figure 24] This figure shows an example of a cross-sectional structure of a solid-state imaging device in a second embodiment of this technology. [Figure 25] This figure shows an example of the procedure for manufacturing the second substrate 200 in a second embodiment of the present technology. [Figure 26] This figure shows an example of the procedure for manufacturing the second substrate 200 in a second embodiment of the present technology. [Figure 27] This figure shows an example of a cross-sectional structure of a solid-state imaging device in a third embodiment of this technology. [Figure 28] This figure shows an example of the procedure for manufacturing the second substrate 200 in a third embodiment of this technology. [Figure 29] This figure shows an example of the procedure for manufacturing the second substrate 200 in a third embodiment of this technology. [Modes for carrying out the invention]

[0017] The following describes the embodiments for implementing this technology. The description will proceed in the following order. 1. First Embodiment (Technique for forming and bonding deep vias separately) 2. Second Embodiment (Example of a case where the via opening aspect ratio is high) 3. Third Embodiment (Example of forming vias on a silicon substrate)

[0018] <1. First Embodiment> [Overall configuration of the solid-state imaging system] Figure 1 shows an example of the overall configuration of a solid-state imaging device, which is an example of a semiconductor device having an image sensor in an embodiment of this technology. This solid-state imaging device is configured as a CMOS (Complementary Metal Oxide Semiconductor) image sensor. This solid-state imaging device has an image sensor 10 and peripheral circuitry on a semiconductor substrate (for example, a silicon substrate) (not shown). The peripheral circuitry includes a vertical drive circuit 20, a horizontal drive circuit 30, a control circuit 40, a column signal processing circuit 50, and an output circuit 60.

[0019] The image sensor 10 is a pixel array in which a plurality of pixels 11, each containing a photoelectric conversion unit, are arranged in a two-dimensional array. Each pixel 11 includes, for example, a photodiode which serves as the photoelectric conversion unit, and a plurality of pixel transistors. Here, the plurality of pixel transistors can be composed of, for example, three transistors: a transfer transistor, a reset transistor, and an amplification transistor. Alternatively, the plurality of pixel transistors can be composed of four transistors by adding a selection transistor. Note that the equivalent circuit of a unit pixel is the same as a general one, so a detailed explanation is omitted.

[0020] Furthermore, pixel 11 can be configured as a single unit pixel, or it can be a shared pixel structure. This shared pixel structure is one in which multiple photodiodes share transistors other than the floating diffusion and transfer transistors.

[0021] The vertical drive circuit 20 drives the pixels 11 row by row. This vertical drive circuit 20 is composed of, for example, a shift register. This vertical drive circuit 20 selects a pixel drive wiring and supplies pulses to the selected pixel drive wiring to drive the pixels 11. As a result, the vertical drive circuit 20 sequentially selects and scans each pixel 11 of the image sensor 10 row by row in the vertical direction and supplies a pixel signal based on the signal charge generated in the photoelectric conversion section of each pixel 11 according to the amount of light received to the column signal processing circuit 50.

[0022] The horizontal drive circuit 30 drives the column signal processing circuits 50 on a column-by-column basis. This horizontal drive circuit 30 is composed of, for example, a shift register. By sequentially outputting horizontal scanning pulses, the horizontal drive circuit 30 selects each of the column signal processing circuits 50 in order and causes each of the column signal processing circuits 50 to output a pixel signal to the horizontal signal line 59.

[0023] The control circuit 40 controls the entire solid-state imaging device. This control circuit 40 receives an input clock and data that commands the operating mode, etc., and outputs data such as internal information of the solid-state imaging device. In other words, based on the vertical synchronization signal, horizontal synchronization signal, and master clock, this control circuit 40 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 20, column signal processing circuit 50, and horizontal drive circuit 30, etc. Then, it inputs these signals to the vertical drive circuit 20, column signal processing circuit 50, and horizontal drive circuit 30, etc.

[0024] The column signal processing circuit 50 is arranged for each column of pixels 11, and performs signal processing such as noise reduction on the signal output from one row of pixels 11 for each pixel column. Specifically, this column signal processing circuit 50 performs signal processing such as CDS (Correlated Double Sampling) to remove fixed pattern noise specific to pixels 11, signal amplification, and AD (Analog / Digital) conversion. A horizontal selection switch (not shown) is connected between the output stage of the column signal processing circuit 50 and the horizontal signal line 59.

[0025] The output circuit 60 processes the signals sequentially supplied from each of the column signal processing circuits 50 through the horizontal signal line 59 and outputs them. In doing so, the output circuit 60 buffers the signals from the column signal processing circuits 50. The output circuit 60 may also perform black level adjustment, column variation correction, and various digital signal processing on the signals from the column signal processing circuits 50.

[0026] Figure 2 shows an example of the division of the substrate of a solid-state imaging device in an embodiment of this technology.

[0027] In the figure, 'a' represents the first example. This first example consists of a first semiconductor substrate 91 and a second semiconductor substrate 92. The first semiconductor substrate 91 is equipped with a pixel region 93 and a control circuit 94. The second semiconductor substrate 92 is equipped with a logic circuit 95 including a signal processing circuit. The first semiconductor substrate 91 and the second semiconductor substrate 92 are electrically connected to each other to form a solid-state imaging device as a single semiconductor chip.

[0028] In the figure, b shows a second example. This second example consists of a first semiconductor substrate 91 and a second semiconductor substrate 92. A pixel region 93 is mounted on the first semiconductor substrate 91. A control circuit 94 and a logic circuit 95 including a signal processing circuit are mounted on the second semiconductor substrate 92. The first semiconductor substrate 91 and the second semiconductor substrate 92 are electrically connected to each other to form a solid-state imaging device as a single semiconductor chip.

[0029] In the figure, c represents a third example. This third example consists of a first semiconductor substrate 91 and a second semiconductor substrate 92. The first semiconductor substrate 91 is mounted with a pixel region 93 and a control circuit 94 that controls the pixel region 93. The second semiconductor substrate 92 is mounted with a logic circuit 95 including a signal processing circuit and a control circuit 94 that controls the logic circuit 95. The first semiconductor substrate 91 and the second semiconductor substrate 92 are electrically connected to each other to form a solid-state imaging device as a single semiconductor chip.

[0030] [Cross-sectional structure of a solid-state imaging device] Figure 3 shows an example of a cross-sectional structure of a solid-state imaging device in the first embodiment of this technology.

[0031] In this first embodiment, in order to reduce the impact on transistor characteristics, the deep TSV formation process is avoided by manufacturing the first substrate 100 and the second substrate 200 separately and then bonding them together. Specifically, shallow vias 145 are formed on the first substrate 100 on which the internal circuit transistor 141 is formed, and deep vias 235 are formed on the second substrate 200, which is separate from the first substrate 100. In other words, the thickness of the second substrate 200 is greater than the shallow vias 145 of the first substrate 100. The first substrate 100 and the second substrate 200 are then bonded together so that the shallow vias 145 and the deep vias 235 are electrically connected.

[0032] The first substrate 100 is constructed by stacking, in order from the surface, a silicon substrate 110, insulating films 120 and 130, a silicon layer 140, and an insulating film 150. A pad electrode 190 is formed on the upper side of the silicon layer 140. Note that the pad electrode 190 is a broad concept that includes the pad electrode and wiring. The second substrate 200 is constructed by stacking, in order from the surface, an insulating film 230 and a silicon substrate 240. Shallow vias 145 in the first substrate 100 penetrate the silicon layer 140. Deep vias 235 in the second substrate 200 are formed in the insulating film 230.

[0033] Here, the first semiconductor substrate 91 described above corresponds to the portion of the silicon substrate 110 and the insulating film 120. The second semiconductor substrate 92 corresponds to the portion below the insulating film 130. In other words, the boundary between the first semiconductor substrate 91, which includes the pixel region 93, and the second semiconductor substrate 92, which includes the logic circuit 95, lies between the insulating film 120 and the insulating film 130.

[0034] After the first substrate 100 and the second substrate 200 are bonded together, the underside of the silicon substrate 240 and the insulating film 230 is removed, exposing the pad electrodes 290 on the back surface. Furthermore, the on-chip lens 180 is formed after the upper side of the silicon substrate 110 is flattened.

[0035] The insulating films 120, 130, 150, and 230 are mainly formed from silicon oxide films such as SiO2. Specifically, the insulating film 120 that insulates the wiring layer of the pixel region 93 uses a SiN film or the like. In addition, the insulating film 130 of the logic circuit 95 employs a layered structure of film types such as SiOC or SiCN to achieve a low dielectric constant.

[0036] [First Embodiment] Figure 4 shows a first embodiment of the solid-state imaging device in the first embodiment of the present technology.

[0037] This first embodiment is a basic form similar to the embodiment described above. That is, the conductive material in the via 145 of the silicon layer 140 and the conductive material in the via 235 of the insulating film 230 are electrically connected in a linear manner. This allows the signal from the pad electrode 190 inside the first substrate 100 to be transmitted to the pad electrode 290 on the back surface of the second substrate 200.

[0038] Figure 5 shows an example of the shape of a via 235 in a solid-state imaging device in the first embodiment of this technology. All of the figures are views of the insulating film 230 cut in a planar manner.

[0039] As shown in figure a, the cross-section of via 235 may be donut-shaped. In this case, it is assumed that the inside of via 235 is filled with a conductive material (for example, copper).

[0040] Furthermore, as shown in figure b, the via 235 may be formed as a plurality of thin cylinders. In this case, it is assumed that the interior of each cylinder of the via 235 is filled with a conductive material (for example, copper).

[0041] [Second Example] Figure 6 shows a second embodiment of the solid-state imaging device in the first embodiment of this technology.

[0042] In this second embodiment, a pad electrode 191 is individually provided on the back surface of the first substrate 100 for every 145 vias, and a pad electrode 291 is individually provided on the upper surface of the second substrate 200 for every 235 vias. This ensures a margin in case of misalignment when bonding the first substrate 100 and the second substrate 200. If the pad electrodes 191 and 291 are made of copper, CuCu bonding can be performed.

[0043] [Third embodiment] Figure 7 shows a third embodiment of the solid-state imaging device in the first embodiment of this technology.

[0044] This third embodiment is similar to the second embodiment described above, but a single pad electrode 192 is provided on the back surface of the first substrate 100 for multiple vias 145, and a single pad electrode 292 is provided on the upper surface of the second substrate 200 for multiple vias 235. This allows for an additional margin to be secured in case of misalignment when bonding the first substrate 100 and the second substrate 200.

[0045] [Fourth embodiment] Figure 8 shows a fourth embodiment of the solid-state imaging device in the first embodiment of this technology.

[0046] This fourth embodiment, compared to the third embodiment described above, makes it possible to change the position of the pad electrodes 290 on the back surface of the second substrate 200 by further utilizing the wiring layer 293 to form a multi-stage path. That is, in the third embodiment, the positions of the vias 235 of the second substrate 200 were aligned on the top and bottom surfaces, but in this fourth embodiment, it is not necessary for the two to be aligned, thereby increasing the degree of freedom in the position of the pad electrodes 290.

[0047] [Fifth Example] Figures 9 to 12 show a fifth embodiment of the solid-state imaging device in the first embodiment of this technology.

[0048] This fifth embodiment is a modification of the first to fourth embodiments described above, in which bumps 280 are provided on the pad electrodes 290 on the back surface of the second substrate 200. While the first to fourth embodiments described above used flat connections, this fifth embodiment uses connections via bumps 280.

[0049] [Manufacturing method for solid-state imaging devices] Figures 13 and 14 show an example of the procedure for manufacturing the first substrate 100 in the first embodiment of this technology.

[0050] First, as shown in Figure 13, a wafer of the first semiconductor substrate 91, which includes a silicon substrate 110 and an insulating film 120, and a wafer of the second semiconductor substrate 92, which includes an insulating film 130 and a silicon layer 140, are joined together. Pad electrodes 190 are formed on the insulating film 130. Note that devices and wiring within the wafer of the first semiconductor substrate 91 and devices within the wafer of the second semiconductor substrate 92 are not shown in the figure.

[0051] Next, as shown in Figure 14, the silicon layer 140 is polished by CMP (Chemical Mechanical Polishing) until it reaches a thickness of several microns (for example, 3 to 10 μm). Then, an insulating film 150 is formed on the back surface of the silicon layer 140 using CVD (Chemical Vapor Deposition).

[0052] Then, below the pad electrode 190, the silicon layer 140 is opened by photoresist and dry etching to form a via 145. An insulating film sidewall is formed on the side of this via 145 by CVD and etch-back. Then, a conductive material 195 (for example, copper) is embedded inside this via 145 by plating and polished by CMP. In this way, the first substrate 100 is formed.

[0053] Figures 15 to 17 show an example of the procedure for manufacturing the second substrate 200 in the first embodiment of this technology.

[0054] First, as shown in Figure 15, an insulating film 230 is formed on the silicon substrate 240 by CVD. Then, in order to form the pad electrode 290, a conductive material (for example, copper) is plated onto the grooved portion and polished by CMP.

[0055] Then, as shown in Figure 16, the insulating film 230 is grown to, for example, about 150 microns by CVD or glass bonding. Then, vias 235 are opened on the upper part of the pad electrode 290 using photoresist, and etching is performed.

[0056] Then, as shown in Figure 17, a conductive material 295 (for example, copper) is embedded inside the via 235 by plating and polished by CMP. In this way, the second substrate 200 is formed.

[0057] Figure 18 shows a first modified example of the second substrate 200 in the first embodiment of the present technology.

[0058] As shown in Example 3 above, a pad electrode 292 may be formed on top of the via 235. In this case, the insulating film 230 can be further grown by repeating the above procedure, and the pad electrode 292 can be formed by plating and CMP.

[0059] Figure 19 shows a second modified example of the second substrate 200 in the first embodiment of the present technology.

[0060] As shown in Example 4 above, a wiring layer 293 may be formed in the middle of the via 235. In this case, by repeating the above procedure, the insulating film 230 can be grown in multiple layers, and the wiring layer 293 can be formed by plating and CMP.

[0061] Figures 20 to 23 show examples of the procedure for manufacturing a solid-state imaging device in the first embodiment of this technology.

[0062] The first substrate 100 and the second substrate 200 formed by the above procedure are bonded together, as shown in Figure 20, such that the conductive material of via 145 and the conductive material of via 235 are electrically connected. As a result, as shown in Figure 21, the pad electrode 190 and the pad electrode 290 are electrically connected.

[0063] Subsequently, as shown in Figure 22, the lower part of the silicon substrate 240 is removed by CMP or silicon etching. Then, the insulating film 230 is removed by CMP until the pad electrode 290 is exposed.

[0064] Then, as shown in Figure 23, the upper surface of the silicon substrate 110 is polished by CMP until it reaches a thickness of, for example, about 2 microns. After that, an on-chip lens 180 is formed on the upper surface of the silicon substrate 110. In this way, a solid-state imaging device consisting of the first substrate 100 and the second substrate 200 is formed.

[0065] Thus, according to the first embodiment of this technology, by forming deep vias 235 on the second substrate 200 and then bonding it to the first substrate 100, it is possible to avoid affecting the transistors connected to the shallow vias 145 of the first substrate 100.

[0066] <2. Second Embodiment> In the first embodiment described above, it was assumed that conductive material would be embedded in the entire via 235, but aperture etching may be difficult when the aperture aspect ratio is high, etc. In this second embodiment, a method for forming conductive material in the via without using aperture etching will be described. Note that the overall configuration of the solid-state imaging device is the same as in the first embodiment described above, so a detailed explanation will be omitted.

[0067] [Cross-sectional structure of a solid-state imaging device] Figure 24 shows an example of a cross-sectional structure of a solid-state imaging device in a second embodiment of this technology.

[0068] In this second embodiment, a conductive material 296 is formed on the inner wall and upper part of the via 236 of the insulating film 230, and then resin 250 is embedded inside. Furthermore, a conductive material 297 is formed on top of the conductive material 296 for connection with the first substrate 100. This electrically connects the pad electrode 190 and the pad electrode 290.

[0069] [Manufacturing method for solid-state imaging devices] Figures 25 and 26 show an example of the procedure for manufacturing the second substrate 200 in the second embodiment of this technology. Note that the manufacturing method for the first substrate 100 is the same as in the first embodiment described above, so a detailed explanation is omitted.

[0070] First, as shown in Figure 25, an insulating film 230 is formed on the silicon substrate 240 by CVD. Then, in order to form the pad electrode 290, a conductive material (for example, copper) is plated onto the grooved portion and polished by CMP.

[0071] Subsequently, the insulating film 230 is grown by CVD or glass bonding. Then, vias 236 are opened on the upper part of the pad electrode 290 using photoresist.

[0072] Then, as shown in Figure 26, a conductive material 296 (for example, copper) is plated, and a resist patterning is performed to form a pattern of the conductive material 296 on the inner wall and top of the via 236.

[0073] Then, resin 250 is applied to the inside of the conductive material 296 and polished by CMP.

[0074] Subsequently, an insulating film 260 is deposited on top of the insulating film 230 by CVD, and then polished by CMP.

[0075] Then, resist patterning is performed in the insulating film 260 to form openings, a conductive material 297 (for example, copper) is plated into these openings, and the film is polished by CMP.

[0076] Subsequently, the first substrate 100 and the second substrate 200 are joined together, and the silicon substrate 240 on the back of the second substrate 200 is removed. The insulating film 230 is also removed until the pad electrodes 290 are exposed.

[0077] Furthermore, the upper part of the silicon substrate 110 is polished by CMP to a thickness of, for example, about 2 microns to create a thin film. After that, an on-chip lens 180 is formed on the upper part of the silicon substrate 110. In this way, the solid-state imaging apparatus of the second embodiment shown in Figure 24 is formed.

[0078] Thus, according to the second embodiment of this technology, even when the aperture aspect ratio of the via 236 of the insulating film 230 is high, the pad electrode 190 and the pad electrode 290 can be electrically connected to bond the first substrate 100 and the second substrate 200 together.

[0079] <3. Third Embodiment> In the second embodiment described above, vias 236 were formed in the insulating film 230. In this third embodiment, a method for forming vias in the silicon substrate 240 will be described. The overall configuration of the solid-state imaging device is the same as in the first embodiment described above, so a detailed explanation will be omitted.

[0080] [Cross-sectional structure of a solid-state imaging device] Figure 27 shows an example of a cross-sectional structure of a solid-state imaging device in a third embodiment of this technology.

[0081] In this third embodiment, an insulating film 270 is formed on the inner wall and surface of the via 245 of the silicon substrate 240, then a conductive material 298 is formed on the inner wall and upper part, and resin 250 is embedded inside. Also, similar to the second embodiment, a conductive material 297 is formed on the upper part of the conductive material 296 for connection with the first substrate 100, so that the pad electrodes 190 and 290 are electrically connected.

[0082] [Manufacturing method for solid-state imaging devices] Figures 28 and 29 show an example of the procedure for manufacturing the second substrate 200 in the third embodiment of this technology. Note that the manufacturing method for the first substrate 100 is the same as in the first embodiment described above, so a detailed explanation is omitted.

[0083] First, as shown in Figure 28, vias 245 are opened in the silicon substrate 240 by aperture etching. Then, an insulating film 270 is deposited on top of the silicon substrate 240 by CVD.

[0084] Then, as shown in Figure 29, a conductive material 298 (for example, copper) is plated onto the insulating film 270. Next, resin 250 is applied to the inside of the conductive material 298 and polished by CMP.

[0085] Subsequently, an insulating film 260 is deposited on top of the conductive material 298 by CVD. Then, resist patterning is performed in the insulating film 260 to form openings, and the conductive material 296 (for example, copper) is plated into these openings and polished by CMP.

[0086] Subsequently, the first substrate 100 and the second substrate 200 are joined together, and the silicon substrate 240 on the back of the second substrate 200 is removed. The insulating film 270 is also removed until the conductive material 298 on the back of the second substrate 200 is exposed.

[0087] Next, an insulating film 249 is deposited on the back surface of the second substrate 200 by CVD. Then, resist patterning is performed in the insulating film 249 to form openings, a conductive material (for example, copper) is plated into these openings, and the film is polished by CMP. This forms the pad electrode 290.

[0088] Furthermore, the upper part of the silicon substrate 110 is polished by CMP to a thickness of, for example, about 2 microns, to create a thin film. After that, an on-chip lens 180 is formed on the upper part of the silicon substrate 110. In this way, the solid-state imaging apparatus of the third embodiment shown in Figure 27 is formed.

[0089] Furthermore, as shown in the diagram, bumps 280 (for example, made of copper) may be formed on the back surface of the second substrate 200.

[0090] Thus, according to the third embodiment of this technology, conductive material 298 can be formed on the inner wall and upper surface of the vias 245 of the silicon substrate 240 via the insulating film 270, thereby enabling the first substrate 100 and the second substrate 200 to be bonded together.

[0091] [effect] Thus, in this embodiment of the technology, by forming deep vias 235 on the second substrate 200, the influence of PID on the transistors of the first substrate 100 can be reduced. For example, the threshold voltage fluctuation of a transistor, which is conventionally several hundred millivolts, can be reduced to about 10 millivolts according to this embodiment.

[0092] Furthermore, conventionally, transistors are generally positioned at a distance from TSVs to avoid stress effects from TSVs, and this distance is called the Keep Out Zone (KOZ). Assuming that the conductive material in the via is copper, the ratio of its coefficient of thermal expansion is smaller for SiO2 than for silicon. Therefore, using SiO2 as the substrate material for forming the vias rather than silicon can reduce stress from the vias and reduce the KOZ by about 70%. Consequently, from the viewpoint of KOZ, forming deep vias 235 in the insulating film 230, as in the first and second embodiments, is more advantageous than forming deep vias 245 in the silicon substrate 240, as in the third embodiment.

[0093] The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology.

[0094] The effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0095] Furthermore, this technology can also be configured as follows. (1) A first substrate comprising a first semiconductor substrate on which a pixel region for photoelectric conversion is formed and a second semiconductor substrate on which a logic circuit for processing the pixel signal output from the pixel region is formed, with a first via extending from the wiring layer of the logic circuit to the back surface, A second substrate comprising a connecting portion on its surface that connects to the first via of the first substrate, and a second via that is electrically connected between the connecting portion and the electrode on the bottom surface by a conductive material. A semiconductor device equipped with the following. (2) The thickness of the second substrate is greater than the depth of the first via. The semiconductor device described in (1) above. (3) The second substrate comprises a plurality of the second vias The semiconductor device described in (1) or (2) above. (4) The second substrate comprises an insulating layer through which the second via opens. A semiconductor device as described in any of (1) to (3) above. (5) The insulating layer through which the second via opens is a silicon oxide film. The semiconductor device described in (4) above. (6) The second substrate comprises a silicon layer through which the second via opens. A semiconductor device as described in any of (1) to (3) above. (7) The connecting portion of the second base is larger in diameter than the first via. A semiconductor device as described in any of (1) to (6) above. (8) The second substrate comprises a wiring layer in the path that electrically connects the connection portion and the electrode. A semiconductor device as described in any of (1) to (7) above. (9) The second substrate is provided with a bump on its lowest surface that is electrically connected to the electrode. A semiconductor device as described in any of (1) to (8) above. (10) A step of forming a first substrate by stacking a first semiconductor substrate on which a pixel region for performing photoelectric conversion is formed and a second semiconductor substrate on which a logic circuit for processing the pixel signal output from the pixel region is formed, The process involves forming an insulating film on the back surface of the first substrate, The process involves opening up the conductive material inside the first substrate to form a first opening, A step of forming an insulating film sidewall inside the first opening, A step of embedding a conductive material inside the insulating film sidewall, A step of planarizing the conductive material, A step of forming a second opening by opening a second substrate different from the first substrate, The process involves forming an insulating film on the back surface of the second substrate, The process involves embedding a conductive material in the second opening, A step of planarizing the conductive material, A step of bonding the first substrate and the second substrate together such that the conductive material in the first opening of the first substrate and the conductive material in the second opening of the second substrate are connected, A step of removing the substrate of the second substrate until a portion of the conductive material inside the second substrate is exposed. A method for manufacturing a semiconductor device comprising the above. (11) In the step of forming the first opening, the first opening is formed in at least the silicon layer. The method for manufacturing a semiconductor device as described in (10) above. (12) The process further includes a step of thinning the film thickness of the upper material of the first substrate after bonding the first substrate and the second substrate together. A method for manufacturing a semiconductor device as described in (10) or (11) above. (13) The upper material of the first substrate is silicon. The method for manufacturing a semiconductor device as described in (12) above. [Explanation of Symbols]

[0096] 10 Image sensor 11 pixels 20 Vertical drive circuit 30 Horizontal drive circuit 40 Control circuits 50-column signal processing circuit 59 Horizontal signal line 60 Output Circuit 91 First semiconductor substrate 92 Second semiconductor substrate 93 pixel area 94 Control circuits 95 Logic Circuits 100 First Substrate 110 Silicon substrate 120, 130 insulating film 140 silicon layers 141 transistors 145 Beer 150 insulating film 180 On-Chip Lens 190~192 Pad electrodes 195 Conductive materials 200 Second Substrate 230 insulating film 235, 236 Beer 240 silicon substrates 245 Beer 249 Insulating film 250 resin 260, 270 insulating film 280 Bump 290~292 Pad electrodes 293 Wiring layer 295-298 Conductive materials

Claims

1. A first substrate comprising a first semiconductor substrate having a pixel region for photoelectric conversion formed thereon and a second semiconductor substrate having a logic circuit for processing the pixel signal output from the pixel region formed thereon, and a first substrate having a first via extending from the wiring layer of the logic circuit to the back surface, A second substrate comprising a connecting portion on its surface that connects to the first via of the first substrate, and a second via that is electrically connected between the connecting portion and the electrode on the bottom surface by a conductive material. A semiconductor device equipped with the following.

2. The thickness of the second substrate is greater than the depth of the first via. The semiconductor device according to claim 1.

3. The second substrate comprises a plurality of the second vias. The semiconductor device according to claim 1.

4. The second substrate comprises an insulating layer through which the second via opens. The semiconductor device according to claim 1.

5. The insulating layer through which the second via opens is a silicon oxide film. The semiconductor device according to claim 4.

6. The second substrate comprises a silicon layer through which the second via opens. The semiconductor device according to claim 1.

7. The connecting portion of the second base is larger in diameter than the first via. The semiconductor device according to claim 1.

8. The second substrate comprises a wiring layer in the path that electrically connects the connection portion and the electrode. The semiconductor device according to claim 1.

9. The second substrate comprises a bump on its lowest surface that is electrically connected to the electrode. The semiconductor device according to claim 1.

10. A step of forming a first substrate by stacking a first semiconductor substrate on which a pixel region for photoelectric conversion is formed and a second semiconductor substrate on which a logic circuit for processing the pixel signal output from the pixel region is formed, The steps include forming an insulating film on the back surface of the first substrate, The process involves opening up the conductive material inside the first substrate to form a first opening, The process involves forming an insulating film sidewall inside the first opening, A step of embedding a conductive material inside the insulating film sidewall, A step of planarizing the conductive material, A step of forming a second opening by opening a second substrate different from the first substrate, The process involves forming an insulating film on the back surface of the second substrate, The process involves embedding a conductive material in the second opening, A step of planarizing the conductive material, A step of bonding the first substrate and the second substrate together such that the conductive material in the first opening of the first substrate and the conductive material in the second opening of the second substrate are connected, A step of removing the substrate of the second substrate until a portion of the conductive material inside the second substrate is exposed. A method for manufacturing a semiconductor device comprising the above.

11. In the step of forming the first opening, the first opening is formed in at least the silicon layer. A method for manufacturing a semiconductor device according to claim 10.

12. The process further includes a step of thinning the film thickness of the upper material of the first substrate after bonding the first substrate and the second substrate together. A method for manufacturing a semiconductor device according to claim 10.

13. The upper material of the first substrate is silicon. A method for manufacturing a semiconductor device according to claim 12.

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