Transistors and display devices

Abstract

To provide a transistor whose characteristic deterioration due to stray light is reduced.SOLUTION: A transistor includes a first insulator, a second insulator on the first insulator, metal oxide on the second insulator, a first conductor and a second conductor on the metal oxide, a third insulator on the first insulator, the second insulator, the metal oxide, the first conductor, and the second conductor, a fourth insulator on the metal oxide, a fifth insulator on the fourth insulator, and a third conductor on the fifth insulator. The third insulator includes an opening overlapping with a region between the first conductor and the second conductor. The fourth insulator, the fifth insulator, and the third conductor exist in an opening. The metal oxide has a bandgap of 3.3 eV or more. The transistor has a Vsh of -0.3 V or more.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a display device, and electronic equipment. Another aspect of the present invention relates to a method for manufacturing a transistor, a semiconductor device, and a display device. Another aspect of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, there has been a growing demand for higher resolution display panels. Examples of devices requiring high-resolution display panels include smartphones, tablet devices, and notebook computers. Furthermore, stationary display devices such as television sets and monitors are also demanding higher resolutions. Among the devices requiring the highest level of resolution are those used for virtual reality (VR) and augmented reality (AR).

[0005] Furthermore, typical examples of display devices applicable to display panels include liquid crystal displays, organic EL (Electro Luminescence) elements, light-emitting devices equipped with light-emitting elements such as LEDs, and electronic paper that displays information using electrophoretic methods.

[0006] While semiconductor materials such as silicon are mainly used as transistors in these display devices, there is growing interest in the technology of using metal oxides that exhibit semiconductor properties as transistors instead of semiconductor materials such as silicon. For example, Patent Documents 1 and 2 disclose a technology for using transistors with zinc oxide or In-Ga-Zn oxide as the semiconductor layer in the pixels of a display device. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2007-96055 [Patent Document 2] Japanese Patent Publication No. 2007-123861 [Overview of the project] [Problems that the invention aims to solve]

[0008] Transistors used in display devices and the like require high reliability. For example, some of the light emitted by the light-emitting elements of a display device (stray light) may enter the transistor. In this case, the stray light can degrade the transistor's characteristics, which can negatively affect the display of images.

[0009] One aspect of the present invention aims to provide a transistor in which characteristic degradation due to stray light is reduced. Another aspect of the present invention aims to provide a display device in which the degradation of transistor characteristics due to stray light is reduced. Another aspect of the present invention aims to provide a display device in which pixel operation is stable. Another aspect of the present invention aims to provide a semiconductor device in which there is little variation in transistor characteristics. Another aspect of the present invention aims to provide a semiconductor device in which there is good electrical characteristics. Another aspect of the present invention aims to provide a semiconductor device in which there is good reliability. Another aspect of the present invention aims to provide a semiconductor device in which miniaturization and high integration are possible. Another aspect of the present invention aims to provide a semiconductor device in which there is low power consumption.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0011] One aspect of the present invention is a transistor having a metal oxide in a channel-forming region. The transistor comprises a first insulator, a second insulator on the first insulator, a metal oxide on the second insulator, a first conductor and a second conductor on the metal oxide, a third insulator on the first insulator, the second insulator, the metal oxide, the first conductor and the second conductor, a fourth insulator on the metal oxide, a fifth insulator on the fourth insulator, and a third conductor on the fifth insulator. The third insulator is superimposed on the region between the first conductor and the second conductor, forming an opening. The fourth insulator, the fifth insulator and the third conductor are located within the opening. The metal oxide has a bandgap of 3.3 eV or more. The transistor has a Vsh of -0.3 V or more.

[0012] In the above transistor, the metal oxide preferably contains In, Ga, and Zn, and the atomic ratio of In, Ga, and Zn is preferably In:Ga:Zn = 2:6:5 or close to it.

[0013] Furthermore, in the above transistor, the fifth insulator contains silicon and oxygen, and the fifth insulator has a nitrogen concentration of 5 × 10¹⁶ obtained by SIMS. 19 atoms / cm 3 It is preferable to have the following regions:

[0014] Another aspect of the present invention is a display device having the above-mentioned transistor and a light-emitting element electrically connected to the transistor. The light-emitting element has a lower electrode, an upper electrode, and a light-emitting layer provided between the lower electrode and the upper electrode. When the light-emitting element is observed in cross-section, the side surface of the lower electrode and the side surface of the light-emitting layer have a region that coincides or substantially coincides.

[0015] In the above-described display device, an insulator is provided between the light-emitting element and adjacent light-emitting elements, and it is preferable that the insulator is made of either an inorganic material or an organic material, or both.

[0016] Another aspect of the present invention is a display device having first to fourth wirings, a light-emitting element, a first capacitor, a second capacitor, and first to fourth transistors. The first transistor has one source and drain electrically connected to the first wiring, the other source and drain electrically connected to one electrode of the first capacitor, and its gate electrically connected to the second wiring. The second transistor has one source and drain electrically connected to the anode of the light-emitting element, the other source and drain electrically connected to the third wiring, and its gate electrically connected to one electrode of the first capacitor. The third transistor has one source and drain electrically connected to the fourth wiring, and the other source and drain electrically connected to the anode of the light-emitting element. The fourth transistor has one source and drain electrically connected to the fourth wiring, the other source and drain electrically connected to one electrode of the first capacitor. The first capacitor has its other electrode electrically connected to the anode of the light-emitting element, and the second capacitor has one electrode electrically connected to one electrode of the first capacitor and its other electrode electrically connected to the third wiring. The first transistor has a metal oxide in its channel-forming region. For the first transistor, Vsh is -0.3V or higher.

[0017] In the above-described display device, the metal oxide comprises In, Ga, and Zn, and the atomic ratio of In, Ga, and Zn is preferably In:Ga:Zn = 2:6:5 or close to it. [Effects of the Invention]

[0018] According to one aspect of the present invention, a transistor with reduced characteristic degradation due to stray light can be provided. Furthermore, according to one aspect of the present invention, a display device with reduced transistor characteristic degradation due to stray light can be provided. Furthermore, according to one aspect of the present invention, a display device with stable pixel operation can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device that can be miniaturized and highly integrated can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0019] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing]

[0020] [Figure 1] Figure 1(A) is a top view of a semiconductor device according to one embodiment of the present invention. Figures 1(B) to 1(D) are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 2] Figures 2(A) and 2(B) are density of states diagrams obtained by calculation. [Figure 3] Figures 3(A) to 3(D) show the calculation model shown in Embodiment 1. [Figure 4] Figure 4 is a diagram illustrating the transition levels. [Figure 5] Figure 5 shows the calculation model shown in Embodiment 1. [Figure 6] Figures 6(A) and 6(B) are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 7]Figure 7(A) is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 7(B) to 7(D) are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 8] Figure 8(A) is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 8(B) to 8(D) are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 9] Figure 9(A) is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 9(B) to 9(D) are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 10] Figure 10(A) is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 10(B) to 10(D) are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 11] Figure 11(A) is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 11(B) to 11(D) are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 12] Figure 12(A) is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 12(B) to 12(D) are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 13] Figure 13(A) is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 13(B) to 13(D) are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 14] Figure 14(A) is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 14(B) to 14(D) are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 15] Figure 15(A) is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 15(B) to 15(D) are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 16] This is a top view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 17] This is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 18] This is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 19] This is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 20] Figure 20(A) is a top view of a semiconductor device according to one embodiment of the present invention. Figures 20(B) to 20(D) are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 21] Figure 21(A) is a plan view of a semiconductor device according to one aspect of the present invention. Figures 21(B) and 21(C) are cross-sectional views of a semiconductor device according to one aspect of the present invention. [Figure 22] Figures 22(A) and 22(B) are perspective views showing an example of a display module. [Figure 23] Figure 23 is a cross-sectional view showing an example of a display device. [Figure 24] Figure 24 is a cross-sectional view showing an example of a display device. [Figure 25] Figures 25(A) to 25(D) are circuit diagrams showing examples of display device configurations. [Figure 26] Figures 26(A) to 26(D) are circuit diagrams showing examples of display device configurations. [Figure 27] Figures 27(A) to 27(D) show examples of the configuration of a light-emitting element. [Figure 28] Figures 28(A) and 28(B) show examples of electronic devices. [Figure 29] Figures 29(A) to 29(D) show examples of electronic devices. [Figure 30] Figures 30(A) to 30(F) show examples of electronic devices. [Figure 31] Figures 31(A) through 31(F) show examples of electronic devices. [Figure 32]Figure 32(A) is a block diagram showing an example of the configuration of a storage device according to one aspect of the present invention. Figure 32(B) is a perspective view showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 33] Figures 33(A) to 33(H) are circuit diagrams showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 34] Figure 34 is a schematic cross-sectional diagram illustrating the configuration of a transistor according to an embodiment. [Figure 35] Figure 35 illustrates the results of the photo-negative bias degradation measurement of a transistor according to the embodiment. [Figure 36] Figure 36 illustrates the results of CPM measurement in an example. [Figure 37] Figures 37(A) to 37(C) illustrate the results of SIMS analysis in the examples. [Modes for carrying out the invention]

[0021] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the following embodiments.

[0022] Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. Also, drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown. For example, in actual manufacturing processes, layers or resist masks may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. Additionally, in drawings, the same reference numerals may be used across different drawings for identical parts or parts with similar functions, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the hatch patterns may be the same, and no specific reference numeral may be assigned.

[0023] Furthermore, in particular, in top views (also called "plan views") or perspective views, descriptions of some components may be omitted to facilitate understanding of the invention. Also, descriptions of some hidden lines may be omitted.

[0024] Furthermore, the ordinal numbers used in this specification, such as "first," "second," etc., are for convenience only and do not indicate the order of processes or stacking. Therefore, for example, "first" can be replaced with "second" or "third," etc., as appropriate in the explanation. Also, the ordinal numbers described in this specification may not be the same as the ordinal numbers used to specify an aspect of the present invention.

[0025] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0026] For example, if it is explicitly stated in this specification that X and Y are connected, then the disclosure in this specification includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, it is not limited to predetermined connection relationships, such as those shown in the figures or text, but also includes connection relationships other than those shown in the figures or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter also referred to as the channel-forming region), and current can flow between the source and the drain through the channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0028] Furthermore, the functions of the source and drain may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification.

[0029] The channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or in the channel formation region, as seen in a top view of a transistor. It should be noted that the channel length is not necessarily the same in all regions of a single transistor. That is, the channel length of a single transistor may not be a single fixed value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0030] Channel width refers to the length of the channel formation region perpendicular to the channel length direction, for example, in a top view of a transistor, where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or within the channel formation region. Note that the channel width is not necessarily the same across all regions in a single transistor. That is, the channel width of a single transistor may not be a single fixed value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value within the channel formation region.

[0031] In this specification, depending on the transistor structure, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and this effect may not be negligible. For example, in a miniature transistor where the gate electrode covers the side surface of the semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width will be larger than the apparent channel width.

[0032] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires the assumption that the semiconductor shape is known. Therefore, if the semiconductor shape is not precisely known, it is difficult to accurately measure the effective channel width.

[0033] In this specification, when simply referred to as "channel width," it may refer to the apparent channel width. Alternatively, when simply referred to as "channel width," it may refer to the effective channel width. Note that channel length, channel width, effective channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0034] Impurities in semiconductors refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor or a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O (Also known as an oxygen vacancy) may form.

[0035] In this specification, silicon oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0036] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer."

[0037] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0038] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0039] Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the drain current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ -18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0040] Furthermore, if upper and lower numerical limits are specified in this specification, configurations in which the upper and lower numerical limits can be freely combined are also disclosed.

[0041] In this specification, elements fabricated using a metal mask or an FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as elements with an MM (metal mask) structure. In addition, in this specification, elements fabricated without using a metal mask or an FMM may be referred to as elements with an MML (metal maskless) structure.

[0042] In this specification, a structure in which different light-emitting layers are created or painted for each color of light-emitting element (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. Also, in this specification, a light-emitting element capable of emitting white light may be referred to as a white light-emitting element. A white light-emitting element can be combined with a colored layer (for example, a color filter) to create a light-emitting element capable of full-color display.

[0043] Furthermore, light-emitting elements can be broadly classified into single structures and tandem structures. A single-structure element has one light-emitting unit between a pair of electrodes, and it is preferable that this light-emitting unit includes one or more light-emitting layers. To obtain white light emission, one should select light-emitting layers such that the light emitted from each of the two or more layers is complementary in color. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a configuration that emits white light as a whole can be obtained. The same applies to light-emitting elements having three or more light-emitting layers.

[0044] In a tandem structure, it is preferable that the element has two or more light-emitting units between a pair of electrodes, and each light-emitting unit includes one or more light-emitting layers. To obtain white light emission, the light from the light-emitting layers of the multiple light-emitting units is combined to produce white light emission. The configuration for obtaining white light emission is the same as that for a single structure. In a tandem structure, it is preferable to provide an intermediate layer, such as a charge-generating layer, between the multiple light-emitting units.

[0045] Furthermore, when comparing the aforementioned white light-emitting elements (single or tandem structure) with SBS structure light-emitting elements, SBS structure light-emitting elements can consume less power than white light-emitting elements. If you want to keep power consumption low, it is preferable to use SBS structure light-emitting elements. On the other hand, white light-emitting elements are preferable because their manufacturing process is simpler than that of SBS structure light-emitting elements, which can lead to lower manufacturing costs or higher manufacturing yields.

[0046] (Embodiment 1) In this embodiment, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention, and a method for manufacturing the same, will be described using Figures 1(A) to 21(C).

[0047] <Example of semiconductor device configuration> The configuration of a semiconductor device having a transistor 200 will be explained using Figures 1(A) to 1(D). Figures 1(A) to 1(D) are top views and cross-sectional views of a semiconductor device having a transistor 200. Figure 1(A) is a top view of the semiconductor device. Figures 1(B) to 1(D) are cross-sectional views of the same semiconductor device. Here, Figure 1(B) is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 1(A), and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 1(C) is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 1(A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Figure 1(D) is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 1(A). Note that in the top view of Figure 1(A), some elements have been omitted for clarity.

[0048] A semiconductor device according to one aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, and an insulator 285 on the insulator 283. The insulators 212, 214, 280, 282, 283, and 285 function as interlayer films. The device also includes conductors 240a and 240b that are electrically connected to the transistor 200 and function as plugs. An insulator 241a is provided in contact with the side surface of conductor 240a, and an insulator 241b is provided in contact with the side surface of conductor 240b. Furthermore, a conductor 246a is provided on the insulator 285 and on the conductor 240a, electrically connected to the conductor 240a and functioning as wiring, and a conductor 246b is provided on the insulator 285 and on the conductor 240b, electrically connected to the conductor 240b and functioning as wiring.

[0049] In the following, conductors 240a and 240b may be collectively referred to as conductor 240. Similarly, insulators 241a and 241b may be collectively referred to as insulator 241. Furthermore, conductors 246a and 246b may be collectively referred to as conductor 246.

[0050] Insulator 241a is provided in contact with the inner wall of the opening of insulator 280, insulator 282, insulator 283, and insulator 285, and conductor 240a is provided in contact with the side surface of insulator 241a. Insulator 241b is provided in contact with the inner wall of the opening of insulator 280, insulator 282, insulator 283, and insulator 285, and conductor 240b is provided in contact with the side surface of insulator 241b. Note that insulator 241a and insulator 241b each have a structure in which a first insulator is provided in contact with the inner wall of the opening, and a second insulator is provided further inside. In addition, conductor 240a (conductor 240b) has a structure in which a first conductor is provided in contact with the side surface of insulator 241a (insulator 241b), and a second conductor is provided further inside. Here, the height of the upper surface of the conductor 240a (conductor 240b) and the height of the upper surface of the insulator 285 in the region overlapping with the conductor 246a (conductor 246b) can be made to be approximately the same.

[0051] In one embodiment of the present invention, a semiconductor device is shown in which a first insulator and a second insulator of insulator 241a (insulator 241b) are stacked, but the present invention is not limited thereto. For example, the insulator 241a (insulator 241b) may be provided as a single layer or as a stacked structure of three or more layers. Also, in the transistor 200, a configuration is shown in which a first conductor and a second conductor of conductor 240a (conductor 240b) are stacked, but the present invention is not limited thereto. For example, the conductor 240a (conductor 240b) may be provided as a single layer or as a stacked structure of three or more layers. When a structure has a stacked structure, ordinal numbers may be assigned to distinguish them according to the order of formation.

[0052] As shown in Figures 1(A) to 1(D), the transistor 200 comprises an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230 on the insulator 224, a conductor 242a on the oxide 230, an insulator 271a on the conductor 242a, and a conductor 242 on the oxide 230. b, an insulator 271b on the conductor 242b, an insulator 252 on the oxide 230, an insulator 250 on the insulator 252, an insulator 254 on the insulator 250, a conductor 260 (conductors 260a and 260b) located on the insulator 254 and overlapping with a part of the oxide 230, and an insulator 275 arranged on the insulator 222, the insulator 224, the oxide 230, the conductor 242a, the conductor 242b, the insulator 271a, and the insulator 271b. Here, as shown in Figures 1(B) and 1(C), insulator 252 is in contact with the top surface of insulator 222, the side surface of insulator 224, the side and top surface of oxide 230, the side surface of conductor 242a, the side surface of conductor 242b, the side surface of insulator 271a, the side surface of insulator 271b, the side surface of insulator 275, the side surface of insulator 280, and the bottom surface of insulator 250. The top surface of conductor 260 is positioned so as to be roughly the same height as the top of insulator 254, the top of insulator 250, the top of insulator 252, and the top surface of insulator 280. Insulator 282 is in contact with at least a portion of the top surfaces of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280.

[0053] In this specification, "approximately matching heights" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, in the manufacturing process of semiconductor devices, planarization (typically CMP) may expose the surfaces of one or more layers. In this case, the surfaces subjected to CMP will have a configuration in which the heights from the reference surface are equal. Furthermore, "approximately matching heights" also includes cases where the heights are identical. However, the heights of multiple layers may differ depending on the processing apparatus, processing method, or material of the surface subjected to CMP. In this specification, this case is also treated as "approximately matching heights." For example, if there are two layers with different heights (here referred to as a first layer and a second layer) with respect to a reference surface, the difference between the height of the top surface of the first layer and the height of the top surface of the second layer being 20 nm or less is also considered "approximately matching heights."

[0054] In the following, conductors 242a and 242b may be collectively referred to as conductor 242. Also, insulators 271a and 271b may be collectively referred to as insulator 271.

[0055] Insulators 280 and 275 are provided with openings that reach the oxide 230. Insulators 252, 250, 254, and 260 are arranged within these openings. In addition, in the channel length direction of transistor 200, conductors 260, 252, 250, and 254 are provided between insulators 271a and conductor 242a, and between insulators 271b and conductor 242b. Insulator 254 has a region in contact with the side surface of conductor 260 and a region in contact with the bottom surface of conductor 260.

[0056] Although the transistor 200 is shown as having a single layer of oxide 230, the present invention is not limited to this configuration. For example, the oxide 230 may be configured as a stacked structure of two or more layers.

[0057] Conductor 260 functions as the first gate (also called the top gate) electrode, and conductor 205 functions as the second gate (also called the back gate) electrode. Insulators 252, 250, and 254 function as the first gate insulators, and insulators 222 and 224 function as the second gate insulators. Note that gate insulators are sometimes called gate insulating layers or gate insulating films. Conductor 242a functions as either the source or the drain, and conductor 242b functions as either the source or the drain. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region.

[0058] In transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor in the oxide 230 including the channel formation region.

[0059] When transistor 200 is used in the pixel circuit of a display device, some of the light emitted from the light-emitting element of the display device (stray light) may enter the transistor 200. In this case, the stray light may degrade the transistor's characteristics and adversely affect the pixel operation.

[0060] The degradation of transistor characteristics due to light is estimated as follows: First, when light is shone on a metal oxide that functions as a semiconductor in a transistor, electrons (carriers) present in the valence band or deep energy levels of the metal oxide are excited to the conduction band. Here, the deep energy levels of the metal oxide are presumed to be energy levels originating from oxygen vacancies in the metal oxide. Next, the electron excitation to the conduction band of the metal oxide generates holes in the valence band or deep energy levels of the metal oxide. When a negative bias is applied between the gate and source, holes accumulate at and near the interface between the metal oxide and the gate insulator. At this time, if a defect level exists at or near the interface, the holes are trapped in that defect level. As a result, the threshold voltage or shift voltage (Vsh) shifts in the negative direction. Consequently, the transistor becomes normally-on, which can adversely affect pixel operation.

[0061] Here, the amount of degradation of transistor characteristics due to stray light can be evaluated, for example, using the change in the transistor's threshold voltage or the change in the shift voltage (Vsh), which is measured in the NBTIS (Negative Bias Temperature Illumination Stress) test of the transistor. The shift voltage (Vsh) is defined as the Vg at which the tangent line at the point where the slope of the drain current (Id)-gate voltage (Vg) curve is maximum intersects the straight line where Id = 1 pA. In the NBTIS test, degradation that changes the transistor's threshold voltage or degradation that changes Vsh is sometimes called photo-negative bias degradation.

[0062] Therefore, it is preferable that the transistor 200 used in the pixel circuit of the display device has reduced effects of stray light. For example, it is preferable that the transistor 200 used in the pixel circuit of the display device has reduced degradation of transistor characteristics due to stray light. Specifically, it is preferable that the transistor 200 used in the pixel circuit of the display device has high resistance to NBTIS testing (reduced degradation of negative optical bias).

[0063] Therefore, it is more preferable to use a metal oxide with a band gap of 3.1 eV or more for the semiconductor function of transistor 200, and even more preferable to use one with a band gap of 3.3 eV or more. The energy of light with a wavelength of 400 nm or more is 3.1 eV or less. In other words, even if light with a wavelength of 400 nm or more is incident on the metal oxide, electrons in the valence band are less likely to be excited to the conduction band. Therefore, by using a metal oxide with a larger band gap in the channel formation region of the transistor, it is possible to improve resistance to NBTIS testing. In other words, by using a metal oxide with a larger band gap in the channel formation region of the transistor, the effects of stray light can be reduced without providing a light-shielding layer, and the degradation of transistor characteristics can be suppressed.

[0064] The band gap of metal oxides can be evaluated using one or more methods such as spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS) or ESCA (Electron Spectroscopy for Chemical Analysis), and X-ray absorption fine structure (XAFS).

[0065] As oxide 230, it is preferable to use a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt). In particular, element M is preferably one or more selected from gallium, aluminum, yttrium, and tin, with gallium being more preferred.

[0066] More specifically, as oxide 230, metal oxides with an atomic ratio of In:M:Zn = 2:6:5 or nearby, metal oxides with an atomic ratio of In:M:Zn = 1:3:4 or nearby, metal oxides with an atomic ratio of In:M:Zn = 1:1:1 or nearby, or metal oxides with an atomic ratio of In:M:Zn = 1:4:5 or nearby can be used. Note that nearby compositions include a range of ±30% of the desired atomic ratio. Furthermore, when depositing metal oxide films by sputtering, the above atomic ratios are not limited to the atomic ratios of the deposited metal oxide film, but may also be the atomic ratios of the sputtering target used for depositing the metal oxide film.

[0067] For example, when describing a composition with an atomic ratio of In:M:Zn = 2:6:5 or close to it, it includes cases where, with an atomic ratio of In being 2, the atomic ratio of M is between 4 and 8, and the atomic ratio of Zn is between 3 and 7.5. Also, when describing a composition with an atomic ratio of In:M:Zn = 1:1:1 or close to it, it includes cases where, with an atomic ratio of In being 1, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of Zn is greater than 0.1 and 2 or less.

[0068] The composition of metal oxides can be evaluated using methods such as inductively coupled plasma mass spectrometry (ICP-MS), XPS, scanning electron microscopy (SEM)-EDX (Energy Dispersive X-ray Spectroscopy), and secondary ion mass spectrometry (SIMS).

[0069] In particular, metal oxides deposited by sputtering using an oxide target with an In:M:Zn = 1:3:4 [atomic ratio] have a band gap of approximately 3.4 eV and can be suitably used as oxide 230. Furthermore, metal oxides deposited by sputtering using an oxide target with an In:M:Zn = 1:3:4 [atomic ratio] have a composition of In:M:Zn = 2:6:5 [atomic ratio] or close to it. That is, metal oxides with a composition of In:M:Zn = 2:6:5 [atomic ratio] or close to it have a band gap of approximately 3.4 eV.

[0070] Furthermore, gallium atoms have a stronger bonding force with oxygen atoms compared to indium atoms. Therefore, by using the above-mentioned metal oxide 230 in which the atomic ratio of gallium to the main metal element is greater than or equal to the atomic ratio of indium to the main metal element, it may be possible to reduce oxygen deficiency in oxide 230.

[0071] Furthermore, holes generated in the metal oxide by light irradiation may be trapped by the negative bias at the interface between the metal oxide and the gate insulator or at defect levels present in the gate insulator, causing fluctuations in the threshold voltage or Vsh. Therefore, to suppress photo-negative bias degradation, it is preferable to reduce the defect level density in the gate insulator.

[0072] When silicon oxide or silicon oxynitride is used as the gate insulator, defect levels involved in photo-negative bias degradation include oxygen-derived defect levels and nitrogen-derived defect levels. An example of a nitrogen-derived defect level is a nitrogen atom bonded to two silicon atoms. This nitrogen atom has a dangling bond. An example of an oxygen-derived defect level is an oxygen atom bonded to one silicon atom. This oxygen atom also has a dangling bond. These dangling bonds can trap holes, causing fluctuations in the threshold voltage or Vsh. Hereafter, a nitrogen atom bonded to two silicon atoms will be referred to as N OIt may be expressed as such. Also, an oxygen atom bonded to one silicon atom may be expressed as a non-bridging oxygen hole trapping center (NBOHC).

[0073] To reduce the defect energy level derived from nitrogen, it is preferable to reduce nitrogen atoms having dangling bonds in the gate insulator. In addition, it may be difficult to quantify nitrogen atoms having dangling bonds in the gate insulator.Therefore, the amount of nitrogen atoms having dangling bonds in the gate insulator may be evaluated, for example, by the nitrogen concentration in the gate insulator. A gate insulator with a small amount of nitrogen atoms is presumed to also have a small amount of nitrogen atoms having dangling bonds.Specifically, the nitrogen concentration in the gate insulator obtained by SIMS is 2×10 20 atoms / cm 3 less than, preferably, 1×10 20 atoms / cm 3 or less, more preferably 5×10 19 atoms / cm 3 or less.

[0074] In addition, in SIMS, it is difficult to detect nitrogen atoms as single ions (N + or N - ). Therefore, nitrogen atoms in the gate insulator may be detected as cluster ions of SiN.

[0075] Also, when the gate insulator has a stacked structure of two or more layers, it is preferable to lower the nitrogen concentration of a layer containing silicon oxide or silicon oxynitride.In the transistor 200 included in the semiconductor device of FIGS. 1(A) to 1(D), each of the insulators 222, 224, 252, 250, and 254 partially functions as a gate insulator.Therefore, it is preferable to use silicon oxide or silicon oxynitride with a low nitrogen concentration for one or more of the insulators 222, 224, 252, 250, and 254.In particular, it is preferable to use silicon oxide or silicon oxynitride with a low nitrogen concentration for the insulator 250.

[0076] Silicon oxide or silicon oxynitride with a low nitrogen concentration can be formed using sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), and other methods. For example, the insulating film that becomes the insulator 250 needs to be deposited with good coverage on the bottom and sides of openings formed in the insulator 280, etc. Therefore, when silicon oxide or silicon oxynitride is used as the insulator 250, it is preferable to deposit the insulating film that becomes the insulator 250 using the CVD or ALD method. In particular, the ALD method is suitable for depositing the insulating film that becomes the insulator 250 because it has excellent step coverage and excellent thickness uniformity.

[0077] Furthermore, examples of defect levels related to photo-negative bias degradation include levels originating from defects formed by the diffusion of atoms in the gate insulator into the metal oxide, and levels originating from defects formed by the diffusion of atoms in the metal oxide into the gate insulator. For example, a defect generated by the diffusion of atoms in the metal oxide into the gate insulator is a defect in which a silicon atom in silicon oxide or silicon oxynitride is replaced by a metal atom contained in the metal oxide. If the metal oxide is an In-Ga-Zn oxide, the defect may be one in which a silicon atom is replaced by an indium atom, gallium atom, or zinc atom. In this specification, a defect in which a silicon atom is replaced by an indium atom is referred to as In Si This is written as Ga Si This is written as Zn, and the defect in which a silicon atom is replaced by a zinc atom is written as Zn Si This is how it is written.

[0078] In Si , Ga Si Zn SiTo suppress the formation of defects such as those mentioned above, it is preferable for the metal oxide to have high crystallinity. By increasing the crystallinity of the metal oxide, it is possible to suppress the diffusion of metal elements contained in the metal oxide into the gate insulator. In addition, it is possible to suppress the diffusion of atoms contained in the gate insulator (for example, silicon atoms) into the metal oxide.

[0079] As described above, the effect of stray light on the transistor 200 can be reduced without providing a light-shielding layer, and the degradation of transistor characteristics can be suppressed. Therefore, a transistor with reduced characteristic degradation due to stray light can be provided. Furthermore, by using this transistor, a display device with reduced transistor characteristic degradation due to stray light can be provided. In addition, a display device with stable pixel operation can be provided.

[0080] <Defects in gate insulators> This section explains defects in the gate insulator using calculations. In this section, the gate insulator is silicon oxide and the metal oxide is In-Ga-Zn oxide. In this case, possible defects related to photo-negative bias degradation include NBOHC and In Si , Ga Si Zn Si These are some of the shortcomings.

[0081] <<Computational Model>> First, we prepare a baseline amorphous silicon oxide model (referred to as the a-SiO2 model). The a-SiO2 model consists of 20 silicon atoms and 40 oxygen atoms.

[0082] A computational model containing one NBOHC is created by removing one silicon atom from the a-SiO2 model described above to form four NBOHCs, and then bonding one hydrogen atom to each of three of these NBOHCs. Si A computational model containing one of these is created by replacing one silicon atom in the above a-SiO2 model with an In atom. Similarly, Ga SiA computational model containing one of these elements is created by replacing one silicon atom in the a-SiO2 model with a Ga atom. Similarly, Zn Si A computational model containing one of these elements is created by replacing one silicon atom in the a-SiO2 model with a Zn atom.

[0083] <<Energy for generating defects>> In the following section, the ease with which defects are generated in gate insulators will be explained using the results of first-principles calculations. Specifically, In Si , Ga Si Zn Si The generation energies of both , and NBOHC are calculated using first-principles calculations to evaluate the ease with which defects are generated in the gate insulator.

[0084] Here, each defect (In Si , Ga Si Zn Si The formation energies of (and NBOHC) are described below. In this specification, the formation energy of a defect is calculated using the following formula. The smaller the formation energy of a defect, the easier it is for that defect to form.

[0085]

number

[0086] Here, ΔE(X Si ) is X Si This is the energy of formation of , where atom X is an In atom, a Ga atom, or a Zn atom. ΔE(NBOHC) is the energy of formation of NBOHC. E(X Si ) is X Si μ is the total energy of a computational model containing one NBOHC, and E(NBOHC) is the total energy of a computational model containing one NBOHC. E(no defect) is the total energy of a computational model without defects (a-SiO2 model). Si μ is the chemical potential of a silicon atom, and μ X μ is the chemical potential of atom X, and μ HThis is the chemical potential of a hydrogen atom.

[0087] The chemical potential μ of a silicon atom Si The chemical potential μ of atom X X , and the chemical potential μ of the hydrogen atom H This is calculated using the following formula.

[0088]

number

[0089] Here, μ O E(O2) is the chemical potential of an oxygen atom. E(O2) is the total energy of an oxygen molecule (O2), E(SiO2) is the total energy of silicon oxide, and E(X a O b ) is a metal oxide (X a O b E(H2O) is the total energy of a water molecule (H2O). If atom X is an In atom or a Ga atom, a is 2 and b is 3. If atom X is a Zn atom, a is 1 and b is 2.

[0090] The above explains the energy required for defect formation.

[0091] <<Ease of generating defects>> First, defects (In Si , Ga Si Zn Si Atomic relaxation calculations were performed on a computational model that included one of the following: , and NBOHC. The calculation conditions were as follows:

[0092] For first-principles calculations, the Vienna Ab-initio Simulation Package (VASP) was used. The Generalized Gradient Approximation (GGA) of the Perdew-Burke-Ernzerhof (PBE) type was used for the exchange-correlation potential, and the Projector Augmented Wave (PAW) method was used for the ion potential. The cutoff energy was set to 800 eV, and a grid consisting only of Γ points was used for the k-points. The overall charge state of the calculation model was assumed to be neutral.

[0093] The generation energy for each defect was calculated using the formula described above. The generation energy for each defect is shown in Table 1.

[0094] [Table 1]

[0095] Table 1 shows that the formation energy of NBOHC is the lowest, suggesting that NBOHC is easily formed. Also, In Si , Ga Si , and Zn Si In Zn Si The energy of production is, In Si , and Ga Si The result was higher than the formation energy of Zn. Si In Si , and Ga Si It is presumed to be less likely to be generated than [another type of].

[0096] <<Density of State Diagram>> Figure 2(A) shows In Si Figure 2(A) shows the density of states diagram obtained after performing atomic relaxation calculations on a computational model that includes one such model. In Figure 2(A), the horizontal axis represents energy [eV], and the vertical axis represents density of states (DOS) [arbitrary units (arb.unit)]. Note that in Figure 2(A), the upper end of the valence band was adjusted so that the horizontal axis is 0 eV.

[0097] Figure 2(A) shows that a deep defect level (level 1 in Figure 2(A)) exists above the upper end of the valence band. This suggests that this defect level traps holes. Additionally, a level (level 2 in Figure 2(A)) exists near the lower end of the conduction band. This level corresponds to the s orbital of the In atom and suggests that it traps electrons.

[0098] Figure 2(B) shows Ga Si The density of states diagram obtained after performing atomic relaxation calculations for a computational model containing one element is shown. In Figure 2(B), the horizontal axis represents energy [eV], and the vertical axis represents density of states (DOS) [arbitrary units (arb.unit)]. Note that in Figure 2(B), the upper end of the valence band was adjusted so that the horizontal axis is 0 eV.

[0099] Figure 2(B) shows that a defect level (the level shown in Figure 2(B)) exists above the upper end of the valence band. This suggests that the defect level traps holes.

[0100] <<Defect Transition Level>> Depending on the type of defect, there may be energy levels (also called transition levels) within the energy gap that involve transitions to different charge states. The depth of these levels and the position of the Fermi level can cause carrier capture or release. Therefore, in this section, we will calculate the defect transition levels using first-principles calculations.

[0101] The defects used to calculate the transition level are defects that can form in the gate insulator, specifically NBOHC, In Si , Ga Si , and Zn Si Therefore, in the transition level calculation, the above calculation model, which includes one NBOHC, In Si A computational model containing one Ga Si A computational model containing one of the following, and Zn Si A computational model containing one of the following is used. The computational models used for calculating transition levels are shown in Figures 3(A) to 3(D). Figure 3(A) is a computational model containing one NBOHC, and Figure 3(B) is InSi This is a computational model that includes one Ga, and Figure 3(C) shows Ga Si This is a computational model that includes one such model, and Figure 3(D) shows Zn Si This is a computational model that includes one of the following. Si , Ga Si , and Zn Si These are defects formed when one Si atom in the gate insulator is replaced by an atom other than Si (In atom, Ga atom, and Zn atom). Si , Ga Si , and Zn Si This can also be called a substitution defect.

[0102] The transition level of a defect is calculated from the creation energy of a charged defect. Creation energy E of a defect with charge q form (defect, q) is calculated using the following formula.

[0103]

number

[0104] Here, E(defect,q) is the energy of the calculation model including a defect of charge q, and E(no defect) is the energy of the calculation model without defects (a-SiO2 model). Atom X1 represents the atom whose number of atoms changed when the defect was created, and n X1 n represents the number of atoms X1 that increased or decreased. Note that if the number of atoms X1 increases, n X1 The sign of is positive, and when the number of atoms X1 decreases, n X1 The sign of μ is negative. X1 ε is the chemical potential of atom X1. VBM E is the energy at the top of the valence band. F E is the energy of the Fermi level relative to the top of the valence band. F The Fermi level, at 0 eV, is located at the top of the valence band. Hereafter, the energy of the Fermi level may be referred to as the Fermi energy.

[0105] Furthermore, ΔV is an electrostatic energy correction and is expressed by the following equation. Because a finite-sized computational model is used when calculating the defect transition level, the electrostatic potential due to the charge does not converge even at positions far from the defect. Therefore, the electrostatic potential V(q,r) at atomic position r of the computational model including a defect with charge q, and the electrostatic potential V(0,r) at atomic position r of the computational model not including a charge-neutral defect are calculated, and the average difference between V(q,r) and V(0,r) at positions far from the defect (r=far) is taken as ΔV.

[0106]

number

[0107] The defect transition level ε(q / q') is calculated using the following formula.

[0108]

number

[0109] The ε(q / q') obtained from the above equation represents the position of the defect's transition level when the upper end of the valence band is set to 0.0 eV. In other words, the value obtained by subtracting the defect's transition level from the energy gap represents the position of the defect's transition level relative to the lower end of the conduction band. Furthermore, if the Fermi level is located closer to the valence band than ε(q / q'), the defect is stable in charge state q, and if the Fermi level is located closer to the conduction band than ε(q / q'), the defect is stable in charge state q'.

[0110] VASP was used for first-principles calculations. The Heyd-Scuseria-Ernzerhof (HSE) functional was used as the hybrid functional, the PBE-type GGA was used for the exchange-correlation potential, and the PAW method was used for the ion potential. The cutoff energy was set to 800 eV, and the number of k-point grids was 3×3×3. The screening parameter for the HSE functional was set to 2 nm. -1The ratio of the exchange term of Hartree-Fock was set to 0.25.

[0111] The transition levels of each defect calculated this time are shown in Fig. 4. In Fig. 4, the vertical axis is the Fermi energy [eV]. Also, in Fig. 4, in order from the left, the transition levels of NBOHC, In Si 's transition level, Ga Si 's transition level, Zn Si 's transition level are shown. In Fig. 4, the position where the Fermi energy is 0 eV represents the top of the valence band (VBM), and the position where the Fermi energy is 6.89 eV represents the bottom of the conduction band (CBM). Also, the transition level ε(2 / 0) is shown by a solid line, the transition level ε(1 / 0) is shown by a dashed line, the transition level ε(0 / -1) is shown by a dotted-dashed line, and the transition level ε(-1 / -2) is shown by a dotted line. In addition, the values of the transition levels of each defect are illustrated in Fig. 4.

[0112] From Fig. 4, in NBOHC, the transition level ε(2 / 0) exists at a position 0.51 eV from the top of the valence band. Also, in In Si , the transition level ε(2 / 0) exists at a position 0.12 eV from the top of the valence band. Also, in Ga Si , the transition level ε(2 / 0) exists at a position 0.32 eV from the top of the valence band. Since the transition levels ε(2 / 0) of NBOHC, In Si , and Ga Si are located near the top of the valence band, they are estimated to be hole trap levels. That is, the hole trap levels derived from In Si and the hole trap levels derived from Ga Si are located closer to the valence band side than the hole trap levels derived from NBOHC. Therefore, In Si and Ga Si generated in the gate insulator are presumed to exhibit hole trapping properties.

[0113] On the other hand, in Zn Si , the transition level ε(1 / 0) exists at a position 1.04 eV from the top of the valence band. In addition, in Zn SiThe transition level ε(1 / 0) is located near the top of the valence band, and is therefore presumed to be a Hole trap level. Si The originating Hole Trap level is the Hole Trap level from NBOHC, In Si The originating Hole Trap level, and Ga Si Because it is located on the conduction band side of the originating Hole trap level, Zn Si NBOHC, In Si , and Ga Si It is presumed to have lower hole-trapping properties.

[0114] Therefore, when using In-Ga-Zn oxide as an oxide semiconductor, defects that can be generated by the diffusion of In and Ga into the gate insulator (In Si and Ga Si It is presumed that this can form a Hole trap level and become a factor in the degradation of the negative optical bias.

[0115] <<Diffusion of metal atoms in metal oxides into gate insulators>> This section explains the diffusion of metal atoms from a metal oxide into a gate insulator using calculations. Note that the diffusion of metal atoms from a metal oxide into a gate insulator can be rephrased as the detachment of metal atoms from the metal oxide. Furthermore, in this section, silicon oxide is used as the gate insulator and In-Ga-Zn oxide as the metal oxide.

[0116] Oxygen vacancies (V) are defects in in-Ga-Zn oxide. O ) are cited as examples. Furthermore, it is presumed that metal atoms near oxygen vacancies are more likely to detach from the metal oxide than metal atoms located farther away from the oxygen vacancies. In other words, we assume that the metal atoms that diffuse from the metal oxide to the gate insulator are the metal atoms near the oxygen vacancies. Therefore, V O The desorption energy of nearby metal atoms is calculated using first-principles calculations.

[0117] Here, we will explain the computational model used in first-principles calculations. First, we prepare a model of a single-crystal In-Ga-Zn oxide. Hereafter, the model of a single-crystal In-Ga-Zn oxide will be referred to as the sc-IGZO model. The composition of the sc-IGZO model is In:Ga:Zn:O = 1:1:1:4 [atomic ratio]. The sc-IGZO model is composed of 112 atoms.

[0118] Next, one oxygen atom is removed from the sc-IGZO model. The oxygen atom to be removed is the oxygen atom bonded to indium and zinc. The sc-IGZO model after the removal of this oxygen atom has an oxygen deficiency. Hereafter, this model may be referred to as the sc-IGZO model with an oxygen deficiency. The sc-IGZO model with an oxygen deficiency is shown in Figure 5. In Figure 5, V O This indicates oxygen deficiency, and In-1 is shown in Figure 5. O This indicates one of the adjacent indium atoms, and In-2 is shown in Figure 5. O This shows another indium atom adjacent to it, and Zn is shown in Figure 5. O The following diagrams show adjacent zinc atoms: Ga-1 represents one of the gallium atoms adjacent to Zn shown in Figure 5, and Ga-2 represents another gallium atom adjacent to Zn shown in Figure 5.

[0119] Next, for the sc-IGZO model containing oxygen vacancies, we prepare models in which In-1, In-2, Ga-1, Ga-2, or Zn are removed, as shown in Figure 5. In other words, we prepare sc-IGZO models containing oxygen vacancies with In-1 removed, sc-IGZO models containing oxygen vacancies with In-2 removed, sc-IGZO models containing oxygen vacancies with Ga-1 removed, sc-IGZO models containing oxygen vacancies with Ga-2 removed, and sc-IGZO models containing oxygen vacancies with Zn removed.

[0120] The desorption energy of metal atom X2 (where X2 is In-1, In-2, Ga-1, Ga-2, or Zn) was calculated using the five calculation models described above. The desorption energy ΔE(V) of metal atom X2 was calculated. O,X2The following formula was used to calculate the detachment energy ΔE(V) of the metal atom X2. O,X2 The smaller the value of ), the easier it is for the metal atom X2 to be removed.

[0121]

number

[0122] Here, ΔE(V O,X2 ) is the elimination energy of metal atom X2, where E(V O,X2 ) is the total energy of the sc-IGZO model including the oxygen vacancy obtained by removing metal atom X2, and E(V O ) is the total energy of the sc-IGZO model including oxygen deficiency, μ X2 This is the chemical potential of metal atom X2.

[0123] Table 2 shows the calculated results of the desorption energy of metal atom X2.

[0124] [Table 2]

[0125] From Table 2, V O It is presumed that the adjacent zinc atom (Zn shown in Figure 5) is easily eliminated. Also, since the elimination energy of In-1 is negative and the elimination energy of In-2 is also small, V O It is presumed that adjacent indium atoms are also easily eliminated. On the other hand, the elimination energy of Ga-1 is smaller than that of Ga-2, with the elimination energy of Ga-1 being 1.29 eV. Therefore, V O It is presumed that zinc and indium atoms are more likely to detach from the surrounding area than gallium atoms. In other words, when using In-Ga-Zn oxide as the metal oxide, it is suggested that zinc and indium atoms are more likely to diffuse into the gate insulator.

[0126] As mentioned above, it is suggested that zinc atoms and indium atoms, among the metal atoms contained in In-Ga-Zn oxide, readily diffuse into the gate insulator. Substitutional defects that may be generated when zinc atoms and indium atoms diffuse into the gate insulator include Zn Si and In Si This is one example. Therefore, Zn Si and In Si The energy of formation of Zn is calculated. Si and In Si The method for calculating the formation energy of Zn can be found in the section on "Defect Formation Energy" above. Si and In Si The calculation conditions for determining the generation energy can be found by referring to the information provided in the previous section on <<defect transition levels>>.

[0127] Zn Si and In Si The formation energy is shown in Table 3. Here, the metal atoms contained in the metal oxide that diffuse into the gate insulator are called diffusing atomic species. When the diffusing atomic species is an In atom, the defect formed after the diffusion of the In atom is In Si Furthermore, if the diffusing atom species is a Zn atom, the defect formed after the diffusion of the Zn atom is Zn Si That is the case.

[0128] [Table 3]

[0129] Tables 2 and 3 show that zinc atoms are easily removed from metal oxides, but substitution defects are Zn Si It is presumed that it is difficult to generate. On the other hand, although indium atoms are less likely to detach from metal oxides than zinc atoms, they are more likely to generate substitutional defects than zinc atoms, so it is presumed that indium atoms diffuse easily into gate insulators.

[0130] The above is an explanation of defects in gate insulators.

[0131] The following describes the details of the semiconductor device configuration shown in Figures 1(A) to 1(D).

[0132] The oxide 230 is preferably crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 230.

[0133] CAAC-OS is a metal oxide with a highly crystalline, dense structure and low levels of impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization (e.g., between 400°C and 600°C), the CAAC-OS can be made to have an even more crystalline and dense structure. By increasing the density of CAAC-OS in this way, the diffusion of impurities or oxygen within the CAAC-OS can be further reduced.

[0134] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230, the extraction of oxygen from the oxide 230 by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230 is reduced, making the transistor 200 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0135] On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, the decrease in electron mobility caused by grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. As a result, metal oxides containing CAAC-OS are heat resistant and highly reliable.

[0136] Here, an enlarged view of the vicinity of the channel formation region in Figure 1(B) is shown in Figure 6(A). As shown in Figure 6(A), the oxide 230 has a region 230bc that functions as the channel formation region of the transistor 200, and regions 230ba and 230bb that are provided so as to sandwich region 230bc and function as the source region or drain region. At least a portion of region 230bc is superimposed on the conductor 260. In other words, region 230bc is provided in the region between conductors 242a and 242b. Region 230ba is provided superimposed on conductor 242a, and region 230bb is provided superimposed on conductor 242b.

[0137] Region 230bc, which functions as a channel-forming region, is a high-resistance region with a lower carrier concentration due to fewer oxygen vacancies or lower impurity concentrations compared to regions 230ba and 230bb. Therefore, region 230bc can be said to be type i (intrinsic) or substantially type i.

[0138] Furthermore, regions 230ba and 230bb, which function as source or drain regions, are regions with high oxygen deficiencies or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements, resulting in increased carrier concentration and low resistance. In other words, regions 230ba and 230bb are n-type regions with higher carrier concentration and lower resistance compared to region 230bc.

[0139] Here, the carrier concentration in region 230bc, which functions as a channel-forming region, is 1 × 10⁻⁶. 18 cm -3 The following is preferable: 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm -3It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration in the region 230bc that functions as a channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0140] Furthermore, a region may be formed between region 230bc and region 230ba (region 230bb) where the carrier concentration is equal to or lower than that of region 230ba (region 230bb) and equal to or higher than that of region 230bc. In other words, this region functions as a junction region between region 230bc and region 230ba (region 230bb). The hydrogen concentration in this junction region may be equal to or lower than that of region 230ba (region 230bb) and equal to or higher than that of region 230bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of region 230ba or region 230bb and equal to or greater than that of region 230bc.

[0141] Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0142] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). OSometimes called H, it forms a channel and generates electrons that become carriers. For this reason, if the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region where the channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0143] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 200 or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor.

[0144] Therefore, in an oxide semiconductor, the region 230bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 230ba and 230bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 230bc of the oxide semiconductor, and V O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 230ba and 230bb.

[0145] Therefore, in this embodiment, with the conductors 242a and 242b placed on the oxide 230, microwave treatment is performed in an oxygen-containing atmosphere to eliminate oxygen deficiencies in region 230bc, and VO The aim is to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Furthermore, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0146] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 230bc. Due to the action of plasma, microwaves, etc., the V of region 230bc O H is oxygen-deficient (V O It can be separated into (V) and hydrogen (H), remove the hydrogen from region 230bc, and repair the oxygen deficiency with oxygen. In other words, in region 230bc, "V O H → H + V O The following reaction occurs, which reduces the hydrogen concentration in region 230bc. Therefore, the oxygen deficiency in region 230bc, and V O This can reduce H and lower the carrier concentration.

[0147] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b and do not reach regions 230ba and 230bb. In addition, the effect of oxygen plasma can be reduced by insulators 271, 275, and 280, which are provided covering oxide 230 and conductor 242. As a result, during microwave processing, V O This reduces H and prevents excessive oxygen supply, thus preventing a decrease in carrier concentration.

[0148] Furthermore, the oxygen injected into region 230bc can take various forms, including oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, which are atoms, molecules, or ions with unpaired electrons). Note that the oxygen injected into region 230bc may be one or more of the above forms, and oxygen radicals are particularly preferred.

[0149] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after the deposition of the insulating film that will become the insulator 252, and / or after the deposition of the insulating film that will become the insulator 250. By performing microwave treatment in an oxygen-containing atmosphere via the insulator 252 and / or the insulator 250 in this way, oxygen can be efficiently injected into region 230bc. In addition, by arranging the insulator 252 in contact with the side surface of the conductor 242 and the surface of region 230bc, the injection of more oxygen than necessary into region 230bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 242. Furthermore, oxidation of the side surface of the conductor 242 can be suppressed when the insulating film that will become the insulator 250 is deposited.

[0150] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V O By reducing H, region 230bc can be made i-type or substantially i-type. Furthermore, it is possible to suppress the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, and maintain the state of the n-type region before microwave processing. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane.

[0151] Furthermore, as shown in Figure 1(C), in a cross-sectional view of the transistor 200 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 230. In other words, the ends of the side surface and the ends of the top surface may be curved (also called rounded).

[0152] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230 in the region overlapping with the conductor 242, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 230 by the insulator 252, insulator 250, insulator 254, and conductor 260 can be improved.

[0153] Furthermore, as shown in Figure 1(C), by providing an insulator 252 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 230, the indium contained in the oxide 230 may be unevenly distributed at and near the interface between the oxide 230 and the insulator 252. As a result, the atomic ratio near the surface of the oxide 230 becomes similar to that of indium oxide, or similar to that of In-Zn oxide. By increasing the atomic ratio of indium near the surface of the oxide 230 in this way, the field-effect mobility of the transistor 200 can be improved.

[0154] It is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, it is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 is an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen does not easily permeate it).

[0155] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0156] For insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, for insulators 212, 275, and 283, it is preferable to use silicon nitride, which has higher hydrogen barrier properties. Also, for example, for insulators 214, 271, 282, and 285, it is preferable to use aluminum oxide, magnesium oxide, etc., which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side via insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulator 285 towards the transistor 200. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224, etc., towards the substrate side via the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280, etc., upward from the transistor 200 via the insulator 282, etc. Thus, it is preferable to have a structure in which the transistor 200 is surrounded by insulators 212, 214, 271, 275, 282, 283, and 285, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0157] Here, it is preferable to use oxides having an amorphous structure as insulators 212, 214, 271, 275, 282, 283, and 285. For example, AlO x (x is any number greater than 0), MgO y It is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, hydrogen contained in the transistor 200, or hydrogen present around the transistor 200, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, it is possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0158] Furthermore, while insulators 212, 214, 271, 275, 282, 283, and 285 are preferably amorphous, they may also have regions of polycrystalline structure. In addition, insulators 212, 214, 271, 275, 282, 283, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer is also possible.

[0159] The insulators 212, 214, 271, 275, 282, 283, and 285 may be deposited using, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of insulators 212, 214, 271, 275, 282, 283, and 285 can be reduced. Note that the deposition method is not limited to sputtering, and CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), ALD, etc. may be used as appropriate.

[0160] Furthermore, it may be preferable to lower the resistivity of insulators 212, 275, and 283. For example, the resistivity of insulators 212, 275, and 283 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 212, 275, and 283 may be able to mitigate the charge-up of conductors 205, 242, 260, or 246 in processes using plasma or the like during semiconductor device manufacturing. The resistivity of insulators 212, 275, and 283 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0161] Furthermore, it is preferable that insulators 216, 280, and 285 have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with voids can be used as insulators 216, 280, and 285 as appropriate.

[0162] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205 is embedded in an opening formed in the insulator 216. In some cases, a portion of the conductor 205 may be embedded in the insulator 214.

[0163] The conductor 205 comprises a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and side wall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is approximately equal to the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0164] Here, it is preferable to use a conductive material for the conductor 205a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0165] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the oxidation of the conductor 205b and the decrease in conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, the conductive material can be used as a single layer or in a laminate for the conductor 205a. For example, titanium nitride can be used for the conductor 205a.

[0166] Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b.

[0167] The conductor 205 may function as a second gate electrode. In that case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0V than when no negative potential is applied.

[0168] Also, the electrical resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electrical resistivity. Also, the film thickness of the insulator 216 is made substantially the same as that of the conductor 205. Here, it is preferable to reduce the film thicknesses of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the film thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that the diffusion of the impurities into the oxide 230 can be reduced.

[0169] Note that the conductor 205 may be provided to be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230, as shown in FIG. 1(A). In particular, as shown in FIG. 1(C), the conductor 205 preferably extends also in the region outside the end portion in the channel width direction of the oxide 230. That is, outside the side surface in the channel width direction of the oxide 230, it is preferable that the conductor 205 and the conductor 260 overlap via an insulator. By having such a configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, the structure of the transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0170] In the present specification and the like, the transistor with an S-channel structure refers to a structure of a transistor that electrically surrounds a channel formation region by electric fields of one and the other of a pair of gate electrodes. Further, the S-channel structure disclosed in the present specification and the like is different from a Fin-type structure and a planar-type structure. By adopting the S-channel structure, it is possible to enhance the resistance to the short-channel effect, or in other words, to obtain a transistor in which the short-channel effect hardly occurs.

[0171] By setting the transistor 200 to normally-off and adopting the above-described S-channel structure, the channel formation region can be electrically surrounded. Therefore, the transistor 200 can also be regarded as having a GAA (Gate All Around) structure or a LGAA (Lateral Gate All Around) structure. By setting the transistor 200 to have an S-Channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be made to cover the entire bulk of the oxide 230. Therefore, since it becomes possible to improve the current density flowing through the transistor, an improvement in the on-current of the transistor or an increase in the field-effect mobility of the transistor can be expected.

[0172] Also, as shown in FIG. 1(C), the conductor 205 is extended to function also as a wiring. However, the present invention is not limited to this, and a configuration may be adopted in which a conductor functioning as a wiring is provided under the conductor 205. Also, the conductor 205 does not necessarily need to be provided one by one for each transistor. For example, a configuration may be adopted in which the conductor 205 is shared by a plurality of transistors.

[0173] In the transistor 200, the conductor 205 is shown as a configuration in which the conductor 205a and the conductor 205b are laminated, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a laminated structure of three or more layers.

[0174] Insulators 222 and 224 function as gate insulators.

[0175] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 224.

[0176] The insulator 222 may be an insulator containing an oxide of either or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side, or the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 or the oxide 230.

[0177] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0178] Furthermore, the insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST), may also be used as the insulator 222.

[0179] The insulator 224 in contact with the oxide 230 can be, for example, silicon oxide, silicon oxide nitride, or the like, as appropriate.

[0180] Furthermore, during the manufacturing process of the transistor 200, it is preferable to perform a heat treatment with the surface of the oxide 230 exposed. This heat treatment may be performed, for example, at a temperature of 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230, thereby reducing oxygen deficiency. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0181] Furthermore, by performing an oxygenation treatment on oxide 230, oxygen deficiencies in oxide 230 are repaired by the supplied oxygen, or in other words, "V OThis can accelerate the reaction "+O → null". Furthermore, the supplied oxygen reacts with the hydrogen remaining in oxide 230, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 230 recombines with the oxygen vacancy and V O This can suppress the formation of H.

[0182] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 224 may be formed in an island-like manner by being superimposed with the oxide 230. In this case, the insulator 275 will be in contact with the side surface of the insulator 224 and the upper surface of the insulator 222.

[0183] Conductors 242a and 242b are provided in contact with the upper surface of the oxide 230. Conductors 242a and 242b function as the source electrode or drain electrode of the transistor 200, respectively.

[0184] As the conductor 242, it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0185] Furthermore, hydrogen contained in oxide 230, etc., may diffuse into conductor 242a or conductor 242b. In particular, by using tantalum-containing nitrides for conductors 242a and 242b, hydrogen contained in oxide 230, etc., is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen present in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230, etc., may be absorbed by conductor 242a or conductor 242b.

[0186] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By using a conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the channel width direction can be increased, as shown in Figure 1(D). This increases the conductivity of the conductor 242 and increases the on-current of the transistor 200.

[0187] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. Preferably, the insulator 271 functions as a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen more than the insulator 280. As the insulator 271, for example, a silicon-containing nitride such as silicon nitride may be used. Furthermore, it is preferable that the insulator 271 has a function to capture impurities such as hydrogen. In that case, as the insulator 271, an amorphous metal oxide, such as aluminum oxide or magnesium oxide, may be used. In particular, it is preferable to use amorphous aluminum oxide or amorphous aluminum oxide as the insulator 271 because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 200 and semiconductor device with good characteristics and high reliability.

[0188] The insulator 275 is provided so as to cover the insulator 224, oxide 230, conductor 242, and insulator 271. Preferably, the insulator 275 has the function of capturing and fixing hydrogen. In that case, it is preferable that the insulator 275 includes silicon nitride or an insulator of a metal oxide having an amorphous structure (e.g., aluminum oxide, magnesium oxide, etc.). Alternatively, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 275.

[0189] By providing the insulators 271 and 275 described above, the conductor 242 can be surrounded by an insulator that has barrier properties against oxygen. In other words, the oxygen contained in the insulators 224 and 280 can be prevented from diffusing into the conductor 242. This prevents the conductor 242 from being directly oxidized by the oxygen contained in the insulators 224 and 280, which would increase its resistivity and reduce the on-current.

[0190] The insulator 252 functions as part of the gate insulator. Preferably, the insulator 252 is a barrier insulating film against oxygen. The insulator 252 can be any insulator that can be used for the insulator 282 described above. The insulator 252 may be an insulator containing an oxide of either or both aluminum and hafnium. Examples of such insulators include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 252. In this case, the insulator 252 is an insulator containing at least oxygen and aluminum.

[0191] As shown in FIG. 1(C), the insulator 252 is provided in contact with the upper and side surfaces of the oxide 230, the side surface of the insulator 224, and the upper surface of the insulator 222. That is, the region of the oxide 230 and the conductor 260 of the insulator 224 is covered with the insulator 252 in the cross section in the channel width direction. Thereby, when heat treatment or the like is performed, the desorption of oxygen in the oxide 230 can be blocked by the insulator 252 having a barrier property against oxygen. Therefore, the formation of oxygen deficiency in the oxide 230 can be reduced. Thereby, the oxygen deficiency and V O H formed in the region 230bc can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved and the reliability can be enhanced.

[0192] Conversely, even if an excessive amount of oxygen is contained in the insulator 280, the insulator 250, etc., the supply of the oxygen to the oxide 230 can be suppressed. Therefore, the excessive oxidation of the regions 230ba and 230bb via the region 230bc, which causes a decrease in the on-current or a decrease in the field-effect mobility of the transistor 200, can be suppressed.

[0193] Also, as shown in FIG. 1(B), the insulator 252 is provided in contact with the respective side surfaces of the conductor 242, the insulator 271, the insulator 275, and the insulator 280. Therefore, the oxidation of the side surface of the conductor 242 and the formation of an oxide film on the side surface can be reduced. Thereby, the decrease in the on-current or the decrease in the field-effect mobility of the transistor 200 can be suppressed.

[0194] Furthermore, the insulator 252, along with the insulator 254, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 252 be thin. The film thickness of the insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 252 has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 252 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 252 has a region with a film thickness thinner than the insulator 250 in at least a part of it.

[0195] To deposit the insulator 252 with a thin film thickness as described above, it is preferable to use the ALD method. ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. The PEALD method is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0196] The ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in several advantages: ultra-thin film deposition is possible, deposition on structures with high aspect ratios is possible, film deposition with fewer defects such as pinholes is possible, film deposition with excellent coverage is possible, and film deposition is possible at low temperatures. Therefore, the insulator 252 can be deposited with good coverage on the sides of openings formed in the insulator 280, etc., with the thin film thickness described above.

[0197] Note that some precursors used in the ALD method contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other deposition methods. The quantity of impurities can be quantified using SIMS or XPS.

[0198] Furthermore, if the insulator 252 has a region of film thickness as described above, it is presumed that the defect levels related to photo-negative bias degradation are not limited to the defect levels at the interface between the oxide 230 and the insulator 252, but also include the defect levels at the interface between the insulator 252 and the insulator 250, or the defect levels within the insulator 250.

[0199] The insulator 250 functions as part of the gate insulator. It is preferable that the insulator 250 is placed in contact with at least a portion of the insulator 252. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. In particular, silicon oxide and silicon oxynitride are preferred because they are stable with respect to heat. In this case, the insulator 250 will be an insulator having at least oxygen and silicon.

[0200] Similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced.

[0201] Furthermore, the film thickness of the insulator 250 is preferably 0.5 nm or more and 20 nm or less, and more preferably 1.0 nm or more and 15.0 nm or less. In this case, the insulator 250 only needs to have a region with the above-mentioned film thickness in at least a part of it.

[0202] Figure 1(B) and others show a configuration in which the insulator 250 is a single layer, but the present invention is not limited to this, and a laminated structure of two or more layers is also possible. For example, as shown in Figure 6(B), the insulator 250 may be a laminated structure of two layers, consisting of an insulator 250a and an insulator 250b on top of the insulator 250a.

[0203] As shown in Figure 6(B), when the insulator 250 has a two-layer laminated structure, it is preferable that the lower insulator 250a is formed using an insulator that is permeable to oxygen, and the upper insulator 250b is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in the insulator 250a. For example, the insulator 250a may be made using a material that can be used for the insulator 250 described above, and the insulator 250b may be an insulator containing an oxide of aluminum and / or hafnium. As such an insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc., can be used. In this embodiment, hafnium oxide is used as the insulator 250b. In this case, the insulator 250b is an insulator having at least oxygen and hafnium. The film thickness of the insulator 250b is 0.5 nm or more and 5.0 nm or less, preferably 1.0 nm or more and 5.0 nm or less, more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 250b has at least a portion of the above-mentioned film thickness region.

[0204] Furthermore, when silicon oxide, silicon oxynitride, or the like is used for insulator 250a, insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250a and insulator 250b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to make the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator thinner. Thus, the dielectric breakdown voltage of insulator 250 can be increased.

[0205] The insulator 254 functions as part of the gate insulator. Preferably, a barrier insulating film against hydrogen is used as the insulator 254. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and the oxide 230. The insulator 254 can be any insulator that can be used for the insulator 283 described above. For example, silicon nitride deposited by the PEALD method can be used as the insulator 254. In this case, the insulator 254 will be an insulator containing at least nitrogen and silicon.

[0206] Furthermore, the insulator 254 may also have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the insulator 250 into the conductor 260.

[0207] Furthermore, the insulator 254, along with the insulator 252, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 254 be thin. The film thickness of the insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 254 has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 254 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 254 has a region with a thinner film thickness than the insulator 250 in at least a part of it.

[0208] The conductor 260 functions as the first gate electrode of the transistor 200. Preferably, the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b. Also, as shown in Figures 1(B) and 1(C), the top surface of the conductor 260 roughly coincides with the top of the insulator 252, the top of the insulator 250, and the top of the insulator 254. In Figures 1(B) and 1(C), the conductor 260 is shown as a two-layer structure of conductor 260a and conductor 260b, but it may also be a single-layer structure or a stacked structure of three or more layers.

[0209] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0210] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0211] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0212] Furthermore, in transistor 200, the conductor 260 is formed self-aligningly to fill the openings formed in the insulator 280 and the like. By forming the conductor 260 in this way, the conductor 260 can be reliably positioned in the region between the conductors 242a and 242b without the need for alignment.

[0213] Furthermore, as shown in Figure 1(C), in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230 do not overlap, with reference to the bottom surface of the insulator 222, is preferably approximately the same as or lower than the height of the bottom surface of the oxide 230. By configuring the conductor 260, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of the oxide 230 via an insulator 250 or the like, it becomes easier to apply the electric field of the conductor 260 to the entire channel formation region of the oxide 230. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230 and the conductor 260 do not overlap, with reference to the bottom surface of the insulator 222, and the height of the bottom surface of the oxide 230, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0214] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulators 252, 250, 254, and conductor 260 are provided. The upper surface of the insulator 280 may also be flattened.

[0215] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance occurring between wirings can be reduced. The insulator 280 is preferably made of the same material as the insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0216] Preferably, the insulator 280 has reduced concentrations of impurities such as water and hydrogen. For example, the insulator 280 may be made of silicon oxides such as silicon oxide or silicon oxynitride.

[0217] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, the insulator 282 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, an amorphous metal oxide, such as aluminum oxide, may be used. In this case, the insulator 282 will be an insulator having at least oxygen and aluminum. By providing an insulator 282 that is in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283 and has the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, using aluminum oxide with an amorphous structure as the insulator 282 is preferable because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0218] The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above. The insulator 283 is placed on top of the insulator 282. Preferably, the insulator 283 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 283. By depositing the insulator 283 by sputtering, a high-density silicon nitride can be formed. Alternatively, as the insulator 283, silicon nitride deposited by PEALD or CVD may be further laminated on top of the silicon nitride deposited by sputtering.

[0219] The conductor 240 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, conductors 240a and 240b may each have a laminated structure.

[0220] Furthermore, when the conductor 240 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged in the vicinity of the insulators 285, 283, 282, 280, 275, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. The conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminate. In addition, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the layer above the insulator 283 into the oxide 230 through the conductor 240.

[0221] As the insulator 241, any barrier insulating film that can be used for insulator 275, etc., may be used. For example, as the insulator 241, an insulator such as silicon nitride, aluminum oxide, or silicon oxide nitride may be used. Since the insulator 241a (insulator 241b) is provided in contact with insulator 283, insulator 282, and insulator 271, it is possible to suppress the mixing of impurities such as water and hydrogen contained in insulator 280, etc., into the oxide 230 through the conductor 240a (conductor 240b). In particular, silicon nitride is preferred because of its high blocking properties for hydrogen. In addition, it is possible to prevent oxygen contained in insulator 280 from being absorbed by conductor 240.

[0222] When the insulators 241a and 241b are arranged in a laminated structure as shown in Figure 1(B), it is preferable that the first insulator in contact with the inner wall of the opening, such as the insulator 280, and the second insulator inside it, use a combination of an oxygen barrier insulating film and a hydrogen barrier insulating film.

[0223] For example, aluminum oxide deposited by the ALD method can be used as the first insulator, and silicon nitride deposited by the PEALD method can be used as the second insulator. This configuration suppresses oxidation of the conductor 240 and further reduces the incorporation of hydrogen into the conductor 240.

[0224] Furthermore, a conductor 246a that functions as wiring and is in contact with the upper surface of the conductor 240a, and a conductor 246b that functions as wiring and is in contact with the upper surface of the conductor 240b may be arranged. It is preferable that the conductor 246 is made of a conductive material mainly composed of tungsten, copper, or aluminum. In addition, each of the conductors 246a and 246b may have a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator.

[0225] By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability and excellent electrical characteristics.

[0226] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0227] <<Substrate>> As the substrate for forming transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0228] <<Insulator>> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0229] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0230] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0231] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0232] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0233] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0234] <<Conductive material>> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0235] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0236] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0237] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0238] <<Metal Oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as oxide 230. Below, metal oxides applicable to oxide 230 according to the present invention will be described.

[0239] It is preferable to use a metal oxide with a band gap of 2 eV or more, and more preferably one with a band gap of 2.5 eV or more, as it functions as a semiconductor. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0240] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0241] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Element M can be aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, it is sometimes permissible to use a combination of multiple of the aforementioned elements as element M.

[0242] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0243] <Classification of crystal structures> Examples of crystalline structures for oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal.

[0244] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. For example, it can be evaluated using the XRD spectrum obtained from a GIXD (Grazing-Incidence XRD) measurement. The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. In the following text, the XRD spectrum obtained from a GIXD measurement may simply be referred to as the XRD spectrum.

[0245] For example, in a quartz glass substrate, the peak shape of the XRD spectrum is nearly symmetrical. On the other hand, in an In-Ga-Zn oxide film with a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical shape of the XRD spectrum peaks clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0246] Furthermore, the crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed using nano-beam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. On the other hand, a spot-like pattern is observed in the diffraction pattern of an In-Ga-Zn oxide film deposited at room temperature, rather than a halo. Therefore, it is presumed that the In-Ga-Zn oxide deposited at room temperature is in an intermediate state, neither single-crystal nor polycrystalline, nor amorphous, and cannot be concluded to be in an amorphous state.

[0247] <<Oxide semiconductor structure>> It should be noted that oxide semiconductors may be classified differently from those described above when considering their structure. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0248] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0249] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0250] Each of the above-mentioned crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of that crystalline region will be less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of that crystalline region may be around several tens of nm.

[0251] Furthermore, in In-Ga-Zn oxides, CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as the (Ga,Zn) layer). Note that indium and gallium are mutually substitutable. Therefore, the (Ga,Zn) layer may contain indium. Also, the In layer may contain gallium. Also, the In layer may contain zinc. This layered structure can be observed, for example, as a lattice image in high-resolution TEM (Transmission Electron Microscope) images.

[0252] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0253] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0254] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to factors such as the non-dense arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distances due to the substitution of metal atoms.

[0255] Furthermore, a crystal structure in which clear grain boundaries can be observed is called a polycrystalline material. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries cannot be observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they can suppress the generation of grain boundaries more effectively than In oxide.

[0256] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities and the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0257] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0258] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0259] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0260] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0261] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0262] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0263] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0264] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0265] Furthermore, CAC-OS in In-Ga-Zn oxide refers to a material composition containing In, Ga, Zn, and O, in which regions with Ga as the main component and regions with In as the main component are arranged in a mosaic-like manner, with these regions existing randomly. Therefore, it is presumed that CAC-OS has a structure in which metal elements are unevenly distributed.

[0266] CAC-OS can be formed by sputtering, for example, under conditions where the substrate is not intentionally heated. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. Furthermore, a lower ratio of the oxygen gas flow rate to the total deposition gas flow rate during film formation is preferable. For example, the ratio of the oxygen gas flow rate to the total deposition gas flow rate during film formation should be 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0267] Furthermore, for example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0268] Here, the first region is a region with higher conductivity compared to the second region. In other words, the conductivity of the metal oxide is exhibited when carriers flow through the first region. Therefore, a high field-effect mobility (μ) can be achieved when the first region is distributed in a cloud-like manner within the metal oxide.

[0269] On the other hand, the second region is a region with higher insulating properties compared to the first region. In other words, the distribution of the second region within the metal oxide can suppress leakage current.

[0270] Therefore, when CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on This enables high field-effect mobility (μ) and good switching operation.

[0271] Furthermore, transistors using CAC-OS offer high reliability. Therefore, CAC-OS is ideal for various semiconductor devices, including display devices.

[0272] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0273] Furthermore, oxide semiconductors may have multiple crystal structures. For example, in oxide semiconductors, if gallium is present in greater quantities than indium, they may have both a layered crystal structure and a spinel-type crystal structure. In this case, the oxide semiconductor may have CAAC-OS, nc-OS, CAAC-OS including a crystalline region with a spinel-type crystal structure, nc-OS including a crystalline region with a layered crystal structure and a crystalline region with a spinel-type crystal structure, and so on.

[0274] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0275] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0276] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm -3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0277] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0278] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0279] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in an oxide semiconductor refer to elements other than the main components that make up the oxide semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities.

[0280] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0281] In oxide semiconductors, the presence of silicon or carbon, which are both Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor (the concentration obtained by SIMS) is 2 × 10⁻¹⁶. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0282] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0283] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0284] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0285] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0286] <Method for fabricating semiconductor devices> Next, a method for manufacturing a semiconductor device, which is one embodiment of the present invention as shown in Figures 1(A) to 1(D), will be explained using Figures 7(A) to 15(D).

[0287] (A) in each figure shows a top view. (B) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in (A), and is also a cross-sectional view of transistor 200 in the channel length direction. (C) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in (A), and is also a cross-sectional view of transistor 200 in the channel width direction. (D) in each figure is a cross-sectional view of the area indicated by the dashed line A5-A6 in (A). Note that some elements have been omitted from the top view (A) in each figure for clarity.

[0288] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD as appropriate.

[0289] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. RF sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing conductive metal films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0290] Furthermore, CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) depending on the source gas used.

[0291] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) contained in semiconductor devices can be charged up by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0292] Furthermore, ALD methods that can be used include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants.

[0293] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and provide good step-level coating. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coating and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other deposition methods that have a faster deposition rate, such as the CVD method.

[0294] Furthermore, the CVD method allows for the deposition of films with arbitrary compositions by changing the flow rate ratio of the source gases. For example, in the CVD method, films with continuously changing compositions can be deposited by changing the flow rate ratio of the source gases while the film is being deposited. When depositing films while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because the time required for transport and pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0295] Furthermore, the ALD method allows for the deposition of films with any desired composition by simultaneously introducing multiple different types of precursors. Alternatively, when introducing multiple different types of precursors, films with any desired composition can be deposited by controlling the number of cycles for each precursor.

[0296] First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate (see Figures 7(A) to 7(D)). The deposition of the insulator 212 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the deposition of the insulator 212 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0297] In this embodiment, silicon nitride is deposited as the insulator 212 using a silicon target in a nitrogen gas atmosphere by pulsed DC sputtering. By using pulsed DC sputtering, the generation of particles due to arcing on the target surface can be suppressed, making the film thickness distribution more uniform. Furthermore, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows for more efficient power supply to the electrode, improving the sputtering rate and film quality.

[0298] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a diffusive metal such as copper is used in the conductor layer below the insulator 212 (not shown), the diffusion of that metal upward through the insulator 212 can be suppressed.

[0299] Next, an insulator 214 is deposited on the insulator 212 (see Figures 7(A) to 7(D)). The deposition of the insulator 214 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0300] In this embodiment, aluminum oxide is deposited as the insulator 214 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen injected into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is 0 W / cm². 2 The above is 1.86 W / cm². 2 The following applies: In other words, the amount of oxygen injected can be varied to suit the characteristics of the transistor by changing the RF power used during the formation of the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. Furthermore, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be inflicted on the substrate.

[0301] It is preferable to use an amorphous metal oxide, such as aluminum oxide, as the insulator 214, which has a high ability to capture and fix hydrogen. This allows for the capture or fixation of hydrogen contained in the insulator 216, etc., preventing the hydrogen from diffusing into the oxide 230. In particular, it is preferable to use amorphous aluminum oxide, or aluminum oxide with an amorphous structure, as the insulator 214, as this may allow for more effective capture or fixation of hydrogen. This makes it possible to fabricate a transistor 200 and semiconductor device with good properties and high reliability.

[0302] Next, an insulator 216 is deposited on the insulator 214. The deposition of the insulator 216 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0303] In this embodiment, silicon oxide is deposited as the insulator 216 using a silicon target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0304] It is preferable to continuously deposit insulators 212, 214, and 216 without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of insulators 212, 214, and 216 with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0305] Next, an opening is formed in the insulator 216 that reaches the insulator 214. The opening includes, for example, grooves and slits. In some cases, the term "opening" refers to the region in which the opening is formed. The opening may be formed using wet etching, but dry etching is preferable for microfabrication. Furthermore, it is preferable to select an insulator 214 that functions as an etching stopper film when etching the insulator 216 to form grooves. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 in which grooves are formed, then silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.

[0306] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0307] After the opening is formed, a conductive film that will become the conductor 205a is deposited. It is desirable that the conductive film contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, a laminated film can be formed of a conductor that has the function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The conductive film can be deposited using sputtering, CVD, MBE, PLD, ALD, etc.

[0308] In this embodiment, a titanium nitride film is formed as the conductive film that will become the conductor 205a. By using such a metal nitride as the layer beneath the conductor 205b, oxidation of the conductor 205b by the insulator 216 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0309] Next, a conductive film to form the conductor 205b is deposited. This conductive film can be made of materials such as tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be deposited using methods such as plating, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, a tungsten film is deposited as the conductive film.

[0310] Next, by performing CMP treatment, a portion of the conductive film that will become conductor 205a and a portion of the conductive film that will become conductor 205b are removed, exposing the insulator 216 (see Figures 7(A) to 7(D)). As a result, conductor 205a and conductor 205b remain only in the opening. Note that a portion of the insulator 216 may be removed by this CMP treatment.

[0311] Next, an insulator 222 is deposited on the insulator 216 and the conductor 205 (see Figures 8(A) to 8(D)). It is preferable to deposit an insulator 222 containing an oxide of either or both aluminum and hafnium. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). An insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 222 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structure surrounding the transistor 200 into the transistor 200 through the insulator 222 is suppressed, thereby suppressing the formation of oxygen vacancies in the oxide 230.

[0312] The insulator 222 can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, hafnium oxide is deposited as the insulator 222 using the ALD method.

[0313] Next, it is preferable to perform a heat treatment. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then further in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0314] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture or other substances being incorporated into the insulator 222 and the like.

[0315] In this embodiment, as a heat treatment, after the insulator 222 is formed, the insulator is treated at a temperature of 400°C for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. Furthermore, when an oxide containing hafnium is used as the insulator 222, a portion of the insulator 222 may crystallize as a result of this heat treatment. The heat treatment can also be performed at a later time, such as after the formation of the insulator 224.

[0316] Next, an insulating film 224A is deposited on the insulator 222 (see Figures 8(A) to 8(D)). The insulating film 224A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, a silicon oxide film is deposited as the insulating film 224A using the sputtering method. By using the sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 224A can be reduced. Since the insulating film 224A will come into contact with the oxide 230 in a later step, it is preferable that the hydrogen concentration is reduced in this way.

[0317] Next, an oxide film 230A is deposited on the insulating film 224A (see Figures 8(A) to 8(D)). The oxide film 230A can be deposited using sputtering, CVD, MBE, PLD, ALD, or other methods.

[0318] For example, when depositing oxide film 230A by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide film by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0319] Furthermore, when the oxide film 230A is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be more than 30% but 100% or less, preferably 70% or more but 100%, an oxygen-rich oxide semiconductor is formed. Transistors using an oxygen-rich oxide semiconductor in the channel formation region can achieve relatively high reliability. However, the present invention is not limited to this. When the oxide film 230A is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be 1% or more but 30% or less, preferably 5% or more but 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using an oxygen-deficient oxide semiconductor in the channel formation region can achieve relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate.

[0320] Furthermore, during the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

[0321] Alternatively, for example, the deposition of the oxide film 230A is preferable because the ALD method can form a film of uniform thickness even in grooves or openings with a large aspect ratio. Furthermore, the PEALD method is preferable because it can form the oxide film 230A at a lower temperature compared to the thermal ALD method.

[0322] In this embodiment, the oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4. The oxide film 230A can be formed according to the desired properties of the oxide 230 by appropriately selecting the deposition conditions and atomic ratio.

[0323] Furthermore, it is preferable to deposit the insulating film 224A and the oxide film 230A by sputtering without exposing them to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This reduces the incorporation of hydrogen into the films between each deposition process for the insulating film 224A and the oxide film 230A.

[0324] Next, it is preferable to perform a heat treatment. The heat treatment should be performed within a temperature range in which the oxide film 230A does not polycrystallize, and should be performed between 250°C and 650°C, preferably between 400°C and 600°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0325] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the oxide film 230A, etc.

[0326] In this embodiment, the heat treatment involves a nitrogen gas to oxygen gas flow rate ratio of 4:1 and a treatment at a temperature of 400°C for 2 hours. This heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230A. By reducing impurities in the film in this way, the crystallinity of the oxide film 230A can be improved, resulting in a denser, more compact structure. This increases the crystalline region in the oxide film 230A and reduces in-plane variation of the crystalline region within the oxide film 230A. Therefore, in-plane variation in the electrical characteristics of the transistor 200 can be reduced.

[0327] Furthermore, the heat treatment containing oxygen gas described above can reduce the density of tail levels near the valence band or the density of deep levels in the oxide film 230A. This allows for a larger band gap in the oxide film 230A compared to before the heat treatment, or reduces the number of electrons excited into the conduction band of the oxide film 230A. Thus, the degradation of transistor characteristics due to stray light can be reduced.

[0328] Next, a conductive film 242A is deposited on the oxide film 230A (see Figures 8(A) to 8(D)). The conductive film 242A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. For example, a tantalum nitride film can be deposited as the conductive film 242A using sputtering. Before depositing the conductive film 242A, a heat treatment may be performed. This heat treatment may be performed under reduced pressure, and the conductive film 242A may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230A can be removed, and the moisture and hydrogen concentrations in the oxide film 230A can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0329] Next, an insulating film 271A is deposited on the conductive film 242A (see Figures 8(A) to 8(D)). The insulating film 271A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to use an insulating film 271A that has the function of suppressing oxygen permeation. For example, an aluminum oxide film or a silicon nitride film can be deposited as the insulating film 271A by sputtering.

[0330] Furthermore, it is preferable to deposit the conductive film 242A and the insulating film 271A by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus may be used. This reduces the amount of hydrogen in the films when depositing the conductive film 242A and the insulating film 271A, and also reduces the amount of hydrogen introduced into the films between each deposition process. In addition, if a hard mask is provided on the insulating film 271A, the hard mask film may also be deposited continuously without exposure to the atmosphere.

[0331] Next, the insulating film 224A, oxide film 230A, conductive film 242A, and insulating film 271A are processed into island-like structures using lithography to form the insulator 224, oxide 230, conductive layer 242B, and insulating layer 271B (see Figures 9(A) to 9(D)). Here, the insulator 224, oxide 230, conductive layer 242B, and insulating layer 271B are formed so that at least a portion of them overlaps with the conductor 205. The above processing can be performed using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. Furthermore, the processing of the insulating film 224A, oxide film 230A, conductive film 242A, and insulating film 271A may be carried out under different conditions.

[0332] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, wet etching after dry etching, or dry etching after wet etching.

[0333] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material is formed on the conductive film 242A, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. Etching of the conductive film 242A, etc., may be performed after removing the resist mask, or it may be performed while the resist mask remains. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask. In this embodiment, an insulating layer 271B is used as the hard mask.

[0334] Here, since the insulating layer 271B functions as a mask for the conductive layer 242B, the conductive layer 242B does not have a curved surface between its side and top surfaces, as shown in Figures 9(B) to 9(D). As a result, the conductor 242 shown in Figures 1(B) and 1(D) has a angular end where the side and top surfaces meet. Because the end where the side and top surfaces of the conductor 242 meet is angular, the cross-sectional area of ​​the conductor 242 is larger compared to when that end has a curved surface. As a result, the resistance of the conductor 242 is reduced, and the on-current of the transistor 200 can be increased.

[0335] Furthermore, as shown in Figures 9(B) to 9(D), the sides of the insulator 224, oxide 230, conductive layer 242B, and insulating layer 271B may be tapered. In this specification, a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface. For example, it is preferable that the angle between the inclined side surface and the substrate surface (hereinafter sometimes referred to as the taper angle) is less than 90°. For example, the insulator 224, oxide 230, conductive layer 242B, and insulating layer 271B may have a taper angle of 60° or more and less than 90°. By making the sides tapered in this way, the coverage of the insulator 275 and the like can be improved in subsequent processes, and defects such as porosity can be reduced.

[0336] However, the above is not limited to the above, and the sides of the insulator 224, oxide 230, conductive layer 242B, and insulating layer 271B may be configured to be approximately perpendicular to the upper surface of the insulator 222. Such a configuration makes it possible to reduce the area and increase the density when providing multiple transistors 200.

[0337] Furthermore, by-products generated in the etching process may form in layers on the sides of the insulator 224, oxide 230, conductive layer 242B, and insulating layer 271B. In this case, the layered by-products will be formed between the insulator 224, oxide 230, conductive layer 242B, and insulating layer 271B and the insulator 275. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of the insulator 222.

[0338] Next, an insulator 275 is formed by covering the insulator 224, oxide 230, conductive layer 242B, and insulating layer 271B (see Figures 10(A) to 10(D)). Here, it is preferable that the insulator 275 is in close contact with the upper surface of the insulator 222 and the side surface of the insulator 224. The insulator 275 can be formed using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable that the insulator 275 is an insulating film that has the function of suppressing oxygen permeation. For example, as the insulator 275, aluminum oxide can be formed using the sputtering method, and silicon nitride can be formed on top of it using the PEALD method. By making the insulator 275 such a layered structure, the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen may be improved.

[0339] In this way, the oxide 230 and the conductive layer 242B can be covered with an insulator 275 and an insulating layer 271B, which have the function of suppressing oxygen diffusion. This reduces the direct diffusion of oxygen from the insulator 280, etc., to the insulator 224, oxide 230, and conductive layer 242B in a later process.

[0340] Next, an insulating film, which will become an insulating film 280, is deposited on the insulating film 275. The insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be deposited as the insulating film using sputtering. By depositing the insulating film using sputtering in an oxygen-containing atmosphere, an insulating film 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 280 can be reduced. Note that a heat treatment may be performed before depositing the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulating film 275 can be removed, and the moisture and hydrogen concentrations in the oxide 230 and the insulating film 224 can be further reduced. The heat treatment conditions described above can be used for this heat treatment.

[0341] Next, the insulating film that will become the insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat top surface (see Figures 10(A) to 10(D)). Alternatively, silicon nitride may be deposited on the insulator 280 by, for example, a sputtering method, and the silicon nitride may be subjected to CMP treatment until it reaches the insulator 280.

[0342] Next, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B are processed to form an opening that reaches the oxide 230. Preferably, the opening is formed so as to overlap with the conductor 205. The formation of the opening creates the insulator 271a, the insulator 271b, the conductor 242a, and the conductor 242b (see Figures 11(A) to 11(D)).

[0343] Here, as shown in Figures 11(B) and 11(C), the sides of the insulators 280, 275, 271, and conductor 242 may be tapered. Also, the taper angle of the insulator 280 may be larger than the taper angle of the conductor 242. Furthermore, although not shown in Figures 11(A) to 11(C), the upper part of the oxide 230 may be removed when forming the above-mentioned opening.

[0344] Furthermore, the processing of a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B can be carried out using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. Moreover, these processing methods may be carried out under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 275 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the conductive layer 242B may be processed by dry etching.

[0345] Here, impurities may adhere to the top and side surfaces of the oxide 230, the side surfaces of the conductor 242, the side surfaces of the insulator 280, etc., and these impurities may diffuse into the interior of these surfaces. A step to remove such impurities may be performed. In addition, a damaged area may be formed on the surface of the oxide 230 during the dry etching process. Such a damaged area may be removed. Examples of such impurities include components contained in the insulator 280, insulator 275, insulating layer 271B, and conductive layer 242B, components contained in the materials used in the apparatus used to form the opening, and components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0346] In particular, impurities such as aluminum and silicon inhibit the CAAC-OS conversion of oxide 230. Therefore, it is preferable that impurity elements that inhibit CAAC-OS conversion, such as aluminum and silicon, are reduced or removed. For example, the concentration of aluminum atoms in oxide 230 and its vicinity should be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, even more preferably 1.0 atomic% or less, and even more preferably less than 0.3 atomic%.

[0347] Furthermore, the region of metal oxides where CAAC-OS formation is inhibited by impurities such as aluminum and silicon, resulting in a-like OS, is sometimes called the non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, therefore V O A large amount of H is formed, making it easier for the transistor to become normally-on. Therefore, it is preferable that the non-CAAC region of oxide 230 is reduced or removed.

[0348] In contrast, it is preferable that the oxide 230 has a layered CAAC structure. In particular, it is preferable that the CAAC structure extends to the lower end of the drain of the oxide 230. Here, in the transistor 200, the conductor 242a or conductor 242b, and its vicinity, function as a drain. That is, it is preferable that the oxide 230 near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230 is removed and a CAAC structure is present, which further suppresses fluctuations in the electrical characteristics of the transistor 200. Furthermore, the reliability of the transistor 200 can be improved.

[0349] In order to remove impurities and other contaminants adhering to the surface of oxide 230 during the etching process described above, a cleaning treatment is performed. Cleaning methods include wet cleaning using a cleaning solution (which can also be called wet etching), plasma treatment using plasma, and cleaning by heat treatment. These cleaning methods may be combined as appropriate. Note that this cleaning treatment may deepen the grooves.

[0350] Wet cleaning may be performed using aqueous solutions of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc., diluted with carbonated water or distilled water, distilled water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0351] In this specification, an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as diluted ammonia water. The concentration and temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water should be 0.01% to 5%, preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid should be 0.01 ppm to 100 ppm, preferably 0.1 ppm to 10 ppm.

[0352] Furthermore, it is preferable to use a frequency of 200 kHz or higher, preferably 900 kHz or higher, for ultrasonic cleaning. Using this frequency can reduce damage to oxides 230 and other components.

[0353] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0354] In this embodiment, the cleaning process described above involves wet cleaning using diluted ammonia water. This cleaning process removes impurities that have adhered to the surface of oxide 230 or diffused into its interior. Furthermore, it can enhance the crystallinity of oxide 230.

[0355] Heat treatment may be performed after the etching or cleaning described above. The heat treatment should be performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 230 and reduces oxygen deficiency. Furthermore, such heat treatment can improve the crystallinity of the oxide 230. The heat treatment may also be performed under reduced pressure. Alternatively, after heat treatment in an oxygen atmosphere, heat treatment may be performed continuously in a nitrogen atmosphere without exposure to the atmosphere.

[0356] Next, the insulating film 252A is deposited (see Figures 12(A) to 12(D)). The insulating film 252A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulating film 252A using the ALD method. As mentioned above, it is preferable to deposit the insulating film 252A with a thin film thickness, and it is necessary to minimize variations in film thickness. In contrast, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (e.g., an oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Also, as shown in Figures 12(B) and 12(C), the insulating film 252A needs to be deposited with good coverage on the bottom and side surfaces of openings formed in the insulator 280, etc. In particular, it is preferable to deposit it with good coverage on the top and side surfaces of the oxide 230 and the side surfaces of the conductor 242. Since atomic layers can be deposited one by one on the bottom and sides of the opening, the insulating film 252A can be formed on the opening with good coverage.

[0357] Furthermore, when the insulating film 252A is deposited by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidizing agents. By using hydrogen-free oxidizing agents such as ozone (O3) and oxygen (O2), the amount of hydrogen diffused into the oxide 230 can be reduced.

[0358] In this embodiment, an aluminum oxide film is formed as the insulating film 252A by thermal ALD method.

[0359] Next, an insulating film 250A is deposited (see Figures 12(A) to 12(D)). A heat treatment may be performed before depositing the insulating film 250A, and this heat treatment may be carried out under reduced pressure, allowing for continuous deposition of the insulating film 250A without exposure to the atmosphere. Furthermore, it is preferable to carry out this heat treatment in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulating film 252A can be removed, and the moisture and hydrogen concentrations in the oxide 230 can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C.

[0360] The insulating film 250A can be deposited using methods such as sputtering, CVD, PECVD, MBE, PLD, and ALD. Furthermore, it is preferable to deposit the insulating film 250A using a deposition method that utilizes a material with reduced or removed hydrogen atoms. This reduces the hydrogen concentration of the insulating film 250A. Since the insulating film 250A will later become an insulator 250 facing the oxide 230 via a thin insulating film 252, it is preferable that the hydrogen concentration is reduced in this manner.

[0361] For example, the deposition of the insulating film 250A is preferably carried out using the CVD method or the ALD method. In particular, the ALD method is preferred because it can form a film of uniform thickness even in grooves or openings with a large aspect ratio. Furthermore, the PEALD method is preferred because it can form the insulating film 250A at a lower temperature compared to the thermal ALD method.

[0362] When depositing insulating film 250A using the PEALD method, gases containing organic substances such as bis(diethylamino)silane (BDEAS, SiH2[N(C2H5)2]2) and tris(dimethylamino)silane (3DMAS, SiH[N(CH3)2]3) can be used as precursors. Alternatively, silicon-containing gases that do not contain hydrocarbons (also called inorganic precursors), such as SiH4, Si2H6, SiF4, SiCl4, SiBr4, SiH2Cl2, and SiH2I2, may be used as precursors. As oxidizing gases, O2, N2O, CO2, O3, NO2, and H2O can be used. When depositing film using the PEALD method, O2 or N2O is more preferred as the oxidizing gas. Furthermore, noble gases such as helium, neon, argon, krypton, and xenon may be added to the oxidizing gas.

[0363] The insulating film 250A can be deposited by the PEALD method, for example, using BDEAS as a precursor and a mixed gas of O2 and argon as the oxidizing agent. By using a gas that does not contain nitrogen atoms as the oxidizing gas, the nitrogen concentration in the insulating film 250A can sometimes be reduced.

[0364] In this embodiment, silicon oxide is deposited as the insulating film 250A by the PEALD method.

[0365] Next, it is preferable to perform microwave treatment in an oxygen-containing atmosphere (see Figures 12(A) to 12(D)).

[0366] The dotted lines shown in Figures 12(B) to 12(D) represent high frequencies such as microwaves and RF, oxygen plasma, or oxygen radicals. For microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus should be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. The power of the power supply for applying microwaves to the microwave processing apparatus should be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the oxide 230.

[0367] Furthermore, the above microwave treatment is preferably performed under reduced pressure, with a pressure of 10 Pa to 1000 Pa, preferably 300 Pa to 700 Pa. The treatment temperature should be 750°C or lower, preferably 500°C or lower, for example, around 400°C. Alternatively, after oxygen plasma treatment, heat treatment may be performed continuously without exposure to the outside air. For example, the temperature should be 100°C to 750°C, preferably 300°C to 500°C.

[0368] Furthermore, for example, the above microwave treatment may be carried out using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O2 / (O2+Ar)) should be greater than 0% and 100% or less. Preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) should be greater than 0% and 50% or less. More preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) should be 10% or more and 40% or less. Even more preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) should be 10% or more and 30% or less. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in region 230bc can be reduced. In addition, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, it is possible to prevent an excessive decrease in carrier concentration in regions 230ba and 230bb.

[0369] As shown in Figures 12(B) to 12(D), by performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasma-generated using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto region 230bc. In other words, microwaves or high-frequency waves such as RF, oxygen plasma, etc., can be applied to region 230bc shown in Figure 6(A). Due to the action of plasma, microwaves, etc., the V of region 230bc O By cleaving H, hydrogen (H) can be removed from region 230bc. In other words, in region 230bc, "V O H → H + V O The following reaction occurs, and V is included in region 230bc. O H can be reduced. Therefore, oxygen deficiency in region 230bc, and V O By reducing H, the carrier concentration can be lowered. Furthermore, by supplying oxygen radicals generated in the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancy formed in region 230bc, the oxygen vacancy in region 230bc can be further reduced, and the carrier concentration can be lowered.

[0370] Meanwhile, conductors 242a and 242b are provided on regions 230ba and 230bb shown in Figure 6(A). Here, it is preferable that the conductor 242 functions as a shielding film against the effects of microwaves, high frequencies such as RF, and oxygen plasma when microwave processing is performed in an oxygen-containing atmosphere. For this reason, it is preferable that the conductor 242 has the function of shielding electromagnetic waves between 300 MHz and 300 GHz, for example, between 2.4 GHz and 2.5 GHz.

[0371] As shown in Figures 12(B) to 12(D), conductors 242a and 242b shield against microwaves, high-frequency waves such as RF, and oxygen plasma, so these effects do not extend to regions 230ba and 230bb. As a result, microwave processing does not affect regions 230ba and 230bb. O This reduces H and prevents excessive oxygen supply, thus preventing a decrease in carrier concentration.

[0372] Furthermore, an insulator 252 having barrier properties against oxygen is provided in contact with the sides of the conductors 242a and 242b. This makes it possible to suppress the formation of an oxide film on the sides of the conductors 242a and 242b by microwave processing.

[0373] As described above, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V O By removing H, region 230bc can be made i-type or substantially i-type. Furthermore, it is possible to suppress the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, and maintain the state of the n-type region before microwave processing. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane.

[0374] In microwave processing, electromagnetic interaction between microwaves and molecules in oxide 230 can directly transfer thermal energy to the oxide 230. This thermal energy can cause the oxide 230 to heat up. This type of heat treatment is sometimes called microwave annealing. Performing microwave processing in an oxygen-containing atmosphere can sometimes achieve effects equivalent to oxygen annealing. Furthermore, if the oxide 230 contains hydrogen, this thermal energy can be transferred to the hydrogen in the oxide 230, potentially causing activated hydrogen to be released from the oxide 230.

[0375] Furthermore, when the insulator 250 is made into a two-layer laminated structure as shown in Figure 6(B), the insulating film that will become the insulator 250b should be deposited after the insulating film 250A has been deposited. The insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable that the insulating film be formed using an insulator that has the function of suppressing oxygen diffusion. With this configuration, the diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen contained in the insulator 250a can be suppressed. The insulating film can be made using the same material as the insulator 222. For example, a hafnium oxide film can be deposited as the insulating film by thermal ALD.

[0376] Microwave treatment may be performed after the deposition of insulating film 252A (before the deposition of insulating film 250A). The microwave treatment may use the same microwave treatment conditions as those used after the deposition of insulating film 250A. Alternatively, microwave treatment may be performed after the deposition of insulating film 252A without performing the microwave treatment after the deposition of insulating film 250A. Furthermore, if an insulating film that will become an insulator 250b is provided as described above, microwave treatment may be performed after the deposition of this insulating film. The microwave treatment may use the same microwave treatment conditions as those used after the deposition of insulating film 250A. Alternatively, microwave treatment may be performed after the deposition of the insulating film that will become an insulator 250b without performing the microwave treatment after the deposition of insulating film 252A and / or insulating film 250A.

[0377] Furthermore, after microwave treatment performed after the deposition of insulating film 252A, after the deposition of insulating film 250A, and after the deposition of the insulating film that becomes the insulator 250b, a heat treatment may be performed while maintaining a reduced pressure state. By performing such treatment, hydrogen can be efficiently removed from insulating film 252A, insulating film 250A, insulating film that becomes the insulator 250b, and oxide 230. In addition, some of the hydrogen may be gettered by the conductor 242. Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after microwave treatment may be repeated multiple times. By repeating the heat treatment, hydrogen can be removed even more efficiently from insulating film 252A, insulating film 250A, insulating film that becomes the insulator 250b, and oxide 230. The heat treatment temperature is preferably 300°C to 500°C. Furthermore, the above microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230 and other components are sufficiently heated by microwave annealing, the heat treatment may not be necessary.

[0378] Furthermore, by performing microwave treatment to modify the film quality of the insulating film 252A, insulating film 250A, and insulating film 250b, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, by subsequent processes such as deposition of a conductive film that becomes the conductor 260, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., to the oxide 230, etc., via the insulating film 252 can be suppressed.

[0379] Next, the insulating film 254A is deposited (see Figures 13(A) to 13(D)). The insulating film 254A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulating film 254A using the ALD method, similar to the insulating film 252A. By using the ALD method, the insulating film 254A can be deposited with a thin film thickness and good coverage. In this embodiment, a silicon nitride film is deposited as the insulating film 254A using the PEALD method.

[0380] Next, a conductive film to become conductor 260a and a conductive film to become conductor 260b are deposited in sequence. The conductive films to become conductor 260a and conductor 260b can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, a titanium nitride film is deposited as the conductive film to become conductor 260a using the ALD method, and a tungsten film is deposited as the conductive film to become conductor 260b using the CVD method.

[0381] Next, by CMP treatment, insulating films 252A, 250A, 254A, the conductive film that will become conductor 260a, and the conductive film that will become conductor 260b are polished until the insulator 280 is exposed, thereby forming insulators 252, 250, 254, and conductor 260 (conductor 260a and conductor 260b) (see Figures 14(A) to 14(D)). As a result, insulator 252 is positioned to cover the opening that reaches the oxide 230. Conductor 260 is also positioned to fill the opening via insulators 252, 250, and 254.

[0382] Next, a heat treatment may be performed under the same conditions as the heat treatment described above. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400°C for 1 hour. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 250 and insulator 280. After the heat treatment, the insulator 282 may be deposited continuously without exposure to the atmosphere.

[0383] Next, insulators 282 are formed on insulators 252, 250, 254, 260, and 280 (see Figures 14(A) to 14(D)). The insulator 282 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulator 282 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0384] In this embodiment, aluminum oxide is deposited as the insulator 282 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0385] Furthermore, by using the sputtering method to deposit the insulator 282 in an oxygen-containing atmosphere, oxygen can be added to the insulator 280 during film formation. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0386] Next, an insulator 283 is formed on the insulator 282. The insulator 283 can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. It is preferable to deposit the insulator 283 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. The insulator 283 may also be multilayered. For example, silicon nitride may be deposited using sputtering, and then silicon nitride may be deposited on the silicon nitride using the ALD method. By providing a highly barrier insulator 283 on the transistor 200, it is possible to prevent moisture and hydrogen from entering from the outside.

[0387] Next, an insulator 285 is formed on the insulator 283 (see Figures 15(A) to 15(D)). The insulator 285 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulator 285 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced.

[0388] In this embodiment, silicon oxide is deposited as the insulator 285 by sputtering.

[0389] Next, openings reaching the conductor 242 are formed in insulators 271, 275, 280, 282, 283, and 285 (see Figures 15(A) and 15(B)). These openings may be formed using lithography. In Figure 15(A), the shape of the opening is shown as circular in a top view, but it is not limited to this. For example, the opening may be approximately circular, such as an ellipse, polygonal, such as a quadrilateral, or a polygonal shape with rounded corners, such as a quadrilateral, in a top view.

[0390] Next, insulating films to form insulators 241a and 241b are deposited, and the insulating films are anisotropically etched to form insulator 241 (see Figure 15(B)). The insulating films can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, it is preferable to deposit an aluminum oxide film using the ALD method, and then deposit a silicon nitride film on top of it using the PEALD method. Silicon nitride is preferred because it has high blocking properties for hydrogen.

[0391] Furthermore, for the anisotropic etching of the insulating films that will become insulators 241a and 241b, a dry etching method, for example, may be used. By providing insulators 241 on the side walls of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductor 240 that will be formed next can be prevented. In addition, impurities such as water and hydrogen contained in the insulator 280 can be prevented from diffusing into the conductor 240.

[0392] Next, conductive films that will become conductor 240a and conductor 240b are formed. It is desirable that the conductive films have a laminated structure that includes a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. The conductive films can be formed using sputtering, CVD, MBE, PLD, ALD, etc.

[0393] Next, by performing CMP treatment, a portion of the conductive film that will become conductors 240a and 240b is removed, exposing the upper surface of the insulator 285. As a result, the conductive film remains only in the openings, making it possible to form conductors 240a and 240b with flat upper surfaces (see Figures 15(A) to 15(D)). Note that this CMP treatment may remove a portion of the upper surface of the insulator 285.

[0394] Next, conductive films that will become conductors 246a and 246b are deposited. These conductive films can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD.

[0395] Next, conductive films that will become conductors 246a and 246b are processed by lithography to form conductor 246a in contact with the upper surface of conductor 240a, and conductor 246b in contact with the upper surface of conductor 240b. At this time, a portion of the insulator 285 in the region where conductors 246a and 246b do not overlap with the insulator 285 may be removed.

[0396] Based on the above, a semiconductor device having the transistor 200 shown in Figures 1(A) to 1(D) can be fabricated. As shown in Figures 7(A) to 15(D), the transistor 200 can be fabricated by using the semiconductor device fabrication method shown in this embodiment.

[0397] <Microwave Processing Equipment> The following describes a microwave processing apparatus that can be used in the manufacturing method of the semiconductor device described above.

[0398] First, we will explain the configuration of a manufacturing equipment that minimizes the inclusion of impurities during the manufacturing of semiconductor devices and other equipment, using Figures 16 to 19.

[0399] Figure 16 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric substrate supply chamber 2701 equipped with a cassette port 2761 for housing substrates and an alignment port 2762 for aligning substrates; an atmospheric substrate transport chamber 2702 for transporting substrates from the atmospheric substrate supply chamber 2701; a load lock chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unload lock chamber 2703b for unloading substrates and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transport chamber 2704 for transporting substrates in a vacuum; and chambers 2706a, 2706b, 2706c, and 2706d.

[0400] Furthermore, the atmospheric substrate transport chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transport chamber 2704, and the transport chamber 2704 is connected to chambers 2706a, 2706b, 2706c, and 2706d.

[0401] Furthermore, gate valves GV are provided at the connection points of each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transport chamber 2702. In addition, a transport robot 2763a is provided in the atmospheric substrate transport chamber 2702, and a transport robot 2763b is provided in the transport chamber 2704. Transport robots 2763a and 2763b can transport substrates within the manufacturing apparatus 2700.

[0402] The back pressure (total pressure) in the transport chamber 2704 and each chamber is, for example, 1 × 10⁻⁶. -4 Pa or less, preferably 3 × 10 -5 Pa or less, more preferably 1 × 10⁻⁶ -5 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with an m / z of 28 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5 Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with an m / z of 44 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5 Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 It should be Pa or less.

[0403] The total pressure and partial pressure in the transport chamber 2704 and each chamber can be measured using an ionization vacuum gauge, mass spectrometer, etc.

[0404] Furthermore, it is desirable that the transport chamber 2704 and each chamber be configured to minimize external or internal leaks. For example, the leak rate of the transport chamber 2704 should be 1 × 10⁻⁶. 0 Pa / min or less, preferably 5 × 10 -1 The pressure should be less than or equal to Pa / min. Furthermore, the leak rate of each chamber should be 1 × 10⁻⁶. -1 Pa / min or less, preferably 5 × 10 -2 The rate should be less than or equal to Pa / min.

[0405] The leak rate can be derived from the total pressure and partial pressure measured using an ionization vacuum gauge, mass spectrometer, etc. For example, it can be derived from the total pressure 10 minutes after starting vacuuming with a vacuum pump such as a turbomolecular pump, and the total pressure 10 minutes after closing the valve. The total pressure 10 minutes after starting vacuuming should be the average value obtained by measuring the total pressure multiple times.

[0406] The leak rate depends on both external and internal leaks. External leaks occur when gas enters from outside the vacuum system due to tiny holes, faulty seals, etc. Internal leaks are caused by leaks from valves or other partitions within the vacuum system, or by the release of gas from internal components. To keep the leak rate below the aforementioned values, countermeasures must be taken from both external and internal leaks.

[0407] For example, the opening and closing parts of the conveying chamber 2704 and each chamber may be sealed with metal gaskets. Preferably, the metal gaskets are made of metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets offer better adhesion than O-rings, reducing external leakage. Furthermore, using a passivated metal coated with iron fluoride, aluminum oxide, or chromium oxide suppresses the release of impurity-containing gases from the metal gasket, thereby reducing internal leakage.

[0408] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit less impurity-containing gas, are used as components of the manufacturing apparatus 2700. Alternatively, the aforementioned metals that emit less impurity-containing gas may be used as a coating on an alloy containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and suitable for processing. Here, reducing the surface area by reducing surface irregularities of the components through polishing or other means can reduce the emission of gas.

[0409] Alternatively, the components of the aforementioned manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0410] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when installing viewing windows made of quartz or the like, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, etc., to suppress the release of gases.

[0411] The adsorbed substances present in the transport chamber 2704 and each chamber do not affect the pressure in the transport chamber 2704 and each chamber because they are adsorbed onto the inner walls, but they cause gas release when the transport chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust rate, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed substances present in the transport chamber 2704 and each chamber as possible and evacuate them in advance. In addition, the transport chamber 2704 and each chamber may be baked to promote the desorption of adsorbed substances. Baking can increase the desorption rate of adsorbed substances by about 10 times. Baking should be performed at a temperature between 100°C and 450°C. At this time, if the adsorbed substances are removed while introducing an inert gas into the transport chamber 2704 and each chamber, the desorption rate of water and other substances that are difficult to desorb by exhaust alone can be further increased. In addition, the desorption rate of adsorbed substances can be further increased by heating the introduced inert gas to the same temperature as the baking temperature. It is preferable to use a noble gas as the inert gas here.

[0412] Alternatively, it is preferable to increase the pressure in the transport chamber 2704 and each chamber by introducing an inert gas such as a heated noble gas or oxygen, and then exhaust the transport chamber 2704 and each chamber again after a certain period of time. By introducing a heated gas, adsorbed substances can be removed from the transport chamber 2704 and each chamber, and impurities present in the transport chamber 2704 and each chamber can be reduced. This process is most effective when repeated 2 to 30 times, preferably 5 to 15 times. Specifically, the pressure in the transport chamber 2704 and each chamber can be set to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa by introducing an inert gas or oxygen with a temperature of 40°C to 400°C, preferably 50°C to 200°C, and the period for maintaining the pressure should be 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Subsequently, the transport chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0413] Next, chambers 2706b and 2706c will be explained using the schematic cross-sectional diagrams shown in Figure 17.

[0414] Chambers 2706b and 2706c are chambers capable of performing microwave processing on an object to be processed. The only difference between chambers 2706b and 2706c is the atmosphere used during microwave processing. Other configurations are common to both chambers, and will therefore be described together below.

[0415] Chambers 2706b and 2706c each have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Outside of chambers 2706b and 2706c, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0416] The high-frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is positioned in contact with the dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is then supplied to chambers 2706b and 2706c through a gas pipe 2806 that passes through the mode converter 2805, waveguide 2807, and dielectric plate 2809. The vacuum pump 2817 has the function of exhausting gas and other substances from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to the substrate holder 2812 via a matching box 2815.

[0417] The substrate holder 2812 has the function of holding the substrate 2811. For example, it has the function of electrostatically or mechanically chucking the substrate 2811. It also functions as an electrode to which power is supplied from the high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has the function of heating the substrate 2811.

[0418] As the vacuum pump 2817, for example, a dry pump, mechanical booster pump, ion pump, titanium sublimation pump, cryopump, or turbomolecular pump can be used. In addition to the vacuum pump 2817, a cryotrap may also be used. Using a cryopump and cryotrap is particularly preferable because it allows for efficient water removal.

[0419] Furthermore, the heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element. Alternatively, it may be a heating mechanism that heats by heat conduction or thermal radiation from a heated medium such as a gas. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heat treatment using a high-temperature gas. An inert gas is used as the gas.

[0420] Furthermore, the gas supply source 2801 may be connected to the purifier via a mass flow controller. It is preferable to use a gas with a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and noble gases (such as argon gas) may be used.

[0421] For example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used as the dielectric plate 2809. Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Since the dielectric plate 2809 will be exposed to particularly high-density regions of the high-density plasma 2810 described later, providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0422] The high-frequency generator 2803 has the function of generating microwaves in frequencies such as 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. The microwaves are then transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with multiple slot holes, and the microwaves pass through these slot holes and the dielectric plate 2809. This generates an electric field below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the type of gas supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0423] At this time, the ions and radicals generated in the high-density plasma 2810 can modify the film on the substrate 2811. It is preferable to apply a bias to the substrate 2811 using the high-frequency power supply 2816. For example, the high-frequency power supply 2816 can be an RF (Radio Frequency) power supply with frequencies such as 13.56 MHz or 27.12 MHz. By applying a bias to the substrate, the ions in the high-density plasma 2810 can efficiently reach deep into the openings of the film on the substrate 2811.

[0424] For example, oxygen radical treatment using high-density plasma 2810 can be performed by introducing oxygen from gas supply source 2801 in chamber 2706b or chamber 2706c.

[0425] Next, chambers 2706a and 2706d will be explained using the schematic cross-sectional diagrams shown in Figure 18.

[0426] Chambers 2706a and 2706d are chambers capable of irradiating the workpiece with electromagnetic waves, for example. The only difference between chambers 2706a and 2706d is the type of electromagnetic wave they emit. Since many other components are common to both, they will be described together below.

[0427] Chambers 2706a and 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Outside of chambers 2706a and 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0428] The gas supply source 2821 is connected to the gas inlet 2823 via valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 via valve 2829. The lamp 2820 is positioned opposite the substrate holder 2825. The substrate holder 2825 has the function of holding the substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has the function of heating the substrate 2824.

[0429] For lamp 2820, for example, a light source having the function of emitting electromagnetic waves such as visible light or ultraviolet light may be used. For example, a light source having the function of emitting electromagnetic waves with peaks in wavelengths of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0430] For example, lamp 2820 can be a light source such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp.

[0431] For example, electromagnetic waves emitted from the lamp 2820 can be partially or entirely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be created or reduced, or impurities can be removed. Furthermore, if the substrate 2824 is heated during the process, the creation or reduction of defects or the removal of impurities can be performed more efficiently.

[0432] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have a heating mechanism 2826 inside.

[0433] For vacuum pump 2828, refer to the description for vacuum pump 2817. For heating mechanism 2826, refer to the description for heating mechanism 2813. For gas supply source 2821, refer to the description for gas supply source 2801.

[0434] The microwave processing apparatus that can be used in this embodiment is not limited to the one described above. The microwave processing apparatus 2900 shown in Figure 19 can be used. The microwave processing apparatus 2900 has a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas pipe 2806, a vacuum pump 2817, and a valve 2818. The microwave processing apparatus 2900 also has a substrate holder 2902 inside the quartz tube 2901 that holds a plurality of substrates 2811 (2811_1 to 2811_n, where n is an integer of 2 or more). The microwave processing apparatus 2900 may also have a heating means 2903 on the outside of the quartz tube 2901.

[0435] Microwaves generated by the high-frequency generator 2803 are irradiated onto a substrate placed inside the quartz tube 2901 via the waveguide 2804. The vacuum pump 2817 is connected to the exhaust port 2819 via the valve 2818, and can adjust the pressure inside the quartz tube 2901. The gas supply source 2801 is connected to the gas pipe 2806 via the valve 2802, and can introduce a desired gas into the quartz tube 2901. The heating means 2903 can heat the substrate 2811 inside the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat the gas supplied from the gas supply source 2801. The microwave processing device 2900 can perform heating and microwave processing on the substrate 2811 simultaneously. Alternatively, the substrate 2811 can be heated first, followed by microwave processing, or the substrate 2811 can be microwaved first, followed by heating.

[0436] Substrates 2811_1 to 2811_n may all be processing substrates forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, substrates 2811_1 and 2811_n may be dummy substrates, and substrates 2811_2 to 2811_n-1 may be processing substrates. Alternatively, substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and substrates 2811_3 to 2811_n-2 may be processing substrates. Using dummy substrates is preferable because it allows multiple processing substrates to be processed uniformly during microwave processing or heat processing, reducing variations between processing substrates. For example, it is preferable to place dummy substrates on the processing substrates closest to the high-frequency generator 2803 and waveguide 2804, as this suppresses direct exposure of the processing substrates to microwaves.

[0437] By using the above manufacturing equipment, it becomes possible to modify the film while suppressing the inclusion of impurities in the processed material.

[0438] <Modified examples of semiconductor devices> In the following, an example of a semiconductor device, which is one embodiment of the present invention, will be described using Figures 20(A) to 20(D).

[0439] Figure 20(A) shows a top view of a semiconductor device. Figure 20(B) is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure 20(A). Figure 20(C) is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure 20(A). Figure 20(D) is a cross-sectional view corresponding to the area indicated by the dashed line A5-A6 in Figure 20(A). In the top view of Figure 20(A), some elements have been omitted for clarity.

[0440] In the semiconductor devices shown in Figures 20(A) to 20(D), structures having the same function as those constituting the semiconductor device shown in <Example of Semiconductor Device Configuration> are denoted by the same reference numerals. Furthermore, in this section as well, the materials used for the semiconductor device components are those described in detail in <Example of Semiconductor Device Configuration>.

[0441] The semiconductor devices shown in Figures 20(A) to 20(D) are modified versions of the semiconductor devices shown in Figures 1(A) to 1(D). The semiconductor devices shown in Figures 20(A) to 20(D) differ from those shown in Figures 1(A) to 1(D) in that they do not have an insulator 282. Therefore, in the semiconductor devices shown in Figures 20(A) to 20(D), the insulator 283 is in contact with the upper surface of the conductor 260, the upper surface of the insulator 280, the uppermost part of the insulator 254, the uppermost part of the insulator 250, and the uppermost part of the insulator 252.

[0442] For example, if sufficient oxygen can be supplied to the oxide 230 by microwave processing as shown in Figures 12(A) to 12(D), the region 230bc can be substantially made i-type without providing an insulator 282 and adding oxygen to the insulator 280. In such cases, as shown in Figures 20(A) to 20(D), by using a configuration without an insulator 282, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0443] Furthermore, the semiconductor devices shown in Figures 20(A) to 20(D) differ from those shown in Figures 1(A) to 1(D) in that the oxide 230 has a layered structure of oxide 230a and oxide 230b. The oxide 230 has oxide 230a disposed on the insulator 224 and oxide 230b disposed on oxide 230a.

[0444] Here, at the junction of oxide 230a and oxide 230b, the lower edge of the conduction band changes smoothly. In other words, the lower edge of the conduction band at the junction of oxide 230a and oxide 230b can be said to change continuously or form a continuous junction. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 230a and oxide 230b. By lowering the defect level density of the mixed layer, the influence of interfacial scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-current and high frequency characteristics.

[0445] For example, if oxide 230a and oxide 230b have a common element other than oxygen as their main component, a mixed layer with a low defect level density can be formed. For example, if oxide 230b is In-M-Zn oxide, oxide 230a may be In-M-Zn oxide, M-Zn oxide, an oxide of element M, In-Zn oxide, indium oxide, etc.

[0446] Furthermore, for example, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. By having oxide 230a below oxide 230b, the diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed.

[0447] Alternatively, for example, it is preferable that oxide 230a has crystalline properties. In particular, it is preferable to use CAAC-OS as oxide 230a. For example, it is preferable to use a metal oxide with a large atomic ratio of zinc to the main metal element. By adopting this configuration, the crystallinity of oxide 230b provided on oxide 230a can be further improved. Therefore, as described above, the transistor 200 can be made stable with respect to the thermal budget.

[0448] Specifically, for oxide 230a, you may use a metal oxide with a composition of Ga:Zn=2:1 [atomic ratio] or nearby, a metal oxide with a composition of Ga:Zn=2:5 [atomic ratio] or nearby, a metal oxide with a composition of In:M:Zn=1:1:2 [atomic ratio] or nearby, or a metal oxide with a composition of In:M:Zn=4:2:3 [atomic ratio] or nearby. Similarly, for oxide 230b, you may use a metal oxide with a composition of In:M:Zn=2:6:5 [atomic ratio] or nearby, a metal oxide with a composition of In:M:Zn=1:3:4 [atomic ratio] or nearby, a metal oxide with a composition of In:M:Zn=1:1:1 [atomic ratio] or nearby, or a metal oxide with a composition of In:M:Zn=1:4:5 [atomic ratio] or nearby. Note that nearby compositions include a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0449] Figures 20(B) and 20(C) show examples in which regions 230ba, 230bb, and 230bc are formed in oxide 230b, but the present invention is not limited to these examples. For instance, each of the above regions may be formed not only in oxide 230b but also in oxide 230a.

[0450] Furthermore, while the semiconductor devices shown in Figures 1(A) to 1(D) and Figures 20(A) to 20(D) show configurations in which the oxide 230 of the transistor 200 is provided as a single-layer or two-layer stacked structure, the present invention is not limited to these. For example, a configuration with a stacked structure of three or more layers may be provided, or the oxide 230b may have a stacked structure.

[0451] Furthermore, the semiconductor devices shown in Figures 20(A) to 20(D) differ from those shown in Figures 1(A) to 1(D) in that they are provided with oxide 243a and oxide 243b. Oxide 243a is provided between oxide 230b and conductor 242a, and oxide 243b is provided between oxide 230b and conductor 242b. Here, it is preferable that oxide 243a is in contact with the upper surface of oxide 230b and the lower surface of conductor 242a. It is also preferable that oxide 243b is in contact with the upper surface of oxide 230b and the lower surface of conductor 242b.

[0452] It is preferable that oxides 243a and 243b have the function of suppressing oxygen permeation. Placing oxide 243a (oxide 243b), which has the function of suppressing oxygen permeation, between the conductor 242a (conductor 242b), which functions as a source electrode or drain electrode, and the oxide 230 is preferable because it reduces the electrical resistance between the conductor 242a (conductor 242b) and the oxide 230. With such a configuration, it may be possible to improve the electrical characteristics, field effect mobility, and reliability of the transistor 200.

[0453] Furthermore, metal oxides containing element M may be used as oxides 243a and 243b. In particular, element M may be aluminum, gallium, yttrium, or tin. It is also preferable that oxides 243a and 243b have a higher concentration of element M than oxides 230b. Gallium oxide may also be used as oxides 243a and 243b. Furthermore, metal oxides such as In-M-Zn oxide may be used as oxides 243a and 243b. Specifically, it is preferable that the atomic ratio of element M to In in the metal oxide used for oxides 243a and 243b is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. The film thickness of oxides 243a and 243b is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. It is also preferable that oxides 243a and 243b are crystalline. When oxides 243a and 243b are crystalline, the release of oxygen from oxide 230 can be effectively suppressed. For example, if oxides 243a and 243b have a crystalline structure such as a hexagonal crystal, the release of oxygen from oxide 230 can be suppressed.

[0454] <Examples of semiconductor device applications> In the following, an example of a semiconductor device, which is one embodiment of the present invention, will be described using Figures 21(A) to 21(C).

[0455] Figure 21(A) shows a top view of the semiconductor device 500. The x-axis in Figure 21(A) is taken parallel to the channel length direction of the transistor 200, and the y-axis is taken perpendicular to the x-axis. Figure 21(B) is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure 21(A), and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 21(C) is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure 21(A), and is also a cross-sectional view of the aperture region 295 and its vicinity. Note that some elements have been omitted from the top view in Figure 21(A) for clarity.

[0456] In the semiconductor devices shown in Figures 21(A) to 21(C), structures having the same function as those constituting the semiconductor devices shown in <Examples of Semiconductor Device Configurations> are denoted by the same reference numerals. Furthermore, in this section as well, the materials used for the semiconductor devices are those described in detail in <Examples of Semiconductor Device Configurations>.

[0457] The semiconductor device 500 shown in Figures 21(A) to 21(C) is a modified example of the semiconductor device shown in Figures 1(A) to 1(D). The semiconductor device 500 shown in Figures 21(A) to 21(C) differs from the semiconductor device shown in Figures 1(A) to 1(D) in that a sealing portion 265 is formed thereon. It also differs from the semiconductor device shown in Figures 1(A) to 1(D) in that an opening region 295 is formed in the insulator 282 and the insulator 280. Furthermore, it differs from the semiconductor device shown in Figures 1(A) to 1(D) in that the sealing portion 265 is formed so as to surround a plurality of transistors 200.

[0458] The semiconductor device 500 has a plurality of transistors 200 and a plurality of aperture regions 295 arranged in a matrix. A plurality of conductors 260, which function as gate electrodes for the transistors 200, are provided extending in the y-axis direction. The aperture regions 295 are formed in areas that do not overlap with the oxide 230 and the conductors 260. Furthermore, a sealing portion 265 is formed to surround the plurality of transistors 200, the plurality of conductors 260, and the plurality of aperture regions 295. Note that the number, arrangement, and size of the transistors 200, conductors 260, and aperture regions 295 are not limited to the structure shown in Figure 21(A), but can be appropriately set according to the design of the semiconductor device 500.

[0459] As shown in Figures 21(B) and 21(C), the sealing portion 265 is provided so as to surround the multiple transistors 200, insulators 216, 222, 275, 280, and 282. In other words, insulator 283 is provided so as to cover insulators 216, 222, 275, 280, and 282. In the sealing portion 265, insulator 283 is in contact with the upper surface of insulator 214. Also in the sealing portion 265, insulator 274 is provided between insulator 283 and insulator 285. The upper surface of insulator 274 is approximately the same height as the uppermost surface of insulator 283. Furthermore, the same type of insulator as insulator 280 can be used for insulator 274.

[0460] This structure allows multiple transistors 200 to be enclosed by insulators 283, 214, and 212. Here, it is preferable that one or more of insulators 283, 214, and 212 function as a barrier insulating film against hydrogen. This prevents hydrogen contained outside the sealing portion 265 from mixing into the sealing portion 265.

[0461] As shown in Figure 21(C), the insulator 282 has an opening in the opening region 295. In addition, the insulator 280 may have a groove in the opening region 295 that overlaps with the opening of the insulator 282. The depth of the groove in the insulator 280 should not exceed the depth at which the upper surface of the insulator 275 is exposed, for example, it should be between 1 / 4 and 1 / 2 of the maximum film thickness of the insulator 280.

[0462] Furthermore, as shown in Figure 21(C), the insulator 283 is in contact with the side surface of the insulator 282, the side surface of the insulator 280, and the upper surface of the insulator 280 inside the opening region 295. In addition, a portion of the insulator 274 may be formed within the opening region 295 to fill the recess formed in the insulator 283. In this case, the height of the upper surface of the insulator 274 formed within the opening region 295 may be approximately the same as the height of the uppermost surface of the insulator 283.

[0463] By forming such an opening region 295 and performing a heat treatment with the insulator 280 exposed through the opening in the insulator 282, oxygen can be supplied to the oxide 230 while a portion of the oxygen contained in the insulator 280 can be diffused outward from the opening region 295. This ensures that sufficient oxygen is supplied from the insulator 280 containing oxygen that is released by heating to the region in the oxide semiconductor layer that functions as a channel-forming region and its vicinity, while preventing the supply of an excessive amount of oxygen.

[0464] At this time, the hydrogen contained in the insulator 280 can combine with oxygen and be released to the outside through the opening region 295. The hydrogen combined with oxygen is released as water. Therefore, the amount of hydrogen contained in the insulator 280 can be reduced, and the mixing of hydrogen contained in the insulator 280 into the oxide 230 can be reduced.

[0465] Furthermore, although the shape of the aperture region 295 in a top view in Figure 21(A) is approximately rectangular, the present invention is not limited to this. For example, the shape of the aperture region 295 in a top view may be rectangular, elliptical, circular, rhombus, or a combination thereof. Also, the area and spacing of the aperture region 295 can be appropriately set according to the design of the semiconductor device including the transistors 200. For example, in areas with a low density of transistors 200, the area of ​​the aperture region 295 can be increased, or the spacing of the aperture region 295 can be decreased. Also, for example, in areas with a high density of transistors 200, the area of ​​the aperture region 295 can be decreased, or the spacing of the aperture region 295 can be increased.

[0466] The insulator 283 may be in contact with a portion of the upper surface of the insulator 212. In this case, the transistor 200 is placed within the region sealed by the insulator 283 and the insulator 212. This configuration makes it possible to suppress the ingress of hydrogen contained outside the sealed region into the sealed region.

[0467] Furthermore, while Figures 21(A) to 21(C) show a transistor 200 in which the insulator 212 and the insulator 283 are provided as single layers, the present invention is not limited to this. For example, the insulator 212 and the insulator 283 may each be provided as a laminated structure of two or more layers.

[0468] According to one aspect of the present invention, a novel transistor can be provided. Alternatively, according to one aspect of the present invention, a transistor with reduced characteristic degradation due to stray light and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a display device with reduced degradation of transistor characteristics due to stray light and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a display device with stable pixel operation can be provided.

[0469] Alternatively, according to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good reliability and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption and a method for manufacturing the same can be provided.

[0470] The configurations and methods described in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments and examples described herein.

[0471] (Embodiment 2) This embodiment describes an example of the configuration of a display device according to one aspect of the present invention.

[0472] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used in the display section of wearable devices that can be worn on the head, such as information terminals (wearable devices) such as wristwatches and bracelets, as well as VR devices such as head-mounted displays and AR devices such as glasses.

[0473] [Display Module] Figure 22(A) shows a perspective view of the display module 400. The display module 400 includes a display device 410A and an FPC 420. Note that the display device included in the display module 400 is not limited to the display device 410A, but may also be the display device 410B described later.

[0474] The display module 400 has substrates 421 and 422. The display module 400 has a display section 431. The display section 431 is an area in the display module 400 that displays an image, and is an area in which light from each pixel provided in the pixel section 434, which will be described later, can be seen.

[0475] Figure 22(B) shows a schematic perspective view illustrating the configuration of the substrate 421. On the substrate 421, a circuit section 432, a pixel circuit section 433 on the circuit section 432, and a pixel section 434 on the pixel circuit section 433 are stacked. In addition, a terminal section 435 for connecting to the FPC 420 is provided in the portion of the substrate 421 that does not overlap with the pixel section 434. The terminal section 435 and the circuit section 432 are electrically connected by a wiring section 436, which is composed of multiple wires.

[0476] The pixel section 434 has multiple pixels 434a arranged periodically. A magnified view of one pixel 434a is shown on the right side of Figure 22(B). The pixel 434a has light-emitting elements 440a, 440b, and 440c, each with a different emission color. The multiple light-emitting elements may be arranged in a stripe pattern as shown in Figure 22(B). A stripe pattern allows for a high-density arrangement of pixel circuits, thus providing a high-resolution display device. Furthermore, various arrangement methods such as delta and pentile patterns can be applied.

[0477] The pixel circuit section 433 has a plurality of pixel circuits 433a arranged periodically.

[0478] A single pixel circuit 433a is a circuit that controls the light emission of the three light-emitting elements of a single pixel 434a. A single pixel circuit 433a may be configured to have three circuits that control the light emission of a single light-emitting element. For example, a single pixel circuit 433a may have at least one selection transistor, one current control transistor (drive transistor), and a capacitive element for each light-emitting element. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to either the source or the drain. This realizes an active-matrix type display device.

[0479] The circuit section 432 has circuits for driving each pixel circuit 433a of the pixel circuit section 433. For example, it is preferable to have one or both of a gate line drive circuit and a source line drive circuit. In addition, it may have at least one of the following: an arithmetic circuit, a memory circuit, and a power supply circuit.

[0480] The FPC420 functions as wiring for supplying video signals or power potential, etc., to the circuit section 432 from an external source. An IC may also be mounted on the FPC420.

[0481] The display module 400 can be configured such that one or both of the pixel circuit section 433 and the circuit section 432 are stacked on the lower side of the pixel section 434, thereby enabling an extremely high aperture ratio (effective display area ratio) of the display section 431. For example, the aperture ratio of the display section 431 can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. Furthermore, it is possible to arrange the pixels 434a at an extremely high density, enabling an extremely high resolution of the display section 431. For example, it is preferable that the pixels 434a in the display section 431 are arranged with a resolution of 20000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and with a resolution of 20000 ppi or less, or 30000 ppi or less.

[0482] Because such a display module 400 is extremely high-resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration where the display part of the display module 400 is viewed through lenses, the display module 400 has an extremely high-resolution display part 431, so even when the display part is magnified with lenses, pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 400 is not limited to this, and can be suitably used in electronic devices with relatively small display parts. For example, it can be suitably used in the display part of wearable electronic devices such as watches.

[0483] [Display device 410A] The display device 410A shown in Figure 23 includes a substrate 341, light-emitting elements 440a, 440b, 440c, a capacitor 330, and a transistor 320.

[0484] Transistor 320 is a transistor in which a metal oxide (also called an oxide semiconductor) is applied to the semiconductor layer where the channel is formed. Transistor 200, as described in Embodiment 1, can be used as transistor 320. For the configuration and effects of transistor 320, refer to the configuration examples of transistor 200 shown in Figures 1(A) to 1(D), etc.

[0485] Substrate 341 corresponds to substrate 421 in Figures 22(A) and 22(B). Substrate 341 can be an insulating substrate or a semiconductor substrate.

[0486] An insulating layer 361 is provided on the substrate 341. The insulating layer 361 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing from the substrate 341 to the transistor 320, and to prevent oxygen from detaching from the metal oxide present in the transistor 320 to the insulating layer 361. As the insulating layer 361, for example, a film that is less susceptible to hydrogen or oxygen diffusion than a silicon oxide film can be used, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0487] Insulating layers 365 and 367 are provided, covering the transistor 320 and insulating layer 363. Insulating layer 363 corresponds to the insulator 280 described in Embodiment 1.

[0488] Insulating layers 363 and 367 function as interlayer insulating layers. Insulating layer 365 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the transistor 320 from insulating layer 367, etc. An insulating film similar to that used for insulating layer 361 can be used for insulating layer 365.

[0489] The plug 362, which is electrically connected to one of the source and drain of the transistor 320, is provided so as to be embedded in the insulating layers 367, 365, and 363. The plug 362 is configured to have a conductive layer as a single layer or a laminated structure of two or more layers. When the plug 362 has a configuration in which two conductive layers are laminated, it is preferable to use a conductive material that does not easily allow hydrogen and oxygen to diffuse as the conductive layer that covers the side surfaces of the openings provided in the insulating layers 367, 365, and 363, etc., and a part of the upper surface of one of the source and drain of the transistor 320. With this configuration, it is possible to suppress the mixing of impurities such as water or hydrogen from the insulating layer 363, etc., into the metal oxide of the transistor 320 through the plug 362. In addition, it is possible to suppress the absorption of oxygen contained in the insulating layer 363 into the plug 362.

[0490] Furthermore, an insulating layer 369 is provided in contact with the side surface of the plug 362. In other words, the insulating layer 369 is provided in contact with the inner wall of the openings provided in the insulating layer 367, insulating layer 365, and insulating layer 363, etc., and the plug 362 may be provided in contact with the side surface of the insulating layer 369 and a part of the upper surface of one of the source and drain of the transistor 320. Note that the insulating layer 369 may not be provided in some cases.

[0491] Transistor 320 can be used as a transistor that constitutes a pixel circuit. Furthermore, transistor 320 can be used as a transistor that constitutes various circuits, such as arithmetic circuits or memory circuits.

[0492] An insulating layer 367 is provided to cover the transistor 320, and a capacitor 330 is provided on the insulating layer 367. The capacitor 330 and the transistor 320 are electrically connected by a plug 362.

[0493] The capacitor 330 has a conductive layer 331, a conductive layer 335, and an insulating layer 333 located between them. The conductive layer 331 functions as one electrode of the capacitor 330, the conductive layer 335 functions as the other electrode of the capacitor 330, and the insulating layer 333 functions as the dielectric of the capacitor 330.

[0494] The conductive layer 331 is provided on the insulating layer 367 and embedded in the insulating layer 371. The conductive layer 331 is electrically connected to either the source or drain of the transistor 320 by a plug 362 embedded in the insulating layer 367, etc. The insulating layer 333 is provided covering the conductive layer 331. The conductive layer 335 is provided in the region that overlaps with the conductive layer 331 via the insulating layer 333.

[0495] An insulating layer 373 is provided covering the capacitance 330, and light-emitting elements 440a, 440b, 440c, etc. are provided on the insulating layer 373. A protective layer 456 is provided on the light-emitting elements 440a, 440b, and 440c, and a substrate 460 is bonded to the upper surface of the protective layer 456 by a resin layer 459. An insulator is provided in the region between adjacent light-emitting elements. In Figure 23, an insulating layer 125 and an insulating layer 127 on the insulating layer 125 are provided in this region. The substrate 460 corresponds to the substrate 422 in Figures 22(A) and 22(B).

[0496] In this embodiment, an example is shown where the display device is a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting device is formed. However, it may also be a bottom-emission type that emits light towards the substrate on which the light-emitting device is formed, or a dual-emission type that emits light on both sides.

[0497] The light-emitting elements 440a, 440b, and 440c are preferably organic EL elements (organic electroluminescent elements). For example, light-emitting element 440a is a light-emitting element that emits red (R) light, light-emitting element 440b is a light-emitting element that emits green (G) light, and light-emitting element 440c is a light-emitting element that emits blue (B) light. In this case, the display device 410A can be realized as a full-color display device by having three types of light-emitting elements that emit red (R), green (G), and blue (B) light. Although Figure 23 illustrates a configuration in which the display device 410A has three colors of light-emitting elements, it is not limited to this, and it may also have a single color, two colors, or four or more colors of light-emitting elements.

[0498] A light-emitting element has an EL layer between a pair of electrodes. In this specification, one of the pair of electrodes may be referred to as the pixel electrode and the other as the common electrode. Of the pair of electrodes in the light-emitting device, one electrode functions as the anode and the other electrode functions as the cathode. In the following, we will explain using the case where the pixel electrode functions as the anode and the common electrode functions as the cathode as an example.

[0499] The light-emitting element 440a includes a pixel electrode 111a on the insulating layer 373, an island-shaped first layer 113a on the pixel electrode 111a, a fourth layer 114 on the island-shaped first layer 113a, and a common electrode 115 on the fourth layer 114. In the light-emitting element 440a, the first layer 113a and the fourth layer 114 can be collectively called the EL layer.

[0500] The light-emitting element 440b has a pixel electrode 111b, a second layer 113b, a fourth layer 114, and a common electrode 115. The light-emitting element 440c has a pixel electrode 111c, a third layer 113c, a fourth layer 114, and a common electrode 115.

[0501] When the light-emitting element is observed in cross-section, the side surface of the lower electrode (pixel electrode) and the side surface of the light-emitting layer have a region that coincides or roughly coincides. Furthermore, when viewed from above, the upper surface shape of the lower electrode and the upper surface shape of the light-emitting layer coincide or roughly coincide.

[0502] In this specification, "side view roughly matches" and "top view roughly matches" mean that, when viewed from above, at least a portion of the contours of the upper and lower layers overlap. This includes, for example, cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in these cases, too, the terms "side view roughly matches" and "top view roughly matches" are used.

[0503] Each color of light-emitting element shares the same film as a common electrode. The common electrode 115, which is common to all colored light-emitting elements, is electrically connected to wiring provided below it via a plug 372 (not shown). As a result, the same potential is supplied to the common electrode of each colored light-emitting element.

[0504] The pixel electrodes of the light-emitting element are electrically connected to either the source or drain of the transistor 320 by plugs 372 embedded in the insulating layer 373, a conductive layer 331 embedded in the insulating layer 371, and plugs 362 embedded in the insulating layer 367, etc. The height of the upper surface of the insulating layer 373 and the height of the upper surface of the plugs 372 are equal or approximately equal. Various conductive materials can be used for the plugs.

[0505] Details of the light-emitting element will be described in Embodiment 3.

[0506] Here, when differentiating EL layers between light-emitting elements of different colors, it is known that they are formed by a vapor deposition method using a shadow mask such as a metal mask. However, with this method, deviations from the design occur in the shape and position of the island-like organic film due to various influences such as the precision of the metal mask, the misalignment between the metal mask and the substrate, the deflection of the metal mask, and the spreading of the contour of the deposited film due to vapor scattering, making it difficult to achieve high resolution and high aperture ratio. For this reason, measures have been taken to artificially increase resolution (also called pixel density) by applying special pixel arrangement methods such as pentile arrangements.

[0507] For example, the EL layer can be processed into a fine pattern without using a shadow mask such as a metal mask. This makes it possible to realize a display device with high resolution and a large aperture ratio, which was previously difficult to achieve. Furthermore, because the EL layer can be manufactured in different ways, it is possible to realize a display device that is extremely vivid, has high contrast, and displays high quality.

[0508] Here, for simplicity, we will explain the case where two different EL layers are created for two-color light-emitting elements. First, a first EL film and a first sacrificial film are laminated and formed, covering the two pixel electrodes. Next, a resist mask is formed on the first sacrificial film at a position overlapping one of the pixel electrodes (the first pixel electrode). Then, the resist mask, a portion of the first sacrificial film, and a portion of the first EL film are etched. At this point, the etching is stopped when the other pixel electrode (the second pixel electrode) is exposed. As a result, a portion of the first EL film (also called the first EL layer), processed into a strip or island shape, and a portion of the sacrificial film (also called the first sacrificial layer) are formed on the first pixel electrode. The sacrificial film may also be called a mask film.

[0509] Next, the second EL film and the second sacrificial film are laminated together. Then, a resist mask is formed at the position overlapping with the first pixel electrode and the position overlapping with the second pixel electrode. Subsequently, the resist mask, a portion of the second sacrificial film, and a portion of the second EL film are etched in the same manner as above. As a result, the first EL layer and the first sacrificial layer are provided on the first pixel electrode, and the second EL layer and the second sacrificial layer are provided on the second pixel electrode. In this way, the first EL layer and the second EL layer can be created separately. Finally, the first and second sacrificial layers are removed, exposing the first and second EL layers, and then a common electrode is formed to create two different colored light-emitting elements. The sacrificial layer may also be called a mask layer.

[0510] Furthermore, by repeating the above process, it is possible to create EL layers with three or more light-emitting elements, thereby realizing a display device having three or four or more light-emitting elements.

[0511] Here, in order to supply potential to the common electrode, an electrode (also called a first electrode or connecting electrode) can be provided on the same plane as the pixel electrode and electrically connected to the common electrode. The connecting electrode is positioned outside the display section on which the pixels are provided. Here, in order to prevent the upper surface of the connecting electrode from being exposed to etching when the first EL film is etched, it is preferable to provide a first sacrificial layer on the connecting electrode as well. Similarly, when etching the second EL film, it is preferable to provide a second sacrificial layer on the connecting electrode. The first and second sacrificial layers provided on the connecting electrode can be removed by etching simultaneously with the first sacrificial layer on the first EL layer and the second sacrificial layer on the second EL layer.

[0512] While it is difficult to reduce the spacing between different colored EL layers to less than 10 μm using, for example, a metal mask formation method, the above method allows for narrowing the spacing to 3 μm or less, 2 μm or less, or even 1 μm or less. For example, by using an exposure apparatus for LSIs, the spacing can be narrowed to 500 nm or less, 200 nm or less, 100 nm or less, and even 50 nm or less. This significantly reduces the area of ​​the non-emitting region that may exist between two light-emitting elements, making it possible to approach an aperture ratio of 100%. For example, an aperture ratio of 50% or more, 60% or more, 70% or more, 80% or more, and even 90% or more, can be achieved, and even less than 100%.

[0513] Furthermore, the pattern of the EL layer itself can be made extremely small compared to when a metal mask is used. Also, for example, when a metal mask is used to create different EL layers, variations in thickness occur between the center and edges of the pattern, so the effective area that can be used as an emitting region is small relative to the total area of ​​the pattern. On the other hand, with the above manufacturing method, the pattern is formed by processing a film deposited to a uniform thickness, so the thickness can be made uniform within the pattern, and even if the pattern is fine, almost the entire area can be used as an emitting region. Therefore, with the above manufacturing method, it is possible to achieve both high resolution and a high aperture ratio.

[0514] Thus, the above manufacturing method makes it possible to realize a display device that integrates fine light-emitting elements. Therefore, there is no need to apply special pixel arrangement methods such as the pentile method to artificially increase the resolution. Thus, it is possible to realize a display device with a resolution of 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or even 5000 ppi or more, using a so-called stripe arrangement in which R, G, and B are each arranged in one direction.

[0515] The sides of each of the pixel electrodes 111a, 111b, 111c, the first layer 113a, the second layer 113b, and the third layer 113c are covered by insulating layers 125 and 127. A fourth layer 114 is provided on the first layer 113a, the second layer 113b, the third layer 113c, the insulating layer 125, and the insulating layer 127, and a common electrode 115 is provided on the fourth layer 114.

[0516] By using the above configuration, it is possible to suppress the fourth layer 114 (or common electrode 115) from coming into contact with any of the sides of the pixel electrode 111a, pixel electrode 111b, pixel electrode 111c, the first layer 113a, the second layer 113b, and the third layer 113c, thereby suppressing a short circuit in the light-emitting element.

[0517] The insulating layer 125 preferably covers at least the sides of the pixel electrodes 111a, 111b, and 111c. Furthermore, it is preferable that the insulating layer 125 covers the sides of the first layer 113a, the second layer 113b, and the third layer 113c. The insulating layer 125 can be configured to be in contact with each of the sides of the pixel electrodes 111a, 111b, 111c, the first layer 113a, the second layer 113b, and the third layer 113c.

[0518] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses formed in the insulating layer 125. The insulating layer 127 can be configured to overlap with the sides of each of the pixel electrodes 111a, 111b, 111c, the first layer 113a, the second layer 113b, and the third layer 113c via the insulating layer 125.

[0519] Furthermore, it is not necessary to provide either the insulating layer 125 or the insulating layer 127. If the insulating layer 125 is not provided, the insulating layer 127 can be configured to be in contact with the respective sides of the first layer 113a, the second layer 113b, and the third layer 113c. The display device may also have an insulating layer that covers the ends of the pixel electrodes. In this case, one or both of the insulating layer 125 and the insulating layer 127 may be provided on the insulating layer.

[0520] The fourth layer 114 and the common electrode 115 are provided on the first layer 113a, the second layer 113b, the third layer 113c, the insulating layer 125, and the insulating layer 127. Before the insulating layers 125 and 127 are provided, a step difference exists due to the region where the pixel electrode and EL layer are provided and the region where the pixel electrode and EL layer are not provided (the region between the light-emitting elements). In one embodiment of the present invention, the presence of the insulating layers 125 and 127 can flatten this step difference and improve the coverage of the fourth layer 114 and the common electrode 115. Therefore, connection failures due to step breaks can be suppressed. Alternatively, it is possible to suppress the local thinning of the common electrode 115 due to the step difference, which would increase its electrical resistance.

[0521] To improve the flatness of the formation surfaces of the fourth layer 114 and the common electrode 115, it is preferable that the heights of the upper surfaces of the insulating layer 125 and the insulating layer 127 match or approximately match the height of at least one of the upper surfaces of the first layer 113a, the second layer 113b, and the third layer 113c, respectively. Furthermore, it is preferable that the upper surface of the insulating layer 127 has a flat shape, but it may have convex or concave portions.

[0522] The insulating layer 125 has regions that are in contact with the sides of the first layer 113a, the second layer 113b, and the third layer 113c, and functions as a protective insulating layer for the first layer 113a, the second layer 113b, and the third layer 113c. By providing the insulating layer 125, it is possible to suppress the intrusion of impurities (oxygen, moisture, etc.) into the interior from the sides of the first layer 113a, the second layer 113b, and the third layer 113c, thereby enabling a highly reliable display device.

[0523] If the width (thickness) of the insulating layer 125 in the region in contact with the sides of the first layer 113a, the second layer 113b, and the third layer 113c is large in a cross-sectional view, the spacing between the first layer 113a, the second layer 113b, and the third layer 113c may increase, resulting in a lower aperture ratio. Conversely, if the width (thickness) of the insulating layer 125 in the region in contact with the sides of the first layer 113a, the second layer 113b, and the third layer 113c is small in a cross-sectional view, the effect of suppressing the intrusion of impurities into the interior from the sides of the first layer 113a, the second layer 113b, and the third layer 113c may be reduced. In a cross-sectional view, the width (thickness) of the insulating layer 125 in the region in contact with the sides of the first layer 113a, the second layer 113b, and the third layer 113c is preferably 3 nm to 200 nm, more preferably 3 nm to 150 nm, more preferably 5 nm to 150 nm, more preferably 5 nm to 100 nm, more preferably 10 nm to 100 nm, and more preferably 10 nm to 50 nm. By setting the width (thickness) of the insulating layer 125 within the above range, a display device with a high aperture ratio and high reliability can be obtained.

[0524] The insulating layer 125 can be an insulating layer having an inorganic material. For example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxidative nitride insulating films, and nitride oxide insulating films can be used for the insulating layer 125. The insulating layer 125 may be a single layer or a laminated structure. Examples of oxide insulating films include silicon oxide film, aluminum oxide film, magnesium oxide film, indium gallium zinc oxide film, gallium oxide film, germanium oxide film, yttrium oxide film, zirconium oxide film, lanthanum oxide film, neodymium oxide film, hafnium oxide film, and tantalum oxide film. Examples of nitride insulating films include silicon nitride film and aluminum nitride film. Examples of oxidative nitride insulating films include silicon oxidative nitride film and aluminum oxidative nitride film. Examples of nitride oxide insulating films include silicon nitride oxide film and aluminum nitride oxide film. In particular, aluminum oxide is preferred because it has a high selectivity ratio with the EL layer during etching and has the function of protecting the EL layer during the formation of the insulating layer 127, which will be described later. In particular, by applying inorganic insulating films such as aluminum oxide films, hafnium oxide films, and silicon oxide films formed by the ALD method to the insulating layer 125, it is possible to form an insulating layer 125 with fewer pinholes and excellent function in protecting the EL layer.

[0525] In this specification, the term "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and the term "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0526] The insulating layer 125 can be formed using sputtering, CVD, PLD, ALD, or other methods. It is preferable to form the insulating layer 125 using the ALD method, which provides good coverage.

[0527] The insulating layer 127 provided on the insulating layer 125 has the function of flattening the recess in the insulating layer 125 formed between adjacent light-emitting devices. In other words, the presence of the insulating layer 127 improves the flatness of the surface on which the common electrode 115 is formed. As the insulating layer 127, an insulating layer having an organic material can be suitably used. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimidoamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins can be applied as the insulating layer 127. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can be used as the insulating layer 127. Furthermore, a photosensitive resin (also referred to as an organic resin) can be used as the insulating layer 127. Photoresist may be used as the photosensitive resin. The photosensitive resin can be either a positive-type or negative-type material.

[0528] The difference between the height of the upper surface of the insulating layer 127 and the height of the upper surface of any of the first layer 113a, the second layer 113b, and the third layer 113c is preferably 0.5 times or less the thickness of the insulating layer 127, and more preferably 0.3 times or less. Alternatively, the insulating layer 127 may be provided such that the upper surface of any of the first layer 113a, the second layer 113b, and the third layer 113c is higher than the upper surface of the insulating layer 127. Alternatively, the insulating layer 127 may be provided such that the upper surface of the insulating layer 127 is higher than the upper surface of the light-emitting layer of the first layer 113a, the second layer 113b, or the third layer 113c.

[0529] [Display device 410B] The display device 410B shown in Figure 24 differs from the display device 410A mainly in its transistor configuration. Note that explanations of parts similar to those of the display device 410A may be omitted.

[0530] Substrate 301 corresponds to substrate 421 in Figures 22(A) and 22(B).

[0531] The transistor 310 is a transistor having a channel-forming region in the substrate 301. The substrate 301 can be a semiconductor substrate such as a single-crystal silicon substrate. The transistor 310 comprises a portion of the substrate 301, a conductive layer 311, a pair of low-resistance regions 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The pair of low-resistance regions 312 are regions of the substrate 301 doped with impurities and function as a source and drain. The insulating layer 314 covers the sides of the conductive layer 311 and functions as an insulating layer.

[0532] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301.

[0533] An insulating layer 351 is provided covering the transistor 310, and a conductive layer 354 is provided on the insulating layer 351. The conductive layer 354 is electrically connected to either the source or drain of the transistor 310 by a plug 352 embedded in the insulating layer 351. An insulating layer 353 is provided covering the conductive layer 354, and a conductive layer 356 is provided on the insulating layer 353. The conductive layers 354 and 356 each function as wiring. An insulating layer 355 and an insulating layer 361 are provided covering the conductive layer 356, and a transistor 320 is provided on the insulating layer 361.

[0534] Transistor 310 can be used as a transistor constituting a pixel circuit, or as a transistor constituting a drive circuit (gate line drive circuit, source line drive circuit) for driving the pixel circuit. Transistor 310 can also be used as a transistor constituting various circuits such as arithmetic circuits or memory circuits.

[0535] This configuration allows for the formation of not only pixel circuits but also drive circuits and other components directly beneath the light-emitting element, making it possible to miniaturize the display device compared to cases where the drive circuits are located around the display area.

[0536] [Example of pixel circuit configuration] The following describes an example of a pixel circuit configuration applicable to a display device according to one aspect of the present invention.

[0537] The pixel circuit PIX1 shown in Figure 25(A) includes transistors M1 and M2, capacitor C1, and light-emitting element EL. Wirings SL, GL, AL, and CL are electrically connected to the pixel circuit PIX1.

[0538] Transistor M1's gate is electrically connected to wiring GL, one of its source and drain is electrically connected to wiring SL, and the other of its source and drain is electrically connected to the gate of transistor M2 and one of the electrodes of capacitor C1. Transistor M2's source and drain are electrically connected to wiring AL, and the other of its source and drain is electrically connected to the anode of light-emitting element EL. Capacitor C1's other electrode is electrically connected to the anode of light-emitting element EL. Light-emitting element EL's cathode is electrically connected to wiring CL.

[0539] Transistor M1 can also be called a selection transistor and functions as a switch to control the selection and deselection of pixels. Transistor M2 can also be called a drive transistor and has the function of controlling the current flowing to the light-emitting element EL. Capacitor C1 functions as a holding capacitor and has the function of holding the gate potential of transistor M2. Capacitor C1 may be a capacitive element such as an MIM capacitor, or the capacitance between the wiring or the gate capacitance of the transistor may be used as capacitor C1.

[0540] The source signal is supplied to wiring SL. The gate signal is supplied to wiring GL. Constant potentials are supplied to wiring AL and wiring CL, respectively. The anode side of the light-emitting element EL can be made to a high potential, and the cathode side to a lower potential than the anode side.

[0541] The pixel circuit PIX2 shown in Figure 25(B) is configured by adding transistor M3 to the pixel circuit PIX1. Wiring V0 is also electrically connected to the pixel circuit PIX2.

[0542] Transistor M3 has its gate electrically connected to wiring GL, and one of its source and drain is electrically connected to the anode of the light-emitting element EL, while the other is electrically connected to wiring V0.

[0543] Wiring V0 provides a constant potential when writing data to the pixel circuit PIX2. This suppresses variations in the gate-source voltage of transistor M2.

[0544] The pixel circuit PIX3 shown in Figure 25(C) is an example where transistors with a pair of electrically connected gates are applied to transistors M1 and M2 of the pixel circuit PIX1. Similarly, the pixel circuit PIX4 shown in Figure 25(D) is an example where the same transistors are applied to the pixel circuit PIX2. This increases the current that the transistors can supply. Here, transistors with a pair of electrically connected gates are used for all transistors, but this is not the only option. Alternatively, transistors with a pair of gates that are electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates and the source are electrically connected.

[0545] The pixel circuit PIX5 shown in Figure 26(A) is configured by adding transistor M4 to the pixel circuit PIX2. Furthermore, three wires (wires GL1, GL2, and GL3) that function as gate wires are electrically connected to the pixel circuit PIX5.

[0546] Transistor M4 has its gate electrically connected to wiring GL3, and one of its source and drain is electrically connected to the gate of transistor M2, while the other is electrically connected to wiring V0. Also, the gate of transistor M1 is electrically connected to wiring GL1, and the gate of transistor M3 is electrically connected to wiring GL2.

[0547] By simultaneously making transistors M3 and M4 conduct, the source and gate of transistor M2 become at the same potential, making transistor M2 non-conducting. This allows the current flowing to the light-emitting element EL to be forcibly interrupted. Such a pixel circuit is suitable for display methods that alternate between display periods and off periods.

[0548] The pixel circuit PIX6 shown in Figure 26(B) is an example of adding capacitor C2 to the pixel circuit PIX5. Capacitor C2 has one electrode electrically connected to the gate of transistor M2 and the other electrode connected to wiring AL. Capacitor C2 functions as a retaining capacitor.

[0549] The pixel circuit PIX7 shown in Figure 26(C) is an example of applying a pair of gate transistors to the pixel circuit PIX5. The pixel circuit PIX8 shown in Figure 26(D) is an example of applying a pair of gate transistors to the pixel circuit PIX6. Transistors M1, M3, and M4 are transistors with a pair of gates electrically connected, while transistor M2 is a transistor in which one of the gates is electrically connected to the source.

[0550] [Vsh's acceptable level of degradation] The transistor M1 shown in Figures 25(A) to 26(D) needs to retain the charge stored in capacitors C1 and C2 for a long period of time. In other words, normally-off characteristics are required for transistor M1. The following describes the allowable degradation of Vsh of transistor M1 for normal pixel operation.

[0551] Here, we calculate the allowable degradation limit of Vsh for transistor M1 based on the pixel circuit PIX8 shown in Figure 26(D).

[0552] First, the I of transistor M1 required to hold the charge stored in capacitors C1 and C2. off The calculation method will be explained.

[0553] The basic formula for capacitors is shown below as equation (1).

[0554]

number

[0555] In equation (1) above, Q is the retained charge of capacitors C1 and C2, C is the combined capacitance of capacitors C1 and C2, V is the voltage change, and t is the retention time. Here, I off Assuming there is no time dependence, equation (1) can be considered as equation (2).

[0556]

number

[0557] The voltage change V can be calculated from equation (3), assuming that it is equivalent to the total gradation width GR of the source line.

[0558]

number

[0559] In equation (3) above, Vgs1 is the gate-source voltage under all-white conditions, and Vgs2 is the gate-source voltage under all-black conditions. Using the voltage change V calculated from equation (3) and equation (2), the I of transistor M1 required to hold the charge stored in capacitor C1 is calculated. off It is possible to calculate this.

[0560] Next, we will explain how to calculate the Vsh required for transistor M1 under the all-black condition. Hereafter, the Vsh required for transistor M1 under the all-black condition will be denoted as Vsh1.

[0561] Under the all-black condition, transistor M1 is suggested to be in the subthreshold region. In this case, it is presumed that the subthreshold leak becomes the dominant term of Ioff. The subthreshold leak is calculated from equation (4).

[0562]

number

[0563] In equation (4), Vsh1 is the gate-source voltage Vgs when the drain current Id is 1 pA, Vdd is the gate-source voltage Vgs2 under all-black conditions, and SS is the subthreshold slope. Note that equation (4) can be replaced with equation (5).

[0564]

number

[0565] Vsh1 can be calculated using equation (5).

[0566] Here, an example of the specifications for the pixel circuit PIX8 is shown in Table 4.

[0567] [Table 4]

[0568] Using the specifications of the pixel circuit PIX8 shown in Table 4 and equation (3), the voltage change V is calculated to be 0.0127V. Furthermore, using the calculated voltage change V and equation (2), the I of transistor M1 required to hold the charge accumulated in capacitors C1 and C2 is calculated. off is 1.17 × 10 -13A is calculated. Also, the I of transistor M1 required to hold the charge stored in the calculated capacitances C1 and C2 off Using equation (5), Vsh1 is estimated to be -0.407V.

[0569] The all-black condition is the minimum requirement for maintaining the charge stored in capacitors C1 and C2. Therefore, if the Vsh of transistor M1 is greater than or equal to Vsh1, it is presumed that the pixel operation of the pixel circuit PIX8 will be normal. Accordingly, it is preferable that the Vsh of transistor M1 is -0.4V or greater.

[0570] Vsh1 depends on the subthreshold slope SS. The subthreshold slope SS may increase depending on the temperature conditions in the NBTIS test, the thickness of the gate insulator, etc. If the subthreshold slope SS is 200mV / dec., Vsh1 is estimated to be -0.313V. Therefore, it is more preferable that the Vsh of transistor M1 is -0.3V or higher.

[0571] Based on the above, by using a transistor M1 with Vsh of -0.4V or higher, preferably -0.3V or higher, the pixel operation of the pixel circuit can be performed normally. Therefore, a display device can be provided in which the degradation of transistor characteristics due to stray light is reduced. Furthermore, a display device with stable pixel operation can be provided.

[0572] Furthermore, the transistor 200 described in Embodiment 1 can be applied to the transistor M1 of the pixel circuit PIX8 shown in Figure 26(D). In other words, if the Vsh of the transistor 200 described in Embodiment 1 is -0.4V or higher, preferably -0.3V or higher, the pixel operation of the pixel circuit can be said to be performed normally. Therefore, the Vsh of the transistor 200 described in Embodiment 1 is preferably -0.4V or higher, and may be more preferably -0.3V or higher.

[0573] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0574] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0575] (Embodiment 3) In this embodiment, a light-emitting element (also called a light-emitting device) that can be used in a display device according to one aspect of the present invention will be described.

[0576] <Example of light-emitting element configuration> As shown in Figure 27(A), the light-emitting element has an EL layer 23 between a pair of electrodes (lower electrode 21, upper electrode 25). The EL layer 23 can be composed of multiple layers, such as layer 4420, light-emitting layer 4411, and layer 4430. Layer 4420 may include, for example, a layer containing a material with high electron injection properties (electron injection layer) and a layer containing a material with high electron transport properties (electron transport layer). Light-emitting layer 4411 may include, for example, a light-emitting compound. Layer 4430 may include, for example, a layer containing a material with high hole injection properties (hole injection layer) and a layer containing a material with high hole transport properties (hole transport layer).

[0577] A configuration having a layer 4420, an emissive layer 4411, and a layer 4430 provided between a pair of electrodes can function as a single emissive unit, and in this specification, the configuration shown in Figure 27(A) is referred to as a single structure.

[0578] Furthermore, Figure 27(B) shows a modified example of the EL layer 23 of the light-emitting element 20 shown in Figure 27(A). Specifically, the light-emitting element 20 shown in Figure 27(B) has a layer 4430-1 on the lower electrode 21, a layer 4430-2 on layer 4430-1, a light-emitting layer 4411 on layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on layer 4420-1, and an upper electrode 25 on layer 4420-2. For example, when the lower electrode 21 is the anode and the upper electrode 25 is the cathode, layer 4430-...

Claims

1. It comprises first to fourth wirings, a light-emitting element, a first capacitor, a second capacitor, and first to fourth transistors. The first transistor has one source and drain electrically connected to the first wiring, the other source and drain electrically connected to one electrode of the first capacitor, and the gate electrically connected to the second wiring. The second transistor has one source and drain electrically connected to the anode of the light-emitting element, the other source and drain electrically connected to the third wiring, and the gate electrically connected to one electrode of the first capacitor. The third transistor has one source and drain electrically connected to the fourth wiring, and the other source and drain electrically connected to the anode of the light-emitting element. The fourth transistor has one source and drain electrically connected to the fourth wiring, and the other source and drain electrically connected to one electrode of the first capacitor. The first capacitance is such that the other electrode is electrically connected to the anode of the light-emitting element. The second capacitor has one electrode electrically connected to one electrode of the first capacitor, and the other electrode electrically connected to the third wiring. The first transistor has a metal oxide in the channel formation region. The aforementioned metal oxide has a band gap of 3.3 eV or more. The first transistor has a Vsh of -0.3V or higher. The Vsh is defined as the Vg at which the tangent line at the point where the slope of the drain current (Id)-gate voltage (Vg) curve of the first transistor is maximum intersects the straight line where Id = 1 pA. Display device.

2. In claim 1, The aforementioned metal oxide includes In, Ga, and Zn. The atomic ratio of In, Ga, and Zn is In:Ga:Zn = 2:6:5 or close to it. Display device.

3. A transistor having a metal oxide in the channel formation region, A first insulator and The second insulator on the first insulator, The metal oxide on the second insulator and, A first conductor and a second conductor on the metal oxide, The first insulator, the second insulator, the metal oxide, the first conductor, and the third insulator on the second conductor, A fourth insulator on the aforementioned metal oxide, The fifth insulator on the fourth insulator, The fifth insulator has a third conductor, The third insulator is superimposed on the region between the first conductor and the second conductor, and has an opening formed therein. The fourth insulator, the fifth insulator, and the third conductor are located within the opening. The aforementioned metal oxide has a band gap of 3.3 eV or more. The transistor has a Vsh of -0.3V or higher. The Vsh is defined as the Vg at which the tangent line at the point where the slope of the drain current (Id)-gate voltage (Vg) curve of the transistor is maximum intersects the straight line where Id = 1 pA. Transistor.

4. In claim 3, The aforementioned metal oxide includes In, Ga, and Zn. The atomic ratio of In, Ga, and Zn is In:Ga:Zn = 2:6:5 or close to it. Transistor.

5. In claim 3, The fifth insulator comprises silicon and oxygen, The fifth insulator has a nitrogen concentration of 5 × 10⁻¹⁶ obtained by SIMS. １９ atoms / cm ３ Having the following region: Transistor.

6. A transistor according to any one of claims 3 to 5, A display device having a light-emitting element electrically connected to the transistor, The light-emitting element comprises a lower electrode, an upper electrode, and a light-emitting layer provided between the lower electrode and the upper electrode. When the light-emitting element is observed in cross-section, the side surface of the lower electrode and the side surface of the light-emitting layer have a region that coincides or substantially coincides with it. Display device.

7. In claim 6, An insulator is provided between the light-emitting element and the adjacent light-emitting element. The insulator comprises either an inorganic material or an organic material, or both. Display device.

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