Superjunction power semiconductor device and method for manufacturing a superjunction power semiconductor device

Abstract

The present disclosure relates to a super-junction power semiconductor device (20) comprising a substrate (1), a plurality of core structures (4), and a plurality of annular shell structures (5). Each core structure (4) has a cylindrical shape extending in a direction perpendicular to a major surface of the substrate (1) and including a first semiconductor material of a first conductivity type. Each shell structure (5) surrounds one of the core structures (4) on its exterior and includes a second semiconductor material of a second conductivity type. The present disclosure further relates to a method (30) for manufacturing the super-junction power semiconductor device (20).

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices and methods of manufacturing the same, and more particularly to a novel approach including selectively grown superjunction nanostructures for power semiconductor devices.

Background Art

[0002] Wide bandgap (WBG) semiconductor materials such as silicon carbide (SiC) have advantageous properties including high critical electric fields and electron mobilities or high frequency switching. Thus, they result in a much larger Baliga figure-of-merit (BFOM) compared to commonly used semiconductor materials such as silicon, and are a good option for power semiconductor devices such as power MISFETs. These advantages enable several applications for energy efficiency and electrical transport.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Today, most commercially available power SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are based on a cell design having a planar channel aligned to the silicon (Si) face, i.e., the SiC(0001) wafer surface. However, an increase in current density in such switches is hindered due to an increase in junction-FET (JFET) resistance due to downscaling of the injector, as well as low inversion channel mobility.

[0004] As an alternative approach, trench MOSFETs containing dry-etched U-shaped channels enable the achievement of low on-resistance due to the absence of JFET regions and high cell density. Particularly for SiC channel devices, trench MOSFET architectures allow for optimization of carrier mobility by designing channels for different crystal planes and enhancing gate dielectric control. Despite utilizing different crystal planes for carrier transport, the trench pitch and cell width of known trench MOSFET devices remain considerably large when using conventional manufacturing techniques. This, in turn, hinders the higher cell density and therefore improved current density of the finished semiconductor power device. Furthermore, single-crystal SiC wafers are relatively expensive, further delaying the widespread adoption of the above techniques on a large scale.

[0005] Therefore, novel processing methods and device architectures that enable higher currents in a smaller area, i.e., improved current density, are desirable. Furthermore, it would be desirable to integrate such architectures into a wide range of widely available and competitively priced substrates, such as Si, gallium nitride (GaN), 4H-SiC, or polycrystalline SiC substrates. [Means for solving the problem]

[0006] Embodiments of this disclosure relate to a superjunction power semiconductor device comprising a substrate, a plurality of core structures, and a plurality of annular shell structures, and a method for manufacturing a superjunction power semiconductor device.

[0007] According to a first aspect of this disclosure, a superjunction power semiconductor device is provided. The device is circuit board and A plurality of core structures, each having a cylindrical shape extending in a direction perpendicular to the main surface of the substrate, and containing a first semiconductor material of a first conductivity type, Multiple annular shell structures, each shell structure surrounding one of the core structures on its outside, and containing a second semiconductor material of the second conductivity type, and It is equipped with.

[0008] The proposed device concept is based on vertically oriented, preferably very narrow, superjunction structures that can be selectively grown from suitable semiconductor materials, including WBG semiconductor materials. Due to their small size and vertical orientation, these structures are also called nanowires or nanopillars. Such superjunction structures far surpass conventional trench designs, and the proposed selective growth technique enables improved pitch scaling, i.e., higher currents in smaller areas, and integration into a variety of widely available substrates.

[0009] According to at least one embodiment, the device further comprises a dielectric layer disposed on the main surface of a substrate. Multiple shell structures enclosing multiple core structures are embedded in the dielectric layer. Embedding the superjunction structure within the dielectric layer has several advantages compared to conventional superjunction structures formed directly within bulk semiconductor material. Firstly, it reduces the amount of semiconductor material required to implement the device. Secondly, the individual superjunction structures are electrically insulated from one another. Thirdly, at least a portion of the dielectric layer can function as a growth template for creating core structures and / or annular shell structures, and / or as a support structure for bearing terminal contacts.

[0010] According to at least one embodiment, the dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is located between the substrate and the second sublayer and comprises a plurality of passages between them. The second sublayer includes at least the lower part of each of the plurality of shell structures. The device further comprises a plurality of plug structures, each plug structure comprising a third semiconductor material of a second conductivity type and located in a region of one of the passages so as to be in contact with the main surface of the substrate and one of the shell structures, respectively. The above structures enable electrical contact between the shell structures and the substrate of the device. Simultaneously, defect filters may be implemented using the passages.

[0011] According to at least one embodiment, the device further comprises a plurality of channel regions formed in each of the shell structures, each channel region comprising a fourth semiconductor material of a first conductivity type and located in a control layer of the device. The device further comprises at least one gate structure located in the control layer, the at least one gate structure being insulated from at least a portion of each of the shell structures and surrounding at least a portion of each of the shell structures. The device comprises a so-called gate-all-around structure that provides very high electric field control of the channel regions. The channel regions can be used to implement various known power semiconductor switching cells, such as MOSFETs.

[0012] According to different embodiments, the substrate may be one of Si, SiC, or GaN semiconductor substrates. The first semiconductor material is a p-type semiconductor material, in particular Si, or a p-type WBG semiconductor material, in particular SiC, GaN, or gallium oxide (Ga x O y ), may particularly include gallium trioxide (Ga2O3). The second semiconductor material may be an n-type semiconductor material, particularly Si, an n-type WBG semiconductor material, particularly SiC, GaN, Ga x O y It may also contain Ga2O3 or n-type diamond.

[0013] The above-mentioned substrate materials are widely available. At least some of them are considerably cheaper than single-crystal SiC wafers. Furthermore, specific semiconductor materials used for core end-cell structures are also widely available and can be processed with conventional semiconductor processing equipment.

[0014] According to different embodiments, the core structure and / or shell structure may extend over a length of 1 to 100 μm, particularly over a length of 3 to 15 μm, in a direction perpendicular to the main surface of the substrate. The core structure may have a diameter of 25 nm to 5 μm, particularly 0.1 to 5 μm. The annular cell structure may have a thickness of 0.1 to 5 μm. Multiple core structures may be arranged in a regular pattern, particularly in an array structure, with a pitch distance of less than 1 μm and in a range of 1.1 to 2.5 times the total diameter of one of the core structures surrounded by one of the shell structures.

[0015] The above dimensions and configuration are suitable for manufacturing high-density, high-voltage, and / or high-current semiconductor power switching devices. For example, lengths of 1 to 100 μm are suitable for mounting semiconductor switching devices having a switching voltage of 1.2 to 3.3 kV at the device level. Core structures with a diameter of about 25 nm are particularly suitable for heteroepitaxy, while larger diameters are suitable for higher current and / or homoepitaxy. Current density is also affected by the dopant concentration of the semiconductor material used. Preferably, the wall thickness of the shell structure may be similar to the diameter of the core structure and / or the diameter of any plug structure, for example, having an aspect ratio of 1:1.

[0016] In at least one embodiment, multiple core structures and / or shell structures are electrically connected in parallel to form a multi-cell field-effect transistor (FET), in particular a metal-insulator-semiconductor field-effect transistor (MISFET), a MOSFET, an insulated gate bipolar transistor (IGBT), and / or a JFET.

[0017] A second aspect of this disclosure provides a method for manufacturing a superjunction power semiconductor device. This method is To provide a growth substrate, By providing multiple vertical growth masks on the growth substrate, Selectively growing a first semiconductor material within multiple vertical growth masks to form multiple corresponding core structures in a direction perpendicular to the main surface of the growth substrate, To remove at least partially multiple vertical growth masks, thereby exposing the vertical surfaces of multiple core structures, By selectively growing a second semiconductor material on the vertical plane of multiple core structures, a corresponding number of shell structures are formed surrounding each core structure. Includes.

[0018] In particular, the method steps described above enable the fabrication of the core-shell superjunction structure detailed above with respect to a first embodiment, for example, to implement a nanowire-based superjunction power MOSFET.

[0019] For example, instead of processing devices using a conventional top-down approach, such as that used in the manufacture of conventional trench-gate MOSFETs, the manufacturing method of the present disclosure is based on a bottom-up approach based on selective epitaxy. This allows for the advantageous use of materials in forming high-density power devices, as described above with respect to the first embodiment.

[0020] Multiple vertical growth masks may be formed in a two-step process. In at least one embodiment, a growth seed mask layer having multiple first openings corresponding to the pitch distance between multiple core structures is formed first. Subsequently, a core structure mask layer having multiple second openings is formed, each of which is located in a region corresponding to each first opening and is wider than each first opening. Such a two-layer structure allows for the implementation of defect filters for a later selective growth stage. Furthermore, by using different materials for sublayers, for example, and selective etching, only the upper part of the vertical growth mask can be partially removed.

[0021] Similarly, the plurality of core structures may be formed in a two-step process. In at least one embodiment, in the first step, a plurality of plug structures are formed by selectively growing a third semiconductor material containing impurities of the first conductivity type, particularly n-type SiC, directly on a growth substrate within a plurality of vertical growth masks. Thereafter, as a separate step or within a continuous vertical growth process with a modified dopant profile, a main portion of the plurality of core structures is formed by selectively growing a first semiconductor material containing impurities of the second conductivity type, particularly p-type SiC, within the plurality of vertical growth masks.

[0022] In at least one embodiment, forming the plurality of shell structures includes covering the upper surfaces of the plurality of core structures with one of a growth inhibiting material, particularly silicon dioxide (SiO2), silicon nitride (SiN) or aluminum oxide (Al2O3), removing the upper portions of the plurality of vertical growth masks, particularly the core structure masks, such that the remaining lower portions of the plurality of vertical growth masks, particularly the growth seed masks, cover the growth substrate, and then forming the plurality of shell structures by selectively growing a second semiconductor material containing impurities of the first conductivity type, particularly n-type SiC, in a radial direction. The above steps enable controlled radial growth of the shell structures.

[0023] This disclosure includes some aspects of a novel architecture for high-density semiconductor devices, particularly superjunction power semiconductor devices. All features described with respect to one aspect are disclosed herein with respect to other aspects as well, even if each feature is not explicitly recited in the context of a particular aspect.

[0024] The accompanying drawings are included to provide further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals, even if they are part of different embodiments and / or have different configurations. It should be understood that the embodiments shown in the figures are exemplary representations and are not necessarily drawn to scale.

Brief Description of the Drawings

[0025] [Figure 1] This is a schematic cross-sectional view of a single cell of a power semiconductor switching device. [Figure 2] This is a perspective view of a power semiconductor device equipped with multiple nanopillars. [Figure 3A] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3B] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3C] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3D] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3E] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3F] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3G] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3H] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3I] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3J] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3K] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3L] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3M] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 3N] This illustrates the various stages in the manufacturing of power semiconductor devices. [Figure 4] The steps for manufacturing superjunction power semiconductor devices are shown in flowchart format. [Modes for carrying out the invention]

[0026] Figure 1 shows a cross-sectional view of cell 10 of a power semiconductor device or similar semiconductor device. A complete semiconductor device can typically consist of a relatively large number of similar cells electrically connected in parallel to achieve a desired function, including a desired current rating. However, for simplicity of representation, only a single cell 10 is shown in Figure 1 and will be described below.

[0027] Cell 10 includes a substrate 1, which acts as a carrier substrate and also provides an electrical bottom contact, as will be described later.

[0028] A dielectric layer 2 is disposed on the upper main surface of the substrate 1. The dielectric layer 2 may be formed from SiO2 or any other suitable insulating material. In the embodiments described herein, the dielectric layer 2 comprises several sublayers 2a to 2c, as will be described later.

[0029] A superjunction structure 3 is embedded in the dielectric layer 2. The superjunction structure 3 comprises a core structure 4 and a shell structure 5, the latter surrounding the former on the outside. In the embodiments described herein, the core structure 4 has a cylindrical shape surrounded by an annular shell structure. However, in other embodiments, an elongated, fin-shaped or stripe-shaped core structure 4 may be surrounded by the corresponding shell structure. When the superjunction structure 3 is essentially cylindrical, it is also called a nanowire or nanopillar.

[0030] The core structure 4 is made of a first semiconductor material, particularly a first conductivity type WBG semiconductor material such as p-type SiC. The shell structure 5 is made of a second semiconductor material of a different second conductivity type, such as n-type SiC. Preferably, the numerous charge carriers of the superjunction structure 3 balance each other.

[0031] The superjunction structure 3 further comprises a plug structure 6 at the lower end of the core structure 4. The plug structure 6 is made of a third semiconductor material of the second conductivity type. For example, the second and third semiconductor materials may be the same. The plug structure 6 electrically connects the material of the shell structure 5 to the material of the substrate 1. For this purpose, a relatively narrow passage or opening 13 is formed in the bottommost sublayer 2a of the dielectric layer 2. The opening 13 can also function as a defect filter for the semiconductor material of the superjunction structure 3 during the growth stage, as will be described later.

[0032] The superjunction structure 3 further comprises a channel region 7. The channel region 7 forms part of the shell structure 5. In the embodiment shown in Figure 1, the channel region 7 is located on top of the annular shell structure 5. The plane containing the channel region 7 is also called the control layer, as the channel region 7 can be used to control the flow of current through the superjunction structure 3. The thickness of the channel region 7 can be 100 nm to 1000 nm. This can be formed, for example, by implanting a suitable dopant species, such as Al or B, into the top of the shell structure 5 to form a p-type region within the n-type semiconductor material of the shell structure 5. This can be achieved, for example, by ion implantation.

[0033] The conductivity of the channel region 7 is controlled by the surrounding gate structure 8. The gate structure 8 should overlap the channel region 7 on both sides. Its thickness can be 200 nm to 1500 nm. In the illustrated embodiment, the gate structure 8 is embedded in the dielectric layer 2. In particular, it is located between its two upper sublayers 2b and 2c. The gate structure 8 is electrically insulated from the shell structure 5 containing the channel region 7 by a relatively thin gate insulator 9. For example, the gate insulator 9 may be formed by a film formed by selective oxidation or deposition of an insulating material.

[0034] A drain electrode 11 is formed on the lower second main surface of the substrate 1 to contact the upper and lower ends of the superjunction structure 3, respectively. In addition, a source electrode 12 is formed on the upper surface of the cell 10, including the upper surface of the uppermost sublayer 2c of the dielectric layer 2 and the upper end of the superjunction structure 3 itself.

[0035] Figure 2 shows a perspective view of a power semiconductor device 20 comprising a plurality of switching cells, such as the cell 10 described above with respect to Figure 1. The switching cells are arranged in a regular pattern, particularly in an array structure having a grid or pitch distance d. In the embodiments described herein, the pitch distance may be about 1 μm or less. Each cell comprises a superjunction structure 3 as detailed above. As previously mentioned, these take the form of nanowires or nanopillars. To achieve a high current density, the pitch distance d may be selected to be slightly larger than the total diameter of each superjunction structure 3, for example, having an aspect ratio of 1.1:1 to 2.5:1.

[0036] As seen in the front of Figure 2, a single cylindrical gate structure 8 surrounds each channel region of the superjunction structure 3. These so-called gate-all-around structures 8 are interconnected by a metal layer 15. As detailed above, the gate-all-around structures 8 are embedded between sublayers 2b and 2c formed from dielectric material. In the illustrated embodiment, the metal layer 15 is thinner than the vertical thickness of the gate-all-around structures 8. However, it may also have the same thickness, resulting in a uniform metal layer 15 that essentially acts as a common gate structure 8 for all the superjunction structures 3.

[0037] In the embodiment shown in Figure 2, the upper end of the superjunction structure 3 extends slightly over the upper surface of the topmost sublayer 2c of the dielectric material. These ends are directly embedded in the metallic material of the source electrode 12 formed thereon. Outside the array of superjunction structures 3, the dielectric material is even thicker, forming a termination region 16. A metallic layer 15 and a gate runner 17, which is used as an external contact for the gate structure 8, are formed on the upper surface of the termination region 16.

[0038] Figure 2 further illustrates that the substrate 1 may include multiple sublayers. In the illustrated embodiment, the lower sublayer 1a may be formed from a wafer material such as a silicon wafer. An epitaxial growth layer forms a second upper sublayer 1b on its upper surface. For example, polycrystalline SiC may be grown on the lower sublayer 1a as a seed material for growing a superjunction structure 3. In this case, the upper sublayer 1b removes growth defects. In other embodiments, the upper sublayer 1b itself may form part of the finished semiconductor device 20. For example, the upper sublayer 1b may act as part of a drift layer. In yet another embodiment, the upper sublayer 1b may be omitted entirely.

[0039] Figures 3A to 3N show various stages in the manufacturing of superjunction semiconductor devices, such as the superjunction power semiconductor device 20 shown in Figure 2.

[0040] In the first stage shown in Figure 3A, the substrate 1 is provided. As detailed above, the substrate 1 itself comprises two sublayers 1a and 1b. In the embodiments described herein, the first sublayer 1a is a silicon wafer. The sublayer 1b is an epitaxially grown silicon carbide layer. The substrate 1 is covered with a first dielectric layer 21. As shown in Figure 1, the first dielectric layer 21 covers the upper surface of the sublayer 1b of the substrate 1. The first dielectric layer 21 is silicon oxide, SiO2 x They may be essentially derived from SiO2, silicon nitride, SiN, or Al2O3, in particular.

[0041] As shown in Figure 3B, a portion of the first dielectric layer 21 may be removed to form a number of openings 13. The openings 13 may be formed at regular intervals to form an array or other regular structure on the upper surface of the substrate 1. Such openings 13 may be formed, for example, using conventional lithography. Alternatively, the dielectric material may be deposited only in the regions between the intended openings 13, for example, using a suitable selective deposition method. The material of the underlying substrate 1 or its uppermost sublayer 1b acts as a growth seed. In the embodiments described herein, the openings 13 may have a cross-section of 25 nm. Passages of this diameter effectively function as defect filters for selectively growing core structures on substrates containing different semiconductor materials and / or crystallographic configurations, for example, to grow a SiC superjunction structure on a Si wafer using heteroepitaxy. Thus, the first dielectric layer 21 is also referred to as a growth seed mask layer. If homoepitaxy is used to grow a SiC superjunction structure on a SiC wafer or epitaxial layer, for example, the openings 13 may be wider, for example, to correspond to the diameter of the core structure 4 that is later formed.

[0042] Figure 3C shows a further stage of the manufacturing process. At this stage, the top surface of the device under manufacture is covered with dielectric material to form a second dielectric layer 22. The second dielectric layer 22 is also called the core structure mask layer because it forms a growth mask for the actual core structure. The second dielectric layer 22 is made of SiO x These may essentially consist of SiO2, SiN, or Al2O3. If selective etching is employed later, the materials of the first dielectric layer 21 and the second dielectric layer may be different. The second dielectric layer 22 may be planarized using commonly known semiconductor processing methods.

[0043] Figure 3D shows the state after the material of the second dielectric layer 22 has been structured. This can be achieved, for example, using conventional lithography and selective etching. As seen in Figure 3D, several hollow vertical growth templates or masks 23 are formed. The vertical growth mask 23 includes the opening 13 of the first dielectric layer 21 and the wider opening 24 of the second dielectric layer 22. The vertical growth mask 23 is used to selectively grow a suitable semiconductor material, such as WBG semiconductor material, which later forms the core structure 4.

[0044] In the first selective growth stage shown in Figure 3E, the plug structure 6 is formed by selective regional epitaxy. This can be achieved, in particular, by selectively growing, i.e., depositing, the semiconductor material only inside the vertical growth mask 23, while growth is suppressed in other regions covered by the growth template material, namely the first dielectric layer 21 and the second dielectric layer 22.

[0045] As shown in the figure, the plug structure 6 is grown within the opening 13 of the first dielectric layer 21 and at the bottom of the opening 24 of the second dielectric layer 22. In the embodiment described herein, the plug structure 6 is formed by depositing n-type SiC material.

[0046] Subsequently, the remaining core structure 4 is grown on the upper end of the plug structure 6. The growth of the main portion 4a of the core structure 4 may be carried out as a separate selective growth step, or as a series of selective growth steps having a modified dopant profile. In the embodiments described herein, p-type semiconductor material is selectively grown to form the main portion 4a of the core structure 4. The completed core structure 4 is shown in Figure 3F.

[0047] In the situation shown in Figure 3G, the upper end of the core structure 4 is capped by a capping element 25. In the embodiments described herein, this is achieved by filling the remaining portion of the opening 24 of the second dielectric layer 22 with a dielectric material. The capping element 25 may be formed by depositing a growth-inhibiting material such as SiO2, SiN, or Al2O3.

[0048] Figure 3H shows the device under manufacture after the remaining material of the second dielectric layer 22 has been removed. This can be achieved, for example, by a selective etching process, which exposes each of the vertical surfaces 26 of the pre-formed core structure 4.

[0049] In the subsequent step shown in Figure 3I, the shell structure 5 grows radially outward, starting from each of the vertical planes 26. This step can be carried out again using a suitable selective growth method, either homoepitaxy, e.g., forming a SiC shell on a SiC core, or heteroepitaxy, e.g., forming a GaN shell on a SiC core, a diamond shell on a SiC core, or a SiC shell on a Si core. Since both the capping elements 25 and the first dielectric layer contain growth-inhibiting material, the shell structure 5 grows only on the vertical planes 26, but not on the first dielectric layer 21 covering the substrate 1, or on or to the sides of the capping elements 25. In the embodiments described herein, the shell structure 5 is grown using an n-type SiC material, thereby completing a plurality of superjunction structures 3 comprising a p-type core structure 4 and an n-type shell structure 5.

[0050] In the situation shown in Figure 3J, the capping element 25 is removed, for example, by selective etching.

[0051] Figure 3K shows the situation after the channel region 7 has been implanted into the shell structure 5. For this purpose, ions of a suitable species of the first conductivity type are implanted from the top surface of the superjunction structure 3. This is indicated by the dotted arrow shown in Figure 3K. Suitable species for p-type implantation include, for example, Al and B. Note that the additional charge carriers implanted by ion implantation do not significantly affect the electrical properties of the core structure 4. However, they overcompensate for the charge concentration in the shell structure 5, changing it from an n-type semiconductor material to a p-type semiconductor material.

[0052] In the subsequent processing state shown in Figure 3L, a third dielectric layer 27 can be formed and planarized. In the illustrated embodiment, a suitable dielectric layer is deposited in the region between the individual superjunction structures 3. The third dielectric layer 27 is SiO x It may essentially consist of SiO2, SiN, or Al2O3, in particular. It may also be the same material as the second dielectric layer 22. The third dielectric layer 27 serves as the base for a gate electrode that is formed later and corresponds to the second sublayer 2b in the embodiment shown in Figure 1.

[0053] The gate insulation structure 9 may be formed, for example, by selective oxidation or controlled deposition of a dielectric material on the exposed portion of the vertical surface 26 of the shell structure 5.

[0054] In the further processing step shown in Figure 3M, a metallic material is deposited on the upper surface of the third dielectric layer 27 and optionally planarized to form the gate structure 8. In the embodiments described herein, the gate structure 8 essentially covers the entire surface of the third dielectric layer 27, thereby forming the gate all-around structure 14 as shown in Figure 2.

[0055] In the situation shown in Figure 3N, the upper surface of the gate structure 8 is covered by the fourth dielectric layer 28, which corresponds to the third sublayer 2c in Figure 1. This completes the insulation of the gate structure 8, together with the third dielectric layer 27 and the gate insulator 9.

[0056] Subsequently, as shown in Figure 3N, the source electrode 12 may be formed on the flattened upper surface of the device under manufacture. Similarly, the drain electrode 11 may be formed on the opposite main surface of the substrate 1, i.e., on the back surface of the lower sublayer 1b (not shown in Figure 3N).

[0057] Figure 4 shows a method 30 for manufacturing a superjunction power semiconductor device, including steps S31 to S35.

[0058] In step S31, a growth substrate such as a substrate 1 having sublayers 1a and 1b is provided.

[0059] In step S32, a plurality of vertical growth masks 23 are formed on the growth substrate 1. This may be achieved by the method steps detailed above with respect to Figures 3A to 3d, or it may be carried out using additive manufacturing technology.

[0060] In step S33, the first semiconductor material is selectively grown within a plurality of vertical growth masks to form a plurality of corresponding core structures in a direction perpendicular to the main surface of the growth substrate. This can be carried out in one or more selective growth stages, as described above with respect to Figures 3E and 3F. For example, an n-type plug structure 6 may be formed first, followed by the formation of the p-type main portion 4a of the core structure.

[0061] In step S34, multiple vertical growth masks are removed at least partially, thereby exposing the vertical surfaces of multiple core structures. This can be achieved, for example, by a selective etching method as described above with respect to Figures 3G and 3H, or by other suitable methods such as controlling the length of the etching step to achieve material removal to a desired depth.

[0062] In step S35, a second semiconductor material, such as an n-type semiconductor material, is selectively grown on the pre-exposed vertical surfaces of the multiple core structures to form multiple shell structures surrounding each core structure. This effectively forms multiple superjunction structures. As described above with respect to Figure 3I, selective growth can be limited to desired surfaces by covering other surfaces with a dielectric material. Alternatively, the second semiconductor material may be grown on all surfaces of the device under fabrication, and any unwanted portions of the deposited second semiconductor material may be removed later.

[0063] For example, as described above with respect to Figures 3J to 3N, further process steps may follow to create additional functional areas within the created superbonded structure and / or metal-contact region.

[0064] Novel device architectures and manufacturing methods are described in relation to superjunction power semiconductor devices. However, the use of the architectures and manufacturing methods described herein is not limited to power semiconductor devices but can also be applied to other conventional cell-based, very high-density semiconductor devices. Such devices may include sensor arrangements such as photocells and image sensors, as well as other optical devices such as matrix displays.

[0065] It should be noted that the embodiments shown in Figures 1 to 4 above represent exemplary embodiments of the improved device structure and the method for its implementation only. They do not constitute a complete list of all embodiments of the improved device and method. Actual devices and manufacturing methods may differ from the embodiments described herein, for example, with respect to the materials used, processing steps and parameters, dimensions and circuit configuration. [Explanation of symbols]

[0066] Reference sign 1 circuit board 1a,1b Sublayers (of the substrate) 2 Dielectric layers 2a~2c Sublayers (of the dielectric layer) 3 Super-junction structure 4 Core Structure 4a Main part (of the core structure) 5. Shell structure 6 Plug Structure 7 Channel Area 8-gate structure 9 Gate insulator 10 cells 11 Drain electrode 12 Source electrodes 13 (First) Opening 15 metal layer 16 Termination area 17 Gaterunner 20 Power Semiconductor Devices 21. First dielectric layer (growth seed mask layer) 22 Second dielectric layer (core structure mask layer) 23 Vertical growth mask 24 (Second) Opening 25 Capping Elements 26 Vertical plane 27 Third Dielectric Layer 28. Fourth Dielectric Layer 30 Manufacturing method d Pitch distance

Claims

1. A superjunction power semiconductor device (20), Circuit board (1), A plurality of core structures (4), each having a cylindrical shape extending in a direction perpendicular to the main surface of the substrate (1), and containing a first semiconductor material of a first conductivity type, A plurality of annular shell structures (5), each annular shell structure (5) surrounding one of the core structures (4) on its outside, and comprising a second semiconductor material of the second conductivity type, A dielectric layer (2) disposed on the main surface of the substrate (1) and Equipped with, The plurality of annular shell structures (5) surrounding the plurality of core structures (4) are embedded within the dielectric layer (2). The dielectric layer (2) comprises at least a first sublayer (2a) and a second sublayer (2b), The first sublayer (2a) is disposed between the substrate (1) and the second sublayer (2b), and has a plurality of passages that penetrate the first sublayer (2a) in the thickness direction. A superjunction power semiconductor device (20) in which the second sublayer (2b) surrounds at least the lower part of each of the plurality of annular shell structures (5).

2. The superjunction power semiconductor device (20) further comprises a plurality of plug structures (6), each plug structure (6) comprising the third semiconductor material of the second conductivity type, and is positioned in one region of the passage so as to be in contact with the main surface of the substrate (1) and each of the plurality of annular shell structures (5). The superjunction power semiconductor device (20) according to claim 1.

3. A plurality of channel regions (7) formed in each of the plurality of annular shell structures (5), wherein each channel region (7) contains the fourth semiconductor material of the first conductivity type and is arranged within the control layer of the superjunction power semiconductor device (20), At least one gate structure (8) disposed within the control layer, wherein the at least one gate structure (8) is insulated from at least a portion of each of the plurality of annular shell structures (5) and surrounds at least a portion of each of the plurality of annular shell structures (5). A superjunction power semiconductor device (20) according to claim 1 or 2, further comprising:

4. The superjunction power semiconductor device (20) according to claim 3, wherein at least one gate structure (8) is embedded in a dielectric layer (2).

5. The substrate (1) is one of silicon (Si), single-crystal or polycrystalline silicon carbide (SiC), or gallium nitride (GaN) semiconductor substrates. The first semiconductor material includes a p-type semiconductor material or a p-type wide-bandgap (WBG) semiconductor material, and / or The second semiconductor material includes an n-type semiconductor material, an n-type WBG semiconductor material, or an n-type diamond. The superjunction power semiconductor device (20) according to claim 1 or 2.

6. The core structure (4) and / or the plurality of annular shell structures (5) extend over a length of 1 to 100 μm in a direction perpendicular to the main surface of the substrate (1). The core structure (4) has a diameter of 25 nm to 5 μm. The plurality of annular shell structures (5) have a thickness of 0.1 to 5 μm, and / or The plurality of core structures (4) are arranged in a regular pattern, and the pitch distance (d) is less than 1 μm and / or within the range of 1.1 to 2.5 times the total diameter of one of the core structures (4) surrounded by one of the plurality of annular shell structures (5). The superjunction power semiconductor device (20) according to claim 1 or 2.

7. A drain electrode (11) formed on the second main surface of the substrate (1), Source electrodes (12) formed on the dielectric layer (2) and interconnecting the upper ends of each of the plurality of core structures (4), and / or A gate electrode electrically connected to at least one gate structure (8) A superjunction power semiconductor device (20) according to claim 1 or 2, further comprising at least one of the above.

8. The superjunction power semiconductor device (20) according to claim 1 or 2, wherein the plurality of core structures (4) and / or the plurality of annular shell structures (5) are electrically connected in parallel to form a multi-cell field-effect transistor (FET), a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a junction-gate field-effect transistor (JFET).

9. A method (30) for manufacturing a superjunction power semiconductor device (20), wherein the method is Providing a growth substrate (1) (S31), Forming a plurality of vertical growth masks (23) on the growth substrate (1) (S32), The first semiconductor material is selectively grown within the plurality of vertical growth masks (23) to form a plurality of corresponding core structures (4) in a direction perpendicular to the main surface of the growth substrate (1) (S33), The plurality of vertical growth masks (23) are removed at least partially, thereby exposing the vertical surfaces (26) of the plurality of core structures (4) (S34), Selectively growing a second semiconductor material on the vertical surfaces (26) of the plurality of core structures (4) to form a plurality of corresponding annular shell structures (5) surrounding each of the plurality of core structures (4) (S35) Includes, Forming the plurality of vertical growth masks (23) (S32) The method involves forming a growth seed mask layer (21) having a plurality of first openings (13), wherein the plurality of first openings (13) have a distance corresponding to the pitch distance (d) between the plurality of core structures (4), The method involves forming a core structure mask layer (22) having a plurality of second openings (24), wherein each second opening (24) is located in a region corresponding to each of the plurality of first openings (13) and is wider than each of the plurality of first openings (13). Method (30), including the following.

10. Forming the aforementioned multiple core structures (4) A third semiconductor material containing a first conductivity type impurity is selectively grown directly on the growth substrate (1) within the plurality of vertical growth masks (23) to form a plurality of plug structures (6). Subsequently, the main portion (4a) of the plurality of core structures (4) is formed by selectively growing the first semiconductor material containing a second conductivity type impurity within the plurality of vertical growth masks (23). The method according to claim 9 (30), including the method according to claim 9.

11. Forming the aforementioned plurality of annular shell structures (5) Covering the upper surface of the plurality of core structures (4) with a growth-inhibiting material, The upper part of the plurality of vertical growth masks (23) is removed such that the remaining lower part of the plurality of vertical growth masks (23) covers the growth substrate (1), Subsequently, the plurality of annular shell structures (5) are formed by selectively growing the second semiconductor material containing the first conductivity type impurity in the radial direction. The method according to claim 10 (30), including the method according to claim 10.

12. The process involves injecting dopant species into the control layer of the superjunction power semiconductor device (20) to form channel regions (7) in each of the plurality of annular shell structures (5), In at least the region corresponding to the channel region (7), the outer surfaces of each of the plurality of annular shell structures (5) are electrically insulated, The method involves forming at least one gate structure (8) within the control layer, wherein the gate structure (8) surrounds the insulated channel region (7) of the plurality of annular shell structures (5). The method according to claim 9 or 10, further comprising (30).

13. In order to form a common drain electrode (11) for the superjunction power semiconductor device (20), a first conductive layer is deposited on the second main surface of the growth substrate (1). To provide a common gate structure (8) for the superjunction power semiconductor device (20), a second conductive layer is deposited on a planar first dielectric layer (27) surrounding the lower part of the plurality of annular shell structures (5), and / or In order to form a common source electrode (12) for the superjunction power semiconductor device (20), a third conductive layer is deposited on the upper surface of the second dielectric layer (28). The method according to claim 9 or 10 (30), further comprising at least one of the above.

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