Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing formation of an inversion layer in an isolation region to suppress a leakage current from a high-voltage circuit region to the isolation region and a transistor element region.SOLUTION: A semiconductor device comprises a high-voltage circuit region 2A, a transistor element region 2B, an isolation region 4 for element isolation between the transistor element region and the high-voltage circuit region, and capacitively coupled field plates 20A and 20B each including a plurality of rows of conductors, these regions and plates being provided on a semiconductor substrate. In a plan view of the semiconductor device, the capacitively coupled field plate 20B is arranged so as to transverse the transistor element region 2B and surround the high-voltage circuit region 2A. At least one row of the plurality of rows of conductors in the capacitively coupled field plates comprises a dividing part that divides the conductor to make it discontinuous.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a high-voltage circuit region, a transistor element region, a separation region that separates the transistor element region and the high-voltage circuit region, and a capacitive coupling type field plate including a plurality of conductors.

Background Art

[0002] Power devices such as IGBTs and power MOSFETs are used in many fields such as inverters for motor control, power supply applications such as PDPs (plasma display panels) and liquid crystal panels, and home appliance inverters such as air conditioners and lighting. In recent years, with the progress of LSI (large-scale integrated circuit) technology, high-voltage semiconductor devices (high-voltage ICs) up to the 1200V class used in industrial power supplies of the AC400V system have been put into practical use.

[0003] A high-voltage gate driver IC (HVIC) in which a low-side drive circuit, a high-side drive circuit, and a level shift circuit responsible for the level-up / level-down function of a control signal are built in one chip is used. FIG. 19 is a plan view of a semiconductor region of a semiconductor device described in FIG. 1 of Patent Document 1, and shows a plan view of a general HVIC of a level shift element. As illustrated in FIG. 19, the high-voltage circuit region (high-side drive circuit) is mounted on a first semiconductor region (N diffusion region 42b) surrounded by a high-voltage isolation region 32b on its outer periphery.

[0004] HVICs are known in which a high-voltage circuit region, on which the high-potential side circuit section 110 shown in Figure 18 (described later) is mounted, and high-voltage LDMOSFETs (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistors; sometimes simply called high-voltage LDMOSs) of a level-shift circuit corresponding to HVNMOS 101 and 102 shown in Figure 18 (described later) are formed on the same semiconductor substrate. In HVICs, the high-voltage isolation region described in Patent Documents 1 and 2 is formed with a RESURF (Reduced Surface Field) isolation structure. Furthermore, the first semiconductor region of the high-voltage isolation region and the second semiconductor region that becomes the high-voltage LDMOS are electrically isolated from each other by isolation regions composed of trench isolation such as the annular trench described in Patent Document 3 or the trench isolation structure described in Patent Document 4, or PN junction isolation described in the P-slit region of Patent Documents 1 and 5. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 9-283716 [Patent Document 2] International Publication No. 2018 / 051412 [Patent Document 3] Japanese Patent Publication No. 2018-195640 [Patent Document 4] Japanese Patent Publication No. 2004-349296 [Patent Document 5] Japanese Patent Publication No. 2018-117069 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] Figure 18 shows the circuit configuration of a typical HVIC incorporating the level shift element described in Figure 5 of Patent Document 5. The HVIC 100 shown in Figure 18 is a gate driver IC that drives the IGBT 121 on the high-potential side (upper arm) of the IGBTs 121 and 122 that form, for example, one phase of the bridge circuit 120. The bridge circuit 120 is connected in series between the positive terminal potential (power supply potential) Vdc of the main DC power supply and the common potential COM on the negative terminal side.

[0007] The symbol OUT is the connection point between the emitter of IGBT121 on the upper arm of the bridge circuit 120 and the collector of IGBT122 on the low-potential side (lower arm), and is the AC output terminal of the bridge circuit 120. The level shift element 200 consists of HVNMOS (high-voltage n-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 101, 102, load resistors (resistors) 103, 104, constant voltage diodes 105, 106, NOT gates 107, 108, RS flip-flop (RS-FF) 109, high-potential side circuit section 110, and auxiliary DC power supply E1, which are level shift circuits for driving IGBT121 on the upper arm of the bridge circuit 120. The symbol Vcc1 is the potential of the positive electrode line of the auxiliary DC power supply E1 on the high-potential side (the highest potential of HVIC), and is the potential of the cathode terminal.

[0008] HVNMOS101 conducts upon receiving an ON signal 131 from a pulse generated by the control circuit (not shown), and the voltage drop across the load resistor 103 due to the conduction of HVNMOS101 is used as a signal to turn on IGBT121. HVNMOS102 conducts upon receiving an OFF signal 132 from a pulse generated by the control circuit, and the voltage drop across the load resistor 104 due to the conduction of HVNMOS102 is used as a signal to turn off IGBT121. The control circuit is supplied with current from the potential Vcc2 of the positive line of the low-voltage auxiliary DC power supply E2, which is referenced to the common potential COM.

[0009] In the level shift circuit, the two HVNMOS transistors 101 and 102 form the circuit portion that inputs a signal referenced to a common potential COM to the subsequent stage (NOT gates 107 and 108). HVNMOS transistors 101 and 102, and load resistors 103 and 104 are typically configured to be equal in magnitude to each other. HVNMOS transistors 101 and 102 are configured as source followers, with resistors 111 and 112 connected between the source and the common potential COM, respectively, for negative current feedback.

[0010] A predetermined breakdown voltage (e.g., 30V) is required between the first semiconductor region, which is an N-type diffusion layer in the high-voltage circuit region, and the second semiconductor region, which is an N-type diffusion layer in the transistor element region. It is also required that no leakage current flows between the high-voltage circuit region and the transistor element region. In high-voltage isolation structures between high-voltage circuit regions and transistor element regions, a capacitively coupled field plate (MFFP: Multiple Floating Field Plate) including a conductor electrically connected to the first semiconductor region and a conductor electrically connected to the second semiconductor region may be used. When this technology is applied to the HVIC described in Figure 19, for example, when the potential of the high-voltage circuit region facing the isolation region becomes higher than the potential of the transistor element region facing the isolation region (hereinafter also referred to as "when different voltages occur"), the potential of the isolation region below the field plate may fluctuate in accordance with the potential change of the field plate. Furthermore, a conductivity type inversion phenomenon may occur on the surface of the isolation region, and a leakage path of the inversion layer may be generated on the surface of the isolation region that separates the high-voltage circuit region and the high-voltage LDMOS (transistor element region). [Means for solving the problem]

[0011] The present invention has been made to solve the above problems, and is a semiconductor device comprising a high-voltage circuit region, a transistor element region, an isolation region that separates the transistor element region and the high-voltage circuit region, and a capacitively coupled field plate including a plurality of rows of conductors, provided on a semiconductor substrate. In a plan view of the semiconductor device, the capacitively coupled field plate is arranged to traverse the transistor element region and surround the high-voltage circuit region. The present invention provides a semiconductor device in which at least one of the multiple rows of conductors in the capacitively coupled field plate is provided with a discontinuous portion that divides the conductor.

[0012] With such a semiconductor device, even if the potentials of the high-voltage circuit region and the transistor element region opposite the isolation region are different, the potential fluctuations on the surface side of the isolation region can be reduced. Furthermore, leakage current from the high-voltage circuit region to the isolation region and the transistor element region due to parasitic transistors in the high-voltage circuit region, isolation region, and transistor element region can be suppressed.

[0013] In this case, in a plan view of the semiconductor device, the dividing portion may be positioned on the high-voltage circuit region side with respect to the separation region.

[0014] This makes it possible to more effectively suppress leakage current from the high-voltage circuit region to the isolation region and the transistor element region caused by parasitic transistors.

[0015] Furthermore, in a plan view of the semiconductor device, the dividing portion may be positioned on the transistor element region side with respect to the separation region.

[0016] This makes it possible to more effectively suppress leakage current from the high-voltage circuit region to the isolation region and then to the transistor element region caused by parasitic transistors. Furthermore, by extending the conductor from the high-voltage circuit region onto the isolation region, it becomes possible to suppress the effect of charge injection into the conductor on the isolation region on the ON resistance of elements within the transistor element region.

[0017] Further, the capacitive coupling type field plate may include at least one row of conductors having a dividing portion disposed on the high-voltage circuit region side with respect to the isolation region in a plan view of the semiconductor device, and at least one row of conductors having a dividing portion disposed on the transistor element region side with respect to the isolation region.

[0018] As a result, leakage current from the high-voltage circuit region to the isolation region and the transistor element region due to the parasitic transistor can be more effectively suppressed. Further, by extending the conductor onto the isolation region from the high-voltage circuit region side, even if charge is injected into the conductor on the isolation region, it is possible to suppress the influence on the ON resistance of the elements within the transistor element region.

[0019] Further, the dividing portion may be arranged to overlap the isolation region in a plan view of the semiconductor device.

[0020] As a result, leakage current from the high-voltage circuit region to the isolation region and the transistor element region due to the parasitic transistor can be more effectively suppressed.

[0021] Further, the semiconductor device according to the present invention may include a shield electrode disposed on the dividing portion.

[0022] As a result, the influence of external ions can be suppressed.

[0023] At this time, all of the plurality of rows of conductors of the capacitive coupling type field plate may have the dividing portion.

[0024] As a result, leakage current can be more effectively suppressed.

[0025] At this time, in a plan view of the semiconductor device, a RESURF region may be arranged around the high-voltage circuit region.

[0026] The present invention is particularly effective in semiconductor devices having such a resurfacing region.

[0027] In this case, the resurf region may not be located in the region sandwiched between the high-voltage circuit region and the transistor element region when viewed in plan view of the semiconductor device.

[0028] Even with such a semiconductor device, the present invention provides an effect of suppressing leakage current from the high-voltage circuit region.

[0029] Furthermore, in the semiconductor device according to the present invention, in a plan view of the semiconductor device, the width of the separation of the conductor by the separation portion can be less than or equal to the width of the separation region.

[0030] This ensures that the field plate effect and leakage current suppression effect are reliably obtained.

[0031] In this case, the semiconductor device according to the present invention may further include a low-voltage circuit region.

[0032] The present invention is particularly effective in such a subsidiary.

[0033] In this case, the semiconductor substrate has a first conductivity type, The high-voltage circuit region is located within the first semiconductor region of the second conductivity type on the semiconductor substrate. The transistor element region comprises, on the semiconductor substrate, a high-pressure side main electrode on a second semiconductor region of a second conductivity type separated from the first semiconductor region, a low-pressure side main electrode, and a control electrode disposed between the high-pressure side main electrode and the low-pressure side main electrode. The aforementioned isolation region is a semiconductor region of the first conductivity type, The capacitively coupled field plate, in a plan view of the semiconductor device, comprises a first group of conductors that overlaps with a part of the outer edge of the high-voltage circuit region and is spaced apart from each other so as to be capacitively coupled, and a second group of conductors that is positioned between the high-voltage side main electrode and the control electrode of the transistor element region and is spaced apart from each other so as to be capacitively coupled, wherein one end of the first group of conductors is electrically connected to the first semiconductor region, the other end of the first group of conductors is electrically connected to a third semiconductor region of a first conductivity type that is electrically connected to the semiconductor substrate, one end of the second group of conductors is electrically connected to the high-voltage side main electrode, and the other end of the second group of conductors is electrically connected to the control electrode or the low-voltage side main electrode. The aforementioned separation portion can be configured to separate and discontinuously separate the conductors of the first group of conductors and the conductors of the second group of conductors that are adjacent to the conductors of the first group of conductors.

[0034] This suppresses the inversion of the semiconductor region on the surface of the separation area, thereby suppressing leakage current from the high-voltage circuit region to the separation area and the transistor element region. [Effects of the Invention]

[0035] As described above, according to the semiconductor device of the present invention, when the potential of the first semiconductor region in the high-voltage circuit region becomes different from the potential of the second semiconductor region in the transistor element region, the potential fluctuation of the isolation region can be reduced. Furthermore, leakage current from the high-voltage circuit region to the isolation region and the transistor element region can be suppressed. [Brief explanation of the drawing]

[0036] [Figure 1] This is a plan view of a semiconductor device according to the first embodiment of the present invention. [Figure 2] Figure 1 is a cross-sectional view AA of the semiconductor device 10. [Figure 3] Figure 1 is a cross-sectional view of the semiconductor device 10, specifically the part BB shown. [Figure 4] This is a cross-sectional view of the semiconductor device 10 shown in Figure 1. [Figure 5] Figure 1 is a cross-sectional view of the semiconductor device 10 via DD. [Figure 6] Figure 1 is a cross-sectional view of semiconductor device 10. [Figure 7] Figure 2 is a cross-sectional view of the semiconductor device 10 shown, with each conductor of the field plate 20A labeled with a reference numeral. [Figure 8] Figure 5 is a cross-sectional view of the semiconductor device 10, showing each conductor of the field plate 20B with reference numerals. [Figure 9] This is a schematic diagram (enlarged view of the vicinity of the separation region in a plan view) showing an example of the positional relationship between the divided portion 6 and the separation region 4 of the field plate of the semiconductor device 10 according to the present invention. [Figure 10] This is a schematic diagram (enlarged view of the vicinity of the separation region in a plan view) showing a modified example 1 of the positional relationship between the divided portion 6 and the separation region 4 of the field plate of the semiconductor device 10 according to the present invention. [Figure 11] This is a schematic diagram (enlarged view of the vicinity of the separation region in a plan view) showing a modified example 2 of the positional relationship between the divided portion 6 and the separation region 4 of the field plate of the semiconductor device 10 according to the present invention. [Figure 12] This is a schematic diagram (enlarged view of the vicinity of the separation region in a plan view) showing a modified example 3 of the positional relationship between the divided portion 6 and the separation region 4 of the field plate of the semiconductor device 10 according to the present invention. [Figure 13] This is a schematic diagram (enlarged view of the vicinity of the separation region in a plan view) showing a modified example 4 of the positional relationship between the divided portion 6 and the separation region 4 of the field plate of the semiconductor device 10 according to the present invention. [Figure 14] This is a schematic diagram (enlarged view of the vicinity of the separation region in a plan view) showing a modified example 5 of the positional relationship between the divided portion 6 and the separation region 4 of the field plate of the semiconductor device 10 according to the present invention. [Figure 15] This is a schematic diagram (enlarged view of the vicinity of the separation region in a plan view) showing a modified example 6 of the positional relationship between the divided portion 6 and the separation region 4 of the field plate of the semiconductor device 10 according to the present invention. [Figure 16]This is a schematic diagram (enlarged view of the vicinity of the separation region in a plan view) showing a modified example 7 of the positional relationship between the divided portion 6 and the separation region 4 of the field plate of the semiconductor device 10 according to the present invention. [Figure 17] Figure 16 shows a cross-sectional view of the divided portion 6 of the field plate of a semiconductor device 10 according to modified example 7 of the present invention. [Figure 18] This shows a typical HVIC circuit configuration with a built-in level-shifting element. [Figure 19] A general plan view of a level-shifting element (HVIC) is shown. [Modes for carrying out the invention]

[0037] The present invention will be described in detail below, but the present invention is not limited to these descriptions.

[0038] As described above, in the semiconductor device 10 according to the present invention, a recess is provided in a part of the high-voltage circuit region 2A in a plan view of the semiconductor device 10, and a part of the transistor element region (LDMOS) 2B is provided within the recess of the high-voltage circuit region (HVDi) 2A (see Figure 1). As shown in Figures 2, 5, 7, and 8, capacitively coupled field plates 20A and 20B containing multiple rows of conductors are provided on the outer periphery of the high-voltage circuit region 2A and between the high-voltage side main electrode 27 and control electrode 26 of the transistor element region (LDMOS) 2B, respectively, and each conductor of the capacitively coupled field plates 20A and 20B is capacitively coupled. As shown in Figures 1, 2, 3, and 7, a resurf region 11 is provided on the outer periphery of the high-voltage circuit region 2A. Each conductor of the field plate affects the surface potential of the resurf region 11 directly beneath it, and the depletion layer within the resurf region 11 extends further outward in a plan view of the semiconductor device. As a result, the breakdown voltage of the semiconductor device is ensured. Note that although the transistor element region (LDMOS) 2B in Figure 1 is provided in two separate regions, it may also be a single transistor element region. If the high-voltage circuit region 2A and the transistor element region (LDMOS) 2B are at different potentials, such that the high-voltage circuit region 2A is higher than the transistor element region (LDMOS) 2B (for example, +15V), the field plate has conductors connected to the high-voltage circuit region 2A and conductors electrically connected to the transistor element region (LDMOS) 2B. Therefore, due to the influence of the different voltages, the potential of other conductors in the capacitively coupled field plate also rises to a certain potential due to capacitive coupling. In accordance with this potential, the potential of the surface of the P-type semiconductor layer in the isolation region 4 below the conductors of the field plate (or the surface of the semiconductor layer including the P-type semiconductor substrate 1 or any electrically connected semiconductor layers of the same conductivity type (first conductivity type semiconductor region) on the P-type semiconductor substrate 1) also rises. This results in a problem where leakage occurs from the high-voltage circuit region 2A to the isolation region 4 and then to the transistor element region 2B.

[0039] Thus, there was a need for a semiconductor device that could suppress leakage current from the high-voltage circuit region to the isolation region and the transistor element region.

[0040] As a result of diligent study on the above problems, the inventors have found that a semiconductor device comprising a high-voltage circuit region, a transistor element region, an isolation region separating the transistor element region and the high-voltage circuit region, and a capacitively coupled field plate containing multiple rows of conductors, wherein in a plan view of the semiconductor device, the capacitively coupled field plate is arranged to traverse the transistor element region and surround the high-voltage circuit region, and at least one of the multiple rows of conductors in the capacitively coupled field plate is provided with a discontinuous portion that divides the conductors, thereby suppressing leakage current from the high-voltage circuit region to the isolation region and the transistor element region, and have completed the present invention.

[0041] The following explanation will be given with reference to the drawings. In the following explanation, expressions such as "placed on" or "provided on" include both cases where they are placed in contact with each other and cases where they are placed with other layers or structures in between.

[0042] [Semiconductor device] As shown in Figure 1, a plan view of the semiconductor device 10, the semiconductor device according to the first embodiment comprises a high-voltage circuit region (HVDi) 2A, a transistor element region (LDMOS) 2B, and an isolation region 4 that separates the transistor element region (LDMOS) 2B and the high-voltage circuit region (HVDi) 2A, all provided on a semiconductor substrate of a first conductivity type (here referred to as P-type). Furthermore, as shown in Figures 2, 4-8, it comprises capacitively coupled field plates 20A and 20B containing multiple rows of conductors. In the example in Figures 2, 4-8, the capacitively coupled field plates 20A and 20B are composed of two groups of conductors of different heights, but they may be composed of groups of conductors of approximately the same height, or any group of one or more conductors. In the example shown in Figure 1, a low-voltage circuit region 5 is formed around the high-voltage circuit region (HVDi) 2A and the transistor element region (LDMOS) 2B.

[0043] Figure 2 is a cross-sectional view of Figure 1, specifically AA, showing the high-voltage circuit region (HVDi) 2A, the resurf region 11, and the low-voltage circuit region 5. Figure 3 is a cross-sectional view of Figure 1, BB, showing the cross-section passing through the discontinuous section 6 that separates the conductors of the capacitively coupled field plates 20A and 20B (corresponding to the BB cross-section in Figure 9). Figure 4 is a cross-sectional view of Figure 1, CC, showing the cross-section passing through the isolation region 4 that separates the high-voltage circuit region 2A and the transistor element region (LDMOS) 2B. Figure 5 is a cross-sectional view of Figure 1, DD, showing the cross-section passing through the isolation region 4 that separates the high-voltage circuit region 2A and the transistor element region (LDMOS) 2B. Figure 6 is a cross-sectional view of Figure 1, EE, showing the cross-section passing through the isolation region 4 that separates the high-voltage circuit region 2A and the transistor element region (LDMOS) 2B. Figure 7 is a cross-sectional view of the semiconductor device 10 shown in Figure 2, with each conductor of the capacitively coupled field plate 20A labeled with a reference numeral. Figure 8 is a cross-sectional view of the semiconductor device 10 shown in Figure 5, with each conductor of the capacitively coupled field plate 20B labeled with a reference numeral. Figures 2 to 17 explain the range from the area around the left recess of the high-voltage circuit region (HVDi) 2A to the left area of ​​the transistor element region (LDMOS) 2B, which is partially provided within that recess, in the plan view of the semiconductor device of Figure 1. However, the structure from the area around the left recess of the high-voltage circuit region (HVDi) 2A to the right area of ​​the transistor element region (LDMOS) 2B, which is partially provided within that recess, may also have a similar divided section structure to any of Figures 2 to 17. Furthermore, the structure from the area around the right recess of the high-voltage circuit region (HVDi) 2A to the left and / or right area of ​​the transistor element region (LDMOS) 2B, which is partially provided within that recess, may also have a similar divided section structure to any of Figures 2 to 17. In other words, four separation sections may be provided above or near the separation region 4 to separate the conductors of the capacitively coupled field plate.

[0044] (Semiconductor substrate) In the semiconductor device according to the present invention, each element region and the like that constituting the semiconductor device described below are formed and arranged on a semiconductor substrate 1. A known substrate can be used as the semiconductor substrate 1, and its type is not particularly limited. In the following description, the semiconductor substrate 1 is assumed to have a first conductivity type. Here, the first conductivity type is described as P-type, but it is not limited to this.

[0045] (High-voltage circuit area) Each element within the high-voltage circuit region 2A is arranged within a first semiconductor region 2 of the second conductivity type (N-type) on the semiconductor substrate 1. Specifically, a deep N-type diffusion layer is formed by diffusion on the P-type semiconductor substrate 1, and each element within the high-voltage circuit region 2A is arranged on this N-type diffusion layer. Examples of elements include PMOSFETs (PMOS) and NMOSFETs (NMOS). On the outer periphery of the high-voltage circuit region (the side of the low-voltage circuit region described later), for example, a shallow N-type diffusion layer resurf region 11 is provided. The resurf region 11 has a lower impurity concentration than the first semiconductor region 2. This so-called resurfing technology makes it easier for the depletion layer spreading from the low-voltage circuit region 5 side to spread within the resurf region 11, thereby achieving high breakdown voltage. A capacitively coupled field plate 20A is provided on the resurf region 11 via an insulating film 21.

[0046] (Transistor element region) The high-voltage main electrode 27 of the transistor element region (LDMOS) 2B is provided on the semiconductor substrate 1 on a second semiconductor region 7 of the second conductivity type (N-type) that is spaced apart from the first semiconductor region 2. A fourth semiconductor region 28 of the second conductivity type (N-type) is provided on a third semiconductor region 24 of the first conductivity type (P-type) that forms a channel region. A control electrode 26 is provided on the third semiconductor region 24 that forms the channel region, and comprises a low-voltage main electrode 29 electrically connected to the fourth semiconductor region 28 and a high-voltage main electrode 27 electrically connected to the second semiconductor region 7. The semiconductor region 25 is a high-voltage side contact region of the second conductivity type (N-type) to obtain good electrical connection with the high-voltage main electrode 27, and the semiconductor region 25 is optional. The control electrode 26 is formed on the third semiconductor region 24 of the first conductivity type (P-type) formed on the semiconductor substrate 1 via an insulating film. For example, a resurf region 12 of an N-type diffusion layer is formed between the second semiconductor region 7 and the third semiconductor region 24. A capacitively coupled field plate 20B is provided on the resurf region 12 via an insulating film 21.

[0047] (separation area) The isolation region 4 is a region that isolates the transistor element region (LDMOS) 2B from the high-voltage circuit region 2A. In the following description, the isolation region 4 is a first-conductivity type (P-type) semiconductor region between the first semiconductor region 2 and the second semiconductor region 7. As shown in Figure 6, the transistor element region (LDMOS) 2B and the high-voltage circuit region 2A are made of N-type semiconductors, and the isolation region 4 is made of a P-type semiconductor, and is separated by a PN junction. That is, in this embodiment, the isolation region 4 separates the first semiconductor region 2 in the high-voltage circuit region 2A from the second semiconductor region 7 of the transistor element region (LDMOS) 2B by PN junction separation. The desired breakdown voltage (e.g., 30V) is ensured by this isolation region 4. The dopant concentration in the isolation region 4 is selected so that when high voltage is applied, the space between the first semiconductor region 2 on the high-voltage circuit region 2A side and the second semiconductor region 7 on the transistor element region (LDMOS) 2B side is completely depleted, and the desired breakdown voltage is ensured. In Figure 2, etc., a first conductivity type (P-type) semiconductor region 14 with a higher impurity concentration than the semiconductor substrate 1 is provided on the P-type semiconductor substrate 1, but the first conductivity type semiconductor region 14 does not need to be provided.

[0048] The isolation region 4 is not particularly limited as long as it can separate the transistor element region (LDMOS) 2B and the high-voltage circuit region 2A. PN junction isolation is optimal, but other methods include isolation using an embedded insulator (or dielectric) or isolation using a trench.

[0049] (Capacitive-coupled field plate) As shown in Figures 2, 4-8, etc., the capacitively coupled field plates 20A and 20B, in a plan view of the semiconductor device, overlap with a part of the outer edge of the high-voltage circuit region 2A and comprise a first group of conductors spaced apart from each other so as to be capacitively coupled, and a second group of conductors positioned between the high-voltage side main electrode 27 and the control electrode 26 of the transistor element region (LDMOS) 2B and also spaced apart from each other so as to be capacitively coupled. In other words, it is a technology using a two-layer floating plate with two groups of conductors arranged in the vertical direction. Note that the AA cross section of Figure 1 is shown in Figure 2. As shown in Figure 7, conductor a6, which is one end of the first group of conductors, is electrically connected to the first semiconductor region 2, and conductor a1, which is the other end of the first group of conductors, is electrically connected to the semiconductor substrate 1. Furthermore, the diagram shows an example in which conductor c6, which is one end of the second group of conductors, is electrically connected to the high-voltage main electrode 27, and conductor c1, which is the other end of the second group of conductors, is electrically connected to the control electrode 26 or the low-voltage main electrode 29.

[0050] Furthermore, when multiple conductors are arranged to surround the high-voltage circuit region 2A, the capacitance on the high-potential side (capacitance between conductors a6 and b5 in Figure 7) is smaller than the capacitance on the low-potential side (capacitance between conductors a1 and b1 in Figure 7). The voltage between conductors (capacitor voltage) is inversely proportional to the capacitance. Therefore, in order to increase the capacitance on the low-potential side, the opposing area between conductors on the high-potential side (for example, the opposing area between conductors a6 and b5) may be increased compared to the opposing area between conductors on the low-potential side (for example, the opposing area between conductors a1 and b1). Conversely, the opposing area between conductors on the high-potential side may be made smaller than the opposing area between conductors on the low-potential side, creating a structure where the high-voltage circuit region 2A bears the potential.

[0051] A semiconductor device employing this two-layer floating plate technology is a semiconductor device that is more effective at stabilizing the surface potential of the resurf regions 11 and 12 by the capacitively coupled field plates 20A and 20B, and is a more reliable semiconductor device that can suppress leakage current between the high-voltage circuit region 2A and the transistor element region 2B by incorporating the separation portion 6, which is a characteristic feature of the present invention.

[0052] The capacitively coupled field plates 20A and 20B traverse the transistor element region (LDMOS) 2B (Figure 5) and include multiple rows of conductors positioned on the outer periphery of the high-voltage circuit region 2A (Figure 2). In the cross-sectional view of Figure 7, which is cut on the high-voltage circuit region 2A side of the dividing section 6 (described later), the conductor a6 of the capacitively coupled field plate 20A on the high-voltage circuit region 2A side is electrically connected to the high-potential side main electrode 23, which is electrically connected to the first semiconductor region 2 of the high-voltage circuit region 2A. In Figure 2, etc., the second conductivity type (N-type) semiconductor region (semiconductor region 15 provided within the high-voltage circuit region) located in the first semiconductor region 2 is electrically connected to the high-potential side main electrode 23. In the capacitively coupled field plate 20A on the high-voltage circuit region 2A side of the division section 6, the outer conductor a1 is electrically connected to the low-potential side main electrode 22, which is electrically connected to the reference potential outside the resurf region 11 (semiconductor substrate 1 or, for example, a first-conductivity semiconductor region 14 that is approximately the same potential as the semiconductor substrate 1) (see, for example, Figure 7). Also, in the cross-sectional view of Figure 8, which is cut on the transistor element region (LDMOS) 2B side of the division section 6, the high-potential side conductor c6 in the capacitively coupled field plate 20B is electrically connected to the high-voltage side main electrode 27. In the cross-sectional view of Figure 8, which is cut on the transistor element region (LDMOS) 2B side of the division section 6, the low-potential side conductor c1 in the capacitively coupled field plate 20B is electrically connected to the control electrode 26.

[0053] Here, "multiple rows" refers to each row of conductors a1 to a6 constituting the first conductor group P1, each row of conductors b1 to b5 constituting the second conductor group P2, each row of conductors c1 to c6 constituting the first conductor group P1, and each row of conductors d1 to d5 constituting the second conductor group P2, as shown in Figures 7 and 8. In the capacitively coupled field plates 20A and 20B, as shown in the examples in Figures 7 and 8, the first and second conductor groups P1 and P2, each consisting of multiple rows of conductors spaced apart from each other to be capacitively coupled, are stacked vertically in the semiconductor device to form two layers (conductor groups). The capacitively coupled field plates 20A and 20B, i.e., the layers of conductor groups, may be one layer or multiple layers. Known materials can be used as conductors, with polycrystalline silicon (polysilicon) being a typical example.

[0054] The conductors of the capacitively coupled field plate 20A, which is provided to surround the outer periphery of the high-voltage circuit region 2A, have different circumferential lengths in the inner row of conductors, for example, conductor a6, and the outer row of conductors, for example, conductor a1. The opposing area between rows of conductors (the thickness of each conductor) may be different for the inner row of conductors, for example, conductor a6, and the outer row of conductors, for example, conductor a1. Furthermore, when using two layers of conductor groups, the overlap area of ​​opposing conductors within each conductor group may be changed between the inner and outer layers. For example, the overlap may be reduced from the overlap between the inner conductor a6 and conductor b5 to the overlap between the outer conductor a1 and conductor b1. This makes it possible to reduce the difference between the capacitance generated by the overlap of the inner conductors and the capacitance generated by the overlap of the outer conductors within the conductor group.

[0055] (Divided section) Next, the discontinuous portion 6 in the capacitively coupled field plates 20A and 20B will be described. The discontinuous portion 6 has two layers of conductive material, and the discontinuous portion 6 divides and discontinuously separates at least one row of conductive material in the first conductive material group and each of the conductive material in the second conductive material group P2 adjacent to any of the conductive material in the first conductive material group. The semiconductor device according to the present invention is characterized in that at least one row of the multiple rows of conductive material in the capacitively coupled field plates 20A and 20B is provided with a discontinuous portion that divides and discontinuously separates the conductive material. Figure 3 is a diagram showing the BB cross section in Figure 1, and shows a cross-sectional view of the line passing through the discontinuous portion 6 in the capacitively coupled field plates 20A and 20B. The discontinuous portion 6 is a region in which at least one row of the multiple rows of conductive material in the capacitively coupled field plates 20A and 20B is divided and discontinuous, and is a portion in which no conductive material exists.

[0056] Here, "a conductor in the second group of conductors adjacent to a conductor in the first group of conductors" refers to the relationship between conductor a1 and conductor b1, and conductor a3 and conductor b2 or conductor b3, among the conductors a1 to a6 of the first group of conductors P1 and conductors b1 to b5 of the second group of conductors P2, which are arranged vertically in the semiconductor device as shown in Figure 7. In other words, for example, conductor a1 and any of conductors b3 to b6 are not "adjacent".

[0057] By providing such a separation section 6, the reversal of the conductivity type on the surface side of the separation region 4 can be suppressed, and leakage current from the high-voltage circuit region 2A to the transistor element region (LDMOS) 2B can be suppressed.

[0058] It is sufficient that one or more rows of conductors in the first group of conductors, or one or more rows of conductors in the second group of conductors, are provided with a dividing portion 6, and the position where the dividing portion 6 is provided is not particularly limited. Examples of the position where the dividing portion 6 is provided include the first to fourth examples.

[0059] As shown in Figures 9 to 11, the separation section 6 may be provided on the high-voltage circuit region 2A side. As shown in Figure 12, the separation section may be provided on the transistor element region (LDMOS) 2B side. As shown in Figure 13, the separation section 6 may be provided on both the high-voltage circuit region 2A side and the transistor element region (LDMOS) 2B side. As shown in Figures 14 and 15, the separation section 6 may be provided on the isolation region 4. A more detailed explanation follows.

[0060] As a first example, the position where the separation section 6 is provided can be as shown in Figures 9 to 11, where, in a plan view of the semiconductor device, it is located on the high-voltage circuit region 2A side (left side of the paper) with respect to the separation region 4. In this case, the capacitively coupled field plate on the separation region 4 becomes the capacitively coupled field plate 20B, and the potential distribution on the surface of the separation region 4 is based on the potential distribution of the capacitively coupled field plate 20B on the transistor element region (LDMOS) 2B side, rather than on the high-voltage circuit region 2A side. As a result, the effects of potential fluctuations in the event of different voltages can be reduced more effectively. It becomes possible to more effectively suppress leakage current from the high-voltage circuit region 2A to the transistor element region 2B and the separation region 4.

[0061] In Figure 9, when viewing the capacitively coupled field plate in plan view, the dividing section 6, located on the high-voltage circuit region 2A side with respect to the separation region 4, separates the conductors a1-a6 of the capacitively coupled field plate 20A from the conductors c1-c6 of the capacitively coupled field plate 20B, and further separates the conductors b1-b5 of the capacitively coupled field plate 20A from the conductors d1-d5 of the capacitively coupled field plate 20B.

[0062] The plan view of the semiconductor device shown in Figure 10 is an example (modified example 1) in which a dividing section 6A is provided only on the high-potential side, so that the conductors a5~a6 on the high-potential side of the capacitively coupled field plate 20A are separated from the conductors c5~c6 of the capacitively coupled field plate 20B, and the conductors b4~b5 of the capacitively coupled field plate 20A are separated from the conductors d4~d5 of the capacitively coupled field plate 20B. Here, the conductors a1~a4 on the low-potential side and the conductors c1~c4 on the low-potential side are not separated, and the row of conductors on the high-voltage circuit region 2A side and the row of conductors in the adjacent transistor element region 2B are connected to each other. Similarly, the conductors b1~b3 on the low-potential side and the conductors d1~d3 on the low-potential side are not separated, and the row of conductors on the high-voltage circuit region 2A side and the row of conductors in the adjacent transistor element region 2B are connected to each other.

[0063] The plan view of the semiconductor device shown in Figure 11 is an example (modified example 2) in which a dividing section 6B is provided only on the low-potential side, so that the conductors a1-a3 on the low-potential side of the capacitively coupled field plate 20A are separated from the conductors c1-c3 of the capacitively coupled field plate 20B, and the conductors b1-b2 of the capacitively coupled field plate 20A are separated from the conductors d1-d1 of the capacitively coupled field plate 20B. Here, the conductors a4-a6 and c4-c6 on the high-potential side are not separated, and the row of conductors on the high-voltage circuit region 2A side and the row of conductors in the adjacent transistor element region 2B are connected to each other. Similarly, the conductors b3-b5 on the high-potential side and d3-d5 on the low-potential side are not separated, and the row of conductors on the high-voltage circuit region 2A side and the row of conductors in the adjacent transistor element region 2B are connected to each other.

[0064] As a second example of the location for providing the separation portion 6, as shown in Figure 12, the separation portion 6C can be positioned on the transistor element (LDMOS) 2B side with respect to the separation region 4 in a plan view of the semiconductor device (modification example 3). When viewing the capacitively coupled field plate in a plan view, the separation portion 6 positioned on the transistor element (LDMOS) 2B side with respect to the separation region 4 divides the capacitively coupled field plate 20A into conductors a1-a6 and the capacitively coupled field plate 20B into conductors b1-b5 and the capacitively coupled field plate 20B into conductors d1-d5. In this case, the surface of the separation region 4 is more strongly affected by the potential distribution of the capacitively coupled field plate 20A on the high-voltage circuit region 2A side located above it.

[0065] As shown in Figures 4 and 6, since the second semiconductor region 7 and the adjacent resurf region 11 are not formed in the isolation region 4, the depletion layer does not easily extend into the isolation region 4, and the electric field in and around the isolation region 4 becomes stronger. In particular, the low-potential side of the isolation region 4 (the low-voltage circuit region 5 side, which is the left side of the page in Figure 4) is less likely to be depleted, so a potential difference is more likely to occur between the surface of the isolation region 4 and the capacitively coupled field plates 20A and 20B provided above the isolation region 4. As shown in Figure 9, if the separation section 6 is positioned on the high-voltage circuit region 2A side with respect to the isolation region 4, the potential difference between the control electrode (e.g., gate electrode) or low-voltage main electrode (e.g., source electrode) on the transistor element (LDMOS) 2B side and the first row of conductors (conductor c1, which is the first row from the low-potential side) of the capacitively coupled field plate 20B also becomes large, and a leakage current may flow in the insulating film between the control electrode or low-voltage side electrode and the first row of conductors c1, causing electrons to be charged into the first row of conductors c1. This leads to a problem where the surface density of the semiconductor in the transistor element region (LDMOS) 2B beneath the capacitively coupled field plates 20A and 20B decreases, and the on-resistance of the transistor element region (LDMOS) 2B increases.

[0066] Therefore, as shown in Figures 12 and 13 (modification example 4 described later), by positioning at least a portion of the separation section 6 on the transistor element region (LDMOS) 2B side, particularly on the low-potential side of the capacitively coupled field plate, the field plate above the low-potential side of the separation section 6 becomes a capacitively coupled field plate 20A extending from the high-voltage circuit region 2A side. Thus, the above problem is less likely to occur in the capacitively coupled field plate 20B. In other words, in addition to suppressing leakage current from the high-voltage circuit region (HVDi), it is also possible to suppress the increase in the ON resistance of the transistor element region (LDMOS) 2B.

[0067] As a third example of the location where the dividing section 6 is provided, the capacitively coupled field plates 20A and 20B may include, as shown in modified example 4 of Figure 13, at least one row of conductors having a dividing section 6B located on the high-voltage circuit region 2A side with respect to the isolation region 4, and at least one row of conductors having a dividing section 6C located on the transistor element region 2B side with respect to the isolation region 4, in a plan view. In Figure 13, when the capacitively coupled field plate is viewed in plan, the dividing section 6B located on the high-voltage circuit region 2A side with respect to the isolation region 4 divides it into conductors a5, a6 and conductors c5, c6, and conductors b4, b5, b6 and conductors d4, d5, d6. Then, the dividing section 6C located on the high-voltage circuit region 2B side with respect to the isolation region 4 divides it into conductors a1, a2, a3 and conductors c1, c2, c3, and conductors b1, b2 and conductors d1, d2. In other words, with respect to the isolation region 4, the high-potential separation section 6B is provided on the high-voltage circuit region 2A side, and the low-potential separation section 6C is provided on the transistor element region (LDMOS) 2B side. In this case, the capacitively coupled field plate on the isolation region 4 becomes the capacitively coupled field plate 20B on the high-potential side and the capacitively coupled field plate 20A on the low-potential side. Here, it is desirable that the length of the separation section (length in the vertical direction of the paper in Figure 13) of separation section 6B is longer than that of separation section 6C. Even in such a semiconductor device, in addition to suppressing leakage current from the high-voltage circuit region (HVDi), it is possible to suppress the increase in the ON resistance of the transistor element region (LDMOS) 2B. Alternatively, conversely to Figure 13, with respect to the isolation region 4, the high-potential separation section 6B of the capacitively coupled field plate may be provided on the transistor element region (LDMOS) 2B side, and the low-potential separation section 6C of the capacitively coupled field plate may be provided on the high-voltage circuit region 2A side. Even in such a semiconductor device, leakage current from the high-voltage circuit region (HVDi) can be suppressed.

[0068] Furthermore, as a fourth example of the location for providing the separation portion 6D of the capacitively coupled field plate, as shown in Modification 5 of Figure 14, it may be positioned above the separation region 4 so as to overlap with the separation region 4 in a plan view of the semiconductor device. In this case as well, it is possible to more effectively suppress leakage current from the high-voltage circuit region 2A to the transistor element region (LDMOS) 2B and the separation region 4.

[0069] As shown in Figures 9, 12, and 14, it is preferable that all of the multiple rows of conductors included in the capacitively coupled field plate have a discontinuing portion 6, but it is sufficient if at least one of the multiple rows of conductors has a discontinuing portion that divides the conductor. Alternatively, any combination of the first to fourth examples described above may be used. Regardless of whether all of the multiple rows of conductors are divided or only a portion are divided, the discontinuing portion may be provided on either the high-potential side or the low-potential side of the capacitively coupled field plate. The discontinuing portion may also be provided separately on the high-potential side and the low-potential side of the capacitively coupled field plate.

[0070] In a plan view of the semiconductor device, the division width of the capacitively coupled field plate by the division portion 6D (L1 in Figure 14) can be less than or equal to the width of the separation region 4 (L2 in Figure 14). Even with such a division portion 6D, the field plate effect and leakage current suppression effect can be stably obtained. As shown in modified example 6 in Figure 15, the division width of the capacitively coupled field plate by the division portion 6E (L1 in Figure 14) may be larger than the width of the separation region 4 (L2 in Figure 14). Even with such a division portion 6E, the field plate effect and leakage current suppression effect can be stably obtained.

[0071] Furthermore, as shown in Modification 7 of Figures 16 and 17, it is preferable to have a shield electrode 30 (floating metal) on the divided portion 6. Figure 16 is the same as the plan view in Figure 9 with the shield electrode 30 added. Figure 17 shows a cross-sectional view of the divided portion 6 in Figure 16, and the capacitively coupled field plate 20A is enclosed by a dotted line to illustrate the positional relationship in the height direction. By providing the shield electrode 30 above the divided portion 6, the exposure of the semiconductor surface by the divided portion 6 can be suppressed, and the influence of external ions entering from outside the semiconductor device can be suppressed.

[0072] (Low-voltage circuit region) The semiconductor device according to the present invention may further include a low-voltage circuit region 5 (see Figure 1, etc.). The present invention is particularly effective in such a semiconductor device.

[0073] (Resurf area) In the semiconductor device according to the present invention, the resurf region 11 may be arranged on the outer periphery of the high-voltage circuit region 2A in a plan view of the semiconductor device. Alternatively, the resurf region 12 may be arranged between the high-voltage side electrode 27 and the control electrode 26 of the transistor element region (LDMOS) 2B in a plan view of the semiconductor device.

[0074] It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention. [Explanation of Symbols]

[0075] 1... Semiconductor substrate, 2... First semiconductor area, 2A…High-voltage circuit region, 2B…Transistor element region (LDMOS), 4...Isolation region, 5...Low-voltage circuit region, 6, 6A, 6B, 6C, 6D, 6E... Divided regions, 7... Second semiconductor region, 10… Semiconductor device, 11, 12… Resurf region, 14… First conductivity type semiconductor region, 15...Semiconductor region provided within the high-voltage circuit region, 20A, 20B...Capacitively coupled field plates, 21...Insulating film, 22... Low-potential main electrode, 23... High-potential main electrode, 24... Third semiconductor region, 25…Semiconductor region (high-voltage side contact region), 26...Control electrode, 27...High-voltage side main electrode, 28...Fourth semiconductor region, 29... Low-pressure main electrode, 30... Shield electrode, 32b...High pressure isolation region, 42b...N diffusion region, 100…HVIC, 101,102…HVNMOS, 103, 104... Load resistors (resistors), 105, 106... Constant voltage diodes, 107, 108... NOT gate, 109... RS flip-flop (RS-FF), 110...High-potential side circuit section, 111,112...Resistors, 120...Bridge circuit, 121, 122... IGBT, 131... ON signal, 132... OFF signal 200... Level shift element. P1…First group of conductors, P2…Second group of conductors a1, a2, a3, a4, a5, a6...conductor, b1, b2, b3, b4, b5...conductor, c1, c2, c3, c4, c5, c6...conductor, d1, d2, d3, d4, d5... conductors, L1…Dissection width of the capacitively coupled field plate, L2…Width of the isolation region 4, COM…Common potential, E1…Auxiliary DC power supply, E2…Auxiliary DC power supply, Vdc...potential (power supply potential), Vcc1...Position of the positive electrode line of the auxiliary DC power supply E1 on the high-potential side. Vcc2…Potential of the positive electrode line.

Claims

1. A semiconductor device comprising a high-voltage circuit region, a transistor element region, an isolation region separating the transistor element region and the high-voltage circuit region, and a capacitively coupled field plate containing multiple rows of conductors, provided on a semiconductor substrate, In a plan view of the semiconductor device, the capacitively coupled field plate is arranged to traverse the transistor element region and surround the high-voltage circuit region. A semiconductor device characterized in that two or more adjacent rows of conductors in the capacitively coupled field plate are provided with a discontinuing portion that separates the conductors.

2. The semiconductor device according to claim 1, characterized in that, in a plan view of the semiconductor device, the dividing portion is arranged on the high-voltage circuit region side with respect to the separation region.

3. The semiconductor device according to claim 1, characterized in that, in a plan view of the semiconductor device, the dividing portion is arranged on the side of the transistor element region with respect to the separation region.

4. The capacitively coupled field plate includes, in a plan view of the semiconductor device, at least one row of conductors having the dividing portion arranged on the high-voltage circuit region side with respect to the isolation region, and at least one row of conductors having the dividing portion arranged on the transistor element region side with respect to the isolation region. The semiconductor device according to claim 1, characterized in that the dividing portion located on the high-voltage circuit region side and the dividing portion located on the transistor element region side are dividing portions formed in two or more adjacent rows of the multiple rows of conductors.

5. The semiconductor device according to claim 1, characterized in that the dividing portion is arranged to overlap with the separation region in a plan view of the semiconductor device.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that it is provided with a shield electrode arranged on the divided portion.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that the capacitively coupled field plate has all of the multiple rows of conductors having the division portion.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, in a plan view of the semiconductor device, a resurf region is arranged around the high-voltage circuit region.

9. The semiconductor device according to claim 8, characterized in that, in a plan view of the semiconductor device, the resurf region is not located in the region sandwiched between the high-voltage circuit region and the transistor element region.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, in a plan view of the semiconductor device, the width of the separation of the conductor by the separation portion is less than or equal to the width of the separation region.

11. Furthermore, the semiconductor device according to any one of claims 1 to 10 is characterized by having a low-voltage circuit region.

12. The semiconductor substrate has a first conductivity type, The high-voltage circuit region is located within the first semiconductor region of the second conductivity type on the semiconductor substrate. The transistor element region comprises a high-pressure side main electrode on the semiconductor substrate, a second semiconductor region of a second conductivity type spaced apart from the first semiconductor region, a low-pressure side main electrode, and a control electrode disposed between the high-pressure side main electrode and the low-pressure side main electrode. The aforementioned isolation region is a semiconductor region of the first conductivity type, The capacitively coupled field plate, in a plan view of the semiconductor device, comprises a first group of conductors that overlaps with a part of the outer edge of the high-voltage circuit region and is spaced apart from each other so as to be capacitively coupled, and a second group of conductors that is positioned between the high-voltage side main electrode and the control electrode of the transistor element region and is spaced apart from each other so as to be capacitively coupled, wherein one end of the first group of conductors is electrically connected to the first semiconductor region, the other end of the first group of conductors is electrically connected to a third semiconductor region of a first conductivity type that is electrically connected to the semiconductor substrate, one end of the second group of conductors is electrically connected to the high-voltage side main electrode, and the other end of the second group of conductors is electrically connected to the control electrode or the low-voltage side main electrode. The semiconductor device according to any one of claims 1 to 11, characterized in that the dividing portion divides and discontinuates the conductors of the first group of conductors and the conductors of the second group of conductors adjacent to the conductors of the first group of conductors.

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