Information processing device, access control program, and access control method

Abstract

To reduce the time required to transmit a command.SOLUTION: An information processing device controls the range of commands to be divided into a block according to consecutive patterns of data read or data write for commands issued via a serial bus; and accesses the controlled range of commands divided into a block.SELECTED DRAWING: Figure 21

Description

Technical Field

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[0001] The present invention relates to an information processing apparatus, an access control program, and an access control method.

Background Art

[0002] A Service Processor (SP) performs control for inspection at the factory and log collection (in other words, issuance of Inter-Integrated Circuit (I2C) access commands) on a large number of components mounted on a computer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] The number of executions of the I2C access command varies depending on the model and type of processing, but in one process, it may be approximately several thousand to several tens of thousands per node. As a result, an Input Output (IO) interrupt waiting time of several milliseconds to more than ten milliseconds occurs in the firmware for each I2C access command, so there is a risk that it will take several minutes for inspection at the factory and log collection.

[0005] In one aspect, it is an object to reduce the time required for command transmission.

Means for Solving the Problems

[0006] In one aspect, the information processing device controls the range of commands that are blocked in a sequence of data writes or data reads in a command issued via a serial bus, and accesses the controlled range of blocked commands. Furthermore, if the continuous pattern includes only data reads, the range of the command to be blocked is not specified. It is equipped with a processor. [Effects of the Invention]

[0007] One aspect of this is that it can reduce the time it takes to transmit commands. [Brief explanation of the drawing]

[0008] [Figure 1] This block diagram schematically shows an example of the hardware configuration of an information processing device in a related example. [Figure 2] This diagram illustrates I2C single access and I2C block access in related examples. [Figure 3] This block diagram schematically shows an example of the SP firmware configuration in a related example. [Figure 4] Figure 3 shows examples of functions for each module in the SP firmware. [Figure 5] This diagram illustrates the cases in related examples of I2C block access where read data is used during control and where it is not used during control. [Figure 6] Figure 3 illustrates an example of a hardware control program. [Figure 7] Figure 1 is a flowchart illustrating the I2C write process in the information processing device shown. [Figure 8] Figure 1 is a flowchart illustrating the I2C read process in the information processing device shown. [Figure 9] Figure 1 is a flowchart illustrating the process of initiating I2C block access in the information processing device shown. [Figure 10] Figure 1 is a flowchart illustrating the termination process for I2C block access in the information processing device shown. [Figure 11] This is a flowchart for explaining I2C write processing when only single I2C access is performed. [Figure 12] This is a flowchart for explaining I2C read processing when only single I2C access is performed. [Figure 13] This is a flowchart for explaining common hardware control processing when only single I2C access is performed. [Figure 14] This is a block diagram schematically showing an example of the hardware configuration of an information processing apparatus in the first embodiment. [Figure 15] This is a block diagram schematically showing an example of the firmware configuration of the SP shown in FIG. 14. [Figure 16] This is a block diagram schematically showing an example of the firmware configuration of the Complex Programmable Logic Device (CPLD) shown in FIG. 14. [Figure 17] This is a diagram for explaining an operation example of the SP firmware shown in FIG. 15. [Figure 18] This is a diagram exemplifying a hardware control program in the case of the automatic block access mode in the information processing apparatus shown in FIG. 14. [Figure 19] This is a diagram exemplifying a hardware control program in the case of the manual block access mode in the information processing apparatus shown in FIG. 14. [Figure 20] This is a diagram exemplifying a hardware control program for CPU inspection in the information processing apparatus shown in FIG. 14. [Figure 21] This is a flowchart for explaining block access processing in the information processing apparatus shown in FIG. 14. [Figure 22] This is a flowchart for explaining the details of the block access processing shown in FIG. 21. [Figure 23] This is a flowchart for explaining I2C write processing in the information processing apparatus shown in FIG. 14. [Figure 24] This is a flowchart for explaining I2C read processing in the information processing apparatus shown in FIG. 14. [Figure 25] This is a flowchart for explaining the start process of I2C block access in the information processing apparatus shown in FIG. 14. [Figure 26] This is a flowchart for explaining the end process of I2C block access in the information processing apparatus shown in FIG. 14. [Figure 27] This is a flowchart for explaining the start process of manual I2C block access in the information processing apparatus shown in FIG. 14. [Figure 28] This is a flowchart for explaining the end process of manual I2C block access in the information processing apparatus shown in FIG. 14. [Figure 29] This is a flowchart for explaining the common hardware control process in the information processing apparatus shown in FIG. 14. [Figure 30] This is a block diagram schematically showing an example of the hardware configuration and functional configuration of the information processing apparatus in the second embodiment. [Figure 31] This is a diagram for explaining an example of read-modify-write processing in the information processing apparatus shown in FIG. 14. [Figure 32] This is a diagram for explaining an example of read-modify-write processing in the information processing apparatus shown in FIG. 30. [Figure 33] This is a diagram showing an example of the format of a command in the information processing apparatus shown in FIG. 30. [Figure 34] This is a diagram showing an example of the generation process of I2C write data in read-modify-write processing in the information processing apparatus shown in FIG. 30. [Figure 35] This is a sequence diagram for explaining the processing content including read-modify-write processing in the information processing apparatus shown in FIG. 14. [Figure 36] This is a sequence diagram for explaining the processing content including read-modify-write processing in the information processing apparatus shown in FIG. 30.

Embodiments for Carrying Out the Invention

[0009] 〔A〕Related Examples Figure 1 is a block diagram schematically showing an example of the hardware configuration of the information processing device 100 in a related example.

[0010] The information processing device 600 shown in Figure 1 comprises an SP6 and multiple boards 7. Each of the multiple boards 7 is connected to the SP6 and includes a Maintenance Bus Controller (MBC) 71, a buffer 72, and multiple components 73a to 73e.

[0011] On each of the multiple boards 7, in response to execution instructions from SP6, a series of processing procedures (in other words, commands) to be executed on each board 7 are read one by one from a buffer 72 that stores these procedures. The processing corresponding to the read procedures is then executed sequentially on each board 7, controlling multiple components 73a to 73e, and the execution result of the series of processing procedures is notified to SP6.

[0012] In other words, SP6 writes the command list to buffer 72, the control circuit performs processing according to its contents, and the processing result is notified to SP6. This allows multiple processes to be combined into one, thus reducing the overhead of device driver calls for SP6.

[0013] Figure 2 illustrates I2C single access and I2C block access in related examples.

[0014] The MBC71 shown in Figure 1 may consist of an FPGA or CPLD, and this hardware mechanism may be called an I2C block access controller. An I2C block access controller is necessary for SP6 to perform I2C block access.

[0015] Hardware control programs 631 to 634 (see Figure 3) may be constructed such that the current waveforms for the I2C write data and read data are exactly the same in the case of a single I2C access as indicated by symbol A1 and in the case of an I2C block access as indicated by symbol A2.

[0016] A single I2C access, indicated by code A1, includes I2C commands #1 to #3. An I2C block access, indicated by code A2, includes I2C commands #1 to #3 in a single I2C block access command.

[0017] The processing of each I2C command within an I2C block access is implemented in hardware. The time required for hardware operation (several microseconds to several hundred microseconds) is extremely small compared to the time required for firmware operation and can therefore be ignored. For this reason, the time required for one block access is the same as the time required for a single I2C access command, which is several milliseconds to tens of milliseconds.

[0018] In the example shown in Figure 2, the access time is 10 msec × 3 = 30 msec for single I2C accesses, while it is 10 msec × 1 = 10 msec for I2C block accesses. By converting as many I2C commands as possible to block accesses, significant performance improvements can be expected.

[0019] Figure 3 is a block diagram schematically showing an example configuration of the SP firmware 60 in a related example.

[0020] As shown in Figure 3, the common hardware control execution engine 62 is called from the inspection library 611 and log collection library 612, which are triggered by a command, and the component name (e.g., CPU or memory) and function (e.g., inspection or log collection) are selected as arguments and executed.

[0021] The common hardware control execution engine 62 executes hardware control programs 631 to 634 according to the arguments.

[0022] Hardware control programs 631-634 execute the I2C block access library 64 and the I2C single access library 65. Then, the hardware control programs 631-634 execute the I2C block access driver 66 and the I2C single access driver 67, respectively, from these I2C block access library 64 and the I2C single access library 65 to perform hardware access.

[0023] The control of each device's unique I2C registers is contained within the respective hardware control programs 631-634. As shown in symbols B2-B5, hardware control programs 631-634 are developed by the respective hardware team. Due to the large number of types and control patterns, hardware control programs 631-634 are relatively large in scale, approximately 100k steps.

[0024] On the other hand, the common framework, which is not device-specific, is located outside of the hardware control programs 631-634. As shown in symbols B1 and B6, the common framework, which is not device-specific, is developed by the firmware team. Unlike the hardware control programs 631-634, the common framework, which describes common operations, is relatively small in scale, at about 10,000 steps.

[0025] Figure 4 shows examples of functions for each module in the SP firmware 60 shown in Figure 3.

[0026] The functions of the common hardware control execution engine 62, indicated by symbol C1, are a framework for commonly executing each hardware control program 631 to 634, and may include, for example, functions for calls from the inspection library 611 and functions for calls from the log collection library 612.

[0027] The functions of hardware control programs 631-634, shown in code C2, are layers that depend on the I2C register specifications specific to each device (e.g., header, data, read / write procedures).

[0028] In the functions of the I2C block access library 64 and the I2C single access library 65 shown in code C3, the I2C slave address and bus number are determined by the component name, and below this layer, they are common and independent of the I2C register specifications of each device.

[0029] Figure 5 illustrates the difference between using read data during control and not using read data during control in an I2C block access example.

[0030] When I2C read data is used for subsequent control, block access is temporarily interrupted and separated, as shown by symbol D1. In the example shown in Figure 5, I2C block access command #1 contains I2C commands #1 to #3, and I2C block access command #2 contains I2C commands #4 to #6.

[0031] On the other hand, if the I2C read data is not used for subsequent control, block access does not need to be separated and can be combined, as shown in symbol D2. In the example shown in Figure 5, I2C block access command #1 includes I2C commands #1 to #6.

[0032] In other words, when I2C command #3 is used for reading data and I2C command #4 is used to write that read data, the block access commands are separated as shown in symbol D1.

[0033] Here, let's consider a scenario where, when writing the read data from I2C command #3 using I2C command #4, the program is written as a single unit as shown in symbol D2. In such a case, at the time of the block access kick (in other words, the start of hardware operation) after I2C command #6, the read data from I2C command #3 has not been obtained, and therefore the firmware does not have the write data for command #4. As a result, an undefined value or an initial value within the program is written using I2C command #4, leading to a malfunction.

[0034] Figure 6 is an example of the hardware control programs 631 to 634 shown in Figure 3.

[0035] In hardware control programs 631-634, the hardware controller determines and implements the scope of I2C block access on a command-by-command basis. Block access is specified by inserting block access start and end functions before and after the I2C read and I2C write functions, as shown in Figure 6. Note that xxx, yyy, ..., kkk in hardware control programs 631-634 are variables representing the various I2C parameters.

[0036] The implementation of block access itself incurs costs. In particular, if hardware control programs 631-634 become large and are divided into subroutines, it may become difficult to determine whether block access is specified or not.

[0037] The I2C write process in the information processing device 600 shown in Figure 1 will be explained according to the flowchart (steps S1 to S3) shown in Figure 7.

[0038] Currently, determine if the I2C block access has started but not yet finished, i.e., if STATUS_I2C_BLOCK_EN == true (Step S1).

[0039] If the I2C block access has not been started or is not yet completed (see NO route in step S1), a single I2C write is performed via hardware access (step S2). Then, the I2C write process is completed.

[0040] On the other hand, if the I2C block access has started but not yet finished (see the YES route in step S1), the I2C write information is loaded into the SP firmware 60's memory without hardware access (step S3). Then, the I2C write process is completed.

[0041] Next, the I2C read process in the information processing device 600 shown in Figure 1 will be explained according to the flowchart (steps S11 to S13) shown in Figure 8.

[0042] Currently, it is determined whether the I2C block access has started but not yet finished, i.e., whether STATUS_I2C_BLOCK_EN == true (step S11).

[0043] If the I2C block access has not been started or is not yet completed (see NO route in step S11), a single I2C read is performed via hardware access (step S12). Then, the I2C read process is terminated.

[0044] On the other hand, if the I2C block access has started but not yet finished (see the YES route in step S11), the I2C read information is loaded into the SP firmware 60's memory without hardware access (step S13). Then, the I2C read process is completed.

[0045] Next, the process for initiating I2C block access in the information processing device 600 shown in Figure 1 will be explained according to the flowchart (step S21) shown in Figure 9.

[0046] The current state is flagged as "I2C block access started," i.e., STATUS_I2C_BLOCK_EN == true (step S21). Then, the I2C block access start process is completed.

[0047] Next, the termination process for I2C block access in the information processing device 600 shown in Figure 1 will be explained according to the flowchart (steps S31 to S33) shown in Figure 10.

[0048] Hardware access triggers I2C commands already stored in the SP firmware 60's memory as block access (step S31).

[0049] The memory of SP firmware 60 is cleared (step S32).

[0050] The current state is flagged as I2C block access termination, i.e., STATUS_I2C_BLOCK_EN == false (step S33). Then, the I2C block access termination process is completed.

[0051] Next, the I2C write process when only a single I2C access is performed will be explained according to the flowchart (step S41) shown in Figure 11.

[0052] A single I2C read is performed via hardware access (step S41). Then, the I2C write process is completed.

[0053] Next, the I2C read process when only a single I2C access is performed will be explained according to the flowchart (step S51) shown in Figure 12.

[0054] A single I2C read is performed via hardware access (step S51). Then, the I2C read process is completed.

[0055] Next, the common hardware control process when only single I2C access is performed will be explained according to the flowchart (step S61) shown in Figure 13.

[0056] The hardware control programs 631-634 specified by the arguments are executed (step S61). Then, the common hardware control process ends.

[0057] [B] Embodiment An embodiment will be described below with reference to the drawings. However, the embodiment shown below is merely illustrative, and there is no intention to exclude various modifications or applications of techniques not explicitly shown in the embodiment. In other words, this embodiment can be implemented in various ways without departing from its spirit. Furthermore, each figure is not intended to represent only the components shown in the figure, but may include other functions, etc.

[0058] In the following diagrams, the same symbols indicate the same parts, so their explanations are omitted.

[0059] [B-1] First Embodiment [B-1-1] Example of the configuration of the first embodiment Figure 14 is a schematic block diagram showing an example of the hardware configuration of the information processing device 100 in the first embodiment.

[0060] The information processing device 100 includes SP1, CPLD2, Central Processing Unit (CPU) 31, memory 32, Power Supply Unit (PSU) 33, and other control devices 34.

[0061] The CPU 31 is, as an example, a processing unit that performs various control and calculations, and realizes various functions by executing the Operating System (OS) and programs stored in the memory 32.

[0062] Memory 32 is, for example, a storage device that includes Read Only Memory (ROM) and Random Access Memory (RAM). The RAM may be, for example, Dynamic RAM (DRAM). A program such as a Basic Input / Output System (BIOS) may be written to the ROM of memory 32. The software program in memory 32 may be read by the CPU 31 as appropriate and executed. The RAM of memory 32 may be used as primary storage memory or working memory.

[0063] The PSU33 supplies power to the SP1, CPLD2, CPU31, memory32, and other control devices34.

[0064] Other control devices 34 may be, for example, a display control device, a storage device, an input interface (IF), an external recording medium processing device, or a communication interface.

[0065] SP1 is connected to CPLD2 via a control bus and manages CPLD2. Details of SP1 will be described later using Figure 15, etc.

[0066] CPLD2 is connected to the CPU 31, memory 32, PSU 33, and other control devices 34 via an I2C control bus (in other words, a serial bus). CPLD2 may also be a Field Programmable Gate Array (FPGA).

[0067] Figure 15 is a block diagram schematically showing an example of the firmware configuration of SP1 shown in Figure 14.

[0068] The SP firmware 10 executed on SP1 includes an I2C library 11, a control program 12, and a control engine 13.

[0069] The I2C library 11 functions as an access mode determination unit 111, a range specification unit 112, a write data storage unit 113, and an I2C access execution unit 114.

[0070] The access mode determination unit 111 determines whether automatic I2C block access mode or manual I2C block access mode is activated. In automatic I2C block access mode, the scope of block access is dynamically specified and block access processing is performed. On the other hand, in manual I2C block access mode, conventional block access processing is performed.

[0071] The range specification unit 112 dynamically specifies or does not specify the range of block access based on the degree of continuity of I2C write / read instructions. Specifically, in automatic I2C block access mode, the range specification unit 112 specifies the range of block access separately for cases where an I2C write is performed, where an I2C read is performed after an I2C write, and where an I2C read is performed. When an I2C write is performed, the range of the write is specified; when an I2C read is performed after an I2C write, the ranges of both the write and read are specified; and when an I2C read is performed, the range of block access is not specified.

[0072] In other words, the range specification unit 112 controls the range of commands that are blocked in a command issued via the serial bus according to a sequence of data write or data read operations.

[0073] The range specification section 112 may specify the range of the block command as the range of consecutive data writes in a consecutive pattern. Furthermore, the range specification section 112 does not need to specify the range of the block command if the consecutive pattern only includes data reads. Additionally, if a consecutive pattern includes data reads after a series of data writes, the range specification section 112 may specify the range from the consecutive data writes to the data reads as the range of the block command.

[0074] The write data storage unit 113 writes the I2C command list to the buffer.

[0075] The I2C access execution unit 114 performs block access within the range specified by the range specification unit 112.

[0076] In other words, the I2C access execution unit 114 accesses a controlled range of blocked commands.

[0077] The control program 12 functions as an access mode specification unit 121, a library call unit 122, a read data storage unit 123, and a termination notification unit 124.

[0078] The access mode specification unit 121 starts by specifying either automatic I2C block access mode or manual I2C block access mode. The access mode specification unit 121 can specify the start or end of manual I2C block access mode using the automatic / manual block access mode switching library called from each hardware control program 104. The start of manual I2C block access mode may be specified by the function void HAPI_BLOCK_ACCESS_MANUAL_MODE_START(); and the end by the function void HAPI_BLOCK_ACCESS_MANUAL_MODE_END();. When manual block access ends with the function for ending manual I2C block access mode, it switches to automatic block access mode. Both functions set flags within the SP firmware 10.

[0079] The library calling unit 122 calls the I2C library 11.

[0080] The read data storage unit 123 stores the results of the I2C read in memory.

[0081] The termination notification unit 124 notifies the control engine 13 that the control program 12 has terminated.

[0082] The control engine 13 functions as a program call unit 131, an unprocessed command determination unit 132, a range reset instruction unit 133, and a block access execution unit 134.

[0083] The program calling unit 131 calls the control program 12.

[0084] The unprocessed command determination unit 132 determines whether or not there are any unprocessed commands.

[0085] The range reset instruction unit 133 instructs the range specification unit 112 of the I2C library 11 to reset the range of block access.

[0086] The block access execution unit 134 performs block access to the range specified by the range specification unit 112 of the I2C library 11.

[0087] Figure 16 is a schematic block diagram showing an example of the firmware configuration of the CPLD2 shown in Figure 14.

[0088] The CPLD2 shown in Figure 14 functions as an I2C control unit 20. The I2C control unit 20 includes a single-access control unit 21 and a block access control unit 22.

[0089] The single-access control unit 21 executes a single access.

[0090] The block access control unit 22 performs block access and includes a command list buffer 221 and a read data buffer 222.

[0091] The command list buffer 221 buffers the I2C command list. The read data buffer 222 buffers the I2C read data.

[0092] Figure 17 is a diagram illustrating an example of the operation of the SP firmware 10 shown in Figure 15.

[0093] As shown in Figure 17, the common hardware control execution engine 103 is called from the inspection library 101 and log collection library 102, which are invoked by a command, and the component name (e.g., CPU or memory) and function (e.g., inspection or log collection) are selected as arguments and executed.

[0094] The common hardware control execution engine 103 includes start and end processes for automatic block access mode within its function and executes a hardware control program 104 according to the arguments.

[0095] The hardware control program 104 selects either automatic I2C block access mode or manual I2C block access mode within the program and executes the I2C block access library 105 and the I2C single access library 106. Then, the hardware control program 104 executes the I2C block access driver 107 and the I2C single access driver 108, respectively, from these I2C block access library 105 and I2C single access library 106 to perform hardware access.

[0096] As shown in symbols E1 and E3, the inspection library 101, log collection library 102, common hardware control execution engine 103, I2C block access library 105, I2C single access library 106, I2C block access driver 107, and I2C single access driver 108 are created by the firmware engineer.

[0097] On the other hand, as shown in symbol E2, each hardware control program 104 is created by the respective hardware person in charge.

[0098] Figure 18 is an example of a hardware control program 104 when the information processing device 100 shown in Figure 14 is set to automatic block access mode.

[0099] As indicated by symbol F1, in this embodiment, the default is automatic block access mode, so it is not necessary to specify automatic block access mode, and the hardware control program 104 may be executed. Note that xxx, yyy, ..., jjj are variables that represent the I2C parameters.

[0100] Figure 19 is an example of a hardware control program 104 when the information processing device 100 shown in Figure 14 is set to manual block access mode.

[0101] As indicated by symbols G1 and G2, the hardware control program 104 for manual block access mode specifies the start and end of manual block access mode, respectively. Note that xxx, yyy, ..., jjj are variables representing the I2C parameters.

[0102] Figure 20 is an example of a hardware control program 104 for CPU testing in the information processing device 100 shown in Figure 14.

[0103] As shown in Figure 20, the hardware control program 104 can be, for example, a CPU test hardware control program that is executed in the factory during mass production of the information processing device 100.

[0104] [B-1-2] Example of operation in the first embodiment The block access process in the information processing device 100 shown in Figure 14 will be explained according to the flowchart (steps S71 to S80) shown in Figure 21.

[0105] The access mode determination unit 111 determines whether the automatic I2C block access mode is activated (step S71).

[0106] If the automatic I2C block access mode is not activated and the manual I2C block access mode is activated (see NO route in step S71), the block access execution unit 134 performs normal block access processing (step S72). Then, the block access processing is terminated.

[0107] On the other hand, if the automatic I2C block access mode is activated (see the YES route in step S71), the range specification unit 112 dynamically specifies the range of block access based on the degree of continuity of I2C write / read instructions, or does not specify the range of block access (step S73). The range specification unit 112 specifies the write range when performing an I2C write, specifies the write and read ranges when performing an I2C read after an I2C write, and does not specify the block access range when performing an I2C read.

[0108] The range specification unit 112 specifies block access in the range of data W → data W → ... → data W → data R when performing an I2C read after an I2C write in the order of data W → data W → ... → data W → data R (step S74). Note that W indicates a read and R indicates a write. At the time of the I2C write, the SP firmware 10 simply processes the command parameters by loading them into memory, and at the time of the I2C read instruction, it moves on to the subsequent flow.

[0109] The control engine 13 initiates hardware access processing (step S76). Here, data R is determined and becomes available for use in the logic within the control program (step S76).

[0110] The unprocessed command determination unit 132 determines whether there are any I2C commands remaining in the subsequent control program 12 (step S77).

[0111] If there are any remaining I2C commands (see the YES route in step S77), the process returns to step S73.

[0112] On the other hand, if there are no remaining I2C commands (see NO route in step S77), the block access process terminates.

[0113] In step S73, when performing an I2C read of data R, the range specification unit 112 does not specify a range for block access (step S75). Then, the process proceeds to step S76.

[0114] In step S73, when I2C writing is performed in the order of data W → data W → ... → data W, the range specification unit 112 specifies block access in the range of data W → data W → ... → data W (step S78). The I2C write instruction can be executed simply by stacking its command parameters onto the memory of the SP firmware 10.

[0115] The termination notification unit 124 issues a termination notification for the control program 12 and has it received by the control engine 13 (step S79).

[0116] The control engine 13 initiates the hardware access process (step S80). Then, the block access process is terminated.

[0117] Next, the details of the block access process shown in Figure 21 will be explained according to the flowchart (steps S81 to S96) shown in Figure 22.

[0118] The access mode determination unit 111 determines whether the automatic I2C block access mode is activated (step S81).

[0119] If automatic I2C block access mode is activated (see the YES route in step S81), the range specification unit 112 determines whether the command is an I2C read (step S82).

[0120] If the command is an I2C read (see YES route in step S82), the range specification section 112 does not set a range for block access (step S83).

[0121] The I2C access execution unit 114 performs a single I2C access (step S84).

[0122] The termination notification unit 124 determines whether the control program 12 has terminated (step S85).

[0123] If control program 12 has not finished (see NO route in step S85), the process returns to step S82. On the other hand, if the control program 12 has finished (see the YES route in step S85), the block access process is terminated.

[0124] In step S82, if the command is not an I2C read (see NO root in step S82), the range specification unit 112 determines whether the I2C write is the last line of the control program 12 (step S86).

[0125] If the I2C write is on the last line of the control program 12 (see the YES route in step S86), the range specification unit 112 does not set a range for block access (step S87).

[0126] The I2C access execution unit 114 performs a single I2C access (step S88). Then, the block access process ends.

[0127] In step S86, if the I2C write is not on the last line of the control program 12 (see NO route in step S86), the range specification unit 112 determines whether there is an I2C read after the I2C write (step S89).

[0128] If there is no I2C read after an I2C write (see NO route in step S89), the range specification unit 112 sets the range of consecutive I2C writes as the range of block access (step S90).

[0129] The I2C access execution unit 114 performs block access processing within a range where I2C writes are continuous (step S91). Then, the block access processing is completed.

[0130] In step S89, if there is an I2C read after the I2C write (see YES route in step S89), the range specification unit 112 sets the range of block access to the period from the I2C write to the I2C read (step S92).

[0131] The I2C access execution unit 114 performs block access processing in the range from I2C write to I2C read (step S93).

[0132] The termination notification unit 124 determines whether the control program 12 has terminated (step S94).

[0133] If the control program 12 has not finished (see NO route in step S94), the process returns to step S82.

[0134] On the other hand, if the control program 12 terminates (see the YES route in step S94), the block access process terminates.

[0135] In step S81, if the automatic I2C block access mode is not activated (see NO route in step S81), the range specification unit 112 sets the range of block access that has been stored in advance (step S95).

[0136] The I2C access execution unit 114 executes block access processing within the scope of block access stored in advance (step S96). Then, the block access processing is completed.

[0137] Next, the I2C write process in the information processing device 100 shown in Figure 14 will be explained according to the flowchart (steps S101 to S104) shown in Figure 23.

[0138] The access mode determination unit 111 determines whether the current state is manual I2C block access mode, that is, whether MODE_I2C_BLOCK_MANUAL_EN == true (step S101).

[0139] Currently, if manual I2C block access mode is not in place (see NO route in step S101), the write data storage unit 113 loads the I2C read information into the SP firmware 10's memory without hardware access (step S102). Then, the I2C write process is completed.

[0140] On the other hand, if the system is currently in manual I2C block access mode (see the YES route in step S101), the I2C access execution unit 114 determines whether manual I2C block access has started and not yet finished, i.e., whether STATUS_I2C_BLOCK_EN == true (step S103).

[0141] If manual I2C block access has been started but is not yet completed (see the YES route in step S103), the process proceeds to step S102.

[0142] On the other hand, if the I2C block access has not been started or is not yet completed (see NO route in step S103), the I2C access execution unit 114 performs a single I2C read using hardware access (step S104). Then, the I2C write process is completed.

[0143] Next, the I2C read process in the information processing device 100 shown in Figure 14 will be explained according to the flowchart (steps S111 to S117) shown in Figure 24.

[0144] The access mode determination unit 111 determines whether the current state is manual I2C block access mode, i.e., whether MODE_I2C_BLOCK_MANUAL_EN == true (step S111).

[0145] Currently, if manual I2C block access mode is not being used (see NO route in step S111), the write data storage unit 113 loads the I2C read information onto the SP firmware 10's memory without hardware access (step S112).

[0146] The I2C access execution unit 114 uses hardware access to trigger I2C commands that are already stored in the memory of the SP firmware 10 (step S113).

[0147] The access mode determination unit 111 clears the memory (step S114). Then, the I2C read operation is terminated.

[0148] In step S111, if the system is currently in manual I2C block access mode (see the YES route in step S111), the I2C access execution unit 114 determines whether manual I2C block access has started and not yet finished, i.e., whether STATUS_I2C_BLOCK_EN == true (step S115).

[0149] If manual I2C block access has been started but is not yet completed (see the YES route in step S115), the write data storage unit 113 loads the I2C read information onto the SP firmware 10's memory without hardware access (step S117). Then, the I2C read process is completed.

[0150] On the other hand, if the I2C block access has not been started or is not yet completed (see NO route in step S115), the I2C access execution unit 114 performs a single I2C read using hardware access (step S116). Then, the I2C read process is completed.

[0151] Next, the process for initiating I2C block access in the information processing device 100 shown in Figure 14 will be explained according to the flowchart (steps S121 to S123) shown in Figure 25.

[0152] The access mode determination unit 111 determines whether the current state is manual I2C block access mode, i.e., whether MODE_I2C_BLOCK_MANUAL_EN == true (step S121).

[0153] If the system is not currently in manual I2C block access mode (see NO route in step S121), the access mode determination unit 111 outputs a message indicating an error in the hardware control program 104 and terminates (step S122). The I2C block access start process then ends.

[0154] On the other hand, if the system is currently in manual I2C block access mode (see the YES route in step S121), the access mode determination unit 111 sets the current state to "I2C block access started" by setting STATUS_I2C_BLOCK_EN = true (step S123). Then, the I2C block access start process is completed.

[0155] Next, the termination process for I2C block access in the information processing device 100 shown in Figure 14 will be explained according to the flowchart (steps S131 to S135) shown in Figure 26.

[0156] The access mode determination unit 111 determines whether the current state is manual I2C block access mode, i.e., whether MODE_I2C_BLOCK_MANUAL_EN == true (step S131).

[0157] If the system is not currently in manual I2C block access mode (see NO route in step S131), the access mode determination unit 111 outputs a message indicating an error in the hardware control program 104 and terminates forcibly (step S132). The I2C block access termination process then ends.

[0158] On the other hand, if the system is currently in manual I2C block access mode (see the YES route in step S131), the I2C access execution unit 114 uses hardware access to trigger I2C commands already stored in the SP firmware 10's memory as block access (step S133).

[0159] The I2C access execution unit 114 clears the memory (step S134).

[0160] The access mode determination unit 111 sets the current state to "I2C block access terminated" by setting STATUS_I2C_BLOCK_EN = False (step S135). Then, the I2C block access termination process is completed.

[0161] Next, the process for initiating manual I2C block access in the information processing device 100 shown in Figure 14 will be explained according to the flowchart (step S141) shown in Figure 27.

[0162] The access mode specification unit 121 changes the current mode to manual I2C block access by setting MODE_I2C_BLOCK_MANUAL_EN = true (step S141). Then, the process for starting manual I2C block access is completed.

[0163] Next, the termination process for manual I2C block access in the information processing device 100 shown in Figure 14 will be explained according to the flowchart (step S151) shown in Figure 28.

[0164] The access mode specification unit 121 changes the current mode to automatic I2C block access by setting MODE_I2C_BLOCK_MANUAL_EN = false (step S151). Then, the process for starting manual I2C block access is completed.

[0165] Next, the common hardware control processing in the information processing device 100 shown in Figure 14 will be explained according to the flowchart (steps S161 to S165) shown in Figure 29.

[0166] The library call unit 122 executes the hardware control program 104 specified by the argument (step S161).

[0167] The access mode determination unit 111 determines whether the current state is manual I2C block access mode, i.e., whether MODE_I2C_BLOCK_MANUAL_EN == true (step S162).

[0168] If the current mode is manual I2C block access mode (see the YES route in step S162), the common hardware control process terminates.

[0169] On the other hand, if the system is not currently in manual I2C block access mode (see NO route in step S162), the unprocessed command determination unit 132 determines whether there are I2C commands in the memory of the SP firmware 10 (step S163).

[0170] If there are no I2C commands in memory (see NO route in step S163), the common hardware control process terminates.

[0171] On the other hand, if an I2C command exists in memory (see the YES route in step S163), the I2C access execution unit 114 triggers the I2C command already stored in the memory of the SP firmware 10 via hardware access (step S164).

[0172] The I2C access execution unit 114 clears the memory (step S165). Then, the common hardware control processing ends.

[0173] [B-2] Second Embodiment [B-2-1] Example of configuration of the second embodiment Figure 30 is a schematic block diagram showing an example of the hardware and functional configuration of the information processing device 200 in the second embodiment. Components similar to those in the information processing device 100 in the first embodiment are denoted by the same reference numerals and described accordingly.

[0174] In the second embodiment, the information processing device 200 issues a number of commands, including a Read Modify Write command. The information processing device 200 designates the range of commands to be blocked as the range that includes at least the commands before and after the Read Modify Write command.

[0175] A "read-modify-write command" reads data, modifies (changes, processes) the values ​​of specified bits in the read data, and then writes the modified data. Bits that are not specified remain unchanged. Read-modify-write is also called data-read-modify-write.

[0176] The information processing device 200 may include SP1, CPLD2, and multiple boards 9.

[0177] SP1 issues several commands to CPLD2 via control bus 3, including at least read-modify-write commands. Control bus 3 is an example of a serial bus.

[0178] In this example, even if the command from SP1 to CPLD2 is a read-after-write command, it is integrated as a read-modify-write command.

[0179] SP1 may have an I2C read-modify-write function for issuing read-modify-write commands in the I2C block access library 105 shown in Figure 17.

[0180] SP1 may block a range of commands that includes the commands before and after a read-modify-write command, depending on the sequence pattern of commands. The range specification unit 112 (see Figure 15) may specify the range of commands to be blocked as the range of commands that includes the commands before and after a read-modify-write command. In other words, the range specification unit 112 does not need to separate the read-modify-write command into two block commands before and after it.

[0181] The range specification unit 112 controls the range of commands to be blocked in a command issued via the control bus 3, according to a sequence of combinations of data write, data read, and read-modify-write operations.

[0182] The range specification unit 112 may specify the range of the command to be blocked as the range that includes at least one of data write and read modify write in a continuous pattern. Furthermore, the range specification unit 112 may not specify the range of the command to be blocked as the range that includes at least one of data write and read modify write in a continuous pattern. Additionally, if a data read is included after the range that includes at least one of data write and read modify write in a continuous pattern, the range specification unit 112 may specify the range from that range to the data read as the range of the command to be blocked.

[0183] In SP1, the I2C access execution unit 114 (see Figure 15) performs block access within the range specified by the range specification unit 112. In other words, the I2C access execution unit 114 accesses a range of controlled, blockable commands. For example, the control engine 13 initiates hardware access processing. In other words, SP1 sends a block access initiation instruction to the CPLD2. A block access initiation instruction is an example of an execution instruction.

[0184] SP1 may have the same configuration as shown in Figure 14, except that it can issue read-modify-write commands and that there is a difference in the range specification section 112, and may have the same firmware configuration as shown in Figures 15 and 17.

[0185] Each of the multiple boards 9 is equipped with multiple components 93a to 93c, which are components to be controlled. The components 93a to 93c may include the CPU 31, memory 32, PSU 33, and other control devices 34 shown in Figure 14 of the first embodiment. The multiple components 93a to 93c provided on each board 9 may be of the same type or of different types.

[0186] CPLD2 is connected to components 93a to 93c via an I2C control bus. CPLD2 may be provided on each of the boards 9.

[0187] CPLD2 is an example of a control circuit. CPLD2 may function as an MBC. Instead of CPLD2, an FPGA may be provided in the information processing device 200.

[0188] CPLD2 is connected to SP1 via control bus 3.

[0189] The CPLD2 may include a component control unit 80, a buffer 81, a buffer control unit 82, an I2C control circuit 83, and a read / modify / write control unit 84. Each function of the CPLD2 may be implemented as firmware.

[0190] Buffer 81 may be a storage unit within the CPLD2, or it may be a storage unit located outside the CPLD2, as shown in Figure 1. Buffer 81 can be accessed and updated by SP1 and component control unit 80.

[0191] Buffer 81 may include a command list buffer 811 and a read data buffer 812. The command list buffer 811 buffers the I2C command list. The read data buffer 812 buffers the I2C read data. In the second embodiment, the CPLD2 may receive a block of commands from the SP1 via the control bus 3, including commands before and after at least a read-modify-write command, and store it in the command list buffer 811.

[0192] The I2C command list contains a series of commands that are executed sequentially on board 9 as a sequence of processing steps (i.e., a sequence of steps) that are executed sequentially on board 9.

[0193] The buffer control unit 82 controls the writing and reading of data to and from the buffer 20b. The buffer control unit 82 may also function as a read unit that reads a series of commands one by one from the command list buffer 811 in response to execution instructions received from SP1.

[0194] The component control unit 80 identifies the control target component to be controlled by the command from among the multiple components 93a to 93c based on the command read by the buffer control unit 82. The component control unit 80 also controls multiple components by activating the I2C control circuit 83, which corresponds to the I2C control interface method, and sequentially executing the processing corresponding to the read command on each of the multiple boards 9. The component control unit 80 notifies SP1 of the execution results of the series of commands.

[0195] The component control unit 80 may include a command format decoder 85. The command format decoder 85 decodes the command format of the command received from SP1. The command format decoder 85 has not only I2C read and I2C write functions, but also I2C read-modify-write functions, and decodes the command formats for data write, data read, and read-modify-write.

[0196] The read-modify-write control unit 84 performs control based on the read-modify-write command received from SP1. For example, the read-modify-write control unit 84 performs I2C read processing from a specified register, modification processing (merging processing) within CPLD2, and I2C write processing of the modified data to a specified register. The I2C read and I2C write processing may be performed by activating the interface circuit, the I2C control circuit 83.

[0197] The modification process within CPLD2 involves modifying (changing) the value of a specified bit in the read data. The specified bit may be specified by the mask field in the read-modify-write command received from SP1. The specified data, which is the value to be modified, may be specified in the data field of the read-modify-write command. The configuration of the fields in the read-modify-write command will be described later.

[0198] Figure 31 illustrates an example of read-modify-write processing in the information processing device 100 shown in Figure 14. On the other hand, Figure 32 illustrates an example of read-modify-write processing in the information processing device 200 shown in Figure 30.

[0199] Figures 31 and 32 show the case where the commands are executed in the following order: data write W, data write W, read modify write RMW, data write W, data read R.

[0200] In the example shown in Figure 31, for read-modify-write (RMW), SP1 issues I2C read command #3 and I2C write command #4 to CPlD2.

[0201] SP1 receives read data from CPLD2 via I2C read command #3. SP1 then modifies (merges) the received read data to prepare write data for I2C write command #4.

[0202] In the example shown in Figure 31, SP1 issues I2C write command #1 → I2C write command #2 → I2C read command #3 (the read portion of read-modify-write) in that order, with the I2C read command coming after the I2C write command. Therefore, based on the fact that I2C read command #3 is a read command, the range specification unit 112 sets the range of I2C write command #1, I2C write command #2, and I2C read command #3 as the range of commands to be blocked.

[0203] Similarly, the range specification section 112 defines the range of commands that block the ranges of I2C write command #4 (the write portion of read-modify-write), I2C write command #5, and I2C read command #6 according to a sequence of data write or data read patterns.

[0204] As a result, with respect to the read-modify-write (RMW) command, commands issued before (e.g., I2C write command #2) and commands issued after (e.g., I2C write command #5) are separated into separate block access commands #1 and #2. In the example in Figure 31, I2C block access command #1 includes I2C write command #1, I2C write command #2, and I2C read command #3. I2C block access command #2 includes I2C write command #4, I2C write command #5, and I2C read command #6.

[0205] In the information processing device 100, even if the data written by I2C write command #4 is the same data obtained from the read process of I2C read command #3, it will not malfunction. However, since the block access is split into two, CPID2 sends a completion notification to SP1 each time each block access is completed. SP1 needs to check the execution result after each of the two block accesses is completed.

[0206] In contrast, in the information processing device 200 that performs the processing shown in Figure 32, read-modify-write (RMW) is added as one of the block access command formats to the I2C block access library 105 of SP1.

[0207] Therefore, SP1 can issue "I2C read-modify-write command #3" after I2C write command #1 and I2C write command #2.

[0208] The range specification unit 112 of the information processing device 200 designates the range of commands to be blocked, which includes the I2C write commands #2 and #4 before and after the I2C read-modify-write command #3. In other words, the range specification unit 112 does not divide the I2C read-modify-write command #3 into two block commands before and after it.

[0209] The range specification unit 112 controls the range of commands to be blocked in a command issued via the control bus 3, according to a sequence of combinations of data write, data read, and read-modify-write operations.

[0210] In the example shown in Figure 32, the range specification unit 112 specifies the range to be blocked, noting that in a continuous pattern, a data read (#5) is included after a range (range #1 to #4) that includes at least one of a data write and a read modify write. In Figure 32, the range specification unit 112 specifies the range from the range #1 to #4 to the data read (#5) as the range of commands to be blocked.

[0211] As a result, I2C write command #1, I2C write command #2, I2C read-modify-write command #3, I2C write command #4, and I2C read command #5 are blocked into a single I2C block access command #1.

[0212] The read-modify-write control unit 84 shown in Figure 30 may perform control based on the read-modify-write command received from SP1. For example, the read-modify-write control unit 84 may execute I2C read command #3-1 from the specified register, perform modification processing within CPLD2, and execute I2C write command #3-2 to the specified register of the modified data.

[0213] In the second embodiment, the CPLD2 prepares the write data for the I2C write command #3-2 by modifying (merging) the read data obtained in response to the I2C read command #3-1.

[0214] According to the process shown in Figure 32, the series of commands are not separated into two block commands, one before and one after the I2C read-modify-write command #3. Therefore, according to the information processing device 200 shown in Figure 30, the frequency with which SP1 checks the execution result after each block access can be reduced. As a result, the busy rate of SP1 can be lowered. In addition, the number of block accesses can be reduced, and the overall time required for block access can be shortened.

[0215] Figure 33 shows an example of the command format in the information processing device 200 shown in Figure 30. However, the command format is not limited to the example shown in Figure 33.

[0216] Each command may include a command format field, a controller field, a slave address field, a byte count field, a PEC field, a header length field, a data length field, and a header field. Furthermore, I2C write commands and I2C read-modify-write commands may include a data field. Additionally, I2C read-modify-write commands may include a mask field.

[0217] The command format field specifies the type of command. For example, a command format field of 0 indicates an I2C write command, a command format field of 1 indicates an I2C read command, and a command format field of 2 indicates an I2C read modify command.

[0218] The slave address command indicates the address assigned to the connected components on the I2C bus. The byte count field indicates whether a byte count is performed. The PEC field indicates whether packet error checking is performed. The header length field indicates the header length. The data length field indicates the data length. The header field includes the header.

[0219] The data field contains data. In I2C write commands, the data in the data field is the data to be written. In I2C read-modify-write commands, the data in the data field is the data used to modify (change) the specified bits specified by the mask field.

[0220] The mask field contains information (sometimes referred to as "mask information") indicating which bits of data in the data field should be written to. In the example in Figure 33, the bits of data in the data field that should be written (i.e., the bits to be modified) are shown as 0, and the bits of read data that should be written as is are shown as 1. However, the mask field is not limited to this case.

[0221] Figure 34 shows an example of the I2C write data generation process in the read-modify-write process of the information processing device 200 shown in Figure 30.

[0222] CPLD2 receives an I2C read-modify-write command from SP1, and when a block access kick is triggered, it performs actions based on the I2C read-modify-write command received from SP1.

[0223] As indicated by symbol H1, an I2C read-modify-write command may include a data field (RM-Data). In Figure 34, the specified data RM-Data in the data field is 0x10.

[0224] An I2C read-modify-write command may include a mask field (RM-Mask). In Figure 34, the mask information in the mask field is 0x0f.

[0225] The read-modify-write control unit 84 generates an I2C read command to obtain read data from a specified register (slave address). As a result, as shown in symbol H2, the CPLD2 receives read data (R-Data) corresponding to the I2C read command from at least one of components 93a to 93b. For example, in Figure 34, the read data R-Data is 0x22.

[0226] During the modification process within CPLD2, CPLD2 sets the bit with a value of 1 in the mask information (0x0f) of the mask field to the corresponding bit value of the read data (0x22). Additionally, CPLD2 sets the bit with a value of 0 in the mask information (0x0f) of the mask field to the corresponding bit value of the specified data RM-Data (0x10) in the data field. As a result, CPLD2 obtains 0x12 as the modified data.

[0227] In other words, CPLD2 calculates a first result (00000010), which is the logical AND of the mask information (00001111) and the read data (00100010). CPLD2 also calculates a second result (00010000), which is the logical AND of the negation NOT of the mask information (00001111), (111100000), and the specified data RM-Data (00010000) in the data field. Finally, CPLD2 may calculate a third result (00010010), which is the logical OR of the first result (00000010) and the second result (00010000), i.e., 0x12. This third result is the modified data.

[0228] As shown in code H3, CPLD2 generates an I2C write command to write the modified data to the specified register. As a result, the modified data is written to the specified register. The specified register may be the same register from which the read data was read.

[0229] [B-2-2] Example of operation in the second embodiment An example of the processing content including read-modify-write operations in the information processing device 200 shown in Figure 30 will be explained according to the sequence diagram (steps S201 to S217) shown in Figure 36. For reference, an example of the processing content including read-modify-write operations in the information processing device 100 shown in Figure 14 is also shown in Figure 35.

[0230] Figures 35 and 36 illustrate the case where the commands are executed in the order of DataWriteW, DataWriteW, ReadModifyWriteRMW, DataWriteW, and DataReadR, as shown in Figures 31 and 32. Note that in Figures 35 and 36, the # symbol is omitted from commands #1 to #6.

[0231] First, referring to Figure 35, the processing performed by the information processing device 100 shown in Figure 14 will be explained. In Figure 35, SP1 places I2C write command #1 into the queue (step S171). For example, the process of placing the command into the queue may be the process by which the write data storage unit 113 (see Figure 15) stores information for I2C read in the memory of the SP firmware 10 without hardware access. Furthermore, SP1 places I2C write command #2 into the queue (step S172).

[0232] The read-modify-write (RMW) command is issued separately as I2C read command #3 and I2C write command #4. Therefore, SP1 places I2C read command #3 into the queue (step S173). The processing in steps S171 to S173 is an example of the process by which SP1 places each I2C control content from the hardware control program into a queue within SP1.

[0233] The range specification unit 112, based on the fact that #3 is a read command, specifies the range of I2C write command #1, I2C write command #2, and I2C read command #3 as the range of commands to be blocked. SP1 writes the series of I2C write command #1, I2C write command #2, and I2C read command #3 to the command list buffer 221 of CPLD2 (step S174). I2C write command #1, I2C write command #2, and I2C read command #3 are blocked as a single I2C block access command #1.

[0234] SP1 sends a block access initiation command to CPLD2 (step S175).

[0235] When CPLD2 receives a block access initiation instruction, it writes the data of I2C write command #1 to the component to be controlled (step S176). CPLD2 also writes the data of I2C write command #2 to the component to be controlled (step S177). Furthermore, CPLD2 reads data from the register of the component specified by I2C read command #3 (step S178).

[0236] Steps S176 to S178 are an example of the process by which the MBC executes its respective I2C control for each component.

[0237] CPLD2 stores the read data from the register specified by I2C read command #3 in the read data buffer 222 (step S179). In step S179, CPLD2(MBC) may store all read data in the read data buffer 222.

[0238] CPLD2 sends completion notifications for a series of I2C write commands #1, #2, and #3, i.e., completion notifications for I2C block access command #1, to SP1 (step S180).

[0239] SP1 reads the read data from the register specified by the I2C read command #3 from the read data buffer 222 of the CPLD2 (step S181). SP1 may read all the read data from the read data buffer 222. SP1 may store each of the values ​​of all the read data it has read in the read data area of ​​the hardware control program. For example, the read data area of ​​the hardware control program is the read data storage unit 123 in Figure 15.

[0240] SP1 modifies the read data read in step S181 by specifying bits to specify data (step S182). The specified bits and specified data may be specified by the hardware control program 104 (see Figure 17).

[0241] SP1 pushes I2C write command #4 into the queue (step S183). I2C write command #4 is a command that writes the modified data (merged data), in which the specified bits were modified in step S182, to the specified register.

[0242] SP1 places I2C write command #5 into the queue (step S184). Furthermore, SP1 places I2C read command #6 into the queue (step S185).

[0243] Based on the fact that #6 is a read command, the range specification section 112 sets the range of I2C write command #4, I2C write command #5, and I2C read command #6 as the range of commands to be blocked.

[0244] SP1 writes I2C write command #4, I2C write command #5, and I2C read command #6 to the command list buffer 221 of CPLD2 (step S186).

[0245] I2C write command #4, I2C write command #5, and I2C read command #6 are blocked together as a single I2C block access command #2.

[0246] SP1 sends a block access initiation command to CPLD2 (step S187).

[0247] When CPLD2 receives a block access activation instruction, it writes the data of I2C write command #4 to the component to be controlled (step S188). CPLD2 also writes the data of I2C write command #5 to the component to be controlled (step S189).

[0248] Furthermore, CPLD2 reads data from the registers of the component specified by I2C read command #6 (step S190).

[0249] CPLD2 stores the read data from the register specified by I2C read command #6 into the read data buffer 222 (step S191).

[0250] CPLD2 sends completion notification for a series of I2C write commands #4, #5, and #6 to SP1 (step S192).

[0251] SP1 reads the read data from the register specified by the I2C read command #6 from the read data buffer 222 of CPLD2 (step S193).

[0252] According to the process shown in Figure 35, SP1 can read the target read data to be modified before performing the modification (merge) process, thus preventing malfunctions. However, the completion notification of block access from CPLD2 to SP1 will be sent twice (steps S180 and S192).

[0253] Next, referring to Figure 36, the processing performed by the information processing device 200 shown in Figure 30 will be explained.

[0254] The processes in steps S201 and S202 are the same as the processes in steps S171 and S172 in Figure 35.

[0255] SP1 places I2C read-modify-write command #3 into the queue (step S203). In the I2C block access library 105 of SP1 of the information processing device 200, read-modify-write (RMW) has been added as one of the block access command formats.

[0256] SP1 places I2C write command #4 into the queue (step S204). SP1 also places I2C write command #5 into the queue (step S205).

[0257] The range specification unit 112 controls the range of commands to be blocked based on a sequence of patterns of combinations of data write, data read, and read modify write in a series of commands.

[0258] In this example, the range specification unit 112 focuses on the fact that in a continuous pattern, a data read (#5) is included after a range (#1 to #4) which includes at least one of a data write and a read modify write. The range specification unit 112 specifies the range from #1 to #4 to the data read (#5) as the range of the command to be blocked.

[0259] In other words, the range specification section 112 may specify a range that includes at least the commands (#2, #4) before and after the I2C read-modify-write command #3 as the range of commands to be blocked.

[0260] The processing from step S201 to step S205 is an example of SP1 queuing each I2C control content in the hardware control program within SP1. As shown in FIG. 36, SP1 may queue the control content before and after, including the control content of read modify write, in the queue within SP1 based on the control content of read modify write.

[0261] SP1 writes a series of I2C write commands #1, I2C write command #2, I2C read modify write command #3, I2C write command #4, and I2C read command #5 to the command list buffer 811 of CPLD2 (step S206).

[0262] In other words, I2C write command #1, I2C write command #2, I2C read modify write command #3, I2C write command #4, and I2C read command #5 are blocked into one I2C block access command #1.

[0263] SP1 sends a startup instruction for block access to CPLD2 (step S207).

[0264] When CPLD2 receives the startup instruction for block access, it writes the data of I2C write command #1 to the component to be controlled (step S208). Also, CPLD2 writes the data of I2C write command #2 to the component to be controlled (step S209).

[0265] CPLD2 executes an I2C read command #3-1 corresponding to the read part of the I2C read modify write command #3 (S210). For example, CPLD2 reads data from the register of the component specified by the I2C read modify command #3.

[0266] CPLD2 modifies the designated bits in the read data read in step S210 to the designated data (step S211). The designated bits may be designated by the mask information included in the mask field of the I2C read modify command #3. The designated data may be designated in the data field in the read modify write command.

[0267] CPLD2 executes the I2C write command #3-2 (step S212). The I2C write command #3-2 is a command corresponding to the write part for writing the modified data in which the designated bits are modified in step S211. Based on the I2C write command #3-2, the modified data is written into the designated register.

[0268] CPLD2 writes the data of the I2C write command #4 to at least one of the components 93a to 93c to be controlled (step S213).

[0269] Furthermore, CPLD2 reads data from the register of the component designated by the I2C read command #5 (step S214).

[0270] The processes of steps S208 to S210 and steps S212 to S214 are an example of the processes in which CPLD2 (MBC) executes I2C control for each of the components 93a to 93c. However, the read modify write process (steps S210 to S212) is executed between the MBC and each of the components 93a to 93c. The process of SP1 may not intervene during the read modify write process.

[0271] In other words, SP1 may cause CPLD2 to execute the read modify write process as a non-blocking process.

[0272] CPLD2 stores the read data from the register specified by I2C read command #5 in the read data buffer 812 (step S215). In step S215, CPLD2(MBC) may store all read data in the read data buffer 812. Therefore, data including the result of the read-modify-write operation is stored in the read data buffer 812.

[0273] CPLD2 sends completion notifications for a series of I2C write commands #1, #2, #3, #4, and #5, i.e., completion notifications for I2C block access command #1, to SP1 (step S216).

[0274] SP1 reads the read data from the register specified by the I2C read command #5 from the read data buffer 812 of the CPLD2 (step S217). This allows SP1 to obtain data including the result of the read-modify-write operation.

[0275] [C] Effect According to the program, information processing devices 100, 200, access control program, and access control method in the above-described embodiment, the following effects can be achieved, for example.

[0276] The range specification unit 112 controls the range of commands to be blocked in a command issued via the serial bus, according to a sequence of data writes or data reads. The I2C access execution unit 114 accesses the controlled range of commands to be blocked. This reduces the time required for command transmission.

[0277] The range specification unit 112 specifies the range of consecutive data writes in a continuous pattern as the range of the command to block the data writes. This reduces the processing time for the data writes.

[0278] The range specification section 112 does not specify the range of commands to be blocked if the continuous pattern is limited to data reads. This reduces the processing time for data reads.

[0279] The range specification unit 112 specifies the range from the consecutive data writes to the data reads as the range of the command to be blocked, in the case where a data read is included after a series of data writes in a consecutive pattern. This ensures that the processing of data reads that use the processing results of data writes can be carried out reliably.

[0280] The range designation unit 112 issues multiple commands via the serial bus, including at least a read-modify-write command. The range designation unit 112 designates a range of commands that includes the commands before and after the read-modify-write command, depending on the sequence pattern, as a block of commands. The I2C access execution unit 114 accesses the controlled block of commands. This reduces the processing time for read-modify-write operations and also reduces the time required for command transmission.

[0281] The range specification unit 112 controls the range of commands to be blocked according to a sequence pattern of data write, data read, and read-modify-write operations in commands issued via the serial bus. This reduces the time required for command transmission.

[0282] A read-modify-write command includes at least a data field containing data and a mask field containing information indicating which bits to write the data in the data field to. This reduces the time required for command transmission.

[0283] The information processing device 200 further comprises a CPLD2 and multiple boards 9 on which multiple components are mounted. The CPLD2 receives a series of blocked commands from the SP1 via the serial bus, including commands before and after at least read-modify-write commands, and stores them in a buffer 81. In response to execution instructions received from the SP1 via the serial bus, the CPLD2 reads the series of commands one by one from the buffer 81 and controls multiple components 93 by sequentially executing the processing corresponding to the read commands on each of the multiple boards 9. The CPLD2 notifies the SP1 of the execution results of the series of commands. This reduces the time required for command transmission.

[0284] In automatic block access mode, blocks of "(I2C) write, write, ..., write, read" in the hardware control program 104 are automatically converted into block access. In most cases (for about 95k steps out of a total of 100ksteps in the hardware control program 104), effective performance improvements can be expected in automatic block access mode. The automatic block access mode, which is used by the majority, should be considered the default. In other words, the hardware control program 104, which is written with manual block access, can be reduced from 100ksteps to 5ksteps, resulting in a significant reduction in implementation costs.

[0285] In other words, automating block access can reduce implementation costs by 95%. As a result of this automation, for example, the number of block access-related logical failures can be reduced from 10 per model to 1.

[0286] In the hardware control program 104, if an I2C read occurs but the data obtained is not used (for example, for subsequent control writes or conditional branching), there is no need to separate the block access; it can be grouped together without logical problems. Grouping can improve performance, and for this reason, the option to select "manual block access mode" is provided.

[0287] By fulfilling the functions of the common part (the module outside each hardware control program), the total implementation cost can be reduced and the quality can also be improved.

[0288] 〔D〕Others The disclosed technology is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the spirit of this embodiment. Each configuration and each process of this embodiment can be selectively adopted as necessary, or can be appropriately combined.

[0289] 〔E〕Supplementary Notes Regarding the above embodiments, the following supplementary notes are further disclosed.

[0290] (Supplementary Note 1) Controlling the range of commands to be blocked according to the continuous pattern of data write or data read in the commands issued via the serial bus, Accessing the controlled range of the commands to be blocked, An information processing apparatus including a processor.

[0291] (Supplementary Note 2) When data write is continuous in the continuous pattern, the processor designates the range of the continuous data write as the range of the commands to be blocked, The information processing apparatus according to Supplementary Note 1.

[0292] (Supplementary Note 3) When only data read is included in the continuous pattern, the processor does not designate the range of the commands to be blocked, The information processing apparatus according to Supplementary Note 1 or 2.

[0293] (Supplementary Note 4) When data read is included after data write is continuous in the continuous pattern, the processor designates the range from the continuous data write to the data read as the range of the commands to be blocked, An information processing device as described in any one of the appendices 1 to 3.

[0294] (Note 5) It issues several commands via the serial bus, including at least read-modify-write commands. Depending on the sequence pattern of the aforementioned commands, the range including the commands before and after the read-modify-write command is designated as the command range to be blocked. Access the specified range of the blocking command, An information processing device equipped with a processor.

[0295] (Note 6) The processor controls the range of the commands to be blocked in accordance with a sequence of combinations of data write, data read, and read-modify-write operations in the commands issued via the serial bus. The information processing device described in Appendix 5.

[0296] (Note 7) The information processing apparatus according to Appendix 5 or 6, wherein the read-modify-write command includes at least a data field containing data and a mask field containing information indicating bits to write the data in the data field.

[0297] (Note 8) Control circuit and Multiple boards on which multiple components are mounted, Furthermore, The aforementioned control circuit is At least a block of commands including commands before and after the read-modify-write command is received from the processor via the serial bus and stored in a buffer. In response to execution instructions received from the processor via the serial bus, the system reads the series of commands one by one from the buffer, sequentially executes processing corresponding to the read commands on each of the multiple boards to control the multiple components, and notifies the processor of the execution results of the series of commands. An information processing device as described in any one of the items 5 to 7 of the appendix.

[0298] (Note 9) In commands issued via a serial bus, the range of commands to be blocked according to a sequence of data writes or data reads is controlled. Accessing the controlled range of the blocking commands, An access control program that allows a computer to execute a process.

[0299] (Note 10) If data writes are consecutive in the aforementioned consecutive pattern, the range of such consecutive data writes is specified as the range of the blocking command. An access control program as described in Appendix 9, which causes the computer to perform the processing.

[0300] (Note 11) If the sequence pattern includes only data reads, the range of the block command is not specified. An access control program as described in Appendix 9 or 10, which causes the computer to perform the processing.

[0301] (Note 12) If a data read is included after a series of data writes in the aforementioned sequence pattern, the range from the consecutive data writes to the data reads is specified as the range of the blocking command. An access control program described in any one of the appendices 9 to 11, which causes the computer to perform the processing.

[0302] (Note 13) It issues several commands via the serial bus, including at least read-modify-write commands. Depending on the sequence pattern of the aforementioned commands, the range including the commands before and after the read-modify-write command is designated as the command range to be blocked. Access the specified range of the blocking command, An access control program that allows a computer to execute a process.

[0303] (Note 14) The command issued via the serial bus controls the range of the block of the command according to a sequence of combinations of data write, data read, and read-modify-write. An access control program as described in Appendix 13, which causes the computer to execute the processing.

[0304] (Note 15) The read-modify-write command is an access control program as described in Appendix 13 or 14, comprising at least a data field containing data and a mask field containing information indicating bits to write the data in the data field.

[0305] (Note 16) At least a block of commands, including read, modify, and write commands, is received from the processor via the serial bus and stored in a buffer. In response to execution instructions received from the processor via the serial bus, the series of commands are read one by one from the buffer, and the processing corresponding to the read command is sequentially executed on each of the multiple boards on which multiple components are mounted to control the multiple components, and the execution result of the series of commands is notified to the processor. An access control program that directs the control circuit to execute a process.

[0306] (Note 17) In commands issued via a serial bus, the range of commands to be blocked according to a sequence of data writes or data reads is controlled. Accessing the controlled range of the blocking commands, A method of access control in which a computer performs a process.

[0307] (Note 18) If data writes are consecutive in the aforementioned consecutive pattern, the range of such consecutive data writes is specified as the range of the blocking command. The access control method described in Appendix 17, wherein the computer performs the processing.

[0308] (Note 19) If the sequence pattern includes only data reads, the range of the block command is not specified. The access control method described in Appendix 17 or 18, wherein the computer performs the processing.

[0309] (Note 20) If a data read is included after a series of data writes in the aforementioned sequence pattern, the range from the consecutive data writes to the data reads is specified as the range of the blocking command. An access control method according to any one of the appendices 17 to 19, wherein the computer performs the processing.

[0310] (Note 21) It issues several commands via the serial bus, including at least read-modify-write commands. Depending on the sequence pattern of the aforementioned commands, the range including the commands before and after the read-modify-write command is designated as the command range to be blocked. Access the specified range of the blocking command, A method of access control in which a computer performs a process.

[0311] (Note 22) The command issued via the serial bus controls the range of the block of the command according to a sequence of combinations of data write, data read, and read-modify-write. The access control method described in Appendix 21, wherein the computer performs the processing.

[0312] (Note 23) The access control method according to Appendix 21 or 22, wherein the read-modify-write command includes at least a data field containing data and a mask field containing information indicating bits to write the data in the data field.

[0313] (Note 24) At least a block of commands, including read, modify, and write commands, is received from the processor via the serial bus and stored in a buffer. In response to execution instructions received from the processor via the serial bus, the series of commands are read one by one from the buffer, and the processing corresponding to the read command is sequentially executed on each of the multiple boards on which multiple components are mounted to control the multiple components, and the execution result of the series of commands is notified to the processor. An access control method in which a control circuit executes the processing. [Explanation of Symbols]

[0314] 100,200,600: Information Processing Device 1,6 :SP 10,60: SP Firmware 11: I2C Library 12: Control Program 13: Control Engine 101,611: Inspection Library 102,612: Log collection library 103,62: Common Hardware Control Execution Engine 104,631~634: Hardware control programs 105,64: I2C Block Access Library 106,65: I2C single-use access library 107,66: I2C Block Access Driver 108,67: I2C single access driver 111: Access mode determination unit 112: Range selection section 113: Data storage section 114: I2C Access Execution Unit 121: Access mode specification section 122: Library Call Section 123: Read data storage unit 124: Termination notification section 131: Program Call Section 132: Unprocessed command determination unit 133: Range reset instruction unit 134: Block Access Execution Unit 20: I2C control unit 21: Single-use access control unit 22: Block Access Control Unit 221: Command list buffer 222: Read data buffer 3: Control bus 31: CPU 32: Memory 33: PSU 34: Other control devices 7: Board 71: MBC 72: Buffer 73a~73e: Parts 80: Component Control Unit 81: Buffer 811: Command list buffer 812: Read data buffer 82: Buffer Control Unit 83: I2C control circuit 84: Read Modify Write Control Unit 85: Command format decoder 9: Board 93a~93c: Parts

Claims

1. In commands issued via a serial bus, the range of commands to be blocked according to a sequence of data write or data read operations is controlled. Access the controlled range of the blocking commands, If the sequence pattern includes only data reads, the range of the block command is not specified. An information processing device equipped with a processor.

2. The processor, when data writes are consecutive in the consecutive pattern, specifies the range of the consecutive data writes as the range of the blocking command. The information processing apparatus according to claim 1.

3. The processor, if a data read is included after a series of data writes in the sequence pattern, specifies the range from the sequence of data writes to the data read as the range of the blocking command. The information processing apparatus according to claim 1 or 2.

4. It issues several commands via the serial bus, including at least read-modify-write commands. Depending on the sequence pattern of the aforementioned commands, the range including the commands before and after the read-modify-write command is designated as the command range to be blocked. Access the specified range of the blocking command, An information processing device equipped with a processor.

5. The processor controls the range of the commands to be blocked in accordance with a sequence of combinations of data write, data read, and read-modify-write operations in the commands issued via the serial bus. The information processing apparatus according to claim 4.

6. The information processing apparatus according to claim 4 or 5, wherein the read-modify-write command includes at least a data field containing data and a mask field containing information indicating bits to write the data in the data field.

7. Control circuit and Multiple boards on which multiple components are mounted, Furthermore, The aforementioned control circuit is At least a block of commands including commands before and after the read-modify-write command is received from the processor via the serial bus and stored in a buffer. In response to execution instructions received from the processor via the serial bus, the system reads the series of commands one by one from the buffer, sequentially executes processing corresponding to the read commands on each of the multiple boards to control the multiple components, and notifies the processor of the execution results of the series of commands. The information processing apparatus according to any one of claims 4 to 6.

8. In commands issued via a serial bus, the sequence of data write or data read Control the range of commands to be blocked according to the subsequent pattern. Access the controlled range of the blocking commands, If the sequence pattern includes only data reads, the range of the block command is not specified. An access control program that allows a computer to execute a process.

9. It issues several commands via the serial bus, including at least read-modify-write commands. Depending on the sequence pattern of the aforementioned commands, the range including the commands before and after the read-modify-write command is designated as the command range to be blocked. Access the specified range of the blocking command, An access control program that allows a computer to execute a process.

10. In commands issued via a serial bus, the range of commands to be blocked according to a sequence of data write or data read operations is controlled. Access the controlled range of the blocking commands, If the sequence pattern includes only data reads, the range of the block command is not specified. A method of access control in which a computer performs a process.

11. It issues several commands via the serial bus, including at least read-modify-write commands. Depending on the sequence pattern of the aforementioned commands, the range including the commands before and after the read-modify-write command is designated as the command range to be blocked. Access the specified range of the blocking command, A method of access control in which a computer performs a process.

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