Silicon carbide semiconductor equipment

Abstract

To provide a SiC semiconductor device in which the deterioration in yield can be suppressed.SOLUTION: An element separation region In includes a deep layer 15 formed in a surface layer part of a first impurity region 13, a base layer 21 formed on the deep layer 15, and a separation structure 40 that electrically separates the base layer 21 existing on a main cell region Rm side and the base layer 21 existing on a sense cell region Rs side. In the deep layer 15 of the element separation region In, a part existing on the main cell region Rm side and a part existing on the sense cell region Rs side are disposed apart from each other by a predetermined distance B3. The predetermined distance B3 is wider than distances B1 and B2 of the deep layer 15 in the cell region. The JFET layer 14 is formed in a region of the cell region 1 that is different from the element separation region In.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide (hereinafter also referred to as SiC) semiconductor device having a trench gate structure in which a main cell region and a sense cell region are provided within the cell region. [Background technology]

[0002] Conventionally, SiC semiconductor devices have been proposed in which a cell region is provided with a main cell region and a sense cell region, and the current flowing in the main cell region is detected in the sense cell region (see, for example, Patent Document 1). Specifically, in this SiC semiconductor device, MOSFET elements with the same structure are formed in the main cell region and the sense cell region. In addition, in this SiC semiconductor device, an element isolation region is provided between the main cell region and the sense cell region.

[0003] The main cell region and sense cell region have a trench gate structure, and below the trench gate structure, p-type deep layers and n-type JFET layers are formed, extending in one direction as the longitudinal direction. The deep layers and JFET layers are arranged alternately along a direction intersecting the longitudinal direction, such that a JFET layer is placed between adjacent deep layers.

[0004] The device isolation region has deep layers and JFET layers similar to those in the main cell region. The deep layers in the device isolation region are spaced apart by a predetermined distance from the main cell region and the sense cell region. In this SiC semiconductor device, the voltage breakdown strength of the device isolation region is improved by making the spacing of the deep layers in the device isolation region narrower than that of the deep layers in the main cell region. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2021-93481 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] However, when the inventors conducted a detailed examination of the spacing of the deep layers in the device isolation region of the above-mentioned SiC semiconductor device, they confirmed the following: In other words, it was confirmed that it is preferable to have a spacing of 0.6 μm or less between the deep layers in the device isolation region of the above-mentioned SiC semiconductor device. In this case, if the deep layers are to be formed by ion implantation, the remaining width of the mask used during ion implantation must be set to 0.6 μm or less to match the spacing of the deep layers. For this reason, in the above-mentioned SiC semiconductor device, the mask processing may become unstable, potentially leading to a decrease in yield.

[0007] In view of the above points, the present invention aims to provide a SiC semiconductor device that can suppress deterioration of yield. [Means for solving the problem]

[0008] Claim 1, for achieving the above objective, is a SiC semiconductor device in which a semiconductor element having a trench gate structure is formed in a cell region (1) including a main cell region (Rm) and a sense cell region (Rs), and the main cell region and the sense cell region are electrically separated by an element isolation region (In), comprising a substrate (11) made of SiC of a first conductivity type or a second conductivity type, and a first impurity region (13) of the first conductivity type formed on the surface of the substrate and having a lower impurity concentration than the substrate, wherein the main cell region and the sense cell region are formed in the surface layer of the first impurity region. The JFET layer (14) is made of a first conductivity type SiC with a higher impurity concentration than the first impurity region, a deep layer (15) is made of a second conductivity type SiC formed on the surface of the first impurity region and alternately arranged with the JFET layer in the planar direction of the substrate, a base layer (21) is made of a second conductivity type SiC formed on the JFET layer and the deep layer, a gate insulating film (25) is formed on the inner wall surface of a trench (24) that is deeper than the base layer and has one direction as the longitudinal direction, and a gate electrode (26) is formed on the gate insulating film within the trench. The device has a trench gate structure, a second impurity region (22) formed in contact with the trench gate structure on the surface of the base layer and made of first conductivity type SiC with a higher impurity concentration than the first impurity region, a first electrode (28) provided separately in the main cell region and the sense cell region, electrically connected to the second impurity region and the base layer of the main cell region and electrically connected to the second impurity region and the base layer of the sense cell region, and a second electrode (31) arranged on the back side of the substrate and electrically connected to the substrate, and the device isolation region is The device has a deep layer formed on the surface of the first impurity region, a base layer formed on the deep layer, and an isolation structure (40, 41) that electrically separates the base layer located on the main cell region side from the base layer located on the sense cell region side. The deep layer in the device isolation region is arranged with a predetermined distance (B3) between the portion located on the main cell region side and the portion located on the sense cell region side, and this predetermined distance is wider than the distance (B1, B2) between the deep layers in the cell region. The JFET layer is formed in a region of the cell region that is different from the device isolation region.

[0009] According to this, a structure is adopted in which a JFET layer having a higher concentration than the first impurity region is not formed in the element isolation region. For this reason, it is easier to suppress the rise of equipotential lines due to the influence of voltage as compared with the case where a JFET layer is formed in the element isolation region. Therefore, the interval between deep layers in the element isolation region can be made greater than or equal to the interval between deep layers in the cell region. As a result, when forming the deep layers by ion implantation, a mask corresponding to the interval between deep layers in the element isolation region can be easily arranged, and a SiC semiconductor device can be obtained that suppresses deterioration of the yield.

[0010] The reference numerals with parentheses attached to each component etc. show an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of Drawings

[0011] [Figure 1] It is a plan view of the SiC semiconductor device in the first embodiment. [Figure 2] It is a cross-sectional view taken along line II-II in FIG. 1. [Figure 3] It is a perspective view of the cell region. [Figure 4] It is a cross-sectional view taken along line IV-IV in FIG. 1. [Figure 5] It is a diagram showing the relationship between the width of the element isolation region and the breakdown voltage between drain and source. [Figure 6] It is a cross-sectional view of the element isolation region in the second embodiment. [Figure 7] It is a cross-sectional view of the cell region and the outer peripheral region in the third embodiment. [Figure 8] It is a perspective view of the cell region and the outer peripheral region in the fourth embodiment. [Figure 9] It is a cross-sectional view of the element isolation region in the fourth embodiment [Figure 10] It is a cross-sectional view of the element isolation region in a modification of the fourth embodiment. [Figure 11]This is a cross-sectional view of the cell region and the peripheral region in another embodiment. [Modes for carrying out the invention]

[0012] The embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0013] (First Embodiment) The first embodiment will be described with reference to the drawings. As shown in Figure 1, the SiC semiconductor device of this embodiment has a configuration comprising a cell region 1 and an outer peripheral region 2 surrounding the cell region 1. The cell region 1 comprises a main cell region Rm equipped with a main cell, a sense cell region Rs equipped with a sense cell, and an element isolation region In positioned between the main cell region Rm and the sense cell region Rs to electrically isolate the main cell region Rm and the sense cell region Rs. In the SiC semiconductor device of this embodiment, the main current flowing through the main cell region Rm is detected by the sense current flowing through the sense cell region Rs and the area ratio.

[0014] In this embodiment, the main cell region Rm and the sense cell region Rs are arranged such that the sense cell region Rs is located within the main cell region Rm. The element isolation region In is arranged in a frame shape to surround the sense cell region Rs. In this embodiment, MOSFETs with a trench gate structure of the same type are formed in the main cell region Rm and the sense cell region Rs.

[0015] As shown in Figure 2, the outer peripheral region 2 has a configuration comprising a guard ring portion 2a and a connecting portion 2b positioned inside the guard ring portion 2a. In other words, the outer peripheral region 2 has a configuration comprising a guard ring portion 2a and a connecting portion 2b positioned between the cell region 1 and the guard ring portion 2a.

[0016] The following description of a SiC semiconductor device equipped with an n-channel MOSFET in cell region 1 will be explained with reference to Figures 2 and 3. As described above, MOSFETs of the same structure are formed in the main cell region Rm and the sense cell region Rs. In the following description, one direction in the plane direction of the substrate 11, which will be described later, will be referred to as the X-axis direction, the direction intersecting one direction in the plane direction of the substrate will be referred to as the Y-axis direction, and the direction intersecting the X-axis direction and the Y-axis direction will be referred to as the Z-axis direction. In this embodiment, the X-axis direction and the Y-axis direction are orthogonal. In this embodiment, the Z-axis direction corresponds to the thickness direction of the semiconductor substrate 10, which will be described later, and also corresponds to the stacking direction of the substrate 11 and the low-density layer 13, which will be described later. The Y-axis direction is, for example, the <11-20> direction.

[0017] The SiC semiconductor device is constructed using a semiconductor substrate 10. Specifically, the SiC semiconductor device is made of n made of SiC. + The substrate 11 is of a specific type. In this embodiment, the substrate 11 has, for example, an off-angle of 0 to 8° with respect to the (0001)Si plane, and the concentration of n-type impurities such as nitrogen and phosphorus is 1.0 × 10⁻⁶. 19 / cm 3 It is said that a substrate with a thickness of approximately 300 μm is used. In this embodiment, the substrate 11 constitutes the drain region.

[0018] An n-type buffer layer 12 made of SiC is formed on the surface of the substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The n-type impurity concentration of the buffer layer 12 is set to be between the impurity concentration of the substrate 11 and the low-concentration layer 13 described later, and the thickness is approximately 1 μm.

[0019] On the surface of buffer layer 12, for example, the n-type impurity concentration is 5.0 to 20.0 × 10 15 / cm 3 It is said that the n is made of SiC with a thickness of about 7 to 15 μm. -A low-concentration layer 13 of a type is formed. The impurity concentration of this low-concentration layer 13 may be constant in the Z-axis direction, but it is preferably inclined in the concentration distribution so that the side of the low-concentration layer 13 closer to the substrate 11 has a higher concentration than the side farther from the substrate 11. For example, in the low-concentration layer 13, the impurity concentration in the portion about 3 to 5 μm from the surface of the substrate 11 is preferably made higher than other portions by about 2.0×10 15 / cm 3 This can reduce the internal resistance of the low-concentration layer 13 and reduce the on-resistance. In this embodiment, the low-concentration layer 13 corresponds to the first impurity region.

[0020] In the surface layer portion of the low-concentration layer 13, at the connecting portion 2b of the cell region 1 and the outer peripheral region 2, a JFET layer 14 and a first deep layer 15 are formed. In this embodiment, the JFET layer 14 and the first deep layer 15 each extend along the X-axis direction and have linear portions alternately arranged in the Y-axis direction. That is, the JFET layer 14 and the first deep layer 15 are each in a stripe shape extending along the X-axis direction in the normal direction to the surface of the substrate 11 (hereinafter also simply referred to as the normal direction), and they are configured in a layout where they are alternately arranged along the Y-axis direction. Note that the normal direction to the surface of the substrate 11 can also be said to be when viewed from the normal direction to the surface of the substrate 11. Also, the normal direction to the surface of the substrate 11 is also the direction along the stacking direction of the drift layer 19 and the base layer 21 described later, and is the direction along the Z-axis direction.

[0021] The JFET layer 14 is of an n-type with an impurity concentration higher than that of the low-concentration layer 13, and its thickness is 0.3 to 1.5 μm. In this embodiment, the JFET layer 14 has an n-type impurity concentration of 5.0×10 16 ~1.0×10 17 / cm 3 The first deep layer 15 has a p-type impurity concentration of 2.0×10 17 ~2.0×10 18 / cm 3This is considered to be the extent of the configuration. Specifically, as will be described later, in this embodiment, the JFET layer 14 is not formed in the element isolation region In of the cell region 1. In other words, the JFET layer 14 is formed only in the main cell region Rm and the sense cell region Rs within the cell region 1. In this embodiment, the region of the cell region 1 where the JFET layer 14 is not formed is defined as the element isolation region In.

[0022] Furthermore, the first deep layer 15 in this embodiment is formed to be shallower than the JFET layer 14. In other words, the first deep layer 15 is formed so that its bottom is located within the JFET layer 14. To put it another way, the first deep layer 15 is formed so that the JFET layer 14 is located between it and the low-concentration layer 13. The JFET layer 14 and the first deep layer 15 are formed by appropriately ion-implanting impurities into the surface layer of the low-concentration layer 13.

[0023] Here, as described above, the main cell region Rm and the sense cell region Rs have similar configurations, and their perspective views are both shown in Figure 3. However, in this embodiment, the spacing B2 between adjacent first deep layers 15 in the sense cell region Rs is narrower than the spacing B1 between adjacent first deep layers 15 in the main cell region Rm. Therefore, the diagrams corresponding to Figure 2 for the main cell region Rm and the sense cell region Rs actually show that the spacing B2 between adjacent first deep layers 15 in the sense cell region Rs is narrower than the spacing B1 between adjacent first deep layers 15 in the main cell region Rm. The spacing between adjacent first deep layers 15 can also be said to be the spacing between first deep layers 15 arranged along the Y-axis. Furthermore, below, the spacing B1 between adjacent first deep layers 15 in the main cell region Rm will also be simply referred to as spacing B1, and the spacing B2 between adjacent first deep layers 15 in the sense cell region Rs will also be simply referred to as spacing B2.

[0024] Furthermore, the surface portion of the low-concentration layer 13 is provided with multiple p-shaped guard rings 16 in the guard ring portion 2a of the outer peripheral region 2, so as to surround the cell region 1. In this embodiment, the upper surface layout of the guard rings 16 is such that the four corners are rounded, or the shape is a square or a circle in the normal direction.

[0025] On the JFET layer 14 and the first deep layer 15 in cell region 1, a current dispersion layer 17, a second deep layer 18, a base layer 21, a source region 22, a contact region 23, etc., are formed.

[0026] The current dispersion layer 17 is made of n-type impurities with a higher impurity concentration than the low-concentration layer 13 and is formed to connect with the JFET layer 14. Therefore, in this embodiment, the low-concentration layer 13, the JFET layer 14, and the current dispersion layer 17 are connected, and these together constitute the drift layer 19. The current dispersion layer 17 has a thickness of 0.5 to 2.0 μm and an n-type impurity concentration of 1.0 × 10⁻¹⁶ 17 ~3.0×10 17 cm 3 It is considered to be of a certain degree.

[0027] The second deep layer 18 is p-type and its thickness is equal to that of the current dispersion layer 17. Furthermore, the second deep layer 18 is formed to be connected to the first deep layer 15. In this embodiment, the second deep layer 18 has a p-type impurity concentration of 2.0 × 10⁻⁶. 17 ~2.0×10 18 / cm 3 It is considered to be of a certain degree.

[0028] The current distribution layer 17 and the second deep layer 18 extend in a direction intersecting the striped portion of the JFET layer 14 and the longitudinal direction of the first deep layer 15. In this embodiment, the current distribution layer 17 and the second deep layer 18 extend in the longitudinal direction along the Y-axis, and are arranged in a layout in which multiple layers are alternately arranged along the X-axis. The formation pitch of the current distribution layer 17 and the second deep layer 18 is matched to the formation pitch of the trench gate structure described later, and the second deep layer 18 is formed so as to sandwich the trench 24 described later.

[0029] The base layer 21 is p-type and is formed on the current dispersion layer 17 and the second deep layer 18. Therefore, the first deep layer 15 is connected to the base layer 21 via the second deep layer 18. The base layer 21 has, for example, a p-type impurity concentration of 5.0 × 10⁻⁶. 16 ~2.0×10 19 / cm 3 It is said to have a thickness of approximately 2.0 μm.

[0030] Source region 22 is n + It is a type and is formed on the surface of the base layer 21. The contact area 23 is p + It is a type and is formed on the surface of the base layer 21. Specifically, the source region 22 is formed to be in contact with the side surface of the trench 24, which will be described later, and the contact region 23 is formed on the opposite side of the trench 24, which will be described later, with the source region 22 in between. In this embodiment, the source region 22 has an n-type impurity concentration (i.e., surface concentration) in the surface layer, for example, 1.0 × 10⁻⁶ 18 The density is given as / cm3 and the thickness is given as approximately 0.3 μm. The contact region 23 has a p-type impurity concentration (i.e., surface concentration) in the surface layer, for example, 1.0 × 10 21 / cm 3 It is said that the thickness is approximately 0.3 μm. In this embodiment, the source region 22 corresponds to the second impurity region.

[0031] On the low-concentration layer 13, JFET layer 14, first deep layer 15, and guard ring 16 in the outer peripheral region 2, a current dispersion layer 17, a second deep layer 18, a base layer 21, and a contact region 23 are formed. The second deep layer 18 is formed in the connecting portion 2b of the outer peripheral region 2 and is formed to connect with the first deep layer 15 which extends from the cell region 1 to the outer peripheral region 2.

[0032] The base layer 21 is formed on the second deep layer 18 and extends from the cell region 1. The contact region 23 is formed on the surface of the base layer 21 and has the same configuration as the contact region 23 formed in the cell region 1. In this embodiment, the entire surface of the connecting portion 2b in the outer peripheral region 2 is the contact region 23.

[0033] In this embodiment, the semiconductor substrate 10 is composed of the substrate 11, buffer layer 12, low-concentration layer 13, JFET layer 14, first deep layer 15, current-dispersing layer 17, second deep layer 18, base layer 21, source region 22, contact region 23, etc., as described above. Since the semiconductor substrate 10 is composed as described above, it can be said that the semiconductor substrate 10 is composed of SiC. In addition, in this embodiment, one side 10a of the semiconductor substrate 10 is composed of the source region 22 and contact region 23, and the other side 10b of the semiconductor substrate 10 is composed of the substrate 11.

[0034] In this embodiment, the current dispersion layer 17, the second deep layer 18, the base layer 21, the source region 22, and the contact region 23 are constructed by ion implantation. Therefore, it can also be said that the current dispersion layer 17, the second deep layer 18, the base layer 21, the source region 22, and the contact region 23 are composed of ion implantation layers.

[0035] Furthermore, in the semiconductor substrate 10, a trench 24 is formed in the cell region 1, for example, with a width of 0.4 to 0.8 μm, that penetrates the source region 22 and the base layer 21, etc., and reaches the current dispersion layer 17 from one side 10a, with its bottom surface located within the current dispersion layer 17. The trench 24 is formed so as not to reach the JFET layer 14 and the first deep layer 15. In other words, the trench 24 is formed so that the JFET layer 14 and the first deep layer 15 are located below the bottom surface of the trench 24, at a distance from the trench 24.

[0036] Furthermore, multiple trenches 24 are provided extending along the Y-axis direction, and are arranged at equal intervals along the X-axis direction to form a striped pattern. In other words, in this embodiment, the trenches 24 are formed so that their longitudinal direction is perpendicular to the longitudinal direction of the first deep layer 15. The trenches 24 are also formed so as to be sandwiched between the second deep layer 18 in the Z-axis direction.

[0037] A gate insulating film 25 is formed on the inner wall surface of the trench 24, and a gate electrode 26 made of doped poly-Si or the like is formed on the gate insulating film 25. This constitutes a trench gate structure. The gate insulating film 25 is formed by thermal oxidation of the inner wall surface of the trench 24 or by CVD (chemical vapor deposition). The thickness of the gate insulating film 25 is approximately 100 nm on both the side and bottom surfaces of the trench 24.

[0038] Furthermore, the gate insulating film 25 is also formed on surfaces other than the inner wall surface of the trench 24. Specifically, the gate insulating film 25 is formed to cover a portion of one surface 10a of the semiconductor substrate 10. More specifically, in the cell region 1, the gate insulating film 25 is formed to cover a portion of the surface of the source region 22. In other words, in the cell region 1, the gate insulating film 25 has contact holes 25a that expose the source region 22 and the contact region 23 in a portion different from the portion where the gate electrode 26 is located.

[0039] The gate insulating film 25 is also formed on the surface of the contact region 23 in the connecting portion 2b. Furthermore, the gate insulating film 25 has a contact hole 25c formed in the connecting portion 2b of the outer peripheral region 2 that exposes the contact region 23. The gate electrode 26 extends onto the surface of the gate insulating film 25 in the connecting portion 2b. In this embodiment, the contact hole 25c is formed on the side of the guard ring portion 2a that the gate electrode 26 extends onto the gate insulating film 25 in the connecting portion 2b. The trench gate structure of this embodiment is configured as described above.

[0040] Furthermore, in the semiconductor substrate 10, a recess 10c is formed in the guard ring portion 2a of the outer peripheral region 2, penetrating the base layer 21 and reaching the second deep layer 18 and the current dispersion layer 17. The SiC semiconductor device of this embodiment is a mesa structure type in which the recess 10c is formed in the outer peripheral region 2 in this manner.

[0041] An interlayer insulating film 27 is formed on one surface 10a of the semiconductor substrate 10, covering the gate electrode 26, gate insulating film 25, etc. The interlayer insulating film 27 is made of BPSG (abbreviation for Borophosphosilicate Glass) or the like.

[0042] The interlayer insulating film 27 has a contact hole 27a in the cell region 1 that communicates with the contact hole 25a and exposes the source region 22 and the contact region 23. The interlayer insulating film 27 also has a contact hole 27b that exposes the portion of the gate electrode 26 that extends to the connecting portion 2b. Furthermore, the interlayer insulating film 27 has a contact hole 27c in the connecting portion 2b of the outer peripheral region 2 that communicates with the contact hole 25c and exposes the contact region 23. In other words, the interlayer insulating film 27 has a contact hole 27a in the cell region 1, and contact holes 27b and 27c in the outer peripheral region 2.

[0043] The contact hole 27a formed in the interlayer insulating film 27 of cell region 1 is formed to communicate with the contact hole 25a formed in the gate insulating film 25, and functions together with the contact hole 25a as a single contact hole. For this reason, in the following, contact holes 25a and 27a will be collectively referred to as contact hole 25b. Similarly, the contact hole 27c formed in the interlayer insulating film 27 of the connecting portion 2b is formed to communicate with the contact hole 25c formed in the gate insulating film 25, and functions together with the contact hole 25c as a single contact hole. For this reason, in the following, contact holes 25c and 27c will be collectively referred to as the connecting portion contact hole 25d. The patterns of the contact holes 25b and the connecting portion contact holes 25d are arbitrary and include, for example, a pattern of multiple squares arranged in a row, a pattern of rectangular lines arranged in a row, or a pattern of line-shaped elements arranged in a row. In this embodiment, the contact hole 25b and the connecting contact hole 25d are in the shape of a line along the longitudinal direction of the trench 24.

[0044] An upper electrode 28 is formed on the interlayer insulating film 27, which is electrically connected to the source region 22 and the contact region 23 through a contact hole 25b. In this embodiment, the upper electrode 28 is also connected to the contact region 23 formed on the base layer 21 of the outer peripheral region 2 through a connecting contact hole 25d. Furthermore, the upper electrode 28 is provided separately for the main cell region Rm and the sense cell region Rs in the cell region 1. Each upper electrode 28 is capable of independently making an electrical connection to the outside. In this embodiment, the upper electrode 28 corresponds to the first electrode. In addition, a gate wiring 29 is formed on the interlayer insulating film 27, which is electrically connected to the gate electrode 26 through a contact hole 27b.

[0045] The upper electrode 28 of this embodiment is composed of multiple metals, such as Ni / Al. The portion of the multiple metals that contacts the n-type SiC (i.e., the source region 22) is composed of a metal capable of ohmic contact with the n-type SiC. Furthermore, at least the portion of the multiple metals that contacts the p-type SiC (i.e., the contact region 23) is composed of a metal capable of ohmic contact with the p-type SiC. The gate wiring 29 may have the same configuration as the upper electrode 28, or it may be composed of Al-Si or the like.

[0046] Furthermore, a protective film 30 made of polyimide or the like is formed to cover the connecting portion 2b and the guard ring portion 2a. In this embodiment, the protective film 30 is formed from the outer peripheral region 2 to the outer edge of the cell region 1 in order to suppress the occurrence of creepage discharge between the upper electrode 28 and the lower electrode 31, which will be described later. Specifically, in the cell region 1, the protective film 30 is formed to cover the portion of the upper electrode 28 on the outer peripheral region 2 side while exposing the portion of the upper electrode 28 on the inner edge side.

[0047] A lower electrode 31 is formed on the other side 10b of the semiconductor substrate 10, which is electrically connected to the substrate 11. In this embodiment, the lower electrode 31 corresponds to the second electrode.

[0048] In the SiC semiconductor device of this embodiment, a trench gate structure MOSFET, which is an inverted type of n-channel MOSFET, is formed in the main cell region Rm and the sense cell region Rs. Next, the configuration of the element isolation region In will be described.

[0049] The element isolation region In is formed so as to surround the sense cell region Rs as described above, and is located between the main cell region Rm and the sense cell region Rs. Furthermore, as shown in Figure 4, the element isolation region In has a configuration similar to cell region 1, including a substrate 11, a buffer layer 12, and a low-concentration layer 13.

[0050] In the surface layer of the low-concentration layer 13, only the first deep layer 15 is formed, and the JFET layer 14 is not formed. In this embodiment, the region between the main cell region Rm and the sense cell region Rs where the JFET layer 14 is not formed is defined as the device isolation region In. In other words, the JFET layer 14 is formed in a region different from the device isolation region In.

[0051] Furthermore, the first deep layer 15 is arranged with a gap B3 between the main cell region Rm side and the sense cell region Rs side. However, the gap B3 of the first deep layer 15 in the element isolation region In (hereinafter also simply referred to as gap B3) is set to be greater than or equal to the gaps B1 and B2 in the main cell region Rm and sense cell region Rs. In this embodiment, for example, the gap B1 is set to 0.9 μm and the gap B3 is set to 1.0 to 1.4 μm.

[0052] On the first deep layer 15, a current distribution layer 17, a second deep layer 18, a base layer 21, and a contact region 23 are formed. The second deep layer 18 has a main cell region Rm side portion and a sense cell region Rs side portion separated by a distance B4. However, the distance B4 of the second deep layer 18 is wider than the distance B3 of the first deep layer 15. The current distribution layer 17 is positioned between the second deep layer 18.

[0053] The base layer 21 is placed on the second deep layer 18, and the contact region 23 is formed on the surface of the base layer 21. The impurity concentrations of each component in the element isolation region In are the same as those in the cell region 1.

[0054] Furthermore, in the element isolation region In, isolation trenches 40 are formed as isolation structures so as to reach the current dispersion layer 17 and the second deep layer 18. This electrically isolates the base layer 21 and contact region 23 on the main cell region Rm side from the base layer 21 and contact region 23 on the sense cell region Rs side. In this embodiment, the isolation trenches 40 have the same depth as the trenches 24 and are formed simultaneously when the trenches 24 are formed.

[0055] In this embodiment, the width Ind of the element isolation region In is set to 7.0 μm or more, as will be described later. The width Ind of the element isolation region In is the length of the portion located between the main cell region Rm and the sense cell region Rs. Also, the width 40a of the isolation trench 40 is set to 7.4 μm or more, as will be described later.

[0056] The above describes the configuration of the SiC semiconductor device in this embodiment. In this embodiment, n - type, n type, n + The type corresponds to the first conductivity type, p type, p + The type corresponds to the second conductivity type. Next, the operation of the above SiC semiconductor device will be explained.

[0057] First, in the SiC semiconductor device described above, in the off state before a gate voltage is applied to the gate electrode 26, no inversion layer is formed in the base layer 21. Therefore, even if a positive voltage, for example 1600V, is applied to the lower electrode 31, electrons do not flow from the source region 22 into the base layer 21, and no current flows between the upper electrode 28 and the lower electrode 31.

[0058] Furthermore, before a gate voltage is applied to the gate electrode 26, an electric field is present between the drain and gate, which can cause electric field concentration at the bottom of the gate insulating film 25. However, in the SiC semiconductor device described above, the first deep layer 15 and the JFET layer 14 are located deeper than the trench 24. Therefore, the depletion layer formed between the first deep layer 15 and the JFET layer 14 suppresses the rise of equipotential lines due to the influence of the drain voltage, making it difficult for high electric fields to penetrate the gate insulating film 25. Consequently, in this embodiment, the destruction of the gate insulating film 25 can be suppressed.

[0059] When a predetermined gate voltage, for example 20V, is applied to the gate electrode 26, a channel is formed on the surface of the base layer 21 that is in contact with the trench 24. As a result, electrons injected from the upper electrode 28 flow from the source region 22 through the channel formed in the base layer 21 to the current dispersion layer 17. The electrons that flow through the current dispersion layer 17 then pass through the JFET layer 14 to the low-concentration layer 13, and then pass through the substrate 11, which acts as the drain layer, to the lower electrode 31. This causes a current to flow between the upper electrode 28 and the lower electrode 31, turning on the SiC semiconductor device. In this embodiment, since the electrons that pass through the channel pass through the current dispersion layer 17, the JFET layer 14, and the low-concentration layer 13 to the substrate 11, it can be said that a drift layer 19 having the current dispersion layer 17, the JFET layer 14, and the low-concentration layer 13 is configured.

[0060] Furthermore, in this embodiment, the element isolation region In does not include a JFET layer 14 which has a higher concentration than the low-concentration layer 13. Therefore, the rise of equipotential lines due to the influence of drain voltage is further suppressed. Accordingly, in this embodiment, as described above, the spacing B3 can be made larger than or equal to the spacings B1 and B2. As a result, when forming the first deep layer 15 by ion implantation, a mask corresponding to the spacing B3 can be easily placed, resulting in a SiC semiconductor device that suppresses deterioration of yield.

[0061] The inventors investigated the drain-source breakdown voltage and obtained the results shown in Figure 5. Specifically, as shown in Figure 5, it was confirmed that the drain-source breakdown voltage gradually increased until the width Ind of the element isolation region In reached 7.0 μm, and then remained almost unchanged above 7.0 μm. For this reason, it is preferable that the width Ind of the element isolation region In be 7.0 μm or greater.

[0062] In this case, with the SiC semiconductor device configured as described above, the breakdown voltage of cell region 1 will be approximately 1500V. Therefore, by making the width of the element isolation region In 7.0 μm or more, the breakdown voltage of the element isolation region In can be made higher than that of cell region 1. This suppresses the breakdown of the element isolation region In, which tends to have a small area, before it can break down. However, the element isolation region In is an inactive region where current does not easily flow. Therefore, it is preferable to make the width Ind of the element isolation region In as narrow as possible within the range of 7.0 μm or more.

[0063] Furthermore, according to the inventors' studies, considering the processing accuracy of the mask when forming the first deep layer 15, it was confirmed that the width 40a of the separation trench 40 is preferably derived by the following formula. Specifically, according to the inventors' studies, when a SiC semiconductor device is constructed with the above-mentioned impurity concentration, it was confirmed that the maximum spacing B3 is preferably 1.4 μm. Also, considering the alignment misalignment, it was confirmed that the difference between spacing B3 and spacing B4 is preferably at least 2.0 μm. Furthermore, considering the alignment misalignment between spacing B2 and the separation trench 40, it was confirmed that it is preferable to have a margin of at least 1.0 μm. Therefore, the minimum value of the width 40a of the separation trench 40 is shown by the following formula 1.

[0064] (Equation 1) (1.4 + 2 × 2.0) + 2 × 1.0 = 7.4 (μm) ... (Equation 1) Based on the above, in this embodiment, the width 40a of the separation trench 40 is set to 7.4 μm or more.

[0065] According to the embodiment described above, a JFET layer 14 with a higher concentration than the low-concentration layer 13 is not formed in the element isolation region In. Therefore, compared to the case where a JFET layer 14 is formed in the element isolation region In, it is easier to suppress the rise of equipotential lines due to the influence of the drain voltage. Accordingly, in the SiC semiconductor device of this embodiment, the spacing B3 can be made larger than or equal to the spacing B1 and B2. As a result, when forming the first deep layer 15 by ion implantation, a mask corresponding to the spacing B3 can be easily placed, resulting in a SiC semiconductor device that suppresses deterioration of yield.

[0066] (1) In this embodiment, the spacing B2 of the sense cell region Rs is narrower than the spacing B1 of the main cell region Rm. Therefore, the normalized on-resistance during operation of the sense cell region Rs can be made equivalent, and the linearity between the current value of the main cell region Rm and the current value of the sense cell region Rs can be easily improved.

[0067] (2) In this embodiment, the separation structure is formed by a separation trench 40. Therefore, the process of forming the trench 24 and the process of forming the separation trench 40 can be made common, thereby simplifying the manufacturing process. Furthermore, in the element separation region In, the separation trench 40 is formed so as to penetrate the base layer 21 and contact region 23 on the main cell region Rm side and the base layer 21 and contact region 23 on the sense cell region Rs side, so it is not necessary to pattern the base layer 21 and contact region 23 in detail. Therefore, in this respect as well, the manufacturing process can be simplified.

[0068] (3) In this embodiment, the width 40a of the separation trench 40 is set to 7.4 μm or more. Therefore, alignment deviations can be adequately accommodated, and deterioration of yield can be suppressed.

[0069] (4) In this embodiment, the width of the element isolation region In is set to 7.0 μm or more. Therefore, the drain-source breakdown voltage in the element isolation region In can be made sufficiently high.

[0070] (Second Embodiment) A second embodiment will now be described. This embodiment is a modification of the separation structure compared to the first embodiment. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.

[0071] In the SiC semiconductor device of this embodiment, as shown in Figure 6, an n-type isolation layer 41 is formed in the element isolation region In between the base layer 21 and contact region 23 of the main cell region Rm and the base layer 21 and contact region 23 of the sense cell region Rs. The base layer 21 and contact region 23 of the main cell region Rm and the base layer 21 and contact region 23 of the sense cell region Rs are electrically isolated by the isolation layer 41.

[0072] According to the embodiment described above, a JFET layer 14 with a higher concentration than the low-concentration layer 13 is not formed in the element isolation region In. Therefore, the same effects as in the first embodiment can be obtained.

[0073] (1) In this embodiment, the base layer 21 and contact region 23 of the main cell region Rm are electrically separated from the base layer 21 and contact region 23 of the sense cell region Rs by the separation layer 41. Therefore, compared to the case in which the separation structure is composed of a separation trench 40, surface irregularities are less likely to occur, improving the reliability of the SiC semiconductor device and enabling the miniaturization of the SiC semiconductor device.

[0074] (Third embodiment) A third embodiment will now be described. This embodiment is a modification of the configuration of the outer peripheral region 2 compared to the first embodiment. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.

[0075] In the SiC semiconductor device of this embodiment, as shown in Figure 7, at the connecting portion 2b of the outer peripheral region 2, on the opposite side from the cell region 1, n +A source region 22 of the type is formed. In other words, the outer peripheral region 2 is configured to have parts arranged in the order of contact region 23 and source region 22 from the cell region 1 side. In other words, the surface layer of the connecting portion 2b of the outer peripheral region 2 is not formed by the contact region 23 alone.

[0076] Furthermore, the source region 22 formed in the connecting portion 2b is formed such that the upper electrode 28 formed in the connecting portion 2b is connected to at least the contact region 23, in order to maintain the pressure resistance of the guard ring portion 2a. In other words, the connecting portion contact hole 25d formed in the connecting portion 2b is formed to expose at least the contact region 23 formed in the connecting portion 2b. In this embodiment, the connecting portion contact hole 25d is formed to expose only the contact region 23 formed in the connecting portion 2b.

[0077] In the SiC semiconductor device of the first embodiment described above, the source region 22 and the contact region 23 are formed by ion implantation layers, and the impurity concentration in the contact region 23 is higher than that in the source region 22.

[0078] When manufacturing such a SiC semiconductor device, the source region 22 and contact region 23 are formed by ion implanting n-type impurities from one side 10a of the semiconductor substrate 10, followed by ion implantation of p-type impurities. In other words, the contact region 23 is formed by creating a region with a high impurity concentration in the source region 22, which has a low impurity concentration. In this case, the inventors' studies have shown that if the contact region 23 is to be formed over the entire surface of the connecting portion 2b, the warping of the semiconductor substrate 10 becomes significant. Therefore, in this embodiment, the source region 22 is formed in the connecting portion 2b of the outer peripheral region 2. In other words, a source region 22 that is not impregnated into the contact region 23 remains in the connecting portion 2b of the outer peripheral region 2.

[0079] According to the embodiment described above, a JFET layer 14 with a higher concentration than the low-concentration layer 13 is not formed in the element isolation region In. Therefore, the same effects as in the first embodiment can be obtained.

[0080] (1) In this embodiment, at the connecting portion 2b of the outer peripheral region 2, a contact region 23 is formed on the cell region 1 side, and a source region 22 is formed on the opposite side from the cell region 1 side. Therefore, warping of the SiC semiconductor device (i.e., semiconductor substrate 10) can be suppressed.

[0081] (Fourth Embodiment) A fourth embodiment will now be described. This embodiment is a modification of the configuration of cell region 1 compared to the first embodiment. Other aspects are the same as in the first embodiment, so their explanation will be omitted here.

[0082] In the SiC semiconductor device of this embodiment, as shown in Figure 8, in the cell region 1, a base layer 21 is formed on the JFET layer 14 and the first deep layer 15, and the current dispersion layer 17 and the second deep layer 18 are not formed. Therefore, the drift layer 19 is composed of a low-concentration layer 13 and the JFET layer 14. The trench 24 is formed so that its bottom surface reaches the JFET layer 14 and the first deep layer 15. Note that in Figure 8, the interlayer insulating film 27 and upper electrode 28 located on one side 10a of the semiconductor substrate 10 are omitted.

[0083] Furthermore, a p-shaped third deep layer 50 is formed below each trench 24 so as to be in contact with the bottom surface of the trench 24. Specifically, the third deep layer 50 is formed along the longitudinal direction of the trench 24. In other words, the third deep layer 50 extends along the Y-axis direction that intersects with the first deep layer 15. The third deep layer 50 may be formed by dividing it into multiple sections along the Y-axis direction. However, the third deep layer 50 is formed to be electrically connected to the base layer 21 via the first deep layer 15.

[0084] Furthermore, the third deep layer 50 in this embodiment is formed so that it penetrates the JFET layer 14 and the first deep layer 15, and its bottom surface reaches the low-concentration layer 13.

[0085] This third deep layer 50 is formed by ion implantation after the trench 24 has been formed. In this embodiment, the third deep layer 50 has a lower impurity concentration than the first deep layer 15.

[0086] In the outer peripheral region 2, a base layer 21 is formed on the JFET layer 14 and the first deep layer 15 at the connecting portion 2b, and a contact region 23 is formed on the surface of the base layer 21. The base layer 21 and the contact region 23 are formed by extending from the cell region 1.

[0087] Furthermore, in this embodiment, the recess 10c is not formed in the guard ring portion 2a of the outer peripheral region 2. In the guard ring portion 2a of the outer peripheral region 2, one surface 10a of the semiconductor substrate 10 is composed of a low-density layer 13.

[0088] Similarly, in the element isolation region In, as shown in Figure 9, a base layer 21 is formed on the first deep layer 15, and a contact region 23 is formed on the surface of the base layer 21. As with the first embodiment, the spacing B3 is greater than or equal to the spacing B1 and B2. Also, as with the first embodiment, the JFET layer 14 is not formed in the element isolation region In.

[0089] Furthermore, the separation structure of this embodiment is composed of a separation layer 41, similar to the second embodiment described above. Alternatively, the separation structure may be composed of a separation trench 40, similar to the first embodiment described above.

[0090] In such a SiC semiconductor device, when the device is in the off state, the third deep layer 50 is formed along the bottom surface of the trench 24, which makes it easier for the area around the bottom surface of the trench 24 to be effectively depleted. This further reduces electric field concentration near the bottom surface of the trench 24.

[0091] Furthermore, in this embodiment, the third deep layer 50 is formed to be in contact with the bottom surface of the trench 24. That is, it is formed to be in contact with the gate insulating film 25 located on the bottom surface of the trench 24. Therefore, when the device is off, the third deep layer 50 is preferentially depleted, so that the gate insulating film 25 located at the bottom of the trench 24 is not penetrated by an electric field, and oxide film breakdown is suppressed. In addition, the capacitance (i.e., feedback capacitance) between the gate electrode 26 and the lower electrode 31 can be reduced, and the switching speed can be improved.

[0092] Furthermore, in this embodiment, the third deep layer 50 is formed to penetrate the JFET layer 14 and the first deep layer 15, with its bottom surface reaching the low-concentration layer 13. This suppresses the creeping of the electric field to the JFET layer 14 positioned between the third deep layers 50, thereby improving the breakdown voltage. Moreover, the formation of such a third deep layer 50 makes it easier for breakdown to occur in the third deep layer 50 that protrudes downward when an overvoltage is applied. Therefore, breakdown is more likely to occur in the cell region 1, thereby improving the avalanche withstand capability.

[0093] As described above, even with a configuration that does not include the current dispersion layer 17 and the second deep layer 18, the same effects as in the first embodiment can be obtained because the JFET layer 14, which has a higher concentration than the low-concentration layer 13, is not formed in the element isolation region In.

[0094] (1) In this embodiment, since the third deep layer 50 is formed along the bottom surface of the trench 24, there is no penetration of an electric field into the gate insulating film 25 located at the bottom of the trench 24, and oxide film breakdown is suppressed.

[0095] (2) In this embodiment, since the third deep layer 50 is formed to be in contact with the bottom surface of the trench 24, the capacitance (i.e., feedback capacitance) between the gate electrode 26 and the lower electrode 31 can be reduced, and the switching speed can be improved.

[0096] (3) In this embodiment, the third deep layer 50 is formed to penetrate the JFET layer 14 and the first deep layer 15, with its bottom surface reaching the low-concentration layer 13. This suppresses the creeping of the electric field to the JFET layer 14, which is positioned between the third deep layers 50, thereby improving the breakdown voltage. Furthermore, the formation of such a third deep layer 50 makes it easier for breakdown to occur in the third deep layer 50 that protrudes downward when an overvoltage is applied. Therefore, it becomes easier for breakdown to occur in the cell region 1, thereby improving the avalanche withstand capability.

[0097] (Modified version of the fourth embodiment) A modified version of the fourth embodiment described above will now be explained. In the fourth embodiment, as shown in Figure 10, a source region 22 may be formed on the surface of the base layer 21 in the element isolation region In. Although not specifically shown, in the first to third embodiments as well, a source region 22 may be formed on the surface of the base layer 21 in the element isolation region In.

[0098] Furthermore, in the fourth embodiment described above, the third deep layer 50 may be formed such that its bottom surface is located within the JFET layer 14 and the first deep layer 15. In other words, the third deep layer 50 may be formed so as not to reach the low-concentration layer 13. This makes it difficult for the depletion layer to extend from the third deep layer 50, thereby reducing the on-resistance.

[0099] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of ​​this disclosure.

[0100] For example, in each of the above embodiments, a MOSFET with an n-channel trench gate structure, where the first conductivity type is n-type and the second conductivity type is p-type, was described as an example. However, the SiC semiconductor device may be configured such that, for example, a MOSFET with a p-channel trench gate structure is formed in the cell region 1, where the conductivity types of each component are reversed compared to the n-channel type. Furthermore, the semiconductor device may be configured such that, in addition to the MOSFET, an IGBT with a similar structure is formed. In the case of an IGBT, the n in each of the above embodiments + The substrate 11 of type p + Aside from changing the collector layer type, it is the same as the vertical MOSFET described in each of the embodiments above.

[0101] Furthermore, in each of the above embodiments, the source region 22 may be configured by sequentially arranging multiple regions from the substrate 11 side, including a low-concentration source region and a high-concentration source region which has a higher concentration than the low-concentration source region. In such a configuration, the high-concentration source region corresponds to the high-concentration layer, and the low-concentration source region corresponds to the low-concentration layer.

[0102] Furthermore, in each of the above embodiments, the source region 22 may be composed of an epitaxial layer instead of an ion implantation layer. When the source region 22 is composed of an epitaxial layer, strain stress associated with ion implantation is not generated, and therefore, leakage current between the drain and source due to strain stress can be suppressed. In addition, when the source region 22 is composed of multiple regions, if the source region 22 is composed of an ion implantation layer, the multiple-stage concentration control required when it is composed of an epitaxial layer can be eliminated.

[0103] Furthermore, in the first and third embodiments described above, the depth of the isolation trench 40 may differ from that of the trench 24. Also, the isolation trench 40 may be formed in a process separate from the process of forming the trench 24. Furthermore, the width 40a of the isolation trench 40 may be less than 7.4 μm. Similarly, the width Ind of the element isolation region In may be less than 7.0 μm.

[0104] Furthermore, in the first to third embodiments described above, the recess 10c may not be formed in the outer peripheral region 2, and in the fourth embodiment described above, the recess 10c may be formed in the outer peripheral region 2.

[0105] Furthermore, in the third embodiment described above, an example was described in which the contact hole 25d for the connecting portion of the connecting portion 2b is formed to expose only the contact region 23. However, the contact hole 25d for the connecting portion only needs to be formed to expose at least the contact region 23, and may be formed to expose both the contact region 23 and the source region 22, as shown in Figure 11.

[0106] Furthermore, the above embodiments can be combined. For example, the second embodiment may be combined with the third embodiment so that the separation structure is composed of a separation layer 41. The third embodiment may be combined with the fourth embodiment so that the source region 22 remains in the connecting portion 2b. Moreover, combinations of the above embodiments can be combined even further.

[0107] In addition, when indicating the orientation of a crystal, a bar (-) should ideally be placed above the desired number. However, due to the limitations on expression imposed by electronic filing, a bar is placed before the desired number in this specification. [Explanation of Symbols]

[0108] 1 cell area 11 circuit boards 13 Low concentration layer (first impurity region) 14 JFET layer 15 Deep Layer 21 Base Layer 24 Trench 25 Gate insulating film 26 gate 28 Upper electrode (1st electrode) 31 Lower electrode (second electrode)

Claims

1. A silicon carbide semiconductor device having a trench gate structure is formed in a cell region (1) including a main cell region (Rm) and a sense cell region (Rs), and the main cell region and the sense cell region are electrically separated by an element isolation region (In), A substrate (11) made of silicon carbide of the first or second conductivity type, It has a first impurity region (13) of a first conductivity type formed on the surface of the substrate and having a lower impurity concentration than the substrate, The main cell region and the sense cell region are, A JFET layer (14) is formed on the surface of the first impurity region and consists of a first conductivity type silicon carbide with a higher impurity concentration than the first impurity region, A deep layer (15) made of second-conductivity silicon carbide is formed on the surface of the first impurity region and is arranged alternately with the JFET layer in the planar direction of the substrate, A base layer (21) made of second-conductivity silicon carbide formed on the JFET layer and the deep layer, A trench gate structure having a gate insulating film (25) formed on the inner wall surface of a trench (24) formed deeper than the base layer with one direction as the longitudinal direction, and a gate electrode (26) formed on the gate insulating film within the trench, A second impurity region (22) is formed in contact with the trench gate structure in the surface portion of the base layer and consists of a first conductivity type silicon carbide with a higher impurity concentration than the first impurity region, A first electrode (28) is provided separately in the main cell region and the sense cell region, and is electrically connected to the second impurity region and the base layer of the main cell region, and is also electrically connected to the second impurity region and the base layer of the sense cell region, The substrate has a second electrode (31) which is positioned on the back side of the substrate and electrically connected to the substrate, The aforementioned element isolation region is, The deep layer formed on the surface of the first impurity region, The base layer formed on the deep layer, It has an isolation structure (40, 41) that electrically separates the base layer located on the main cell region side from the base layer located on the sense cell region side, In the element isolation region, the deep layer is arranged such that the portion located on the main cell region side and the portion located on the sense cell region side are separated by a predetermined distance (B3). The predetermined interval is wider than the interval (B1, B2) of the deep layer in the cell region. The JFET layer is formed in a region of the cell region that is different from the element isolation region, in a silicon carbide semiconductor device.

2. The silicon carbide semiconductor device according to claim 1, wherein the spacing of the deep layers (B2) in the sense cell region is narrower than the spacing of the deep layers (B1) in the main cell region.

3. The silicon carbide semiconductor device according to claim 1, wherein the separation structure is a separation trench (40) formed between the base layer located on the main cell region side and the base layer located on the sense cell region side.

4. The silicon carbide semiconductor device according to claim 3, wherein the separation trench has a width (40a) of 7.4 μm or more.

5. The silicon carbide semiconductor device according to claim 1, wherein the separation structure is a first conductivity type separation layer (41) disposed between the base layer located on the main cell region side and the base layer located on the sense cell region side.

6. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the element isolation region has a width (Ind) of 7.0 μm or more.

7. It has an outer peripheral region (2) surrounding the aforementioned cell region, The outer peripheral region has a portion in which a second conductivity type contact region (23) having a higher impurity concentration than the second impurity region and the second impurity region are arranged sequentially from the cell region side, and insulating films (25, 27) are arranged on the surface. The silicon carbide semiconductor device according to claim 1, wherein the insulating film has contact holes (25d) that expose the contact region in at least the outer peripheral region.

8. The silicon carbide semiconductor device according to claim 1, wherein the second impurity region is configured by stacking multiple layers, including a low-concentration layer and a high-concentration layer having a higher impurity concentration than the low-concentration layer, from the substrate side.

9. The silicon carbide semiconductor device according to claim 1, wherein the second impurity region is composed of an ion implantation layer.

10. The silicon carbide semiconductor device according to claim 1, wherein the second impurity region is composed of an epitaxial layer.

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