Manufacturing method of switching elements

Abstract

To suppress variation of a thickness of an electric field relaxation region.SOLUTION: A manufacturing method of a switching element, includes: a step of preparing a semiconductor substrate having an n-type first semiconductor layer; a first implantation step of implanting a p-type impurity to one part of a front surface of the first semiconductor layer to form a first p-type region into the first semiconductor layer; a step of performing an epitaxial growth of an n-type second semiconductor layer onto the first semiconductor layer; a second implantation step of implanting the p-type impurity to one part of the front surface of the second semiconductor layer to form a second p-type region connected to the first p-type region into the second semiconductor layer; a step of performing the epitaxial growth of a third semiconductor layer onto the second semiconductor layer; and a step of forming a trench so that a bottom surface of the trench is positioned into the second p-type region to the front surface of the third semiconductor layer. An electric field relaxation region is formed by the first p-type region and the second p-type region.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing a switching element.

[0002] Patent Document 1 discloses a switching element having a trench-type gate electrode. This switching element has a p-type electric field relaxation region that contacts the bottom surface of the trench. The electric field relaxation region can suppress the electric field concentration around the bottom surface of the trench.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, an electric field relaxation region is formed by implanting p-type impurities into an n-type semiconductor layer. However, it is difficult to accurately control the implantation distance of the p-type impurities, and variations occur in the thickness of the electric field relaxation region during mass production of the switching element. As a result, variations occur in the breakdown voltage of the switching element. In this specification, a technology for suppressing variations in the thickness of the electric field relaxation region is proposed.

Means for Solving the Problems

[0005] A switching element manufactured by the manufacturing method disclosed herein comprises a gate electrode disposed in a trench, an n-type source region in contact with the side surface of the trench, a p-type body region below the source region in contact with the side surface of the trench, an n-type drift region below the body region in contact with the side surface of the trench and extending below the bottom surface of the trench, and a p-type electric field relaxation region in contact with the bottom surface of the trench and the drift region. The manufacturing method comprises the steps of: preparing a semiconductor substrate having an n-type first semiconductor layer; a first injection step of forming a first p-type region within the first semiconductor layer by injecting p-type impurities into a part of the surface of the first semiconductor layer; epitaxially growing an n-type second semiconductor layer on the first semiconductor layer; a second injection step of forming a second p-type region connected to the first p-type region within the second semiconductor layer by injecting p-type impurities into a part of the surface of the second semiconductor layer, wherein the field relaxation region is formed by the first p-type region and the second p-type region; epitaxially growing a third semiconductor layer on the second semiconductor layer; and forming a trench on the surface of the third semiconductor layer such that the bottom surface of the trench is located within the second p-type region.

[0006] In the manufacturing method disclosed herein, an electric field relaxation region is formed by implanting p-type impurities in two stages. Specifically, a first p-type region is formed in a first semiconductor layer by a first implantation step, a second semiconductor layer is formed on the first semiconductor layer on which the first p-type region is formed, and then a second p-type region is formed in the second semiconductor layer by a second implantation step. The formed first p-type region and second p-type region connect to each other to form an electric field relaxation region. Since the thickness of the first p-type region and the second p-type region is thinner than the thickness of the electric field relaxation region, the first p-type region and the second p-type region can be formed with relatively low implantation energy. That is, in the first and second implantation steps, the first p-type region and the second p-type region can be formed with low implantation energy. When the implantation energy of the p-type impurities is low, variations in the implantation depth of the p-type impurities are less likely to occur. Therefore, in the first and second implantation steps, variations in the thickness of the first p-type region and the second p-type region can be suppressed. Therefore, this manufacturing method can suppress variations in the thickness of the electric field relaxation region. [Brief explanation of the drawing]

[0007] [Figure 1] A perspective view including a cross-section of the switching element. [Figure 2] A perspective view of a switching element with the source electrode omitted. [Figure 3] A flowchart showing the manufacturing method of Example 1. [Figure 4] Diagram illustrating the manufacturing method of Example 1. [Figure 5] Diagram illustrating the manufacturing method of Example 1. [Figure 6] Diagram illustrating the manufacturing method of Example 1. [Figure 7] Diagram illustrating the manufacturing method of Example 1. [Figure 8] Diagram illustrating the manufacturing method of Example 1. [Figure 9] Diagram illustrating the manufacturing method of Example 1. [Figure 10] Diagram illustrating the manufacturing method of Example 1. [Figure 11] Diagram illustrating the manufacturing method of Example 1. [Figure 12]Explanatory drawing of the manufacturing method of Example 1. [Figure 13] Graph showing the p-type impurity concentration distribution within the electric field relaxation region formed by the manufacturing method of Example 1. [Figure 14] Graph showing the p-type impurity concentration distribution within the electric field relaxation region formed by the manufacturing method of the comparative example. [Figure 15] Graph showing the p-type impurity concentration distribution within the electric field relaxation region formed by the manufacturing method of the modified example. [Figure 16] Explanatory drawing of the manufacturing method of Example 2. [Figure 17] Explanatory drawing of the manufacturing method of Example 2. [Figure 18] Explanatory drawing of the manufacturing method of Example 2. [Figure 19] Explanatory drawing of the manufacturing method of Example 2.

Embodiments for Carrying Out the Invention

[0008] In an example of the manufacturing method disclosed in this specification, the implantation energy of the p-type impurity in the first implantation step may be lower than the implantation energy of the p-type impurity in the second implantation step.

[0009] According to this configuration, variations in the thickness of the electric field relaxation region can be more effectively suppressed.

[0010] In an example of the manufacturing method disclosed in this specification, the lower end of the implantation range of the p-type impurity in the first implantation step may be located below the lower end of the implantation range of the p-type impurity in the second implantation step.

[0011] According to this configuration, variations in the thickness of the electric field relaxation region can be more effectively suppressed.

[0012] In a configuration disclosed in this specification, the switching element may further have a p-type deep region that protrudes downward from the body region and extends below the lower end of the electric field relaxation region. The manufacturing method may include a third implantation step of forming a third p-type region in the first semiconductor layer by implanting p-type impurities into a part of the surface of the first semiconductor layer, a fourth implantation step of forming a fourth p-type region connected to the third p-type region in the second semiconductor layer by implanting p-type impurities into a part of the surface of the second semiconductor layer, the fourth implantation step in which the deep region is formed by the third p-type region and the fourth p-type region. It may further have.

[0013] According to this configuration, variations in the thickness of the deep region can be suppressed.

Example

[0014] 1 and 2 show a switching element 10 manufactured by the manufacturing method of Example 1. The switching element 10 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductors such as Si or GaN. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, a direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as the y direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z direction. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends linearly in the y direction on the upper surface 12a. Each trench 14 is arranged at intervals in the x direction on the upper surface 12a. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is arranged in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by a gate insulating film 16. An interlayer insulating film 20 is arranged in each trench 14. Each interlayer insulating film 20 covers the upper surface of the gate electrode 18.

[0015] As shown in Figure 1, a source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers the upper surface of the interlayer insulating film 20 and the upper surface 12a of the semiconductor substrate 12. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. A drain electrode 24 is provided on the lower part of the semiconductor substrate 12. The drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.

[0016] As shown in Figures 1 and 2, the semiconductor substrate 12 has multiple source regions 40, multiple contact regions 41, a body region 42, a drift region 44, a buffer region 45, a drain region 46, multiple electric field relaxation regions 48, and multiple deep regions 49.

[0017] The source region 40 is an n-type region having a high n-type impurity concentration. The contact region 41 is a p-type region having a high p-type impurity concentration. The source region 40 and the contact region 41 are located within a semiconductor layer (hereinafter referred to as the inter-trench semiconductor layer) situated between two trenches 14. Within each inter-trench semiconductor layer, the source region 40 and the contact region 41 are alternately arranged along the y-direction. The source region 40 and the contact region 41 are in contact with the source electrode 22. Each source region 40 is in contact with the gate insulating film 16 on the sides of the trenches 14 provided on both sides of the inter-trench semiconductor layer. Each contact region 41 is in contact with the gate insulating film 16 on the sides of the trenches 14 provided on both sides of the inter-trench semiconductor layer.

[0018] The body region 42 is a p-type region having a lower p-type impurity concentration than the contact region 41. The body region 42 is located within the inter-trench semiconductor layer. The body region 42 is located below the source region 40 and the contact region 41. The body region 42 is in contact with the source region 40 and the contact region 41 from below. The body region 42 is in contact with the gate insulating film 16 below the source region 40. That is, the body region 42 is in contact with the gate insulating film 16 on the sides of the trenches 14 provided on both sides of the inter-trench semiconductor layer.

[0019] The drift region 44 is an n-type region having a lower n-type impurity concentration than the source region 40. The drift region 44 is distributed across the lower part of multiple inter-trench semiconductor layers. The upper end of the drift region 44 extends into each inter-trench semiconductor layer. Within each inter-trench semiconductor layer, the drift region 44 is in contact with the body region 42 from below. The drift region 44 is in contact with the gate insulating film 16 on the lower side of the body region 42. That is, the drift region 44 is in contact with the gate insulating film 16 on the sides of the trenches 14 provided on both sides of each inter-trench semiconductor layer.

[0020] The buffer region 45 is an n-type region having a higher n-type impurity concentration than the drift region 44. The buffer region 45 is in contact with the drift region 44 from below.

[0021] The drain region 46 is an n-type region having a higher n-type impurity concentration than the buffer region 45. The drain region 46 is in contact with the buffer region 45 from below. The drain region 46 is in contact with the drain electrode 24 on the lower surface 12b of the semiconductor substrate 12.

[0022] Each field relaxation region 48 is a p-type region having a lower p-type impurity concentration than the contact region 41. Each field relaxation region 48 is located at the bottom of the corresponding trench 14. Each field relaxation region 48 is in contact with the gate insulating film 16 at the bottom surface of the corresponding trench 14. Each field relaxation region 48 extends linearly in the y-direction along the bottom surface of the corresponding trench 14. Drift regions 44 are distributed in the gaps between each field relaxation region 48 and in the region below each field relaxation region 48. Drift regions 44 are in contact with the sides and bottom surface of each field relaxation region 48.

[0023] Each deep region 49 is a p-type region having a lower p-type impurity concentration than the field relaxation region 48. Each deep region 49 is located below the body region 42. Each deep region 49 has a shape that is longer in the z direction than in the y direction, and its upper end is connected to the body region 42. That is, each deep region 49 has a convex shape that protrudes downward from the body region 42. Each deep region 49 extends from the body region 42 to below the lower end of each field relaxation region 48. Each deep region 49 extends linearly in the x direction and intersects with the trench 14 and the field relaxation region 48. Each deep region 49 is spaced apart in the y direction. Drift regions 44 are distributed in the spaces between each deep region 49 and in the region below each deep region 49. Drift regions 44 are in contact with the sides and bottom of each deep region 49. Each deep region 49 is connected to the field relaxation region 48 at the intersection with the field relaxation region 48. Therefore, each electric field relaxation region 48 is connected to the body region 42 via the deep region 49.

[0024] Next, the operation of the switching element 10 will be described. The switching element 10 is a so-called MOSFET (metal-oxide-semiconductor field effect transistor). Under normal circumstances, a higher potential is applied to the drain electrode 24 than to the source electrode 22. When a potential higher than the gate threshold is applied to the gate electrode 18, a channel is formed in the vicinity of the gate insulating film 16 within the body region 42, and the source region 40 and the drift region 44 are connected by this channel. As a result, the switching element 10 turns on, and current flows from the drain electrode 24 to the source electrode 22.

[0025] When the potential of the gate electrode 18 is lowered to a potential lower than the gate threshold, the switching element 10 turns off and the current stops. When the switching element 10 turns off, a depletion layer extends from the body region 42, the deep region 49, and the electric field relaxation region 48 to the drift region 44, and almost the entire drift region 44 is depleted. The electric field relaxation region 48 suppresses electric field concentration at the lower end of the trench 14. In addition, the depletion layer extending from the deep region 49 efficiently depletes the drift region 44. This enables the switching element 10 to withstand high voltage.

[0026] The thickness of the electric field relaxation region 48 (i.e., the dimension in the z-direction) and the thickness of the deep region 49 (i.e., the dimension in the z-direction) greatly affect the breakdown voltage of the switching element 10. If the thickness of the electric field relaxation region 48 and the deep region 49 varies, the breakdown voltage of the switching element 10 will vary greatly. For example, if the lower end of the electric field relaxation region 48 protrudes below the lower end of the deep region 49 due to variations in thickness, electric field concentration is more likely to occur at the lower end of the electric field relaxation region 48, and the breakdown voltage of the switching element 10 will decrease significantly. The following describes a method for manufacturing the switching element 10 that can suppress variations in the thickness of the electric field relaxation region 48 and the deep region 49.

[0027] Figure 3 shows the manufacturing method of Example 1. In this manufacturing method, in step S2, the semiconductor substrate shown in Figure 4 is prepared. The semiconductor substrate shown in Figure 4 is the semiconductor substrate 12 before processing, and has a drain region 46, a buffer region 45, and a first semiconductor layer 44a. The first semiconductor layer 44a is located on the buffer region 45. The first semiconductor layer 44a is an n-type layer having a lower n-type impurity concentration than the buffer region 45. The first semiconductor layer 44a is exposed on the upper surface of the semiconductor substrate. In step S2, the semiconductor substrate shown in Figure 4 may be manufactured or purchased.

[0028] Next, in step S4, as shown in Figure 5, a plurality of p-type regions 48a are formed within the first semiconductor layer 44a. More specifically, first, a mask 50 having an opening is formed on the upper surface of the first semiconductor layer 44a. Next, p-type impurities are injected into a portion of the surface of the first semiconductor layer 44a through the mask 50. This forms a plurality of p-type regions 48a within the first semiconductor layer 44a. Here, a plurality of p-type regions 48a are formed at positions exposed on the upper surface of the first semiconductor layer 44a, spaced apart in the x-direction. Each p-type region 48a extends linearly in the y-direction. After the formation of the p-type regions 48a, the mask 50 is removed.

[0029] Next, in step S6, as shown in Figure 6, a plurality of p-type regions 49a are formed within the first semiconductor layer 44a. More specifically, first, a mask 52 having an opening is formed on the upper surface of the first semiconductor layer 44a. Next, p-type impurities are injected into a portion of the surface of the first semiconductor layer 44a through the mask 52. This forms a plurality of p-type regions 49a within the first semiconductor layer 44a. Here, a plurality of p-type regions 49a are formed at intervals in the y-direction at positions exposed on the upper surface of the first semiconductor layer 44a. Each p-type region 49a extends linearly in the x-direction. Therefore, each p-type region 49a intersects with a p-type region 48a. In step S6, p-type impurities are injected with a higher energy than in step S4. Therefore, the p-type regions 49a are formed to a deeper position than the p-type regions 48a. For this reason, the p-type regions 49a are thicker than the p-type regions 48a. After the formation of the p-type regions 49a, the mask 52 is removed.

[0030] Next, in step S8, as shown in Figure 7, a second semiconductor layer 44b is epitaxially grown on the first semiconductor layer 44a. The second semiconductor layer 44b is an n-type layer having approximately the same n-type impurity concentration as the first semiconductor layer 44a. The thickness of the second semiconductor layer 44b is greater than the thickness of the p-type region 48a.

[0031] Next, in step S10, as shown in Figure 8, a plurality of p-type regions 48b are formed within the second semiconductor layer 44b. More specifically, first, a mask 54 having an opening is formed on the upper surface of the second semiconductor layer 44b. Next, p-type impurities are injected into a portion of the surface of the second semiconductor layer 44b through the mask 54. This forms a plurality of p-type regions 48b within the second semiconductor layer 44b. Here, a plurality of p-type regions 48b are formed at positions exposed on the upper surface of the second semiconductor layer 44b, spaced apart in the x-direction. Each p-type region 48b extends linearly in the y-direction. In step S10, the acceleration voltage is set higher than in step S4, thereby injecting p-type impurities with a higher injection energy than in step S4. This forms a p-type region 48b that extends from the upper surface to the lower surface of the second semiconductor layer 44b. Therefore, the thickness of the p-type region 48b is greater than the thickness of the p-type region 48a. Here, the p-type region 48b is formed above the p-type region 48a. Therefore, the lower end of the p-type region 48b connects to the upper end of the p-type region 48a. The connected p-type regions 48a and 48b form the electric field relaxation region 48. After the formation of the p-type region 48b, the mask 54 is removed.

[0032] Next, in step S12, as shown in Figure 9, a plurality of p-type regions 49b are formed within the second semiconductor layer 44b. More specifically, first, a mask 56 having an opening is formed on the upper surface of the second semiconductor layer 44b. Next, p-type impurities are injected into a portion of the surface of the second semiconductor layer 44b through the mask 56. This forms a plurality of p-type regions 49b within the second semiconductor layer 44b. Here, a plurality of p-type regions 49b are formed at intervals in the y-direction at positions exposed on the upper surface of the second semiconductor layer 44b. Each p-type region 49b extends linearly in the x-direction. Therefore, each p-type region 49b intersects with a p-type region 48b. Here, a p-type region 49b is formed above a p-type region 49a. Therefore, the lower end of the p-type region 49b connects to the upper end of the p-type region 49a. The connected p-type regions 49a and 49b form a deep region 49. After the formation of the p-type regions 49b, the mask 56 is removed.

[0033] The n-type region remaining in the first semiconductor layer 44a and the second semiconductor layer 44b after the formation of the electric field relaxation region 48 and the deep region 49 is the drift region 44.

[0034] Next, in step S14, as shown in Figure 10, an n-type third semiconductor layer 60 is epitaxially grown on the second semiconductor layer 44b.

[0035] Next, in step S16, as shown in Figure 11, a source region 40 and a body region 42 are formed within the third semiconductor layer 60 by ion implantation. Also in step S16, a contact region 41 (see Figures 1 and 2) is formed within the third semiconductor layer 60.

[0036] Next, in step S18, as shown in Figure 12, a plurality of trenches 14 are formed by selectively etching the surface of the third semiconductor layer 60. Here, a trench 14 is formed above each electric field relaxation region 48, extending along the electric field relaxation region 48 (i.e., along the y-direction). Furthermore, the trenches 14 are formed such that their bottom surfaces are located within the p-type region 48b.

[0037] Next, in step S20, a gate insulating film 16, a gate electrode 18, and an interlayer insulating film 20 are formed in the trench 14. Furthermore, a source electrode 22 is formed on the upper surface of the semiconductor substrate 12, and a drain electrode 24 is formed on the lower surface of the semiconductor substrate 12. Through these steps, the switching element 10 shown in Figures 1 and 2 is completed.

[0038] Figure 13 shows the p-type impurity concentration distribution in the depth direction (i.e., z direction) within the electric field relaxation region 48 of the switching element 10 manufactured by the manufacturing method of Example 1. Figure 14 shows the p-type impurity concentration in the depth direction within the electric field relaxation region 48 of the comparative example. Figure 14 shows the case where an electric field relaxation region 48 of the same thickness as in Figure 13 is formed with a single ion implantation using high implantation energy. The implantation distances Da, Db, and Dc in Figures 13 and 14 represent the distance from the surface of the semiconductor layer to the depth of the p-type impurity concentration peak during ion implantation.

[0039] As shown in Figure 14, when the implantation energy is high, the implantation distance Dc is long. Also, since the ion-implanted p-type impurities are dispersed around the target depth, the p-type impurities are distributed in a normal distribution. When the implantation energy is high, the impurities tend to disperse easily. For this reason, in Figure 14, the tails of the normal distribution are wide.

[0040] As shown in Figures 13 and 14, the implantation distance Db for the p-type region 48b (i.e., the implantation distance in step S10) is shorter than the implantation distance Dc. Therefore, the concentration distribution of p-type impurities implanted in step S10 has a narrower tail and a narrower distribution range than the p-type impurity concentration distribution in Figure 14. Also, as mentioned above, ion implantation for the p-type region 48a in step S4 is performed with a lower implantation energy than ion implantation for the p-type region 48b in step S10. Therefore, as shown in Figure 13, the implantation distance Da for the p-type region 48a is shorter than the implantation distance Db for the p-type region 48b. For this reason, the concentration distribution of p-type impurities implanted in step S4 has a narrower tail and a narrower distribution range than the concentration distribution of p-type impurities implanted in step S10. As is clear from Figures 13 and 14, the manufacturing method of Example 1 makes it possible to obtain a p-type impurity concentration distribution with a narrow tail at the lower end of the electric field relaxation region 48.

[0041] When forming a p-type impurity concentration distribution with a broad tail, as shown in Figure 14, by ion implantation, it is difficult to control the distribution range of p-type impurities, and variations in the thickness of the electric field relaxation region 48 are likely to occur. In contrast, in the manufacturing method of Example 1, as shown in Figure 13, a p-type impurity concentration distribution with a narrow tail at the lower end of the electric field relaxation region 48 can be obtained. Therefore, the distribution range of p-type impurities at the lower end of the electric field relaxation region 48 can be accurately controlled, and variations in the thickness of the electric field relaxation region 48 can be suppressed. Consequently, according to the manufacturing method of Example 1, variations in characteristics such as breakdown voltage can be suppressed in the mass-produced switching element 10.

[0042] Furthermore, in the manufacturing method of Example 1, ion implantation into the p-type region 48b above the p-type region 48a is performed with a higher implantation energy than that used for ion implantation into the p-type region 48a. Therefore, the portion of the electric field relaxation region 48 other than the lower end can be formed in a single ion implantation. As a result, the electric field relaxation region 48 can be efficiently formed while suppressing variations in the thickness of the electric field relaxation region 48.

[0043] Furthermore, in the manufacturing method of Example 1, the deep region 49 is formed in the same manner as the electric field relaxation region 48 by performing a first ion implantation (i.e., step S6), epitaxial growth (i.e., step S8), and a second ion implantation (i.e., step S12). Therefore, variations in the thickness of the deep region 49 can be suppressed. As a result, variations in the breakdown voltage of the switching element 10 can be suppressed more effectively.

[0044] In Example 1, as shown in Figure 13, the lower end position Pa of the implantation range for the p-type region 48a (i.e., the position where the concentration of p-type impurities implanted in step S4 reaches the detection limit) is located below the lower end position Pb of the implantation range for the p-type region 48b (i.e., the position where the concentration of p-type impurities implanted in step S10 reaches the detection limit). In this case, since ion implantation for the p-type region 48b does not affect the thickness of the field relaxation region 48, variations in the thickness of the field relaxation region 48 can be suppressed more effectively. However, in other embodiments, as shown in Figure 15, the lower end position Pb of the implantation range for the p-type region 48b may be located below the lower end position Pa of the implantation range for the p-type region 48a. Even in the case of Figure 15, variations in the thickness of the field relaxation region 48 can be suppressed compared to the comparative example shown in Figure 14. [Examples]

[0045] Next, the manufacturing method of Example 2 will be described. In Example 2, the description of the deep region 49 will be omitted. In the manufacturing method of Example 2, processing is carried out in the same manner as in the manufacturing method of Example 1 until the state shown in Figure 5 is reached. Next, as shown in Figure 16, an n-type semiconductor layer 44b-1 is epitaxially grown on the first semiconductor layer 44a. The thickness of the semiconductor layer 44b-1 is thinner than the second semiconductor layer 44b of Example 1 (see Figure 7). Next, as shown in Figure 17, a plurality of p-type regions 48b-1 are formed within the semiconductor layer 44b-1 by ion implantation. Each p-type region 48b-1 is formed to connect with the p-type region 48a below it. Next, as shown in Figure 18, an n-type semiconductor layer 44b-2 is epitaxially grown on the semiconductor layer 44b-1. The thickness of the semiconductor layer 44b-2 is approximately equal to the thickness of the semiconductor layer 44b-1. Next, as shown in Figure 19, multiple p-type regions 48b-2 are formed within the semiconductor layer 44b-2 by ion implantation. Each p-type region 48b-2 is formed to connect with the p-type region 48b-1 below it. The p-type regions 48a, 48b-1, and 48b-2 form the electric field relaxation region 48. Subsequently, the trench 14, gate insulating film 16, gate electrode 18, interlayer insulating film 20, source electrode 22, and drain electrode 24 are formed in the same manner as in Example 1. This completes the switching element 10.

[0046] As in Example 2, the field relaxation region 48 may be formed by repeatedly performing epitaxial growth of the n layer and ion implantation of p-type impurities after forming the p-type region 48a that constitutes the lower end of the field relaxation region 48. The manufacturing method in Example 2 can also suppress variations in the thickness of the field relaxation region 48.

[0047] In the above-described embodiment, the deep region 49 was formed by forming the p-type region 49a, the second semiconductor layer 44b, and the p-type region 49b. However, the deep region 49 may be formed by other methods. For example, the deep region 49 may be formed by a single ion implantation. Also, in the above-described embodiment, the deep region 49 intersected the electric field relaxation region 48. However, the deep region 49 may extend parallel to the electric field relaxation region 48. Furthermore, in a switching element that does not have a deep region, the electric field relaxation region may be formed by the technology disclosed herein.

[0048] p-type region 48a is an example of a first p-type region. p-type region 48b is an example of a second p-type region. p-type region 49a is an example of a third p-type region. p-type region 49a is an example of a fourth p-type region.

[0049] The components of the technology disclosed herein are listed below. (Composition 1) A method for manufacturing a switching element, The aforementioned switching button, A gate electrode located inside the trench, An n-type source region in contact with the side surface of the trench, A p-shaped body region is located below the source region and is in contact with the side surface of the trench, An n-shaped drift region is in contact with the side surface of the trench at the lower side of the body region and extends below the bottom surface of the trench, A p-type electric field relaxation region that is in contact with the bottom surface of the trench and in contact with the drift region, It has, The aforementioned manufacturing method A step of preparing a semiconductor substrate having an n-type first semiconductor layer, A first injection step in which a first p-type region is formed within the first semiconductor layer by injecting a p-type impurity into a part of the surface of the first semiconductor layer, A step of epitaxially growing an n-type second semiconductor layer on the first semiconductor layer, A second injection step, comprising injecting p-type impurities into a portion of the surface of the second semiconductor layer to form a second p-type region connected to the first p-type region within the second semiconductor layer, wherein the first p-type region and the second p-type region form the electric field relaxation region, A step of epitaxially growing a third semiconductor layer on the second semiconductor layer, A step of forming the trench on the surface of the third semiconductor layer such that the bottom surface of the trench is located within the second p-type region, A manufacturing method having (Configuration 2) The manufacturing method according to configuration 1, wherein the injection energy of the p-type impurity in the first injection step is lower than the injection energy of the p-type impurity in the second injection step. (Composition 3) The manufacturing method according to configuration 1 or 2, wherein the lower end of the injection range for p-type impurities in the first injection step is located below the lower end of the injection range for p-type impurities in the second injection step. (Composition 4) The aforementioned switching button, It further has a p-shaped deep region that protrudes downward from the body region and extends below the lower end of the electric field relaxation region, The aforementioned manufacturing method A third implantation step involves implanting a p-type impurity into a portion of the surface of the first semiconductor layer to form a third p-type region within the first semiconductor layer, A fourth injection step, wherein a fourth p-type region connected to the third p-type region is formed within the second semiconductor layer by injecting a p-type impurity into a part of the surface of the second semiconductor layer, the fourth injection step wherein the deep region is formed by the third p-type region and the fourth p-type region. It further possesses, A manufacturing method described in any of configurations 1 to 3.

[0050] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0051] 14: Trench, 44: Drift region, 44a: First semiconductor layer, 44b: Second semiconductor layer, 48: Field relaxation region, 49: Deep region

Claims

1. A method for manufacturing a switching element, The aforementioned switching button, A gate electrode located inside the trench, An n-type source region in contact with the side surface of the trench, A p-shaped body region is located below the source region and is in contact with the side surface of the trench, An n-shaped drift region is in contact with the side surface of the trench at the lower side of the body region and extends below the bottom surface of the trench, A p-type electric field relaxation region that is in contact with the bottom surface of the trench and in contact with the drift region, It has, The aforementioned manufacturing method A step of preparing a semiconductor substrate having an n-type first semiconductor layer, A first injection step is to form a first p-type region within the first semiconductor layer by injecting a p-type impurity into a part of the surface of the first semiconductor layer, A step of epitaxially growing an n-type second semiconductor layer on the first semiconductor layer, A second injection step, comprising injecting p-type impurities into a portion of the surface of the second semiconductor layer to form a second p-type region connected to the first p-type region within the second semiconductor layer, wherein the first p-type region and the second p-type region form the electric field relaxation region, A step of epitaxially growing a third semiconductor layer on the second semiconductor layer, A step of forming the trench on the surface of the third semiconductor layer such that the bottom surface of the trench is located within the second p-type region, A manufacturing method having

2. The manufacturing method according to claim 1, wherein the injection energy of the p-type impurity in the first injection step is lower than the injection energy of the p-type impurity in the second injection step.

3. The manufacturing method according to claim 1 or 2, wherein the lower end of the injection range for p-type impurities in the first injection step is located below the lower end of the injection range for p-type impurities in the second injection step.

4. The aforementioned switching button, It further has a p-shaped deep region that protrudes downward from the body region and extends below the lower end of the electric field relaxation region, The aforementioned manufacturing method A third implantation step in which a third p-type region is formed within the first semiconductor layer by implanting a p-type impurity into a part of the surface of the first semiconductor layer, A fourth injection step in which a fourth p-type region connected to the third p-type region is formed within the second semiconductor layer by injecting a p-type impurity into a part of the surface of the second semiconductor layer, wherein the deep region is formed by the third p-type region and the fourth p-type region. It further possesses, The manufacturing method according to claim 1 or 2.

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