Closed-loopline synchronization for optical modulation

Abstract

A system for transmitting signals over a serial link includes a plurality of lanes for coupling data onto a transmission medium, a skew detector configured to detect skew between two of the plurality of lanes, and a variable delay circuit controlled by the skew detector and configured to delay the start of a clock signal to one of the plurality of lanes.

Description

Technical Field

[0001]

[0003] Embodiments of the present invention relate to the field of optical communication. More particularly, embodiments of the present invention relate to systems and methods for closed-loop lane synchronization for optical modulation.

Background Art

[0002] [Related Applications]

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 023,182, entitled "Closed Loop Lane Synchronization for Optical Modulation," filed May 11, 2020 by Doppalapudi and Iroaga, which is hereby incorporated by reference in its entirety. This application is a continuation-in-part of U.S. Patent Application No. 16 / 818,832, entitled "Optical Modulation Skew Adjustment Systems and Methods," filed Mar. 13, 2020 by Doppalapudi and Echere (Attorney Docket No. MACM-0020-03P01US), which is a continuation-in-part of co-pending U.S. Patent Application No. 16 / 143,493, entitled "Error Detection and Compensation for a Multiplexing Transmitter," filed Sep. 27, 2018, and International Application No. PCT / US19 / 51839, entitled "Error Detection and Compensation for a Multiplexing Transmitter," filed Sep. 19, 2019, all of which are hereby incorporated by reference in their entirety.

[0003]

[0002] This application relates to U.S. Patent No. 8,766,681 and U.S. Patent No. 10,313,099, both of which are hereby incorporated by reference in their entirety.

[0004] [Background Art]

[0004] A typical communication link may include a PAM-4 (Pulse Amplitude Modulation using four levels) or QAM (Quaternary Amplitude Modulation) transmitter and receiver, along with an optical transmitter and / or optical receiver. It should be understood that QAM is applicable to other wireless communications, such as RF (Radio Frequency) communications. The optical transmitter often drives an MZI (Mach-Zehnder interferometer) optical modulator.

[0005]

[0005] It is advantageous to use multiple "lanes" of the driver / modulation component. Multi-lane coherent transceivers are typically used to increase the amount of data that can be transmitted. For example, a 4-lane synchronous transceiver can output four times the data of a transceiver with only a single output.

[0006]

[0006] During operation, the multi-lane coherent transceiver can receive low-speed digital input signals from a digital signal processing (DSP) device or the like, and then serialize the input signals using a high-speed clock to form several high-speed digital signals. These high-speed digital signals drive analog drivers that output corresponding analog signals.

[0007]

[0007] Multi-lane coherent transceivers typically use a clock generation circuit that includes a phase-locked loop (PLL) and a period divider. The PLL generates a high-speed clock signal that is fanned out to each lane, and the period divider divides the high-speed clock signal to form a low-speed clock signal that is also fanned out to each lane.

[0008]

[0008] The order of the serialized high-speed data is determined by a reset signal that gates or enables the minute period. Since the reset signal is generated by a state machine controlled by software or firmware, the reset signal is not synchronized with the high-speed clock signal in each lane.

[0009]

[0009] However, due to variations in the physical arrangement of the integrated circuit, such as the length of the signal trace and / or the number of buffers required for signal quality, and variations in the analog characteristics of the integrated circuit, such as causing different gate delays in similar circuits, timing differences or skew may occur between signals on different lanes. Such skew may degrade performance and / or cause catastrophic failure of the transmitter. [Overview of the project]

[0010]

[0010] Therefore, a system and method for closed loop plane synchronization for optical modulation is needed.

[0011]

[0011] According to an embodiment of the present invention, a system for transmitting a signal over a serial link comprises a plurality of lanes for coupling data onto a transmission medium, a skew detector configured to detect skew between two of the plurality of lanes, and a variable delay circuit controlled by the skew detector and configured to delay the start of a clock signal to one of the plurality of lanes.

[0012]

[0012] According to another embodiment of the present invention, a system for transmitting signals over a serial link comprises a plurality of lanes for coupling data onto a transmission medium and a skew adjustment circuit configured to adjust the skew between two of the plurality of lanes in a closed loop.

[0013]

[0013] According to a further embodiment of the present invention, a system for transmitting a signal over an optical serial link comprises a plurality of lanes for coupling data onto an optical transmission waveguide, and a skew adjustment component for each of the plurality of lanes, configured to adjust the skew of each lane in response to the output of a skew detector. The skew detector is configured to detect skew between two adjacent lanes. The system further comprises a variable delay circuit, controlled by the skew detector and configured to delay the start of a clock signal to one of the plurality of lanes.

[0014]

[0014] The accompanying drawings incorporated herein and forming part thereof illustrate embodiments of the present invention and, together with the description, serve to illustrate the principles of the present invention. Unless otherwise noted, the drawings may not be drawn to scale. [Brief explanation of the drawing]

[0015] [Figure 1] This is an exemplary block diagram of an on-chip optical system according to an embodiment of the present invention. [Figure 2] This is a block diagram of an exemplary on-chip optical driver system according to an embodiment of the present invention. [Figure 3] This is a block diagram of an exemplary on-chip optical device driver system according to an embodiment of the present invention. [Figure 4] This is a block diagram of an exemplary on-chip optical device driver system according to an embodiment of the present invention. [Figure 5] This is an exemplary block diagram of a skew adjustment system according to an embodiment of the present invention. [Figure 6] This is an exemplary block diagram of a skew adjustment system according to an embodiment of the present invention. [Figure 7] This figure shows an exemplary method for adjusting the skew between lanes of a multi-lane transmitter according to an embodiment of the present invention. [Figure 8]This figure shows an exemplary advantageous test data pattern 800 for detecting skew between lanes in a multi-lane transmitter according to an embodiment of the present invention. [Modes for carrying out the invention]

[0016]

[0023] The following descriptions will refer in detail to various embodiments of the present invention illustrated in the accompanying drawings. While the present invention will be described in conjunction with these embodiments, it should be understood that the present invention is not limited to these embodiments. Rather, the present invention encompasses alternative forms, modifications, and equivalents that may fall within the spirit and scope of the present invention as defined by the accompanying claims. Furthermore, the following detailed description of the present invention will include numerous specific details to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention can be carried out without these specific details. In other cases, well-known methods, procedures, components, and circuits will not be described in detail so as not to unnecessarily obscure aspects of the present invention.

[0017]

[0024] Some of the following detailed descriptions are presented with respect to procedures, logic blocks, processes, and other symbolic representations of operations performed by electronic devices and / or circuits. These descriptions and representations are means used by those skilled in the art to most effectively communicate the substance of the work to others skilled in the art. In this application, procedures, methods, logic blocks, processes, etc., are considered to be a consistent set of actions or instructions that produce a desired result. Actions require the physical manipulation of physical quantities. However, it should be noted that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise specified as it is clear from the following descriptions, descriptions using terms such as “filtering,” “slicing,” “improvement,” “updating,” and “access” throughout this application should be understood to refer to actions and processes of electronic devices and / or electronic circuits, including integrated circuits, for example (e.g., Method 700 in Figure 7).

[0018] Closed-loop lane synchronization for optical modulation

[0019]

[0025] FIG. 1 is an exemplary block diagram of an on-chip optical system 100 according to an embodiment of the present invention. The optical system 100 includes a driver 101 and a waveguide 105. The driver 101 includes lanes 110-140 and skew detectors 151-153. The lanes 110-140 each include a respective driver / modulation component 111-141. The driver / modulation components 111-141 each include a respective skew adjustment component 112-142. Data inputs a-d (Din-a to Din-d) are supplied to the respective driver / modulation components 111-141. The driver / modulation components 111-141 generate respective initial modulation driver signal sets Pa / Ma to Pd / Md, and these signal sets are sent to the waveguide 105. One signal from one set and another signal from another set are sent to a skew detector that detects the skew difference between the respective signals. The on-chip optical system 100 can include dummy loads 171, 172 coupled to the Pa signal and the Md signal that are not coupled to the skew detector. <0000​​​​​​​

[0027] The skew adjustment components 112-142 automatically adjust each modulation driver signal according to the detected skew. The skew-adjusted modulation driver signal is supplied to the waveguide 105 to modulate a constant optical input signal to generate a modulated optical output signal. In one embodiment, the skew-adjusted electrical signal is used to drive a light-emitting device, and the light-emitting device emits light to modulate the intensity of the optical output of the waveguide 105 (e.g., constructively, destructively, etc.). In one exemplary implementation, the skew-adjusted modulation driver optical signal is supplied to a waveguide phase shifter to modulate the optical signal of the waveguide 105 (similar to, for example, the Mach-Zehnder method). The modulated optical output signal may conform to various communication standards (e.g., NRZ, PAM-4, PAM-16, PAN-N, etc.).

[0022]

[0028] The skew adjustment component can adjust the skew based on instructions from various sources. Figure 2 is a block diagram of an exemplary on-chip optical driver system 200 according to an embodiment of the present invention. The optical driver system 200 includes lanes 210-230 and skew detectors 271-272. The on-chip optical system 200 may include dummy loads 291, 292 coupled to Pa and Mc signals that are not coupled to the skew detectors. Lanes 210-230 include their respective driver / modulation components 211-231. Driver / modulation components 211-231 include their respective skew adjustment components 212-232. Data inputs a-c (Din-a-Din-d) are supplied to their respective driver / modulation components 211-231. Skew detection components 271, 272 can send skew detection information to the skew adjustment component and off-chip. Skew adjustment components 212 and 222 can adjust skew based on skew adjustment component signals 281 and 282 from skew detection components 271 and 272, respectively. Skew adjustment components 212 and 222 can adjust skew based on instructions from skew calibration components at various locations (e.g., those included in skew detection components 271 and 272, those included in driver circuits 211 and 222, etc.). Skew adjustment components 212, 222, and 232 can also adjust skew based on adjustment commands Adj-a to Adj-c from off-chip.

[0023]

[0029] Figure 3 is a block diagram of an exemplary on-chip optical device driver system 300 according to an embodiment of the present invention. The driver system 300 includes a skew detection component 390 and lanes 301, 302, and 303. Lane A301 includes on-chip components such as a serializer 310, a multiplexing component 320, an output stage 330, and an analog comparator decision logic 340. In one embodiment, the multiplexing component 320 is a high-speed 4:1 multiplexer. The serializer 310 is communicatively coupled to the multiplexing component 320, and the multiplexing component 320 is communicatively coupled to the output stage 330. The analog comparator decision logic 340 is communicatively coupled to the multiplexing component 320 and the output stage 330. In one embodiment, lanes B302 and C303 have a similar configuration to lane A301.

[0024]

[0030] The components of the driver system 300 work together to modulate the optical signal by supplying a modulation driver signal to drive the electro-optic modulator configuration. The serializer 310 is configured to receive parallel data signals and send corresponding serial data signals. The multiplexing component 320 is configured to selectively output the in-phase and quadrature components of the serial data signal. The output stage 330 is configured to output a signal that modulates the optical signal. The skew detection component 390 is configured to detect skew, and the skew calibration component is configured for direct skew adjustment between the first output signal and the second output signal. In one exemplary implementation, the analog comparator and decision logic 340 includes an analog comparator, a digital-to-analog converter, and digital finite state machine (FSM) logic. The analog comparator and decision logic 340 is included in the quadrature error correction (QEC) path and can instruct the selection controller of MUX 321 to adjust Q-PI 323. The QEC path is generally used to compensate for output errors caused by clock misalignment from the Q-PI323 to the I-PI322. The digital-to-analog converter may be configured to eliminate analog comparator mismatch errors.

[0025]

[0031] In one embodiment, the multiplexing component 320 includes a multiplexer (MUX) 321, a first phase interpolation component 322, a second phase interpolation component 323, and a clock period 324. The clock period 324 receives input from the first phase interpolation component 322. The second phase interpolation component 323 may be an N-bit quadrature interpolation (Q-PI) component. The first phase interpolation component 322 may be an N-bit common-mode interpolation (I-PI) component. The multiplexer 321 is communicatively coupled to the first phase interpolation component 322 and the second phase interpolation component 323. The MUX 321 is configured to selectively output the common-mode and quadrature components of the serial data signal based on selection control signals from the first phase interpolation component 322 and the second phase interpolation component 323. The MUX 321, I-PI 322, and Q-PI 323 perform skew adjustment on the first and second output signal modes. The second phase interpolation component 323 is configured to send an orthogonal selection signal to the MUX 321. The first phase interpolation component 322 is configured to send a common-mode selection signal to the MUX 321. In one exemplary implementation, the first phase interpolation component 322 receives instructions from the skew calibration component 352 regarding skew-related adjustments to the common-mode selection signal sent to the MUX 321. Furthermore, the second phase interpolation component 322 receives instructions from the QEC path 340 regarding the orthogonal selection signal sent to the MUX 321 after skew-related adjustments of the first phase interpolator 322.

[0026]

[0032] In one embodiment, the skew detection component 390 includes lane skew detection components (e.g., 350, 360, etc.) and a dummy load 370. The lane skew detection component 350 detects skew between lanes A and B. The lane skew detection component 360 detects skew between lanes B and C. The dummy load 370 is coupled to Pa and Mc signals that are not coupled to the skew detector.

[0027]

[0033] The lane skew detection component 350 includes a skew detector 351 and a skew calibration component 352. The skew detector 351 is configured to detect the skew difference between a first output signal of lane A (e.g., Ma) and a second output signal of lane B (e.g., Pb). The skew calibration component 352 is configured to instruct the adjustment of the skew between the first and second output signals. In one exemplary implementation, the skew calibration component 352 includes an analog comparator and a decision logic 353. The skew calibration path flows from the skew detection component 390 to the common-mode interpolator (I-PI) 322. The skew calibration component 352 is included in the skew correction path and can instruct the selection controller of the MUX 321 to adjust the I-PI 322. The lane skew detection component 390 may include a skew detector similar to the skew detector 351 and a skew calibration component similar to the skew calibration component 352.

[0028]

[0034] In one embodiment, the skew is adjusted so that the skew difference between the first output signal and the second output signal becomes zero. In one exemplary implementation, the skew is adjusted so that the skew difference between the first output signal and the second output signal becomes constant. The first output signal can be associated with a first modulation lane, and the second output signal can be associated with a second modulation lane. In one embodiment, the first and second output signals may be differential signals (e.g., with a phase difference of about 180 degrees). The first output signal can be considered as the positive signal of the first modulation lane, and the second output signal can be considered as the negative signal of the second modulation lane.

[0029]

[0035] Figure 4 is a block diagram of an exemplary on-chip optical device driver system 400 according to an embodiment of the present invention. The on-chip optical device driver system 400 is similar to the on-chip optical device driver system 300, except that the skew calibration component 443 of the on-chip optical device driver system 400 includes logic for selectively instructing skew correction path adjustment and QEC path adjustment. In one exemplary implementation, the skew calibration component 443 utilizes hardware components when performing both types of path adjustment.

[0030]

[0036] The driver system 400 includes a skew detection component 490 and lanes 401, 402, and 403. Lane A401 includes on-chip components such as a serializer 410, a multiplexing component 420, an output stage 430, and an analog comparator decision logic 445. In one embodiment, the multiplexing component 420 is a high-speed 4:1 multiplexer. The serializer 410 is communicatively coupled to the multiplexing component 420, and the multiplexing component 420 is communicatively coupled to the output stage 430. The analog comparator decision logic 445 is communicatively coupled to the multiplexing component 420 and selectively coupled to the output stage 430 and the skew detection component 490. In one embodiment, lanes B402 and C403 have a configuration similar to that of lane A301.

[0031]

[0037] The components of the driver system 400 work together to modulate the optical signal by supplying a modulation driver signal to drive the electro-optic modulator configuration. The serializer 410 is configured to receive parallel data signals and send corresponding serial data signals. The multiplexing component 420 is configured to selectively output the common-mode and quadrature components of the serial data signal. The output stage 430 is configured to output a signal that modulates the optical signal. The skew detection component 490 is configured to detect the skew between the first output signal and the second output signal.

[0032]

[0038] In one embodiment, the multiplexing component 420 includes a multiplexer (MUX) 421, a first phase interpolation component 422, a second phase interpolation component 423, and a clock period 424. The clock period 424 receives input from the first phase interpolation component 422. The second phase interpolation component 423 may be an N-bit quadrature-pi (Q-PI) component. The first phase interpolation component 422 may be an N-bit common-mode interpolation (I-PI) component. The multiplexer 421 is communicatively coupled to the first phase interpolation component 422 and the second phase interpolation component 423. The MUX 421 is configured to selectively output the common-mode and quadrature components of the serial data signal. The second phase interpolation component 423 is configured to send a quadrature selection signal to the MUX 421. The first phase interpolation component 422 is configured to send a common-mode selection signal to the MUX 421. In one exemplary implementation, the first phase interpolation component 422 and the second phase interpolation component 423 selectively receive instructions from the skew calibration component 443 regarding both orthogonal-related adjustments of the orthogonal selection signal and skew-related adjustments of the common-mode selection signal sent to the MUX 421.

[0033]

[0039] In one embodiment, the skew detection component 490 includes lane skew detection components (e.g., 450, 460, etc.) and a dummy load 470. The lane skew detection component 450 detects skew between lanes A and B. The lane skew detection component 460 detects skew between lanes B and C. The dummy load 470 is coupled to Pa and Mc signals that are not coupled to the skew detector.

[0034]

[0040] The lane skew detection component 450 includes a skew detector 451. The skew detector 451 is configured to detect a skew difference between a first output signal from lane A (e.g., Ma) and a second output signal from lane B (e.g., Pb). The lane skew detection component 460 includes a skew detector similar to the skew detector 451.

[0035]

[0041] The skew calibration component 443 is shared between the QEC path and the skew correction path. The QEC path and the skew calibration path are selectively formed by switch 411, the skew calibration component 443, and switch 442. The skew calibration path flows from the skew detection component 490 to the first phase interpolation component 422. The QEC path flows from the output stage 430 to the second phase interpolation component 423. In one exemplary implementation, the skew calibration component 443 includes an analog comparator and decision logic 445. In one exemplary implementation, the analog comparator and decision logic 445 may include an analog comparator with an offset calibration mechanism and be configured to eliminate loop mismatches.

[0036]

[0042] Figure 5 is an exemplary block diagram of a skew adjustment system 500 according to an embodiment of the present invention. The skew adjustment system 500 includes a skew detector 570 and an analog comparator and decision logic 590. The analog comparator and decision logic 590 are included in the skew calibration component. In one embodiment, the skew detector 570 is the same as the skew detector 451, and the analog comparator and decision logic 590 is the same as the analog comparator and decision logic 445.

[0037]

[0043] The skew detector 570 includes a mode selection component 580 and a phase frequency detector (PFD) 550. The mode selection component 580 includes registers 501 and 502 coupled to buffers 503 and 504, respectively, which are coupled to MUX 511 and 512, respectively, and which are coupled to MUX 513 and 514, respectively. MUX 513 is coupled to the buffer chain indicated by 521. MUX 514 is coupled to the buffer chain indicated by 531. Buffers 521 and 531 are coupled to the PFD 550. Registers 501 and 502 can enable electrostatic discharge (ESD) protection. The selection signals of MUX 511 and 512 are used to enable and disable the skew detection period. The selection signals of MUX 513 and 514 are used to enable and disable the calibration mode / detection mode and normal / off mode. MUX513 and 514 may be used to perform load balancing. The buffer chain ensures that identical or similar signals are sent to the PFD550. The PFD550 includes registers 551 and 552, a logic AND gate 553, registers 554 and 555, and a capacitor 557.

[0038]

[0044] The analog comparator and decision logic 590 includes variable current sources 591 and 592 coupled to the analog comparator 593, which is coupled to the digital filter 594. In one embodiment, the variable current sources 591 and 592 supply digitally adjusted offset current. In one exemplary implementation, the analog comparator and decision logic 590 is shared between the QEC path and the skew correction path (similar to, for example, the analog comparator and decision logic 445).

[0039]

[0045] In one embodiment, current is applied or injected. In one exemplary implementation, the current is introduced by a current source (e.g., 591, 592, etc.). The injection of current may cause a voltage change. In one embodiment, skew or offset is adjusted by varying the values ​​of the applied or injected current so that they are not equal.

[0040]

[0046] If there is a systematic offset of the phase detector due to mismatch, this offset may result in a skew offset, which should be calibrated. In one embodiment, the skew detector is an offset-compensated skew detector that compensates for the offset of the phase detector. In one exemplary implementation, the skew detector / phase detector offset is eliminated. Unlike conventional skew detectors (e.g., common-mode locked-loop), the offset-compensated skew detector reduces the risk of performance impacts associated with phase detector mismatch. The offset-compensated skew detector can also relax design requirements and save design costs. In one exemplary implementation, the comparator (e.g., 353, 445) is a flexible offset-programmable comparator.

[0041]

[0047] According to an embodiment of the present invention, a reset variable delay control signal 599 is taken from the output of an analog comparator 593. As further described below in Figure 6, the variable delay control signal 599 is used in conjunction with a skew adjustment system 600 to change the timing of the lane reset signals in order to eliminate harmful skew between reset signals.

[0042]

[0048] Figure 6 is an exemplary block diagram of a skew adjustment system 600 according to an embodiment of the present invention. Figure 6 shows some of the circuits of lane 1, which is the first lane of a multi-lane transmitter. The main clock input signal 640 is received by the phase interpolator 630 to produce a clock signal 641. The phase interpolator 630 provides the ability to change the phase of clock 640, for example, the ability to change the time position of the rising edge of clock 640. For example, the rising edge of clock 641 may be delayed relative to clock 640. The specified clock rate of 14 GHz is exemplary.

[0043]

[0049] Clock 641 may be gated by switch 607, for example, by being turned off. When clock 641 is passed by switch 607, it drives the multiplexer 606 and the periodic minute 605.

[0044]

[0050] The transmit buffer 650 provides data to lane 1 in a 64-bit width. The first multiplexer 601 selects 8 of the 64 bits based on the clock signal from the period division 603. The second multiplexer 604 selects 4 of the 8 bits based on the clock signal from the period division 605, which divides the clock signal 641 into two. The third multiplexer 606 selects 1 of the 4 bits based on the gate-controlled highest-speed clock signal output from switch 607. In some embodiments, the output of multiplexer 606 drives a portion of waveguide 105 (Figure 1). The output of multiplexer 606 also drives the input to skew detector 500 as, for example, signal "In1" (Figure 5). Similarly, the corresponding signal from lane 2 drives the input to skew detector 500 as, for example, signal "In2".

[0045]

[0051] Switch 607 is controlled by the output of a Type D flip-flop 608 via a variable delay element 610, which is triggered by a common reset signal 620. The variable delay element 610 can include any well-known suitable circuit. The common reset signal 620 is applied to all lanes. The common reset signal 620 functions to reset the periodic elements 603 and 605. However, the periodic elements 603 and 605 and the multiplexers 602, 604, and 606 do not receive an active clock signal until clock 641 is passed by switch 607. The variable delay element 610 is controlled by a variable delay control signal 599 (Figure 5). Thus, the variable delay 610 controls the periodic elements 603 and 605 and the multiplexers 602, 604, and 606 when they receive an active clock signal and are actually operating.

[0046]

[0052] The delay control signal 599 is specific to the skew detected between lane 1 and lane 2 (Figure 5). It should be understood that the specific delay control signal 599 is not supplied to lane 2. Lane 2 may be supplied with a similar but different signal, for example, based on a skew comparison between lane 2 and lane 3. According to embodiments of the present invention, the time at which the clock 641 is supplied to the periodic units 603, 605 and the multiplexers 602, 604, 606 may differ for lane 1 compared to when the clock is supplied to the corresponding elements of lane 2. This novel method allows for advantageous adjustment of clock skew between lanes.

[0047]

[0053] Figure 7 shows an exemplary method 700 for adjusting the skew between lanes of a multi-lane transmitter according to an embodiment of the present invention. At 710, a reset line for all lanes, e.g., a common reset signal 620 (Figure 6), is asserted. At 720, in response to the assertion of the reset line, the clock signal in the lane is gated off. At 730, the reset line is asserted for all cards.

[0048]

[0054] At 740, the lane clock signal is gated on according to a specified delay. There may be a default delay for the first pass-through process 700. At 750, a skew detection circuit, e.g., the skew adjustment system 500 in Figure 5, is activated. At 760, if skew is observed between two lanes, a reset delay, e.g., a delay caused by a variable delay element 610 (Figure 6), is adjusted, and the flow continues at 710.

[0049]

[0055] It should be understood that adjusting the reset delay of the first lane, rather than the second lane, causes the lane-specific clock signal of the first lane to skew relative to the clock signal of the second lane. This novel method allows for favorable adjustment of clock skew between lanes.

[0050]

[0056] In one embodiment, adjusting the skew includes enabling a calibration mode and performing an offset adjustment process on the first output signal relative to the second output signal.

[0051]

[0057] Figure 8 shows an exemplary advantageous test data pattern 800 for detecting skew between lanes in a multi-lane transmitter according to an embodiment of the present invention. According to an embodiment of the present invention, the test pattern can be generated by a test pattern generator 660 (Figure 6), loaded into a Tx buffer 650 (Figure 6), and propagated through two lanes to determine the skew.

[0052]

[0058] Signal 805 is the main clock signal, e.g., clock 640 (Figure 6). Exemplary data frames 810 and 811 show a 4-symbol skew between lane 0 and lane 1. Test data 820 shows the clock signal along with the duration of 5 symbols. Test data 821 shows the clock signal along with the duration of 5 symbols, offset by 1 symbol relative to test data 820.

[0053]

[0059] Signal 830 indicates the lead output of the phase frequency detector for the exemplary skew shown by signals 810 and 811, for example, the output of register 551 of the phase frequency detector (PFD) 550 in Figure 5. Signal 831 indicates the delay output of the phase frequency detector, for example, the output of register 552 of the phase frequency detector (PFD) 550 in Figure 5. In general, the output of the phase frequency detector informs the variable clock start delay, for example, the variable delay 610 in Figure 6, of the magnitude and direction of the adjustment.

[0054]

[0060] Figure 8 further shows test data 840, 841 including the duration of seven symbols. Signals 850, 851 show the leading and lagging outputs of the phase frequency detector for the exemplary skew indicated by signals 810, 811.

[0055]

[0061] According to embodiments of the present invention, any given skew between lanes can be identified by sending multiple test data patterns through multiple lanes of a multi-lane transmitter. For example, 5-symbol test data 820, 821 cannot identify a 20-symbol skew. However, such a 20-symbol skew is identified by 7-symbol test data 840, 841. Similarly, 7-symbol test data 840, 841 may not identify a 28-symbol skew. It is advantageous if 5-symbol test data 820, 821 can identify a 28-symbol skew.

[0056]

[0062] According to embodiments of the present invention, the different symbol sizes in the symbol test data may be based on prime numbers having a least common multiple greater than the maximum expected skew size. For example, the symbol size test data of 5 and 7 in this example can detect all skew up to 35 (5 × 7) symbol skew.

[0057]

[0063] Embodiments of the present invention provide a system and method for closed loop plane synchronization for optical modulation.

[0058]

[0064] Various embodiments of the present invention have been described herein. Although the present invention has been described in particular embodiments, it should be understood that the present invention should not be construed as being limited by such embodiments, but rather as being construed in accordance with the following claims.

Claims

1. A plurality of lanes for coupling data onto a transmission medium, comprising a first lane including a first modulation driver signal and a second modulation driver signal, and a second lane including a first modulation driver signal and a second modulation driver signal, A skew detector is electrically coupled to the first output of a modulation driver corresponding to the first modulation driver signal of the first lane among the plurality of lanes, and electrically coupled to the second output of a modulation driver corresponding to the second modulation driver signal of the second lane among the plurality of lanes, and is configured to detect skew between the first lane and the second lane, wherein the first modulation driver signal and the second modulation driver signal constitute a differential signal. A variable delay circuit, controlled by the skew detector, is configured to adjust the time during which a clock signal is supplied to the circuit of the first lane among the plurality of lanes by adjusting the delay of the reset signal that gates the clock signal in the first lane. A system for transmitting signals via a serial link, equipped with the necessary components.

2. The system according to claim 1, wherein the variable delay circuit is configured to adjust the time for which the clock signal is supplied to the circuit of the first lane among the plurality of lanes, thereby adjusting the skew between the lanes.

3. The system according to claim 2, further comprising a test pattern generator configured to supply test patterns to the plurality of lanes used to detect the skew between two of the plurality of lanes.

4. The system according to claim 3, wherein the test pattern includes at least two test patterns based on a different number of symbols.

5. The system according to claim 4, wherein the at least two test patterns include different prime number symbols.

6. The system according to claim 4, wherein the at least two test patterns include the least common multiple of the number of symbols that is greater than the expected size of the symbol skew.

7. The system according to claim 4, wherein the skew detector is configured to control and assert a common reset signal supplied to each lane for resetting the plurality of lanes when an unintended skew is detected between any pair of lanes, and the reset signal in each of the plurality of lanes is based on the common reset signal.

8. A plurality of lanes for coupling data onto a transmission medium, comprising a first lane including a first modulation driver signal and a second modulation driver signal, and a second lane including a first modulation driver signal and a second modulation driver signal, The system includes a skew adjustment circuit configured to adjust the skew between the first lane and the second lane of a plurality of lanes in a closed loop, based on detecting the skew between the outputs of the modulation drivers corresponding to the first modulation driver signal of the first lane and the second modulation driver signal of the second lane, wherein the first modulation driver signal and the second modulation driver signal constitute differential signals. The skew adjustment circuit includes a variable delay circuit that adjusts the time the clock signal is supplied to the circuit of a lane by adjusting the delay of the reset signal that gates the clock signal in either the first lane or the second lane. A system for transmitting signals via a serial link.

9. The system according to claim 8, wherein a skew detector is used to control the skew adjustment circuit and the common reset signal for the plurality of lanes, and the reset signal in each of the plurality of lanes is based on the common reset signal.

10. The system according to claim 8, wherein the skew adjustment circuit is configured to introduce an intentional skew between the two lanes.

11. The system further includes a plurality of the aforementioned skew adjustment circuits, The system according to claim 8, wherein the skew between two or more of the plurality of lanes is adjusted relative to each other by continuously adjusting the skew between all lanes one pair at a time.

12. The system according to claim 8, wherein the skew adjustment circuit is configured to introduce an intentional skew between a plurality of lanes.

13. The system according to claim 8, wherein a skew detector is used to control the skew adjustment circuit to adjust the time over which a clock is supplied to one lane and to assert a common reset signal for the plurality of lanes, and the reset signal in each of the plurality of lanes is based on the common reset signal.

14. Multiple lanes for coupling independent data onto an optical transmission waveguide, A skew adjustment component for each of the plurality of lanes, configured to adjust the skew of each lane in response to the output of a skew detector, the skew adjustment component includes a variable delay circuit, controlled by the skew detector and configured to adjust the time over which a clock signal is supplied to one of the plurality of lanes by adjusting the delay of a reset signal that gates a clock signal, wherein the skew adjustment component comprises: The skew detector is configured to detect skew between two adjacent lanes. The skew detector is configured to sense the output of the modulation driver corresponding to the two adjacent lanes. A system for transmitting signals via an optical serial link.

15. The system according to claim 14, wherein the variable delay circuit is configured to adjust the time over which the clock signal is supplied to one of the plurality of lanes, thereby adjusting the skew between the lanes.

16. The system according to claim 14, further comprising a test pattern generator configured to supply test patterns to the plurality of lanes used for detecting the skew between the two adjacent lanes.

17. The system according to claim 16, wherein the test pattern includes at least two test patterns based on a different number of symbols.

18. The system according to claim 14, wherein the skew detector is configured to control and assert a common reset signal for resetting the plurality of lanes when an unintended skew is detected between any pair of lanes, and the reset signal in each of the plurality of lanes is based on the common reset signal.

19. The system according to claim 14, wherein the skew detector is used to control the skew adjustment component and the common reset signal for the plurality of lanes, and the reset signal in each of the plurality of lanes is based on the common reset signal.

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