Electronic device, method for determining memory access efficiency, and storage medium

Abstract

To provide electronic equipment which improves the hardware utilization ratio of an operator in order to improve the performance of the operator, a method for determining memory access efficiency and a storage medium.SOLUTION: Electronic equipment comprises: a memory configured to store an executable instruction and to-be-processed data divided into a plurality of data blocks; and a processor configured to execute the executable instruction. The method comprises: reading a to-be-tested data block in the plurality of data blocks from the memory; according to the size information of the to-be-tested data block, determining access description information comprising reading period information and a data reading interval; and according to the access description information and channel description information describing a plurality of channels for the processor to read the to-be-processed data from the memory, determining the access efficiency of the processor for reading the to-be-tested data block.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] This disclosure relates to the computer technology field, and more particularly to the technology fields of chips, memory, and processors. More specifically, this disclosure provides electronic devices, a method for determining memory access efficiency, and a storage medium. [Background technology]

[0002] With advancements in artificial intelligence and computer technology, it becomes possible to develop operators based on artificial intelligence (AI) chips. To improve the performance of these operators, it is possible to increase their hardware utilization. [Overview of the project]

[0003] This disclosure provides electronic equipment, a method for determining memory access efficiency, and a storage medium.

[0004] According to one aspect of this disclosure, A memory configured to store executable instructions and data to be processed, which is divided into multiple data blocks, The present invention provides an electronic device comprising: a processor configured to read a data block to be measured from memory among multiple data blocks, determine access description information including read period information and data read intervals based on size information of the data block to be measured, and execute executable instructions to determine the access efficiency of the processor reading the data block to be measured based on the access description information and channel description information describing multiple channels through which the processor reads data to be processed from memory.

[0005] Another aspect of this disclosure provides a method for determining memory access efficiency, which includes reading a data block to be measured from a plurality of data blocks in memory; determining access description information including read cycle information and data read intervals based on the size of the data block to be measured; and determining the access efficiency for reading the data block to be measured based on the access description information and channel description information describing a plurality of channels for reading data to be processed from memory.

[0006] According to another aspect of the present disclosure, an electronic device is provided, comprising at least one processor and memory communicated with the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the methods provided to the present disclosure.

[0007] Another aspect of this disclosure provides a non-temporary, computer-readable storage medium in which computer instructions are stored, causing a computer to perform a computer in a manner provided to this disclosure.

[0008] According to another aspect of this disclosure, a computer program is provided that, when executed by a processor, implements the method provided in this disclosure.

[0009] It should be understood that the contents described in this section are not intended to identify important features of the embodiments of this disclosure, nor to limit the scope of this disclosure. Other features of this disclosure will be readily apparent from the following specification.

[0010] The drawings are for the purpose of better understanding the present invention and do not limit the present disclosure. [Brief explanation of the drawing]

[0011] [Figure 1]FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. [Figure 2A] FIG. 2A is a schematic diagram of a function image of an access description function according to an embodiment of the present disclosure. [Figure 2B] FIG. 2B is a schematic diagram of a periodic square wave according to an embodiment of the present disclosure. [Figure 2C] FIG. 2C is a schematic diagram of a data reading interval according to an embodiment of the present disclosure. [Figure 3A] FIG. 3A is a schematic diagram of the distribution of a plurality of channels according to an embodiment of the present disclosure. [Figure 3B] FIG. 3B is a schematic diagram of a function image of a channel description function according to an embodiment of the present disclosure. [Figure 4A] FIG. 4A is a schematic diagram of a function image of an adjusted target channel description function according to an embodiment of the present disclosure. [Figure 4B] FIG. 4B is a schematic diagram of an adjusted periodic square wave according to an embodiment of the present disclosure. [Figure 4C] FIG. 4C is a schematic diagram of an adjusted data reading interval according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a flowchart of a method for determining memory access efficiency according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a block diagram of an electronic device to which a method for determining memory access efficiency according to an embodiment of the present disclosure can be applied.

Mode for Carrying Out the Invention

[0012] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings. For ease of understanding, various details of the embodiments of the present disclosure are included, and these are merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for clarity and simplicity, descriptions of known functions and structures are omitted in the following description.

[0013] Access-intensive operators may include general matrix multiplication (GEMM) and convolution (conv) operators. The bandwidth utilization of access-intensive operators for video memory can be improved, and the operators can be optimized. If the chip's internal cache is limited, block partitioning may be performed on the data to be processed. The access times for different matrix block partitioning schemes can be determined before invoking the operators. In some cases, channel collisions can affect the overall data access time. For example, if channel contention exists, the bandwidth efficiency may be 1 / cn, which is the reciprocal of the channel number (cn).

[0014] In some implementations, the method for dividing the data to be processed into blocks can be optimized, thereby distributing each access across as many channels as possible and making effective use of multi-channel bandwidth. However, if the internal cache is limited, increasing the bandwidth for read operations may reduce the bandwidth for write operations. Determining a good data block partitioning scheme is difficult when the access efficiency for a specific access width cannot be quantified.

[0015] In some embodiments, a specific data read offset (ld) can be handled. For example, the specific data read offset can be the product of the number of channels and the channel width (ig). When determining the block partitioning scheme, the bandwidth efficiency penalty can be increased for the specific data read offset, so that the final block partitioning scheme can utilize the multi-channel bandwidth as much as possible. However, if the difference between the data read offset and the specific data read offset is small, it becomes difficult to determine an appropriate block partitioning scheme. Also, even if the data read offset is an integer multiple or 0.5 times the specific data read offset, it is difficult to determine an appropriate block partitioning scheme.

[0016] To improve data processing efficiency, this disclosure provides electronic devices, which are described below.

[0017] Figure 1 is a schematic diagram of an electronic device according to one embodiment of the present disclosure.

[0018] As shown in Figure 1, the electronic device 100 may include a memory 110 and a processor 120.

[0019] The memory 110 may be configured to store executable instructions and data to be processed.

[0020] In the embodiments of this disclosure, the data to be processed may be divided into multiple data blocks. For example, the data to be processed can be divided into blocks according to one of the block division methods, and multiple data blocks can be obtained.

[0021] In the embodiments of this disclosure, the memory may be 2x rate synchronous dynamic random access memory (DDR) or video memory (GDDR).

[0022] The processor 120 may be configured to execute instructions that can read data blocks to be measured from memory in a plurality of data blocks. Based on the size information of the data blocks to be measured, access description information is determined. Based on the access description information and channel description information, the access efficiency for reading the data blocks to be measured is determined by the processor.

[0023] In the embodiments of this disclosure, any one of the multiple data blocks may be the data block to be measured.

[0024] In embodiments of this disclosure, the access description information may include read cycle information and data read intervals. For example, the data block to be measured may be implemented as a matrix. The size information of the data block to be measured may include the number of rows and the number of columns. The read cycle information may be determined according to the number of columns. The data read interval can be determined according to the number of rows. In one example, the read cycle information may instruct to read one row of data from the matrix in each read cycle. The row data contains the number of values ​​in the column. The data read interval relates to all the values ​​in the matrix.

[0025] In embodiments of this disclosure, channel description information describes multiple channels through which the processor reads data to be processed from memory. For example, through multiple channels, the processor can read one or more data blocks of data to be processed from memory. Channel description information can describe multiple channels.

[0026] According to the embodiments of this disclosure, access description information is established, and access efficiency is determined based on the access description information and channel description information. Once access efficiency is determined, if the access efficiency is relatively low, the data block partitioning can be adjusted, thereby improving access efficiency and contributing to an improvement in the data processing capacity of electronic devices.

[0027] The above describes the electronic devices of this disclosure. The following further explanation concerns the access description information of this disclosure.

[0028] In some embodiments, the size information of the data block to be measured may include the data read offset, row number, and column number. Based on the data read offset, row number, and column number, access description information can be determined. This access description information may be implemented as an access description function, which will be further explained below with reference to Figure 2A.

[0029] Figure 2A is a schematic diagram of the function image of an access description function according to one embodiment of the present disclosure.

[0030] As shown in Figure 2A, the access description function may be a periodic function, and the function period may be determined based on the data read offset. For example, the access description function x(t) may be (Equation 1).

[0031]

number

[0032] k can be an integer between 0 and row-1 (inclusive). row can be the row number. col can be the column number. ld can be the data read offset.

[0033] The access description function shown in Equation 1 can be considered as the product of a periodicity function and a data interval. For example, the periodicity function may correspond to the reading period information, and the data interval may correspond to the data reading interval.

[0034] In some embodiments, the reading period information may be represented as a periodic square wave. This will be further explained below with reference to Figure 2B.

[0035] Figure 2B is a schematic diagram of a periodic square wave according to one embodiment of the present disclosure.

[0036] In the embodiments of this disclosure, the effective width of the square wave may be the number of rows, and the period of the periodic square wave is determined based on the reading offset amount. As shown in Figure 2B, the reading period function l(t) corresponding to the periodic square wave may be (Equation 2).

[0037]

number

[0038] In some embodiments, the data reading interval may be determined based on the data reading offset and the row number. This will be further explained below with reference to Figure 2C.

[0039] Figure 2C is a schematic diagram of a data reading section according to one embodiment of the present disclosure.

[0040] As shown in Figure 2C, the endpoint value of the first interval corresponding to the data reading interval may be 0, and the endpoint value of the second interval corresponding to the data reading interval may be the product of the data reading offset ld and the row number row, row*ld. For example, the function i(t) corresponding to the data reading interval may be (Equation 3).

[0041]

number

[0042] The embodiments of this disclosure help determine access description information, enable modeling of access behavior, and accurately and quantitatively determine access efficiency.

[0043] The access description information of this disclosure has been explained above. Now, the channel description information of this disclosure will be explained below with reference to Figures 3A and 3B.

[0044] Figure 3A is a schematic diagram of the distribution of multiple channels according to one embodiment of the present disclosure.

[0045] As shown in Figure 3A, the number of channels may be cn, and the channel width may be ig.

[0046] In some embodiments, the channel description information may include the channel bandwidth of the channel. For example, the channel description information may be implemented as a channel description function. Figure 3B shows the function image of the channel description function for channel channel_0 among multiple channels.

[0047] Figure 3B is a schematic diagram of a function image of a channel description function according to one embodiment of the present disclosure.

[0048] As shown in Figure 3B, the channel width of channel_0 may be ig. For example, the channel description function for channel_0 may be (Equation 4).

[0049]

number

[0050] k can be a non-negative integer.

[0051] The embodiments of this disclosure help determine channel description information, enable modeling for channels, and accurately and quantitatively determine access efficiency.

[0052] Having described the channel description information and access description information of this disclosure above, several aspects of determining access efficiency will be described further below.

[0053] In embodiments of this disclosure, the processor may be configured to determine the access time of any channel based on the integral result of access description information and channel description information, the number of channels, and a first predetermined parameter. The first predetermined parameter may be related to the channel bandwidth. For example, for the i-th channel out of cn channels, the access time ci t (Equation 5) may also be used.

[0054]

number

[0055] bw may be the first predetermined parameter. c_i(t) may be the channel description function for the i-th channel. i may be an integer between 0 and cn-1 (inclusive).

[0056] As described above, the access description information may include read cycle information and data read intervals. In embodiments of this disclosure, the processor may be configured to determine the access time of any channel based on the integrated value of the data read interval of the read cycle information and the channel description information, the number of channels, and a first predetermined parameter. For example, for the i-th channel out of cn channels, the access time ci t (Equation 6) may also be used.

[0057]

number

[0058] According to the embodiments of this disclosure, the data reading interval can be set as an integration interval, which is advantageous for determining the access time.

[0059] In some embodiments, the processor may be further configured to determine a target channel among multiple channels. In embodiments of the present disclosure, when multiple channels are used to read data blocks to be measured from memory in parallel, the target channel may be the channel with the largest data transmission load. For example, when cn channels are used to read data blocks to be measured from memory in parallel, channel channel_0 can be the target channel if it has the largest data transmission load.

[0060] In some embodiments, the processor may also be configured to determine the target channel description information for the target channel. For example, if the target channel is channel_0, the channel description information for channel_0 may be used as the target channel description information.

[0061] In some embodiments, the processor may be further configured to determine the access efficiency for reading the data block to be measured, based on the number of columns, the number of rows, a first predetermined parameter, and the target channel of the data block to be measured. For example, the access efficiency η can be determined by the following formula.

[0062]

number

[0063] max(c0 t ,c1 t ...c{cn-1} t ) is a function that determines the target channel among multiple channels. If the target channel is channel_0, equation 7 can be transformed into equation 8.

[0064]

number

[0065] Next, equations 8 and 6 can be combined. That is, in embodiments of the present disclosure, the processor may be configured to determine the access efficiency for reading the data block to be measured based on the integral value of the read cycle information and the target channel description information in the data read interval. For example, the access efficiency for reading the data block to be measured is determined based on the number of channels, the size information of the data block to be measured, and the integral value. If T = row * ld, the access efficiency can be determined by the following equation.

[0066]

number

[0067] As shown in Equations 9, 2, and 4, both c_0(t) and l(t) may be periodic functions. To determine the integral value above, the correlation function can be transformed into the frequency domain. The transformation method may include, for example, Fourier stage expansion, Fourier transform, wavelet transform, etc. For example, when performing Fourier stage expansion, if the correlation function is an even function, only cosine terms exist in the total number of stages, and the computational cost can be reduced. Therefore, in the embodiments of this disclosure, the processor may be configured to adjust the read period function, the target channel description function, and the data reading interval, respectively, to obtain the adjusted read period function and the adjusted target channel description function. The following will be described in detail with reference to Figures 4A-4C.

[0068] Figure 4A is a schematic diagram of the function image of an adjusted target channel description function according to one embodiment of the present disclosure. As shown in Figure 4A, the adjusted target channel function can be obtained by translating the target channel description function along the horizontal axis to half the channel width. The adjusted target channel function may be an even function.

[0069] Figure 4B is a schematic diagram of an adjusted periodic square wave according to one embodiment of the present disclosure. The adjusted reading periodic function can be obtained by translating the reading periodic function to half a column of data along the horizontal axis. The adjusted reading periodic function may be an even function. The adjusted reading periodic function can be represented as an adjusted periodic square wave as shown in Figure 4B.

[0070] Figure 4C is a schematic diagram of an adjusted data reading interval according to one embodiment of the present disclosure. As shown in Figure 4C, the adjusted data reading interval can be obtained by translating the data reading interval along the horizontal axis by the above product of 1 / 2 (row * ld).

[0071] Next, after adjusting the read period function, target channel description function, and data read interval, the processor may be configured in the embodiments of this disclosure to determine the access efficiency for reading the data block to be measured, based on the number of channels, the size information of the data block to be measured, and the integral value of the adjusted data read interval of the adjusted read period information and the adjusted target channel description information. For example, the access efficiency can be determined by the following formula.

[0072]

number

[0073] Next, the processor may be configured to determine multiple first-frequency domain components of the read period information and multiple second-frequency domain components of the target channel description information. For example, the processor may be configured to perform a Fourier stage expansion on the read period information to obtain multiple first-frequency domain components. A Fourier stage expansion is then performed on the target channel description information to obtain multiple second-frequency domain components.

[0074] For example, if the function f(t) is an even function and a periodic function, we may perform an n-stage Fourier expansion on the function f(t).

[0075]

number

[0076] The period of the function f(t) is T f This is also acceptable. ω may be the frequency corresponding to the period. n The nth expansion parameter may be the frequency ω, the 0th expansion parameter a0, and the nth expansion parameter a n The following may also be used for each of them.

[0077]

number

[0078]

Number

[0079]

Number

[0080] r may be the duty ratio of the function f(t).

[0081] Thus, an n-stage Fourier expansion can be performed on the target channel description function c_0(t). c

[0082]

Number

[0083] The period of the target channel description function c_0(t) may be cn*ig. ω c may be the frequency corresponding to this period. ac nc is n c may be the expansion parameter of the n-th stage. The frequency ω c , the expansion parameter ac0 of the 0-th stage and n c may be the expansion parameter ac of the n-th stage nc may be as follows respectively.

[0084]

Number

[0085]

Number

[0086]

Number

[0087] 1 / (cn) may be the duty cycle corresponding to the target channel description function c_0(t). As can be understood, multiple first-frequency domain components are n c It may include n first-frequency domain components. c The second first frequency domain component is ac nc cos(n c ω c t) is also acceptable.

[0088] Furthermore, for the reading period function l(t), n l You may also perform a Fourier expansion of the row.

[0089]

number

[0090] The period of the reading period function l(t) may also be ld. l This may be the frequency corresponding to this period. nl is, n l The expansion parameter of the stage may also be the frequency ω. l , the expansion parameters al0 and n in the 0th stage l Paragraph expansion parameter al nl The following may also be used for each of them.

[0091]

number

[0092]

number

[0093]

number

[0094] col / ld may also be the duty cycle corresponding to the reading period function l(t). As can be understood, multiple second-frequency domain components are n l It may also contain n second-frequency domain components. l The second frequency domain component is al nl cos(n l ω l t) is also acceptable.

[0095] After performing Fourier expansions of the reading cycle information and the target channel description information, a plurality of first-frequency domain components and a plurality of second-frequency domain components can be obtained. Next, in some embodiments, the processor may be configured to determine the access efficiency for reading the data block to be measured based on the plurality of first-frequency domain components and the plurality of second-frequency domain components.

[0096] For example, based on multiple first frequency domain components and multiple second frequency domain components, the integral value

number

number

[0097]

number

number

[0098] Also, for example, the intermediate parameter p(n c ,n l ) may be set, and the intermediate parameter p(n c ,n l ) may also be as follows:

[0099]

number

number

[0100] sinc() can also be the sinc function.

[0101] Therefore, the integral value can be determined based on equations 23 and 24.

[0102]

number

[0103] Next, the processor may determine the access efficiency based on the number of channels, the size information of the data block to be measured, and the integral value. For example, the access efficiency can be determined according to Equations 25 and 10. In one example, n c n may be 5, l It can also be 5.

[0104] In embodiments of this disclosure, reading the access efficiency of a data block to be measured by the processor can represent the uniformity of the data transmission load across multiple channels when the processor reads data blocks to be measured in parallel from memory via multiple channels. According to embodiments of this disclosure, once the size information (data read offset, number of columns, and number of rows) of the data block to be measured is determined, the degree of contention between channels can be accurately determined. Furthermore, determining access efficiency based on size information has good generalization ability, can be adapted to data blocks of different sizes, and can accurately determine access efficiency even when the data read offset has various values. In addition, the block partitioning scheme can be adjusted to improve access efficiency and reduce channel contention.

[0105] To help you understand, the electronic device of this disclosure has been described above. Now, the method for determining the memory access efficiency of this disclosure will be described below.

[0106] Figure 5 is a flowchart of a method for determining memory access efficiency according to one embodiment of the present disclosure.

[0107] As shown in Figure 5, the method 500 may include operations S510 to S530.

[0108] In operation S510, the data block to be measured is read from memory among multiple data blocks.

[0109] In operation S520, the access description information is determined based on the size of the data block to be measured.

[0110] In the embodiments of this disclosure, the access description information includes read cycle information and data read interval.

[0111] In operation S530, the access efficiency for reading the data block to be measured is determined based on the access description information and the channel description information.

[0112] In the embodiments of this disclosure, the channel description information describes a plurality of channels from which data to be processed is read from memory.

[0113] As can be understood, method 500 may be executed by processor 120. Also as can be understood, method 500 may determine the access efficiency related to memory 110.

[0114] In some embodiments, the data read size information to be processed includes the data read offset, number of rows, and number of columns. The read period information is represented as a periodic square wave, where the effective width of the square wave is the number of columns, and the period of the periodic square wave is determined based on the data read offset. The data read interval is determined based on the data read offset and the number of rows.

[0115] In some embodiments, determining the memory access efficiency for reading the data blocks to be measured by the processor, based on access description information and channel description information, includes determining a target channel among multiple channels. For example, if the target channel uses multiple channels to read the data blocks to be measured from memory in parallel, it is the channel with the maximum data transmission load. The target channel description information for the target channel is determined. For example, the target channel description information includes the channel bandwidth of the target channel. Based on the integrated value of the read cycle information and the target channel description information in the data read interval, the access efficiency for reading the data blocks to be measured by the processor is determined.

[0116] In some embodiments, determining the access efficiency for reading data blocks to be measured by the processor based on the integral values ​​of the read cycle information and target channel description information in the data read interval includes determining the access efficiency for reading data blocks to be measured by the processor based on the number of channels, the size of the data blocks to be measured, and the integral value.

[0117] In some embodiments, determining the access efficiency for reading the data block to be measured by the processor based on the integral values ​​of the read period information and the target channel description information in the data read interval includes determining a plurality of first frequency domain components of the read period information and a plurality of second frequency domain components of the target channel description information. Based on the plurality of first frequency domain components and a plurality of second frequency domain components, the access efficiency for reading the data block to be measured by the processor is determined.

[0118] In some embodiments, determining multiple first-frequency domain components of the reading period information and multiple second-frequency domain components of the target channel description information involves performing a Fourier stage expansion on the reading period information to obtain multiple first-frequency domain components. Alternatively, a Fourier stage expansion can be performed on the target channel description information to obtain multiple second-frequency domain components.

[0119] In some embodiments, the access efficiency of the processor reading the data blocks to be measured represents the uniformity of the data transmission load across multiple channels when the processor reads the data blocks to be measured from memory in parallel via multiple channels.

[0120] In the proposed technology disclosed herein, the collection, storage, use, processing, transmission, provision, and disclosure of such user personal information all comply with the provisions of relevant laws and do not violate public order and morals.

[0121] According to embodiments of the present disclosure, the present disclosure further provides electronic devices, readable storage media, and computer program products.

[0122] Figure 6 shows an exemplary block diagram for carrying out an exemplary electronic device 600 of an embodiment of the present disclosure. The electronic device 600 is intended to display various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, large computers, and other suitable computers. The electronic device may further display various forms of mobile devices, such as personal digital assistants, mobile phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are illustrative and not intended to limit the implementation of the present disclosure as described herein and / or requested.

[0123] As shown in Figure 6, the electronic device 600 includes a computing unit 601, which can perform various appropriate operations and processes based on a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. The RAM 603 can also store various programs and data necessary for the operation of the electronic device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0124] Multiple components in the electronic device 600 are connected to the I / O interface 605 and include, for example, input means 606 such as a keyboard and mouse, output means 607 such as various types of displays and speakers, storage means 608 such as magnetic disks and optical disks, and communication means 609 such as a network card, modem, and wireless communication transceiver. The communication means 609 enables the electronic device 600 to exchange information / data with other devices via computer networks such as the Internet and / or various telecommunication networks.

[0125] The computing means 601 may be various general-purpose and / or dedicated processing modules having processing and computing capabilities. Some examples of the computing means 601 include, but are not limited to, a central processing unit (CPU), a GPU (Graphics Processing Unit), various dedicated artificial intelligence (AI) computing chips, computing means for various machine learning model algorithms, a DSP (Digital Signal Processor), and any suitable processor, controller, microcontroller, etc. The computing means 601 performs each of the methods and processes described above, such as a method for determining memory access efficiency. For example, in some embodiments, the method for determining memory access efficiency may be implemented as a computer software program tangibly contained in a machine-readable medium, such as a storage means 608. In some embodiments, part or all of the computer program may be loaded and / or installed into the electronic device 600 via ROM 1002 and / or communication means 609. When the computer program is loaded into RAM 1003 and executed by the computing means 601, one or more steps of the method for determining memory access efficiency described above may be performed. Alternatively, in another embodiment, the computing means 601 may be configured to perform a method for determining memory access efficiency in any other suitable form (e.g., via firmware).

[0126] Various embodiments of the systems and technologies described herein may be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chip (SOCs), complex-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may be implemented in one or more computer programs, which can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, which may include receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0127] Program code for carrying out the methods of this disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a dedicated computer or other programmable data processing device, so that when the program code is executed by the processor or controller, the functions / operations defined in the flowcharts and / or block diagrams are performed. The program code may be executed entirely on a device, partially on a device, partially on a device as a standalone software package, partially on a remote device, or entirely on a remote device or server.

[0128] In the context of this disclosure, a machine-readable medium may be a tangible medium that contains or stores programs used in or in combination with an instruction execution system, device, or electronic device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or electronic devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include one or more wired electrical connections, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0129] To provide user interaction, a computer may be made to implement the systems and techniques described herein, the computer comprising a display device for displaying information to the user (e.g., a CRT (cathode ray tube) display or an LCD (liquid crystal display) monitor), and a keyboard and pointing device (e.g., a mouse or trackball), the user may provide input to the computer via the keyboard and pointing device. Other types of devices may further provide user interaction, for example, feedback provided to the user may be any form of sensing feedback (e.g., visual feedback, auditory feedback, or haptic feedback), and input from the user may be received in any form (including voice input, speech input, or haptic input).

[0130] The systems and technologies described herein can be implemented in computing systems including background components (e.g., a data server), computing systems including middleware components (e.g., an application server), computing systems including front-end components (e.g., a user computer having a graphical user interface or a web browser, through which the user can interact with embodiments of the systems and technologies described herein), or in computing systems including any combination of such background components, middleware components, or front-end components. Components of the system can be connected to one another by digital data communication (e.g., a communication network) in any form or medium. Examples of communication networks include, but are not limited to, local area networks (LANs), wide area networks (WANs), and the Internet.

[0131] A computer system may include clients and servers. Clients and servers are generally geographically separated and typically interact via a communication network. The client-server relationship is generated by a computer program running on the relevant computer that has a client-server relationship.

[0132] It should be understood that various forms of flows shown above may be used, and steps may be rearranged, added, or deleted. For example, each step described in the present invention may be performed in parallel, sequentially, or in a different order, as long as the desired results of the proposed invention of this disclosure can be achieved.

[0133] The specific embodiments described above do not limit the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, subcombinations, and substitutions are possible depending on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. It is an electronic device, A memory configured to store executable instructions and data to be processed, which is divided into multiple data blocks, Read the data block to be measured from the memory, Based on the size information of the data block to be measured, access description information including reading cycle information and data reading interval is determined. A processor configured to execute executable instructions such that the processor determines the access efficiency of reading the data block to be measured, based on the access description information and channel description information describing a plurality of channels through which the processor reads the data to be processed from the memory, The size information of the data block to be measured includes the data read offset, the number of rows, and the number of columns. The aforementioned reading period information is represented as a periodic square wave. The effective width of the aforementioned periodic square wave is the number of columns, The period of the periodic square wave is determined based on the data reading offset. The data reading interval is determined based on the data reading offset and the number of rows. electronic equipment.

2. The aforementioned processor further, Identify a target channel among the multiple channels, and the target channel is the channel that generates the maximum data transmission load when the multiple channels are used to read the data blocks to be measured from the memory in parallel. Determine the target channel description information for the target channel, and the target channel description information includes the channel bandwidth of the target channel. Based on the integral value of the reading cycle information and the target channel description information in the data reading interval, the processor determines the access efficiency for reading the data block to be measured. It is configured to The electronic device according to claim 1.

3. The aforementioned processor further, Based on the number of channels, the size information of the data block to be measured, and the integral value, the processor determines the access efficiency for reading the data block to be measured. It is configured to The electronic device according to claim 2.

4. The aforementioned processor further, The plurality of first frequency domain components of the reading period information are determined, and the plurality of second frequency domain components of the target channel description information are determined. Based on multiple first frequency domain components and multiple second frequency domain components, the processor determines the access efficiency for reading the data block to be measured. It is configured to The electronic device according to claim 2.

5. The aforementioned processor further, A Fourier stage expansion is performed on the aforementioned reading period information to obtain multiple first-frequency domain components. A Fourier stage expansion is performed on the target channel description information to obtain multiple second-frequency domain components. It is configured to The electronic device according to claim 4.

6. The access efficiency by which the processor reads the data block to be measured represents the uniformity of the data transmission load across the multiple channels when the processor reads the data block to be measured from memory in parallel via the multiple channels. The electronic device according to any one of claims 1 to 5.

7. A method for determining memory access efficiency, which is performed by a processor, Reading the data block to be measured from multiple data blocks in memory, Based on the size of the data block to be measured, access description information including reading cycle information and data reading interval is determined. The process includes determining the access efficiency of the processor reading the data block to be measured based on the access description information and channel description information describing multiple channels for reading the data to be measured from the memory, The size information of the data block to be measured includes the data read offset, the number of rows, and the number of columns. The aforementioned reading period information is represented as a periodic square wave. The effective width of the aforementioned periodic square wave is the number of columns, The period of the periodic square wave is determined based on the data reading offset. The data reading interval is determined based on the data reading offset and the number of rows. Method for determining memory access efficiency.

8. Based on the access description information and channel description information, the processor determines the access efficiency for reading the data block to be measured. When reading the data blocks to be measured from the memory in parallel using the multiple channels mentioned above, the target channel is identified as the channel with the maximum data transmission load. Determining the target channel description information of the aforementioned target channel, including the channel bandwidth of the target channel, This includes determining the access efficiency for reading the data block to be measured by the processor based on the integral value of the reading period information and the target channel description information in the data reading interval. The method according to claim 7.

9. Based on the integral value of the reading cycle information and the target channel description information in the data reading interval, the processor determines the access efficiency for reading the data block to be measured. The process includes determining the access efficiency by which the processor reads the data block to be measured, based on the number of channels, the size of the data block to be measured, and the integral value. The method according to claim 8.

10. Based on the integral value of the reading cycle information and the target channel description information in the data reading interval, the processor determines the access efficiency for reading the data block to be measured. The process involves determining a plurality of first frequency domain components of the reading period information and determining a plurality of second frequency domain components of the target channel description information. The process includes determining the access efficiency by which the processor reads the data block to be measured, based on the plurality of first frequency domain components and the plurality of second frequency domain components. The method according to claim 8.

11. Determining the multiple first frequency domain components of the reading period information and determining the multiple second frequency domain components of the target channel description information means that The aforementioned reading period information is subjected to a Fourier stage expansion to obtain multiple first-frequency domain components, This includes performing a Fourier stage expansion on the target channel description information to obtain multiple second-frequency domain components. The method according to claim 10.

12. The access efficiency by which the processor reads the data block to be measured represents the uniformity of the data transmission load across the multiple channels when the processor reads the data block to be measured from memory in parallel via the multiple channels. The method according to claim 7.

13. It is an electronic device, At least one processor, The memory includes at least one processor and is connected to it in communication, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the method according to any one of claims 7 to 12. electronic equipment.

14. A non-temporary computer-readable storage medium in which computer instructions are stored, The computer instruction causes the computer to perform the method described in any one of claims 7 to 12. A non-temporary computer-readable storage medium.

15. A computer program that, when executed by a processor, implements the method according to any one of claims 7 to 12.

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