SiC single crystal substrates and SiC epitaxial wafers

Abstract

To provide a SiC single crystal substrate with diminished local concentration of threading dislocations.SOLUTION: A SiC single crystal substrate 1 has a diameter of 199 mm or more. Across each specific 6 mm square area on the entire substrate surface, the blackness level of PL emission is 5.3 or less when excited at a wavelength of 313 nm.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a SiC single crystal substrate and a SiC epitaxial wafer.

Background Art

[0002] Silicon carbide (SiC) has a breakdown electric field one order of magnitude larger and a bandgap three times larger than that of silicon (Si). In addition, silicon carbide (SiC) has characteristics such as a thermal conductivity about three times higher than that of silicon (Si). Therefore, silicon carbide (SiC) is expected to be applied to power devices, high-frequency devices, high-temperature operation devices, etc. For this reason, in recent years, SiC epitaxial wafers have been used for semiconductor devices as described above.

[0003] A SiC epitaxial wafer is obtained by laminating a SiC epitaxial layer on the surface of a SiC single crystal substrate. Hereinafter, the SiC single crystal substrate before laminating the SiC epitaxial layer may be referred to as a SiC substrate, and the substrate after laminating the SiC epitaxial layer may be referred to as a SiC epitaxial wafer. The SiC substrate is cut out from a SiC ingot.

[0004] In order to realize a SiC device that takes advantage of the excellent characteristics of SiC as described above, it has been proposed to use a SiC substrate with a reduced density of crystal defects (for example, Patent Documents 1 to 3)

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0006] Typical crystal defects include through-edge dislocations (TEDs), through-helic dislocations (TSDs), and basal plane dislocations (BPDs). Methods for evaluating dislocations include etching, photoluminescence, X-ray topography, and transmission electron diffraction.

[0007] As a result of diligent research, the inventors have found that by evaluating a combination of etching and photoluminescence methods, when through-edge dislocations and through-helix dislocations (hereinafter, through-edge dislocations and through-helix dislocations are collectively referred to as "through-dislocations") are densely concentrated locally in a SiC substrate at a density exceeding a predetermined level, stacking faults and triangular faults are concentrated in the SiC epitaxial wafer at locations corresponding to the areas of concentrated through-dislocations after the formation of a SiC epitaxial layer on the SiC substrate. Based on this discovery, the inventors have developed a SiC substrate in which the localized concentration of through-dislocations is reduced, which can suppress the occurrence of such areas of concentrated stacking faults and triangular faults after epitaxial growth.

[0008] The present invention has been made in view of the above circumstances, and aims to provide a SiC single crystal substrate and a SiC epitaxial wafer in which the localized clustering of threading dislocations is reduced. [Means for solving the problem]

[0009] To solve the above problems, the present invention provides the following means.

[0010] Embodiment 1 of the present invention is a method in which the through-dislocation density is 5 × 10 in any 0.25 mm² region of the entire substrate. 4 / cm 2 The following is a SiC single crystal substrate.

[0011] Aspect 2 of the present invention is a SiC single crystal substrate according to aspect 1, wherein the threading dislocation density is 2.2 × 10 4 / cm 2 The following applies:

[0012] A third aspect of the present invention is a SiC single crystal substrate according to aspect 2, wherein the threading dislocation density is 1.0 × 10 4 / cm 2 The following applies:

[0013] Aspect 4 of the present invention is a SiC single crystal substrate according to aspect 1, wherein the blackness of the PL emission intensity at an excitation wavelength of 313 nm is 5.3 or less.

[0014] Aspect 5 of the present invention is a SiC single crystal substrate according to aspect 2, wherein the blackness of the PL emission intensity at an excitation wavelength of 313 nm is 3.8 or less.

[0015] Aspect 6 of the present invention is a SiC single crystal substrate according to aspect 3, wherein the blackness of the PL emission intensity at an excitation wavelength of 313 nm is 2.4 or less.

[0016] Aspect 7 of the present invention is a SiC single crystal substrate according to aspect 1, wherein the diameter is 149 mm or more.

[0017] Aspect 8 of the present invention is a SiC single crystal substrate according to aspect 1, wherein the diameter is 199 mm or more. [Effects of the Invention]

[0018] The SiC single crystal substrate according to the present invention provides a SiC single crystal substrate in which the localized clustering of threading dislocations is reduced. [Brief explanation of the drawing]

[0019] [Figure 1] This is a schematic plan view of a SiC single crystal substrate according to this embodiment. [Figure 2] (a) is a PL image of the SiC single crystal substrate before epitaxial growth, and (b) is a PL image of the SiC epitaxial wafer after epitaxial film growth on the SiC single crystal substrate, with an enlarged PL image of a portion of the 6mm square area also shown. [Figure 3] This image shows a 1 mm square confocal differential interference microscope image of the substrate surface where etch pits were exposed by molten KOH etching, including the center. [Figure 4]It is a schematic diagram showing the plane orientation of the SiC substrate. (a) is a vertical cross-sectional view cut perpendicular to the main surface, and (b) is a plane schematic view seen from a direction perpendicular to the main surface. [Figure 5] It is a diagram schematically showing each process for the method of producing a seed crystal having no through-dislocation dense portion. (a) is a process of specifying the location of the through-dislocation dense portion of the seed crystal by combining molten KOH etching and photoluminescence. (b) is a process of removing and remaking the portion including the location of the through-dislocation dense portion. (c) is a process of performing crystal growth until a seed crystal of sufficient size can be obtained. (d) is a process of cutting out a seed crystal 10-2 larger than the seed crystal 11 from the enlarged diameter portion and performing single crystal growth using this seed crystal 10-2. [Figure 6] It is an enlarged view of the PL image shown in Fig. 2(a).

Embodiments for Carrying Out the Invention

[0020] Hereinafter, the present invention will be described in detail with appropriate reference to the drawings. The drawings used in the following description may show, for the sake of convenience, the characteristic portions enlarged in order to make the features of the present invention easier to understand, and the dimensional ratios and the like of each component may be different from the actual ones. The materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not limited thereto, and it can be appropriately modified and implemented within the range where the effects of the present invention are achieved. Also, in each figure, components well known to those skilled in the art other than the components described in that figure may be omitted.

[0021] Fig. 1 is a plane schematic view of the SiC single crystal substrate according to the present embodiment.

[0022] The SiC single crystal substrate 1 shown in Fig. 1 has a through-dislocation density of 5×10 4 / cm 2 or less in an arbitrary 0.25 mm2 region M on the entire surface of the substrate 1A. The SiC single crystal substrate 1 has a through-dislocation density of 2.2×10 4 / cm 2The following is preferable: In the SiC single crystal substrate 1, the threading dislocation density is 1.0 × 10⁻¹⁰ in any 0.25 mm² region M across the entire surface of the substrate 1A. 4 / cm 2 The following is even more preferable: In Figure 1, only a portion of region M is shown.

[0023] The SiC single crystal substrate 1 shown in Figure 1 has a threading dislocation density of 5 × 10 in any 0.25 mm² region M across the entire surface of the substrate 1A. 4 / cm 2 By having the following configuration, the localized occurrence of stacking faults and triangular faults in the SiC epitaxial wafer after subsequent epitaxial growth is suppressed. Here, "stack fault" refers to a defect in the disorder of the stacked structure of a crystal lattice. Furthermore, while "triangular defects" are broadly a type of stacking fault, they specifically refer to defects formed in a direction where the vertices and opposite sides (bases) of a triangle are aligned sequentially along the step flow growth direction. In other words, the opposite sides (bases) of the triangular defect are positioned perpendicular to the <11-20> direction. Starting from a vertex of the triangle, the triangular defect grows while maintaining a nearly similar triangular shape as it grows through step flow growth, increasing its area. Therefore, triangular defects that originate early in the growth of the SiC epitaxial film are usually larger in size, and the depth of the film at the origin can be estimated from the size of the triangular defect. The fact that the PL images of the triangular defects shown in Figure 2 are all of similar size is thought to be due to their origin being through-dislocations on the substrate surface.

[0024] Furthermore, in this specification, "through dislocation" in "through dislocation density" refers to the combined term for through edge dislocations (TEDs) and through helical dislocations (TSDs). The presence of dislocations in a SiC substrate can be visualized using photoluminescence (PL). Specifically, the in-plane distribution of PL intensity when excitation light is shone on the surface of the sample can be captured by a camera and obtained as a two-dimensional image. In the PL image, areas without dislocations appear bright, while areas with dislocations appear dark (black), allowing for the detection of dislocations based on this contrast.

[0025] The type of dislocation can be determined from the shape of the etch pits revealed by molten KOH etching using an optical microscope, electron microscope (SEM), etc. Generally, etch pits with a medium hexagonal shape and a core correspond to through-helical dislocations (TSDs), while etch pits with a small hexagonal shape and a core correspond to through-edge dislocations (TEDs).

[0026] Figure 2 shows PL images before and after epitaxial growth. (a) is a PL image of the SiC substrate before epitaxial growth, and (b) is a PL image of the SiC epitaxial wafer after growing an epitaxial film with a thickness of approximately 10 μm on the SiC substrate. A magnified PL image of a portion of the 6 mm square area is also shown. Figures 2(a) and (b) are PL images of the same location including the center of the substrate. These are reflected images obtained using a photoluminescence apparatus (Lasertec Corporation, SICA88) with excitation light at a wavelength of 313 nm and reception wavelengths of near-infrared wavelengths (wavelengths of 660 nm or higher). By comparing the PL images in Figures 2(a) and 2(b), it can be seen that numerous stacking faults and / or triangular faults have occurred in the area shown in Figure 2(b) that corresponds to the black area enclosed by a rectangle in the PL image shown in Figure 2(a) (hereinafter sometimes referred to as the "PL black area"). It has been confirmed that the PL black area in the PL image shown in Figure 2(a) is an area where threading dislocations are densely concentrated due to molten KOH etching (hereinafter sometimes referred to as the "threading dislocation concentration area"). A threading dislocation concentration area is an area where threading dislocations are densely concentrated at a higher density than the overall threading dislocation density in the plane.

[0027] The inventors have found that the occurrence of stacking faults and / or triangular faults in SiC epitaxial wafers largely depends on the degree of density of through-dislocations in the SiC substrate, i.e., the through-dislocation density. Table 1 shows the relationship between the through-dislocation density in the SiC substrate and the occurrence of stacking faults and / or triangular faults in the SiC epitaxial wafer after epitaxial growth, within a 6 mm square area including the center of seven SiC substrates.

[0028] [Table 1]

[0029] In Table 1, the presence or absence of PL black areas on the SiC substrate was determined visually. Furthermore, the threading dislocation density on the SiC substrate was calculated by removing the epitaxial layer of the SiC epitaxial wafer by polishing to expose the SiC substrate surface, then capturing microscopic images of the substrate surface (where etch pits were exposed by molten KOH etching) using an optical microscope, importing the images into a computer, and using image analysis software. The presence or absence of stacking faults and triangular defects on the SiC epitaxial wafer was determined using a confocal differential interference microscope (SICA88) from an inspection system (Lasertec Corporation) equipped with both a confocal differential interference microscope and a photoluminescence (PL) observation function.

[0030] As shown in Table 1, the penetrating dislocation density is 1.0 × 10⁻⁶ 4 〔 / cm 2 No PL black areas appeared on the substrate. Consequently, no stacking faults or triangular faults were found in a 6mm square area including the center of the SiC epitaxial wafer after epitaxial growth. The threading dislocation density was 2.2 × 10⁻⁶. 4 〔 / cm 2 In the substrate, PL black areas appeared, but no stacking faults or triangular faults were found in a 6 mm square area including the center of the SiC epitaxial wafer after epitaxial growth. The threading dislocation density was 2.7 × 10⁻⁶. 4 〔 / cm 2 The substrate and the through-dislocation density are 5.0 × 10 4 〔 / cm 2In the substrate, PL black areas appeared, and stacking faults were present in a 6mm square area including the center of the SiC epitaxial wafer after epitaxial growth, but no triangular faults were observed. The threading dislocation density was 6.0 × 10⁻⁶. 4 〔 / cm 2 The substrate has a through-dislocation density of 1.0 × 10⁻⁶. 5 〔 / cm 2 The substrate and the through-dislocation density are 2.0 × 10 5 〔 / cm 2 In all of the substrates, PL black areas appeared, and both stacking faults and triangular faults were present in a 6mm square area including the center of the SiC epitaxial wafer after epitaxial growth.

[0031] Figure 3 shows a 1 mm square confocal differential interference microscope image of the surface of another SiC substrate where etch pits were exposed by molten KOH etching, including the center. The overall penetration dislocation density is 3.3 × 10⁻⁶. 4 〔 / cm 2 ] and on the other hand, in the lower left quarter (dotted frame) only, the penetration dislocation density is 6.1 × 10 4 〔 / cm 2 Based on the results in Table 1, the overall penetration dislocation density of the image was 3.3 × 10⁻⁶. 4 〔 / cm 2 ] represents the penetration dislocation density at which triangular defects do not occur in the SiC epitaxial wafer after epitaxial growth. The penetration dislocation density in the lower left quarter (dotted box) is 6.1 × 10⁻¹⁰. 4 〔 / cm 2 This value represents the threading dislocation density at which both stacking faults and triangular faults occur in a SiC epitaxial wafer after epitaxial growth.

[0032] As shown in Figure 3, only a portion of a 1 mm square (the lower left quarter (dotted line frame)) has a through-dislocation density of 6.0 × 10⁻¹⁶ on the surface of the SiC substrate. 4 〔 / cm 2 If the above-mentioned portion exists locally, then in the SiC epitaxial wafer after epitaxial growth, stacking faults and triangular faults will occur locally, corresponding to a portion of a 1mm square (the lower left quarter (dotted frame)).

[0033] Even if the average through-dislocation density across the entire substrate is sufficiently low, if a SiC epitaxial wafer is fabricated using a SiC substrate that exhibits a non-uniform distribution of through-dislocation density, such as having localized areas (regions) with a through-dislocation density exceeding a predetermined level, stacking faults and triangular faults will occur locally. Thus, in order to suppress the localized clustering of stacking faults and / or triangular faults in a SiC epitaxial wafer, it is necessary to use a SiC substrate that does not have areas of through-dislocation clustering.

[0034] The contrast of the PL image is quantified. Figure 6 shows an enlarged view of the PL image shown in Figure 2(a). In the PL image shown in Figure 6, the blackness (= (mean background - minimum PL black area) / standard deviation of the background) was 7.9, 7.0, 4.5, and 1.2 at the center of the PL black area (indicated by symbol A in Figure 6), halfway between the center and the boundary (indicated by symbol B in Figure 6), the boundary (indicated by symbol C in Figure 6), and a position away from the PL black area (indicated by symbol D in Figure 6), respectively. Note that "mean background" and "standard deviation of the background" refer to the average or standard deviation of the emission intensity of the background area, which is defined as a 0.8 mm square area of ​​the PL image (PL emission intensity image) that does not appear black (for example, the vicinity of the area indicated by symbol D in Figure 6). Furthermore, the penetration dislocation densities at the center of the PL black area (code A), the 1 / 2 position between the center and the boundary (code B), the boundary (code C), and a position away from the PL black area (code D) are, respectively, 2.5 × 10⁻⁶. 5 〔 / cm 2 〕, 1.1×10 5 〔 / cm 2 ], 3.3 × 10 4 〔 / cm 2 ], 5.4×10 3 〔 / cm 2 ]. From the correlation between blackness and penetration dislocation density, blackness was given as K and penetration dislocation density as D [ / cm 2 Assuming this, the blackness K can be calculated using the following formula. K = 1 / 0.5571 x ln (D / 2663.1) From the above formula, the penetrating dislocation density is 1.0 × 10 4 〔 / cm 2], 2.2 × 10 4 〔 / cm 2 ], 2.7 × 10 4 〔 / cm 2 ], 5.0×10 4 〔 / cm 2 ], 6.0×10 4 〔 / cm 2 ], 1 x 10 5 〔 / cm 2 In this case, the blackness can be calculated as 2.4, 3.8, 4.2, 5.3, 5.6, and 6.5, respectively. In the PL image of SiC substrate 1, no PL black areas are visible in the areas with a blackness of 2.4, suggesting that there are no stacking faults or triangular defects in those areas of the SiC epitaxial wafer after epitaxial growth. In the areas with a blackness of 3.8, PL black areas are visible, but it is considered that there are no stacking faults or triangular defects in those areas of the SiC epitaxial wafer after epitaxial growth. In the areas with a blackness of 4.2 and 5.3, PL black areas are visible, but it is considered that there are stacking faults in those areas of the SiC epitaxial wafer after epitaxial growth, but no triangular defects. In the areas with a blackness of 5.6 and 6.5, PL black areas are visible, suggesting that there are both stacking faults and triangular defects in those areas of the SiC epitaxial wafer after epitaxial growth. Therefore, in the PL image of the SiC substrate 1, the blackness is preferably 5.3 or less, more preferably 3.8 or less, and even more preferably 2.4 or less.

[0035] There are no particular restrictions on the external shape of the SiC substrate 1; various flat plate shapes and thicknesses can be used, although it is typically disc-shaped. The thickness of the SiC substrate can be, for example, in the range of 300 to 650 μm. If the SiC substrate 1 is disc-shaped, its dimensions may be, for example, a diameter of 6 inches (145 mm to 155 mm) or a diameter of 8 inches (190 mm to 205 mm). Furthermore, the diameter of the SiC substrate 1 may be 149 mm or larger, or 199 mm or larger.

[0036] The SiC substrate 1 is preferably 4H-SiC. Although there are various polytypes of SiC, 4H-SiC is the one mainly used for fabricating practical SiC devices.

[0037] Figure 4 is a schematic diagram showing the plane orientation of a SiC substrate, where (a) is a perpendicular cross-sectional view taken perpendicular to the main plane, and (b) is a schematic plan view taken from a direction perpendicular to the main plane. The SiC substrate 1 may have a main surface that has an off-angle of 0° to 6° in the <11-20> direction and / or 0° to 0.5° in the <1-100> direction relative to the (0001) plane. A larger off-angle results in fewer wafers being obtained from a SiC single-crystal ingot; therefore, a smaller off-angle is preferable from a cost reduction perspective.

[0038] The SiC single crystal substrate 1 shown in Figure 4 has a notch 2 that serves as an indicator of crystal orientation, but it may also have an OF (orientation flat) instead of a notch 2.

[0039] (Method for manufacturing SiC single crystal substrates) A SiC single crystal substrate without densely packed through-dislocations, i.e., a region of any 0.25 mm² across the entire substrate with a through-dislocation density of 5 × 10⁻¹⁰ 4 / cm 2 To manufacture a SiC single crystal substrate as described below, a seed crystal without densely packed threading dislocations is used, i.e., a threading dislocation density of 5 × 10⁻¹⁶ in any 0.25 mm² region across the entire substrate surface. 4 / cm 2 The following method involves growing a single crystal using a seed crystal. Conventional seed crystals contained a considerable number of threading dislocation clusters. Because attention had not been paid to these localized threading dislocation clusters, their existence was not recognized.

[0040] A method for preparing seed crystals that do not have densely packed threading dislocations will be explained with reference to Figure 5. (1) First, as shown in Figure 5(a), similar to the SiC substrate, the location 10a of the threading dislocation cluster in the seed crystal 10 is identified by combining molten KOH etching and photoluminescence (PL) in the same manner as in substrate defect measurement. (2) Next, as shown in Figure 5(b), the area including the densely packed area of ​​through dislocations 10a is removed, and a smaller seed crystal 11 is created that does not include the densely packed area of ​​through dislocations 10a. Even if a densely packed area of ​​through dislocations occurs near the center, it can be processed to remove it and used as a seed crystal, and then a single crystal of sufficient size can be grown by increasing the diameter. (3) Next, as shown in Figure 5(c), crystal growth is carried out until a seed crystal of sufficient size is obtained, thereby increasing the aperture. Reference numeral 12 indicates the aperture enlargement portion. (4) Next, as shown in Figure 5(d), a seed crystal 10-2 larger than the seed crystal 11 is cut out from the diameter-enlarged portion 12, and a single crystal is grown using this seed crystal 10-2. (5) Repeat steps (1) to (4) above until a seed crystal without densely packed thread dislocations is obtained.

[0041] If a single crystal is grown using a seed crystal obtained in the manner described above, which does not have densely packed threading dislocations, the threading dislocation density in any 0.25 mm² region across the entire substrate will be 5 × 10⁻¹⁶. 4 / cm 2 The following SiC single crystal ingots can be manufactured. By performing normal substrate processing (cylindrical processing, slicing, and polishing) on ​​these SiC single crystal ingots, SiC substrates can be obtained. [Explanation of Symbols]

[0042] 1 SiC single crystal substrate

Claims

1. A SiC single crystal substrate having a diameter of 199 mm or more, wherein the blackness of the PL emission at an excitation wavelength of 313 nm is 5.3 or less in any 6 mm square region across the entire substrate surface.

2. The SiC single crystal substrate according to claim 1, wherein the blackness is 3.8 or less.

3. The SiC single crystal substrate according to claim 1, wherein the blackness is 2.4 or less.

4. A SiC single crystal substrate according to any one of claims 1 to 3, A SiC epitaxial wafer having a SiC epitaxial layer laminated on the surface of the SiC single crystal substrate.

Images