Semiconductor equipment

Abstract

To provide a semiconductor device capable of reducing costs while increasing output and efficiency and suppressing EMI noise.SOLUTION: A semiconductor device includes a power supply circuit that sets one end of a capacitive element to a first potential in a first period and outputs a first power supply voltage from the other end of the capacitive element, and sets one end of the capacitive element to a second potential higher than the first potential during a second period and outputs a second power supply voltage higher than the first power supply voltage from the other end of the capacitive element, and an amplification circuit that receives a pulse width modulated signal, performs a switching operation according to the signal using the first power supply voltage during the first period, and uses the second power supply voltage during the second period to perform the switching operation according to the signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of this specification relate to semiconductor devices. [Background technology]

[0002] Semiconductor devices such as audio amplifiers sometimes perform multi-level Class D amplification on the received signal (see, for example, Patent Document 1). In recent years, in order to reduce environmental impact, there has been a demand for higher output power and higher efficiency in semiconductor devices that perform multi-level Class D amplification. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0304080 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] When performing multi-level Class D amplification in a semiconductor device, multiple types of power supply voltages are used. In order to achieve the high output power described above, a boost power supply circuit is built into the semiconductor device. For example, if a charge pump type power supply circuit is provided in a semiconductor device to generate multiple types of power supply voltages, the number of power transistors used to construct the semiconductor device increases, which may increase the cost of the semiconductor device. Also, when a charge pump type power supply circuit is provided, in the output stage of the Class D amplification, the high-level voltage becomes the boost power supply potential and the low-level voltage becomes the ground potential. As a result, the switching voltage range is large and radiated noise is emitted, so measures to counter radiated noise must be taken.

[0005] The objective of the present invention is to provide a semiconductor device that can achieve higher output, higher efficiency, and suppression of EMI (Electromagnetic Interference) noise while reducing costs. [Means for solving the problem]

[0006] In order to solve the above-described problems and achieve the object, a semiconductor device according to one aspect of the present invention is such that A power transistor comprising a capacitive element, a first power transistor of a first conductivity type whose gate receives a first control signal, whose source is connected to the power supply potential, and whose drain is connected to one end of the capacitive element, a second power transistor of a second conductivity type whose gate receives the first control signal, whose source is connected to a reference potential, and whose drain is connected to the first power transistor and one end of the capacitive element, and a third power transistor of the first conductivity type whose gate receives a second control signal which is the logical inversion of the first control signal, whose source is connected to the other end of the capacitive element, and whose drain is connected to the power supply potential, wherein the first control signal is maintained at a first level and the second control signal is maintained at a second level which is the logical inversion of the first level. one end of the capacitive element is The first power transistor isolates the reference voltage from the power supply potential, while the second power transistor transmits the reference voltage. set to a certain connection potential during a The other end of the capacitive element is connected to the power supply potential via the third power transistor, thereby charging the capacitive element. period, and a first power supply voltage is output from the other end of the capacitive element, Discharge in which the first control signal is maintained at the second level and the second control signal is maintained at the first level one end of the capacitive element is The second power transistor blocks the signal from the reference potential, while the first power transistor transmits the signal. set to the power supply certain connection potential during a By isolating the other end of the capacitive element from the power supply potential using the third power transistor, the capacitive element is discharged while period, and a power supply circuit outputs a second power supply voltage higher than the first power supply voltage from the other end of the capacitive element; receives a pulse-width modulated signal, performs a switching operation according to the signal using the charging first power supply voltage during a Output from the other end of the aforementioned capacitive element period, and performs a switching operation according to the signal using the discharge second power supply voltage during a Output from the other end of the aforementioned capacitive element period, and includes an amplifier circuit.

Advantages of the Invention

[0007] According to the present invention, it is possible to reduce the cost of the semiconductor device while achieving high output, high efficiency, and noise countermeasures.

Brief Description of the Drawings

[0008] [Figure 1] Circuit diagram showing the configuration of a semiconductor device according to the first embodiment. [Figure 2] Waveform diagram showing the operation of a semiconductor device according to the first embodiment. [Figure 3] Circuit diagram showing the configuration of a semiconductor device according to the second embodiment. [Figure 4] Waveform diagram showing the operation of a semiconductor device according to the second embodiment. [Figure 5] Circuit diagram showing the configuration of a semiconductor device according to the third embodiment. [Figure 6] Waveform diagram showing the operation of a semiconductor device according to the third embodiment. [Figure 7]A circuit diagram showing the configuration of a semiconductor device according to the fourth embodiment. [Figure 8] A waveform diagram showing the operation of the semiconductor device according to the fourth embodiment. [Figure 9] A circuit diagram showing the configuration of a semiconductor device including a charge pump type power supply circuit. [Modes for carrying out the invention]

[0009] The embodiments of the semiconductor device will be described in detail below with reference to the drawings. In the following embodiments, parts with the same reference numerals perform the same operation, and redundant explanations will be omitted as appropriate.

[0010] (First embodiment) The semiconductor device according to the first embodiment is, for example, an audio amplifier that performs multi-level Class D amplification on a received signal, and its configuration is designed to achieve high output, high efficiency, and EMI noise suppression at a low cost. For example, the semiconductor device X101 is configured as shown in Figure 1. Figure 1 is a circuit diagram showing the configuration of the semiconductor device X101.

[0011] The semiconductor device X101 is connected between the signal source V102 and the speaker SP. A PWM (Pulse Width Modulation) modulation circuit X103 is connected between the signal source V102 and the semiconductor device X101. A filter X102 is connected between the semiconductor device X101 and the speaker SP. A power supply V101 is connected to the semiconductor device X101. The power supply V101 has a power supply voltage V DD This will cause it to happen.

[0012] The audio signal generated by the signal source V102 is PWM modulated (pulse width modulated) by the PWM modulation circuit X103 and converted into a PWM signal. The semiconductor device X101 receives the PWM signal, performs Class D amplification according to the PWM signal, and outputs the amplified signal. The signal output from the semiconductor device X101 is smoothed by the filter X102 and converted into sound by the speaker SP and output.

[0013] In this case, the semiconductor device X101 may be configured to boost the voltage of the power supply V101. The PWM modulation circuit X103 may be configured to PWM modulate the audio signal and convert it into multiple PWM signals. This allows the semiconductor device X101 to perform multi-level (e.g., 5-level) Class D amplification while suppressing the transition level width to 1 level or the like. In the first embodiment, the transition level width is configured to be the voltage of the power supply V101 supplied to the semiconductor device X101. That is, 1 level corresponds to the voltage width of the power supply V101. Therefore, since the transition level width can be suppressed while increasing the total signal amplitude obtained in Class D amplification operation, EMI noise can be suppressed while increasing the output power of the semiconductor device X101 (e.g., an audio amplifier).

[0014] The semiconductor device X101 has terminals VDD, PWMP1, PWMN1, PWMP0, PWMN0, OUTP, OUTN, processing circuit X111, power supply circuit X105, processing circuit X110, and amplification circuit X104.

[0015] Line PWMP1 is connected to the PWM modulation circuit X103 via terminal PWMP1. Line PWMN1 is connected to the PWM modulation circuit X103 via terminal PWMN1. Line PWMP0 is connected to the PWM modulation circuit X103 via terminal PWMP0. Line PWMN0 is connected to the PWM modulation circuit X103 via terminal PWMN0.

[0016] The amplification circuit X104 is connected to the P-side input node of the filter X102 via terminal OUTP, and to the N-side input node of the filter X102 via terminal OUTN.

[0017] The processing circuit X111 receives and processes the PWM signals PWMP1 and PWMN1 converted by the PWM modulation circuit X103. The processing circuit X111 generates a gate signal GATEBS corresponding to the PWM signals PWMP1 and PWMN1. The processing circuit X111 includes a NOR gate X109.

[0018] The NOR gate X109 has a first input node connected to the PWM modulation circuit X103 via line PWMP1 and terminal PWMP1, a second input node connected to the PWM modulation circuit X103 via line PWMN1 and terminal PWMN1, and an output node connected to the power supply circuit X105 via line GATEBS. The NOR gate X109 performs a negative OR operation on the PWM signal PWMP1 and the PWM signal PWMN1, and supplies the result of the operation as the gate signal GATEBS to the power supply circuit X105.

[0019] The processing circuit X111 supplies the gate signal GATEBS to the power supply circuit X105.

[0020] The power supply circuit X105 receives the power supply voltage Vs1 from power supply V101 and the gate signal GATEBS from processing circuit X111. The power supply circuit X105 can output the received power supply voltage Vs1, and can also boost the power supply voltage Vs1 and output the boosted power supply voltage Vs2.

[0021] The power supply circuit X105 may be configured as a bootstrap type power supply circuit. The power supply circuit X105 may also be able to switch the power supply voltage output from the other end of the capacitive element C101 toward the amplification circuit X104 by switching the potential of one end of the capacitive element C101.

[0022] For example, during a certain period TP1, the power supply circuit X105 raises one end of the capacitive element C101 to a potential V1 in response to the gate signal GATEBS and outputs a power supply voltage Vs1 from the other end of the capacitive element C101. During another period TP2, the power supply circuit X105 raises one end of the capacitive element C101 to a potential V2 (>V1) in response to the gate signal GATEBS and outputs a power supply voltage Vs2 (>Vs1) from the other end of the capacitive element C101. For example, potential V1 = ground potential and potential V2 = V DD Therefore, the power supply voltage Vs1 = V DD Therefore, the power supply voltage Vs2 = 2 × V DD That is the case.

[0023] The power supply circuit X105 is connected to the power supply V101 via terminal VDD. The power supply circuit X105 has terminal CFL, terminal BS, capacitive element C101, driver (first driver) 10 and switch 40.

[0024] Capacitive element C101 has one end connected to driver 10 via terminal CFL, and the other end connected to amplifier circuit X104 via terminal BS.

[0025] The driver 10 has an input node 11 connected to the processing circuit X111, a power supply node 12 connected to the power supply V101 via terminal VDD, a reference node 13 connected to a reference potential (e.g., ground potential), and an output node 14 connected to one end of the capacitive element C101 via terminal CFL. The other end of the capacitive element C101 is connected to the power supply node of the amplification circuit X104 via terminal BS. It connects to the network.

[0026] The driver 10 includes a power transistor M101 (first power transistor) and a power transistor M102 (second power transistor). Power transistor M101 may be a PMOS transistor with enhanced current resistance. The gate of power transistor M101 is connected to the processing circuit X111, the source is connected to the power supply V101 via terminal VDD, and the drain is connected to power transistor M102 and to one end of capacitive element C101 via terminal CFL. Depending on the required current resistance, power transistor M101 has a gate width that is large compared to its gate length, resulting in a relatively large circuit area.

[0027] The power transistor M102 may be an NMOS transistor with enhanced current resistance. The gate of the power transistor M102 is connected to the processing circuit X111, the source is connected to a reference potential (e.g., ground potential), and the drain is connected to the power transistor M101 and also to one end of the capacitive element C101 via terminal CFL. Depending on the required current resistance, the gate width of the power transistor M102 is configured to be large compared to the gate length, resulting in a relatively large circuit area.

[0028] Switch 40 has one end 41 connected to power supply V101 via terminal VDD, the other end 42 connected to the other end of capacitive element C101 via terminal BS, and control node 43 connected to processing circuit X111.

[0029] Switch 40 includes an inverter X106 and a power transistor M103 (a third power transistor). The inverter X106 has an input node connected to the processing circuit X111 and an output node connected to the power transistor M103.

[0030] The power transistor M103 may be a PMOS transistor with enhanced current resistance. The gate of the power transistor M103 is connected to the inverter X106, the source is connected to the other end of the capacitive element C101 via terminal BS, and the drain is connected to the power supply V101 via terminal VDD. Depending on the required current resistance, the power transistor M103 has a gate width that is large compared to the gate length, resulting in a relatively large circuit area.

[0031] As described above, the power supply circuit X105 is constructed using three power transistors M101 to M103.

[0032] The processing circuit X110 receives the PWM signals PWMP0 and PWMN0 converted by the PWM modulation circuit X103, generates gate signals GATEP and GATEN corresponding to the PWM signals PWMP0 and PWMN0, and supplies them to the amplification circuit X104.

[0033] The processing circuit X110 includes inverters X107 and X108. Inverter X107 has its input node connected to PWM modulation circuit X103 via line PWMP0 and terminal PWMP0, and its output node connected to amplifier circuit X104. Inverter X108 has its input node connected to PWM modulation circuit X103 via line PWMN0 and terminal PWMN0, and its output node connected to amplifier circuit X104.

[0034] The amplifier circuit X104 receives gate signals GATEP and GATEN. The amplifier circuit X104 can perform switching operations according to the gate signals GATEP and GATEN using the power supply voltage received from the power supply circuit X105.

[0035] For example, during the period TP1 described above, the amplifier circuit X104 performs switching operations according to the gate signals GATEP and GATEN using the power supply voltage Vs1. During the period TP2 described above, the amplifier circuit X104 performs switching operations according to the gate signals GATEP and GATEN using the power supply voltage Vs2.

[0036] The amplification circuit X104 has a driver (second driver) 20 and a driver (third driver) 30. The amplification circuit X104 constitutes a BTL drive circuit, with driver 20 acting as the P-side driver and driver 30 acting as the N-side driver.

[0037] The driver 20 has an input node 21 connected to the processing circuit X110, a power supply node 22 connected to the other end of the capacitive element C101 via the power supply circuit X105 and terminal BS, a reference node 23 connected to a reference potential (e.g., ground potential), and an output node 24 connected to the filter X102 via terminal OUTP (first output terminal).

[0038] The driver 20 includes power transistors M104 (the fourth power transistor) and M105 (the fifth power transistor). Power transistor M104 may be a PMOS transistor with enhanced current resistance. The gate of power transistor M104 is connected to the processing circuit X110, the source is connected to the power supply circuit X105 and the other end of the capacitive element C101 via terminal BS, and the drain is connected to power transistor M105 and also to filter X102 via terminal OUTP. Depending on the required current resistance, power transistor M104 has a gate width that is large compared to its gate length, resulting in a relatively large circuit area.

[0039] The power transistor M105 may be an NMOS transistor with enhanced current resistance. The gate of power transistor M105 is connected to the processing circuit X110, the source is connected to a reference potential (e.g., ground potential), and the drain is connected to power transistor M104 and also to filter X102 via terminal OUTP. Depending on the required current resistance, power transistor M105 has a gate width that is large compared to its gate length, resulting in a relatively large circuit area.

[0040] The driver 30 has an input node 31 connected to the processing circuit X110, a power supply node 32 connected to the other end of the capacitive element C101 via the power supply circuit X105 and terminal BS, a reference node 33 connected to a reference potential (e.g., ground potential), and an output node 34 connected to the filter X102 via terminal OUTN (second output terminal).

[0041] The driver 30 includes power transistors M106 (sixth power transistor) and M107 (seventh power transistor). Power transistor M106 may be a PMOS transistor with enhanced current resistance. The gate of power transistor M106 is connected to the processing circuit X110, the source is connected to the other end of the capacitive element C101 via the power supply circuit X105 and terminal BS, and the drain is connected to power transistor M107 and also to filter X102 via terminal OUTN. Depending on the required current resistance, power transistor M106 has a gate width that is large compared to its gate length, resulting in a relatively large circuit area.

[0042] The power transistor M107 may be an NMOS transistor with enhanced current resistance. The gate of power transistor M107 is connected to the processing circuit X110, the source is connected to a reference potential (e.g., ground potential), and the drain is connected to power transistor M106 and also to filter X102 via terminal OUTN. Depending on the required current resistance, power transistor M107 has a gate width that is large relative to its gate length, resulting in a relatively large circuit area.

[0043] The amplifier circuit X104 is composed of four power transistors M104 to M107. That is, the semiconductor device X101 is composed of seven power transistors M101 to M107. Each of the power transistors M101 to M107 has a relatively large circuit area, but in the semiconductor device X101, the number of power transistors can be suppressed to seven.

[0044] Next, the operation of the semiconductor device X101 will be described using FIG. 2. FIG. 2 is a waveform diagram showing the operation of the semiconductor device X101.

[0045] In the period TP11, in response to both the PWM signal PWMP1 and the PWM signal PWMN1 being maintained at the L level, the processing circuit X111 maintains the gate signal GATEBS at the H level.

[0046] In the power supply circuit X105, since the power transistor M101 is maintained in the off state and the power transistor M102 is maintained in the on state, one end of the capacitor element C101 is set to the ground potential (the first potential) via the terminal CFL. Also, since the power transistor M103 is maintained in the on state, the power supply voltage V received at the terminal VDD DD is applied to the other end of the capacitor element C101 via the terminal BS, and the capacitor element C101 is charged with the voltage V DD At the same time, the power supply voltage V received at the terminal VDD DD (the first power supply voltage) is supplied to the amplifier circuit X104.

[0047] On the other hand, the processing circuit X110 logically inverts the PWM signals PWMP0 and PWMN0 respectively to generate the gate signals GATEP (the first signal) and GATEN (the second signal).

[0048] In the amplifier circuit X104, in response to the power supply voltage V DD being supplied from the power supply circuit X105, the drivers 20 and 30 respectively use the ground potential as the L level and the power supply potential V DDThis is used. As a result, drivers 20 and 30 logically invert the gate signals GATEP and GATEN, respectively, to determine the ground potential and the power supply potential V DD Generate signals OUTP and OUTN that transition between these two states.

[0049] Accordingly, the difference signals OUTP-OUTN generated by filter X102 are the ground potential and the power supply potential V. DD This signal transitions between [this state] and [that state].

[0050] During period TP12, in accordance with the PWM signal PWMP1 being maintained at a high level, the processing circuit X111 maintains the gate signal GATEBS at a low level.

[0051] In the power supply circuit X105, power transistor M101 is kept ON and power transistor M102 is kept OFF, so one end of the capacitive element C101 is at a potential V via terminal CFL. DD It is set to (the second potential). Also, power transistor M103 is kept in the off state. Capacitor element C101 is set to voltage V DD Since it maintains this, the other end of the capacitive element C101 has a potential of 2V. DD It is set to 2V. DD The (second power supply voltage) is supplied to the amplification circuit X104, and the voltage across the capacitive element C101 is discharged.

[0052] On the other hand, in response to the PWM signal PWMP0 being maintained at a high level, the processing circuit X110 maintains the gate signal GATEP at a low level. In response to the PWM signal PWMN0 being maintained at a low level, the processing circuit X110 maintains the gate signal GATEP at a high level.

[0053] In the amplification circuit X104, the power supply voltage is 2V from the power supply circuit X105. DD Depending on the power supplied, drivers 20 and 30 use the ground potential as the low level and the power supply potential of 2V as the high level, respectively. DDThis is used. As a result, drivers 20 and 30 logically invert the gate signals GATEP and GATEN, respectively, to a potential of 2V. DD It generates the signal OUTP and the ground potential signal OUTN.

[0054] Accordingly, the difference signal OUTP-OUTN generated by filter X102 has a potential of 2V. DD This will be the signal.

[0055] During period TP13, in response to both PWM signals PWMP1 and PWMN1 being maintained at a low level, the processing circuit X111 maintains the gate signal GATEBS at a high level.

[0056] In the power supply circuit X105, power transistor M101 is kept in the off state and power transistor M102 is kept in the on state, so one end of the capacitive element C101 is set to ground potential via terminal CFL. Also, since power transistor M103 is kept in the on state, the power supply voltage V received at terminal VDD is set to ground potential. DD A voltage V is applied to the other end of the capacitive element C101 via terminal BS, and the voltage V is applied to the capacitive element C101. DD The battery is charged. At the same time, the power supply voltage V received at terminal VDD is charged. DD This is supplied to the amplification circuit X104.

[0057] On the other hand, in response to the PWM signal PWMP0 being maintained at a high level, the processing circuit X110 maintains the gate signal GATEP at a low level. In response to the PWM signal PWMN0 being maintained at a low level, the processing circuit X110 maintains the gate signal GATEN at a high level.

[0058] In the amplification circuit X104, the power supply voltage V is supplied from the power supply circuit X105. DD In response to the supply, drivers 20 and 30 use the ground potential as the L level and the power supply potential V as the H level, respectively. DD This is used. As a result, drivers 20 and 30 logically invert the gate signals GATEP and GATEN, respectively, to the power supply potential V DDIt generates the signal OUTP and the ground potential signal OUTN.

[0059] Accordingly, the difference signal OUTP-OUTN generated by filter X102 is at potential V DD This will be the signal.

[0060] Looking at periods TP11, TP12, and TP13, the difference signal OUTP-OUTN is ground potential → potential V DD →2V DD → Potential V DD It changes in three levels. During period TP14, the same operation as period TP12 is performed; during period TP15, the same operation as period TP13 is performed; during period TP16, the same operation as period TP12 is performed; and during period TP17, the same operation as period TP11 is performed. That is, during periods TP11 to TP17, the difference signal OUTP-OUTN is ground potential ⇔ "V DD 」⇔「2V DD The transition range is kept at 1 level while changing between 3 levels.

[0061] During the period TP21-TP27, compared to the period TP11-TP17, the waveform patterns of PWM signal PWMP1 and PWM signal PWMN1 are swapped, and the waveform patterns of PWM signal PWMP0 and PWMN0 are swapped. Accordingly, the operation of the P-side driver 20 and the N-side driver 30 in the amplification circuit X104 are swapped, and the waveform pattern of the output signal OUTP of driver 20 and the waveform pattern of the output signal OUTN of driver 30 are swapped.

[0062] As a result, in the period TP21-TP27, the difference signal OUTP-OUTN has a waveform pattern with reversed polarity compared to the period TP11-TP17. That is, in the period TP11-TP17, the difference signal OUTP-OUTN is at ground potential ⇔ -V DD 」⇔「-2V DD The transition range is kept at 1 level while changing between 3 levels.

[0063] Looking at this over a period corresponding to one cycle, TP11~TP27, the difference signal OUTP-OUTN is "2V DD 」⇔「V DD "⇔Ground potential⇔"-V DD 」⇔「-2V DD The transition range is kept at 1 level while changing between 5 levels.

[0064] In other words, it can be seen that the semiconductor device X101 is able to achieve multi-level (in this case, 5 levels) Class D amplification while suppressing the transition level width to 1 level or the like. Accordingly, the waveform pattern of the smoothed signal "OUTP-OUTN after LPF" that is smoothed by the filter X102 can be made to be close to a sine wave, and appropriate sound can be output from the speaker SP according to the smoothed signal.

[0065] Note that the capacitive element C101 is charged when the gate signal GATEBS is at a high level and terminal BS is at a potential of V. DD This occurs during the period (the first period). Discharge of the capacitive element C101 occurs when the gate signal GATEBS is at a low level and terminal BS is at a potential of 2V. DD It takes place during the period (the second period).

[0066] Here, assuming that the power supply circuit X905 is of the charge pump type, the semiconductor device X901 is configured as shown in Figure 9. Figure 9 is a circuit diagram showing the configuration of the semiconductor device X901 including the charge pump type power supply circuit X905.

[0067] In semiconductor device X901, when the amplification circuit X904 performs 5-level Class D amplification, two types of power supply voltages are used. To generate these two types of power supply voltages, power supply V901 and two capacitive elements C901 and C902 are externally connected to power supply circuit X905. A voltage Vs1 (for example, V) is applied to the capacitive element C901. DD To charge and discharge the capacitor, power transistors M901 and M902 are connected between power supply V901 and one end of capacitive element C901. The voltage of capacitive element C901 is used to supply voltage Vs2 (for example, 2V) to capacitive element C902.DD To charge and discharge the capacitors, power transistors M903 and M904 are connected between capacitive element C901 and capacitive element C902.

[0068] In other words, the power supply circuit X905 is constructed using four power transistors M901 to M904.

[0069] In the amplifier circuit X904, for the P side, power transistors M905 and M907 are connected between the power supply V901 and power transistor M904 and terminal OUTP in order to use voltage Vs1 in accordance with PWM signals PWMP1 and PWMP0. Power transistor M906 is connected between the capacitive element C902 and terminal OUTP in order to use voltage Vs2 in accordance with PWM signal PWMP1. Power transistor M908 is connected between the ground potential and terminal OUTP in order to use the ground voltage in accordance with PWM signal PWMP0.

[0070] In the amplifier circuit X904, for the N side, power transistors M909 and M911 are connected between the power supply V901 and power transistor M904 and terminal OUTN in order to use voltage Vs1 in response to PWM signals PWMN1 and PWMN0. Power transistor M910 is connected between the capacitive element C902 and terminal OUTN in order to use voltage Vs2 in response to PWM signal PWMN1. Power transistor M912 is connected between the ground potential and terminal OUTN in order to use the ground voltage in response to PWM signal PWMN0.

[0071] In other words, the amplification circuit X904 is composed of eight power transistors M905 to M912. Therefore, the semiconductor device X901 is composed of twelve power transistors M901 to M912. Each power transistor M901 to M912 is configured with a gate width that is larger than its gate length, depending on the required current withstand capability, resulting in a relatively large circuit area. A large number of power transistors in the semiconductor device X901 increases the circuit area of ​​the semiconductor device X901, which tends to increase the cost of the semiconductor device X901.

[0072] In contrast, in the first embodiment, the power supply circuit X105 in the semiconductor device X101 is of the bootstrap type. This allows one capacitive element C101 to be used as a capacitive element for generating two types of voltages Vs1 and Vs2, reducing the number of power transistors required to charge and discharge the capacitive element C101, and reducing the number of power transistors required to switch the power supply voltage used for amplification. As a result, the number of power transistors used in the configuration of the semiconductor device X101 can be reduced (for example, from 12 to 7) compared to the configuration in Figure 9. Therefore, the circuit area of ​​the semiconductor device X101 can be reduced, and the cost of the semiconductor device X101 can be reduced.

[0073] Furthermore, in the first embodiment, in the semiconductor device X101, one capacitive element C101 can be used as a capacitive element for generating two types of voltages Vs1 and Vs2, thus reducing the number of capacitive elements required for power generation. Consequently, the cost of operating the semiconductor device X101 as a Class D amplifier circuit can be reduced.

[0074] Furthermore, in the semiconductor device X101 of the first embodiment, a BTL drive configuration is used, and multi-level (5-level) Class D amplification is performed while maintaining a transition width of 1 level between terminals OUTP and OUTN. This makes it possible to suppress radiated noise (EMI noise) while performing high-output and high-efficiency Class D amplification.

[0075] (Second embodiment) Next, a semiconductor device X101a according to the second embodiment will be described. The following description will focus on the differences from the first embodiment.

[0076] In the second embodiment, an example is given of the configuration of the semiconductor device X101a in which the logic of the PWM signal received from the PWM modulation circuit X103a is inverted compared to the first embodiment.

[0077] The semiconductor device X101a is configured as shown in Figure 3. Figure 3 is a circuit diagram showing the configuration of the semiconductor device X101a according to the second embodiment.

[0078] The semiconductor device X101a differs in the configuration of the processing circuit 111a, and the processing circuit X110 (see Figure 1) is omitted.

[0079] The processing circuit X111a receives and processes the PWM signals PWMP1a and PWMN1a converted by the PWM modulation circuit X103a, and generates a gate signal GATEBS corresponding to the PWM signals PWMP1a and PWMN1a. As shown in Figure 4, the logic of the PWM signals PWMP1a and PWMN1a is inverted compared to the PWM signals PWMP1 and PWMN1 of the first embodiment (see Figure 2), but the gate signal GATEBS is the same as in the first embodiment. Figure 4 is a waveform diagram showing the operation of the semiconductor device X101a.

[0080] The processing circuit X111a includes an AND gate X301 instead of a NOR gate X109 (see Figure 1).

[0081] The AND gate X301 has a first input node connected to the PWM modulation circuit X103a via line PWMP1a and terminal PWMP1a, a second input node connected to the PWM modulation circuit X103a via line PWMN1a and terminal PWMN1a, and an output node connected to the power supply circuit X105 via line GATEBS. The AND gate X301 calculates the logical AND of the PWM signal PWMP1a and the PWM signal PWMN1a, and supplies the result of the calculation as the gate signal GATEBS to the power supply circuit X105.

[0082] As shown in Figure 4, the PWM signals PWMP0a and PWMN0a have their logic inverted from the PWM signals PWMP1 and PWMN1 of the first embodiment (see Figure 2), and can be used directly as gate signals GATEP and GATEN. Consequently, inverters X107 and X108 (see Figure 1) become unnecessary, and the processing circuit X110 is omitted.

[0083] As shown in Figure 4, signals other than the PWM signals PWMP1a, PWMN1a, PWMP0a, and PWMN0a are the same as in the first embodiment, and the operation of the semiconductor device X101a is substantially the same as in the first embodiment.

[0084] As described above, in the second embodiment, the processing circuit 110 is omitted in the semiconductor device X101a. Therefore, the circuit area of ​​the semiconductor device X101a can be further reduced, and the cost of the semiconductor device X101a can be further reduced.

[0085] (Third embodiment) Next, a semiconductor device X101b according to the third embodiment will be described. The following description will focus on the differences from the first and second embodiments.

[0086] In the first embodiment, the charging period (first period) during which the capacitive element C101 is charged is the period during which the gate signal GATEBS is at a high level. The discharge period (second period) during which the capacitive element C101 is discharged is the period during which the gate signal GATEBS is at a low level. Furthermore, during the charging period, the terminal BS is at a potential Vs1 (for example, V DD ) is the period during which the power supply potential Vs1 is output from the power supply circuit X105 to the amplification circuit X104. The discharge period is when terminal BS is at potential Vs2 (for example, 2V DD This is the period during which the power supply potential Vs2 (>Vs1) is output from the power supply circuit X105 to the amplification circuit X104.

[0087] In Figure 2, the charging period corresponds to TP11, TP13, TP15, and TP17 when the PWM signal PWMP1 is at a low level, and to TP21, TP23, TP25, and TP27 when the PWM signal PWMN1 is at a low level. The discharging period corresponds to TP12, TP14, and TP16 when the PWM signal PWMP1 is at a high level, and to TP22, TP24, and TP26 when the PWM signal PWMN1 is at a high level.

[0088] The ratio of the discharge period to the sum of the charging and discharging periods will be called the duty cycle. The PWM signals PWMP1 and PWMN1 have their H-level pulse width modulated by the PWM modulation circuit X103 according to the absolute amplitude of the audio signal. For this reason, in the periods TP13-TP16 and TP23-TP26, which correspond to phases with large absolute amplitudes, the H-level pulse width of the PWM signals PWMP1 and PWMN1 becomes relatively large, and the duty cycle tends to be large. For example, the following equations 1 to 4 hold true for the duty cycles of the periods TP11-TP16 and TP21-TP26. TP14 / (TP13+TP14)>TP12 / (TP11+TP12)···Formula 1 TP16 / (TP15+TP16)>TP12 / (TP11+TP12)···Equation 2 TP24 / (TP23+TP24)>TP22 / (TP21+TP22)···Equation 3 TP26 / (TP25+TP26)>TP22 / (TP21+TP22)···Equation 4

[0089] In other words, near the period corresponding to a phase with a large absolute amplitude of the audio signal before PWM conversion, the ratio of the discharge period to the sum of the charging and discharging periods tends to be large. As a result, the charge to the capacitive element C101 may become insufficient, and if the power supply voltage supplied from the power supply circuit X105 to the amplification circuit X104 decreases, the output signal level of the semiconductor device X101 may deteriorate.

[0090] Therefore, in the third embodiment, as shown in Figure 5, a limiting circuit X112b is added to the semiconductor device X101b, and a pulse source V303b is additionally connected to the semiconductor device X101b.

[0091] The limiting circuit X112b is connected between the processing circuit X111 and the power supply circuit X105, and is connected to the pulse source V303b via the terminal MAXDUTY. The limiting circuit X112b uses the pulse MAXDUTY from the pulse source V303b to adjust the gate signal GATEBS to limit the duty cycle, which is the ratio of the discharge period to the sum of the charge and discharge periods. In other words, the limiting circuit X112b adjusts the gate signal GATEBS to limit the ratio of the off period to the sum of the on and off periods of the switch 40. To put it another way, the limiting circuit X112b adjusts the gate signal GATEBS to limit the ratio of the off period to the sum of the on and off periods of the power transistor M103. This ensures that the charge period for the capacitive element C101 is maintained and that the capacitive element C101 is fully charged.

[0092] The limiting circuit X112b includes an OR gate X510b. The OR gate X510b has a first input node connected to the pulse source V303b via line MAXDUTY and terminal MAXDUTY, a second input node connected to the output node of the NOR gate X109, and the output node connected to the power supply circuit X105 via line GATEBS. The OR gate X510b calculates the logical OR of the signal obtained by logically inverting the pulse MAXDUTY from the pulse source V303b and the output signal of the NOR gate X109, and supplies the result of the calculation as the gate signal GATEBS to the power supply circuit X105.

[0093] As shown in Figure 6, the pulse source V303b generates a pulse MAXDUTY with a pulse width PWmax corresponding to the upper limit of the duty cycle and supplies it to the OR gate X510b. Figure 6 is a waveform diagram showing the operation of the semiconductor device X101b. The OR gate X510b calculates the logical OR of the signal obtained by logically inverting the pulse MAXDUTY and the output signal of the NOR gate X109 (gate signal GATEBS in Figure 2), and supplies the calculation result as the gate signal GATEBS to the power supply circuit X105.

[0094] As shown in FIG. 6, the OR gate X510b of the limiting circuit X112b supplies the signal from the processing circuit X111 as it is to the power supply circuit X105 as the gate signal GATEBS if the pulse width of the L-level pulse from the processing circuit X111 is less than or equal to the pulse width PWmax. If the pulse width of the L-level pulse from the processing circuit X111 exceeds the pulse width PWmax, the OR gate X510b of the limiting circuit X112b adjusts the pulse width of the L-level pulse to the pulse width PWmax and supplies the adjusted signal to the power supply circuit X105 as the gate signal GATEBS.

[0095] For example, during the period TP14, an L-level pulse (gate signal GATEBS in FIG. 2) from the processing circuit X111 is output with a pulse width exceeding the pulse width PWmax, but the limiting circuit X112b adjusts the pulse width to PWmax. As a result, the L-level period of the gate signal GATEBS is shortened to TP14b (<TP14), and the H-level periods are extended to TP13b (>TP13) and TP15b (>TP15), respectively.

[0096] Similarly, during the period TP24, an L-level pulse (gate signal GATEBS in FIG. 2) from the processing circuit X111 is output with a pulse width exceeding the pulse width PWmax, but the limiting circuit X112b adjusts the pulse width to PWmax. As a result, the L-level period of the gate signal GATEBS is shortened to TP24b (<TP24), and the H-level periods are extended to TP23b (>TP23) and TP25b (>TP25), respectively.

[0097] Regarding the duty ratios of the periods TP14b to TP16 and TP24b to TP26, they can be made smaller than those in the first embodiment as shown in the following mathematical formulas 5 to 8. TP14b / (TP13b + TP14b) < TP14 / (TP13 + TP14) ··· Mathematical formula 5 TP16 / (TP15b + TP16) < TP16 / (TP15 + TP16) ··· Mathematical formula 6 TP24b / (TP23b + TP24b) < TP24 / (TP23 + TP24) ··· Mathematical formula 7 TP26 / (TP25b + TP26) < TP26 / (TP25 + TP26) ··· Equation 8

[0098] That is, the ratio of the discharge period to the total of the charge period and the discharge period can be reduced. Thereby, it is possible to adjust so that the charging of the capacitive element C101 becomes sufficient.

[0099] As described above, in the third embodiment, in the semiconductor device X101b, the duty ratio, which is the ratio of the discharge period to the total of the charge period and the discharge period, is limited by the limiting circuit X112b. Thereby, it is possible to make the charging of the capacitive element C101 sufficient, suppress a decrease in the power supply voltage supplied from the power supply circuit X105 to the amplifier circuit X104, and suppress deterioration of the output signal level of the semiconductor device X101b.

[0100] (Fourth Embodiment) Next, the semiconductor device X101c according to the fourth embodiment will be described. Hereinafter, the description will focus on the parts different from the first to third embodiments.

[0101] In the fourth embodiment, as a configuration of the semiconductor device X101c, a configuration in which the logic of the PWM signal received from the PWM modulation circuit X103a is inverted compared to the third embodiment is exemplified.

[0102] The semiconductor device X101c is configured as shown in FIG. 7. FIG. 7 is a circuit diagram showing the configuration of the semiconductor device X101c according to the fourth embodiment.

[0103] The semiconductor device X101c has a different configuration of the processing circuit 111a, and the processing circuit X110 (see FIG. 5) is omitted.

[0104] The processing circuit X111a receives and processes the PWM signals PWMP1a and PWMN1a converted by the PWM modulation circuit X103a, and generates a gate signal GATEBS corresponding to the PWM signals PWMP1a and PWMN1a. As shown in Figure 8, the logic of the PWM signals PWMP1a and PWMN1a is inverted compared to the PWM signals PWMP1 and PWMN1 of the third embodiment (see Figure 6), but the gate signal GATEBS is the same as in the third embodiment. Figure 8 is a waveform diagram showing the operation of the semiconductor device X101c.

[0105] The processing circuit X111a includes an AND gate X301 instead of a NOR gate X109 (see Figure 5).

[0106] The AND gate X301 has a first input node connected to the PWM modulation circuit X103a via line PWMP1a and terminal PWMP1a, a second input node connected to the PWM modulation circuit X103a via line PWMN1a and terminal PWMN1a, and an output node connected to the power supply circuit X105 via line GATEBS. The AND gate X301 calculates the logical AND of the PWM signal PWMP1a and the PWM signal PWMN1a, and supplies the result of the calculation as the gate signal GATEBS to the power supply circuit X105.

[0107] As shown in Figure 8, the PWM signals PWMP0a and PWMN0a have their logic inverted from the PWM signals PWMP1 and PWMN1 of the third embodiment (see Figure 6), and can be used directly as gate signals GATEP and GATEN. Consequently, inverters X107 and X108 (see Figure 5) become unnecessary, and the processing circuit X110 is omitted.

[0108] As shown in Figure 8, signals other than the PWM signals PWMP1a, PWMN1a, PWMP0a, and PWMN0a are the same as in the third embodiment, and the operation of the semiconductor device X101c is substantially the same as in the third embodiment.

[0109] As described above, in the fourth embodiment, the processing circuit 110 is omitted in the semiconductor device X101c. Therefore, the circuit area of ​​the semiconductor device X101c can be further reduced, and the cost of the semiconductor device X101c can be further reduced.

[0110] Although embodiments of the present invention have been described above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. The novel embodiments described above can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0111] 10, 20, 30 drivers 40 switches M101~M107, M901~M912 Power Transistors X101, X101a, X101b, X101c, X901 Semiconductor Equipment X104 Amplifier Circuit X105 power circuit X110, X111, X111a processing circuits X112b limiting circuit

Claims

1. A power transistor comprising: a capacitive element; a first power transistor of a first conductivity type having a gate that receives a first control signal, a source connected to the power supply potential, and a drain connected to one end of the capacitive element; a second power transistor of a second conductivity type having a gate that receives the first control signal, a source connected to a reference potential, and a drain connected to the first power transistor and one end of the capacitive element; and a third power transistor of the first conductivity type having a gate that receives a second control signal which is the logical inversion of the first control signal, a source connected to the other end of the capacitive element, and a drain connected to the power supply potential, wherein during a charging period in which the first control signal is maintained at a first level and the second control signal is maintained at a second level which is the logical inversion of the first level, one end of the capacitive element is connected to the first power transistor A power supply circuit that, while disconnecting the capacitive element from the power supply potential by a second power transistor and connecting the other end of the capacitive element to the power supply potential via a third power transistor, charges the capacitive element and outputs a first power supply voltage from the other end of the capacitive element, maintains the first control signal at the second level and during the discharge period in which the second control signal is maintained at the first level, disconnects one end of the capacitive element from the reference potential by a second power transistor and connects the other end of the capacitive element to the power supply potential via a first power transistor and disconnects the other end of the capacitive element from the power supply potential by a third power transistor, discharges the capacitive element and outputs a second power supply voltage higher than the first power supply voltage from the other end of the capacitive element, An amplification circuit that receives a pulse-width modulated signal, performs a switching operation corresponding to the signal using the first power supply voltage output from the other end of the capacitive element during the charging period, and performs a switching operation corresponding to the signal using the second power supply voltage output from the other end of the capacitive element during the discharge period, A semiconductor device equipped with the following features.

2. The aforementioned amplification circuit is A first driver having an input node for receiving a first signal, a power supply node connected to the other end of the capacitive element, a reference node connected to a reference potential, and an output node, A second driver having an input node for receiving a second signal, a power supply node connected to the other end of the capacitive element, a reference node connected to a reference potential, and an output node, has The semiconductor device according to claim 1.

3. The first driver described above is A fourth power transistor, the source of which is connected to the other end of the capacitive element and the drain of which is connected to the first output terminal, A fifth power transistor whose source is connected to the reference potential and whose drain is connected to the fourth power transistor and the first output terminal, It has, The second driver described above is A sixth power transistor, the source of which is connected to the other end of the capacitive element and the drain of which is connected to the second output terminal, A seventh power transistor whose source is connected to the reference potential and whose drain is connected to the sixth power transistor and the second output terminal, has The semiconductor device according to claim 2.

4. The device further comprises a limiting circuit that limits the ratio of the discharge period to the sum of the charging period and the discharge period by adjusting the first control signal to limit the ratio of the time spent at the second level to the sum of the time spent at the first level and the time spent at the second level. The semiconductor device according to claim 1.

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