Push-pull output circuit

Abstract

To provide a push-pull output circuit capable of suppressing increase in the number of components and complication of wiring, and of preventing a transistor from being in saturated with certainty.SOLUTION: A push-pull output circuit 10 comprises: a diode-connected bipolar transistor Q1 that configures a current mirror circuit; a bipolar transistor Q2 whose base terminal is connected with a base terminal of the bipolar transistor Q1; a constant current source Io; a diode D4 whose anode terminal is connected with a collector terminal of the bipolar transistor Q1 and whose cathode terminal is connected with the constant current source; and a lateral bipolar transistor Q3 whose base terminal is commonly connected with the base terminal of the bipolar transistor Q1 and the base terminal of the bipolar transistor Q2, one of whose emitter and collector terminals is connected with the cathode terminal of the diode, and the other of whose emitter and collector terminals is connected with a collector terminal of the bipolar transistor Q2.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a push - pull output circuit.

Background Art

[0002] FIG. 8 is a configuration explanatory diagram of an example of a conventional push - pull output circuit. In the conventional push - pull output circuit shown in FIG. 8, when the collector current of the NPN transistor Q5 stops due to a change in the voltage of the input terminal IN, the base potential of the NPN transistor Q3 rises, and the collector - emitter voltage of the PNP transistor Q2 decreases. The PNP transistor Q2 enters a saturation state, and the parasitic elements of the PNP transistor Q2 operate, which may cause the circuit to perform an unintended operation.

[0003] FIG. 9 is a configuration explanatory diagram of another example of a conventional push - pull output circuit. To avoid this, in the push - pull output circuit of FIG. 9, when the collector current of the NPN transistor Q5 stops and the base potential of the NPN transistor Q3 rises, and the collector - emitter voltage of the PNP transistor Q2 becomes less than or equal to a predetermined voltage, the base - emitter voltage of the PNP transistor Q6 increases, and a current flows through the collector to prevent the PNP transistor Q2 from entering a saturation state.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the circuit in Figure 9, compared to the push-pull output circuit in Figure 8, requires diodes D3-D5 and PNP transistor Q6, resulting in increased circuit area and more complex circuit wiring, which presents new challenges. This new challenge had a significant impact, especially in processes with a small number of wiring layers, making implementation difficult. Therefore, the present invention aims to provide a push-pull output circuit that can reliably prevent transistors from reaching a saturated state while suppressing an increase in the number of components and the complexity of wiring. [Means for solving the problem]

[0006] The push-pull output circuit of the embodiment includes a first bipolar transistor connected by diodes to constitute a current mirror circuit, a second bipolar transistor which constitutes a current mirror circuit and whose base terminal is connected to the base terminal of the first bipolar transistor, a constant current source which constitutes a current mirror circuit, a diode whose anode terminal is connected to the collector terminal of the first bipolar transistor and whose cathode terminal is connected to the constant current source, and a third bipolar transistor which is configured as a lateral bipolar transistor and whose base terminal is commonly connected to the base terminals of the first bipolar transistor and the second bipolar transistor, whose emitter terminal and collector terminal are connected to the cathode terminal of the diode, and whose other emitter terminal and collector terminal are connected to the collector terminal of the second bipolar transistor, The circuit comprises a first NPN transistor and a first PNP transistor that constitute a complementary push-pull output stage, the emitter terminals of the first NPN transistor and the first PNP transistor are connected to the output terminal OUT, the collector terminal of the second bipolar transistor and either the emitter terminal or the collector terminal of the third bipolar transistor are commonly connected to the base terminal of the first NPN transistor, a first diode whose anode terminal is connected to the collector terminal of the second bipolar transistor, a second diode connected in series with the first diode and whose cathode terminal is connected to the base terminal of the first PNP transistor, and a third NPN transistor whose collector terminal is connected to the cathode terminal of the second diode, whose emitter terminal is connected to the low-potential side power supply (ground) GND, and whose base terminal is connected to the input terminal IN. It is equipped with. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is an explanatory diagram of the configuration of the push-pull output circuit of the first embodiment. [Figure 2] Figure 2 is a partial plan view of a semiconductor device that constitutes a push-pull output circuit according to the embodiment. [Figure 3] Figure 3 is an explanatory diagram of the operation of the embodiment. [Figure 4]Figure 4 is an explanatory diagram of the potential states of each terminal of the PNP transistor Q6. [Figure 5] Figure 5 is an explanatory diagram of an example of the simulation circuit configuration. [Figure 6] Figure 6 is an explanatory diagram illustrating the simulation results of the output terminal OUT voltage and the collector current of PNP transistor Q6 using the simulation circuit shown in Figure 5. [Figure 7] Figure 7 is an explanatory diagram of the configuration of the push-pull output circuit of the second embodiment. [Figure 8] Figure 8 is a diagram illustrating the configuration of an example of a conventional push-pull output circuit. [Figure 9] Figure 9 is a diagram illustrating the configuration of another example of a conventional push-pull output circuit. [Modes for carrying out the invention]

[0008] Next, embodiments will be described with reference to the drawings. [1] First Embodiment First, before giving a detailed description of the embodiment, we will explain the principle of the embodiment. Figure 1 is an explanatory diagram of the configuration of the push-pull output circuit of the first embodiment. The push-pull output circuit 10 of the first embodiment includes a PNP transistor Q1 (first bipolar transistor) whose emitter terminal is connected to a high-potential power supply Vcc and whose collector terminal and base terminal are connected to each other, a PNP transistor Q2 (second bipolar transistor) whose emitter terminal is connected to a high-potential power supply Vcc and whose base terminal is connected to the base terminal of PNP transistor Q1, a diode D4 whose anode terminal is connected to the collector terminal of PNP transistor Q1, and a constant current source Io whose one end is connected to the cathode terminal of diode D4 and whose other end is connected to a low-potential power supply (ground) GND.

[0009] As a result, PNP transistor Q1, PNP transistor Q2, and constant current source Io form a current mirror circuit.

[0010] The push-pull output circuit 10 also includes a PNP transistor Q6 (third bipolar transistor) whose base terminal is commonly connected to the base terminals of the PNP transistor Q1 and the PNP transistor Q2, whose emitter terminal is connected to the cathode terminal of the diode D3, and whose collector terminal is connected to the collector terminal of the PNP transistor Q2.

[0011] In this case, the PNP transistor Q1, the PNP transistor Q2, and the PNP transistor Q6 are configured as lateral PNP transistors and are configured as a composite lateral PNP transistor formed in the same epitaxial region.

[0012] Furthermore, the push-pull output circuit 10 includes an NPN transistor Q3 and a PNP transistor Q4 that constitute complementary push-pull output stages. The emitter terminals of the NPN transistor Q3 and the PNP transistor Q4 are connected to the output terminal OUT. The collector terminal of the PNP transistor Q2 and the collector terminal of the PNP transistor Q6 are commonly connected to the base terminal of the NPN transistor Q3.

[0013] The push-pull output circuit 10 also includes a diode D1 whose anode terminal is connected to the collector terminal of the PNP transistor Q2, a diode D2 connected in series with the diode D1 and whose cathode terminal is connected to the base terminal of the PNP transistor Q4, and an NPN transistor Q5 whose collector terminal is connected to the cathode terminal of the diode D2, whose emitter terminal is connected to the low-potential side power supply (ground) GND, and whose base terminal is connected to the input terminal IN.

[0014] FIG. 2 is a partial plan view of a semiconductor device constituting the push-pull output circuit of the embodiment. As shown in FIG. 2, the PNP transistor Q1, the PNP transistor Q2, and the PNP transistor Q6 are arranged adjacent to each other. In the example of FIG. 2, an example of the transistor size ratio between the PNP transistor Q1 and the PNP transistor Q2 is 1:3. Also, the collector terminal c6 of the PNP transistor Q6 and the collector terminal c2 of the PNP transistor Q2 are connected to each other by a substantially L-shaped wiring pattern P2-6 in FIG. 2. Also, the emitter terminal e2 of the PNP transistor Q2 and the emitter terminal e1 of the PNP transistor Q1 are connected to each other by a substantially triangular wiring pattern P2-1 in FIG. 2, and are further connected to the high-potential side power supply Vcc through this wiring pattern P2-1. Furthermore, the emitter terminal e6 of the PNP transistor Q6 is connected to the cathode terminal of the diode D4 through the wiring pattern P1-D4K. Also, the collector terminal c1 of the PNP transistor Q1 is connected to the anode terminal of the diode D4 through the wiring pattern P1-D4A.

[0015] Furthermore, since the base terminals of the PNP transistor Q1, the base terminal of the PNP transistor Q2, and the base terminal of the PNP transistor Q6 are common and formed in the same layer within the semiconductor device, there is no need to perform additional wiring. Further, as shown in FIG. 2, since the PNP transistor Q2 and the PNP transistor Q6 are arranged close to each other, the wiring length of the wiring pattern P2-6 can be shortened, and it is less affected by other wirings. The wiring pattern P2- is easily formed and can be connected to each other, and it is possible to manufacture a semiconductor device with a process having fewer wiring layers.

[0016] Furthermore, since the PNP transistor Q6 is configured as a lateral PNP transistor, the forward current amplification factor β F and the reverse current amplification factor β R are substantially equal. Therefore, even if the collector terminal c6 of the PNP transistor Q6 is connected to the collector terminal of the PNP transistor Q2 and the emitter terminal e6 of the PNP transistor Q6 is connected to the cathode terminal of the diode D4, as will be described later, the PNP transistor Q6 functions as a reverse transistor. Therefore, the same effect can be obtained while reducing the number of elements compared to the conventional example shown in FIG. 9.

[0017] Furthermore, since the lateral PNP transistor Q6 has a high reverse breakdown voltage between its base terminal and emitter terminal, even if the voltage at the collector terminal c2 of the PNP transistor Q2 fluctuates, no leakage current will occur between the collector terminal c6 and the emitter terminal e6.

[0018] Next, the operation of the embodiment will be described. First, let's explain the normal operation. In the initial state, the PNP transistor Q2 is assumed to be in an unsaturated state.

[0019] Since a constant current from the constant current source Io flows from the high-potential power supply Vcc to the diode D4 via the emitter and collector terminals of the PNP transistor Q1, a current corresponding to the transistor size ratio with PNP transistor Q1 also flows through the PNP transistor Q2.

[0020] At this time, when the voltage at the input terminal IN becomes "L" level, the NPN transistor Q5 turns off. Therefore, the base terminal of NPN transistor Q3 becomes "H" level, and NPN transistor Q3 turns on.

[0021] On the other hand, the base terminal of PNP transistor Q4 also becomes "H" level, and PNP transistor Q4 is in the off state, so the output of the output terminal OUT becomes "H" level and performs a push operation.

[0022] In contrast, when the voltage at the input terminal IN reaches a "H" level, the NPN transistor Q5 turns ON.

[0023] At this time, a constant current from the constant current source Io flows from the high-potential power supply Vcc to diode D4 via the emitter and collector terminals of PNP transistor Q1. Therefore, the same current flows through PNP transistor Q2 as the current flowing through PNP transistor Q1, but this current flows to the low-potential power supply (ground) GND via diodes D1, D2, and NPN transistor Q5.

[0024] Therefore, the base terminal of NPN transistor Q3 becomes "L" level, and NPN transistor Q3 is in the off state.

[0025] On the other hand, the base terminal of PNP transistor Q4 also becomes "L" level, so PNP transistor Q4 is in the off state, and the output of output terminal OUT becomes "L" level, resulting in a pull operation. In addition, while the push-pull operation was explained in the case where the voltage at input terminal IN is "H" or "L", it goes without saying that the signal input to input terminal IN can also be an analog signal.

[0026] Next, we will explain the operation when the PNP transistor Q2 reaches a saturation state. Figure 3 is an explanatory diagram of the operation of the embodiment. In the case of the conventional push-pull output circuit shown in Figure 8, if the collector current of NPN transistor Q5 stops due to a change in the voltage at the input terminal IN, the base potential of NPN transistor Q3 rises, and the collector-emitter voltage of PNP transistor Q2 decreases, causing transistor Q2 to reach a saturated state.

[0027] If transistor Q2 reached a saturated state, the parasitic elements associated with transistor Q2 could activate, potentially causing the circuit to behave unintended.

[0028] Figure 4 is an explanatory diagram of the potential states of each terminal of the PNP transistor Q6. In contrast, in the above configuration, the potential of the emitter terminal e6 of PNP transistor Q6 is, when the base terminal-emitter terminal potential of PNP transistor Q1 is Vbe(Q1) and the threshold voltage of diode D4 is Vd(D4), Vcc - (Vbe(Q1) + Vd(D4)) =Vcc-2·Vbe It is expressed as follows.

[0029] Also, the potential of base terminal b6 is, Vcc-Vbe(Q1) It is expressed as follows.

[0030] Therefore, as the potential between the collector terminal c2 and the emitter terminal e2 of PNP transistor Q2 becomes less than 0.6V, the potential at the collector terminal c6 of PNP transistor Q6 becomes higher than the potential at the base terminal b6.

[0031] Therefore, the PNP transistor Q6 functions as a reverse transistor, and as shown by the dashed arrow in Figure 3, the collector current of the PNP transistor Q2 flows into the constant current source Io through Q6.

[0032] As a result, the collector current of PNP transistor Q1 decreases by the amount of the collector current of PNP transistor Q2. Therefore, the collector current of PNP transistor Q2, which forms a current mirror circuit through feedback, also decreases, and PNP transistor Q2 does not reach a saturation state.

[0033] To confirm the above effects, we performed an operational simulation using a simulation circuit. Figure 5 is an explanatory diagram of an example of the simulation circuit configuration. Figure 6 is an explanatory diagram of the simulation results for the input voltage at the input terminal IN, the output voltage at the output terminal OUT, and the collector current (I1) of the PNP transistor Q6, as determined by the simulation circuit in Figure 5. When the PNP transistor Q2 reaches a saturation state and the voltage Vout output from the output terminal OUT becomes constant at the high potential side (saturation state) as shown in Figure 6, the collector-emitter voltage Vce(Q2) of the PNP transistor Q2 can be expressed by the following equation, where Vbe(Q3) is the base-emitter voltage of the NPN transistor Q3, and Vcesat is the collector-emitter saturation voltage of the PNP transistor Q2. Vce(Q2) = Vcc - (Vout + Vbe(Q3)) <Vcesat In this state, the collector current of PNP transistor Q6 increases, decreasing the collector current of PNP transistor Q1 (the reference current of the current mirror circuit). Consequently, the collector current of PNP transistor Q2 also decreases, preventing PNP transistor Q2 from reaching a saturation state.

[0034] [2] Second embodiment Figure 7 is an explanatory diagram of the configuration of the push-pull output circuit of the second embodiment. The push-pull output circuit in Figure 7 is an embodiment in which a Wilson current mirror circuit is configured as the current mirror circuit. The push-pull output circuit 10A of the second embodiment includes a PNP transistor Q1 whose emitter terminal is connected to a high-potential power supply Vcc, a PNP transistor Q7 (fourth bipolar transistor) whose emitter terminal is connected to a high-potential power supply Vcc and whose collector terminal and base terminal are connected to each other, a PNP transistor Q2 whose emitter terminal is connected to a high-potential power supply Vcc and whose base terminal is connected to the base terminals of PNP transistors Q1 and Q7, a PNP transistor Q8 (fifth bipolar transistor) whose base terminal is connected to the collector terminal of PNP transistor Q1 and whose emitter terminal is connected to the collector terminal of PNP transistor Q7, a current limiting resistor R whose one end is connected to the collector of PNP transistor Q8 and whose other end is connected to a low-potential power supply (ground) GND, and a constant current source Io whose one end is connected to the collector of PNP transistor Q1 and whose other end is connected to a low-potential power supply (ground) GND.

[0035] In the above configuration, PNP transistors Q1, Q2, Q7, Q8, and constant current source Io constitute a Wilson current mirror circuit.

[0036] The push-pull output circuit 10A also includes a PNP transistor Q6 whose base terminal is commonly connected to the base terminals of PNP transistors Q1, Q7, and Q2, whose emitter terminal is connected to the collector terminal of PNP transistor Q1 and the base terminal of PNP transistor Q8, and whose collector terminal is connected to the collector terminal of PNP transistor Q2.

[0037] In this case, PNP transistors Q1, Q7, Q2, and Q6 are configured as lateral PNP transistors and are formed as a composite lateral PNP transistor located in the same epitaxial region.

[0038] Furthermore, the push-pull output circuit 10A includes an NPN transistor Q3 and a PNP transistor Q4 that constitute a complementary push-pull output stage. The emitter terminals of the NPN transistor Q3 and the PNP transistor Q4 are connected to the output terminal OUT. Furthermore, the collector terminals of PNP transistor Q2 and PNP transistor Q6 are commonly connected to the base terminal of NPN transistor Q3.

[0039] The push-pull output circuit 10A also includes a diode D1 whose anode terminal is connected to the collector terminal of PNP transistor Q2, a diode D2 connected in series with diode D1 and whose cathode terminal is connected to the base terminal of PNP transistor Q4, and an NPN transistor Q5 whose collector terminal is connected to the cathode terminal of diode D2, whose emitter terminal is connected to the low-potential side power supply (ground) GND, and whose base terminal is connected to the input terminal IN.

[0040] In the above configuration, the current-limiting resistor R connected to the collector of the PNP transistor Q8 and the low-potential power supply (ground) GND is an example of an element that limits the current flowing through the PNP transistor Q8 by setting the voltage between the emitter terminal and collector terminal of the PNP transistor Q8 to a desired voltage value. A current-limiting element other than a resistor, such as a transistor, may also be provided. Alternatively, if it is not necessary to limit the current flowing through the PNP transistor Q8, the collector terminal of the PNP transistor Q8 may be connected to the low-potential power supply (ground) GND.

[0041] The operation of the main components of this second embodiment will be described below. In this second embodiment, the potential of the emitter terminal e6 of PNP transistor Q6 is, when the base terminal-emitter terminal potential of PNP transistor Q1 is Vbe(Q1) and the base terminal-emitter terminal voltage of PNP transistor Q8 is Vbe(Q8), Vcc - (Vbe(Q1) + Vbe(Q8)) =Vcc-2·Vbe It is expressed as follows.

[0042] Also, the potential of base terminal b6 is, Vcc-Vbe(Q1) It is expressed as follows.

[0043] Therefore, as the potential between the collector terminal c2 and the emitter terminal e2 of PNP transistor Q2 becomes less than 0.6V, the potential at the collector terminal c6 of PNP transistor Q6 becomes higher than the potential at the base terminal b6.

[0044] Therefore, similar to the first embodiment, the PNP transistor Q6 functions as a reverse transistor, and the collector current of the PNP transistor Q2 flows from the collector terminal to the emitter terminal of the PNP transistor Q6 and into the constant current source Io.

[0045] As a result, the collector current of PNP transistor Q1 decreases by the amount of the collector current of PNP transistor Q2. Therefore, the collector current of PNP transistor Q2, which forms a current mirror circuit through feedback, also decreases, and PNP transistor Q2 does not reach a saturation state.

[0046] As described above, according to each of the above embodiments, it is possible to reliably prevent the PNP transistor Q2 from reaching a saturation state while suppressing an increase in the number of components, and consequently, it is possible to prevent the parasitic elements of the PNP transistor Q2 from operating and causing the circuit to perform unintended operations. Furthermore, this design suppresses the increase in circuit area required to prevent the saturation state of the PNP transistor Q2, and also simplifies circuit wiring. Therefore, even in semiconductor devices manufactured using processes with a small number of wiring layers, it becomes possible to provide a push-pull output circuit that can suppress the saturation state of the PNP transistor Q2.

[0047] In the above explanation, PNP transistors Q1, Q2, and Q6 were configured as lateral transistors, but if at least PNP transistor Q6 is configured as a lateral transistor, the forward current amplification factor β F And the current amplification factor β in the opposite direction R Since the currents are nearly equal, the collector current of PNP transistor Q2 can be fed into the constant current source, which suppresses the saturation of PNP transistor Q2, suppresses the rise in the base potential of NPN transistor Q3, and suppresses the decrease in the collector-emitter voltage of PNP transistor Q2. As a result, the parasitic elements of PNP transistor Q2 will operate, preventing the circuit from performing unintended actions.

[0048] In the above explanation, the configuration was described using a composite lateral transistor, taking into consideration the circuit area and the number of wiring layers, but it is not limited to this configuration. It is also possible to prevent the PNP transistor Q2 from reaching a saturated state even when using a single transistor. Furthermore, although the explanation was given for the case of a PNP transistor, the same method can be applied by using an NPN transistor instead of a PNP transistor and an NPN transistor instead of a PNP transistor, and reversing the potential relationship.

[0049] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0050] 10, 10A push-pull output circuit D1~D4 Diodes I1 Collector current P1, P2 wiring pattern Q1 PNP transistor (lateral PNP transistor) Q2 PNP transistor (lateral PNP transistor) Q3 NPN transistor Q4 PNP transistor Q5 NPN transistor Q6 PNP transistor (lateral PNP transistor) Q7 PNP transistor Q8 PNP transistor b6 Base terminal c1, c2, c6 collector terminals e1, e2, e6 Emitter terminals IN input terminal Io constant current source OUT output terminal R is a current-limiting resistor. Vbe: Voltage between base terminal and emitter terminal Vcc High potential side power supply Vout voltage

Claims

1. A diode-connected first bipolar transistor constitutes a current mirror circuit, The current mirror circuit comprises a second bipolar transistor whose base terminal is connected to the base terminal of the first bipolar transistor, The constant current source constituting the current mirror circuit, A diode in which the collector terminal of the first bipolar transistor is connected to the anode terminal and the constant current source is connected to the cathode terminal, A third bipolar transistor is configured as a lateral bipolar transistor, with its base terminal being commonly connected to the base terminal of the first bipolar transistor and the base terminal of the second bipolar transistor, one of its emitter terminal and collector terminal being connected to the cathode terminal of the diode, and the other of its emitter terminal and collector terminal being connected to the collector terminal of the second bipolar transistor, It comprises a first NPN transistor and a first PNP transistor that constitute a complementary push-pull output stage, and the emitter terminals of the first NPN transistor and the first PNP transistor are connected to the output terminal OUT. The collector terminal of the second bipolar transistor and either the emitter terminal or the collector terminal of the third bipolar transistor are commonly connected to the base terminal of the first NPN transistor, and the anode terminal of the first diode is connected to the collector terminal of the second bipolar transistor. A second diode is connected in series with the first diode, and its cathode terminal is connected to the base terminal of the first PNP transistor, A third NPN transistor is provided, in which the collector terminal is connected to the cathode terminal of the second diode, the emitter terminal is connected to the low-potential side power supply (ground) GND, and the base terminal is connected to the input terminal IN. A push-pull output circuit equipped with a push-pull output circuit.

2. The first bipolar transistor and the second bipolar transistor are configured as lateral bipolar transistors. The push-pull output circuit according to claim 1.

3. The first bipolar transistor that constitutes the current mirror circuit, The current mirror circuit comprises a second bipolar transistor whose base terminal is connected to the base terminal of the first bipolar transistor, The constant current source constituting the current mirror circuit, A third bipolar transistor is configured as a lateral bipolar transistor, with its base terminal being commonly connected to the base terminal of the first bipolar transistor and the base terminal of the second bipolar transistor, and either its emitter terminal or collector terminal being connected to the collector terminal of the first bipolar transistor, and the other of its emitter terminal or collector terminal being connected to the collector terminal of the second bipolar transistor, The base terminal of the fourth bipolar transistor is connected in common to the base terminals of the first bipolar transistor and the second bipolar transistor, and the diode-connected fourth bipolar transistor, A fifth bipolar transistor is formed in which the emitter terminal is connected to the collector terminal of the fourth bipolar transistor and the base terminal is connected to the collector terminal of the first bipolar transistor, It comprises a first NPN transistor and a first PNP transistor that constitute a complementary push-pull output stage, and the emitter terminals of the first NPN transistor and the first PNP transistor are connected to the output terminal OUT. The collector terminal of the second bipolar transistor and either the emitter terminal or the collector terminal of the third bipolar transistor are commonly connected to the base terminal of the first NPN transistor, and the anode terminal of the first diode is connected to the collector terminal of the second bipolar transistor. A second diode is connected in series with the first diode, and its cathode terminal is connected to the base terminal of the first PNP transistor, A third NPN transistor is provided, in which the collector terminal is connected to the cathode terminal of the second diode, the emitter terminal is connected to the low-potential side power supply (ground) GND, and the base terminal is connected to the input terminal IN. A push-pull output circuit equipped with a push-pull output circuit.

4. The first bipolar transistor, the second bipolar transistor, and the fourth bipolar transistor are configured as lateral bipolar transistors. The push-pull output circuit according to claim 3.

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