Semiconductor integrated circuit equipment

Abstract

To provide a semiconductor integrated circuit device capable of achieving high specific accuracy in both unit capacitance and parasitic capacitance while suppressing antenna effects.SOLUTION: A semiconductor integrated circuit device of the embodiment is a semiconductor integrated circuit device in which a plurality of metal layers are stacked via an insulator layer and has a capacitive element, and a component comprising a current flow path including a current flow path to the capacitive element is arranged at a position rotationally symmetrical n (n:2 or more integers) times about a predetermined rotation axis perpendicular to a stacking direction of the metal layers.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor integrated circuit devices.

Background Art

[0002] In semiconductor integrated circuit devices, it is known that a higher ratio accuracy can be achieved for capacitances formed between metal wirings arranged in parallel or between wiring layers compared to other semiconductor integrated circuit devices. However, in integrated circuits that use capacitances that require particularly high ratio accuracy, such as switch capacitor circuits and capacitive D / A converters, due to the influence of unexpected parasitic capacitances such as inter-wiring parasitic capacitances depending on the layout when the capacitance is realized on the integrated circuit, the ratio accuracy deteriorates. Therefore, not only the actually laid-out capacitance but also a layout having ratio accuracy for parasitic capacitances (for example, wiring parasitic capacitances) is required. As a method for realizing a capacitance with high ratio accuracy, a method has been proposed in which a highly symmetric capacitance layout called a unit capacitance is used as a unit structure, and a plurality of unit capacitances are arranged in a common centroid manner so as to be regular and highly symmetric, and each capacitance layout is connected by a metal wiring.

[0003] In this case, the unit capacitance was surrounded by a metal shield biased at a constant potential in order to eliminate the influence of unexpected parasitic capacitances.

[0004] In addition, with the evolution of recent semiconductor integrated circuit processes, processes having many metal wiring layers have been realized, and it has also become an issue to realize a layout that solves a problem called the antenna effect. Here, the antenna effect is a phenomenon in which a long metal wiring is directly connected to an insulating thin film layer such as a MIM capacitance electrode or the gate of a MOSFET, and the insulating thin film is damaged by plasma etching during the manufacture of the integrated circuit.

[0005] For this reason, as a typical method for suppressing the antenna effect, a method of providing a metal bridge has been proposed.

Prior Art Documents

[0006] [Patent Document 1] Patent No. 5623618 [Patent Document 2] U.S. Patent Application Publication No. 2014 / 0049872 [Non-patent literature]

[0007] [Non-Patent Document 1] pp. 174-175 CMOS VLSI Circuit Design (Fundamentals) by West and Harris [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] Incidentally, in semiconductor integrated circuits, capacitance is generally realized by pairs of metal wiring with long peripheral lengths.

[0009] Therefore, when achieving high ratio accuracy by the capacitance ratio of multiple unit capacitances connected in parallel, there is a risk that the charge generated when multiple capacitance electrodes are manufactured by plasma etching may damage the insulating film of the MIM (Metal-Insulator-Metal) structure capacitance (hereinafter referred to as MIM capacitance) or the gate oxide film of the MOSFET connected to the electrodes of the MIM capacitance. For this reason, a capacitance layout that suppresses the antenna effect is desirable.

[0010] In addition, in order to achieve high specific accuracy in both unit capacitance and parasitic capacitance, a metal bridge structure that does not disrupt the high symmetry of the unit capacitance is desirable in order to cancel out the effects of the first-order gradient of the process, such as the thickness and dielectric constant of the insulating film between MIM capacitances, which affects the variation in unit capacitance values, as well as the thickness of the metal layer (metal wiring layer) and the distance between metal layers, during the manufacturing process. Therefore, the present invention aims to provide a semiconductor integrated circuit device that can achieve high specific accuracy in both unit capacitance and parasitic capacitance while suppressing the antenna effect. [Means for solving the problem]

[0011] The semiconductor integrated circuit apparatus of the embodiment is a semiconductor integrated circuit apparatus having capacitive elements, wherein a plurality of metal wiring layers are stacked via an insulating layer, and a member constituting a current path including a current path to the capacitive elements is arranged at a position that is rotationally symmetrical n times (n: an integer of 2 or more) with respect to a predetermined rotation axis along the stacking direction of the metal wiring layers. Ori , the above The component includes a wiring pattern that constitutes a metal bridge structure, vias that constitute the metal bridge structure, and vias or contacts that connect the wiring patterns to each other. . [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is an explanatory diagram of a metal bridge. [Figure 2] Figure 2 is an explanatory diagram of an example configuration of a metal bridge. [Figure 3] Figure 3 is an overview perspective view of a semiconductor integrated circuit device according to an embodiment. [Figure 4] Figure 4 is an explanatory diagram of the fourth metal wiring layer, ML4. [Figure 5] Figure 5 is an explanatory diagram of the third metal wiring layer ML3. [Figure 6] Figure 6 is an explanatory diagram of the second metal wiring layer ML2. [Figure 7] Figure 7 is an explanatory diagram of the first metal wiring layer ML1. [Figure 8] Figure 8 is a cross-sectional view of the semiconductor integrated circuit apparatus according to the embodiments shown in Figures 4 to 7. [Modes for carrying out the invention]

[0013] Next, embodiments will be described with reference to the drawings. [1] Principle of the embodiment First, before giving a detailed description of the embodiment, we will explain the principle of the embodiment. FIG. 1 is an explanatory diagram of a metal bridge. As shown in FIG. 1(A), as a typical method for suppressing the above-described antenna effect when there is a long metal wiring LN connected to the metal thin film constituting the capacitor C, as shown in FIG. 1(B), there is a method of providing a metal bridge structure MB.

[0014] This is a metal bridge structure MB having a structure in which a long metal wiring connected to the metal thin film constituting the capacitor C is drawn out to the uppermost metal wiring layer used in the process (in the example of FIG. 1, the second metal wiring layer) by a via VIA, and then returned to the original wiring layer (in the example of FIG. 1, the first metal wiring layer). The metal bridge structure MB is arranged near the insulating thin film layer that may be damaged, and the metal wiring LN is divided into a metal wiring LN1 and a metal wiring LN2, thereby suppressing the antenna effect.

[0015] On the other hand, considering that a high ratio accuracy of the main body capacitance and the parasitic capacitance is achieved by arranging a plurality of unit capacitances with the unit capacitance as a basic unit, the metal bridge has the same structure for each of the plurality of unit capacitances constituting the capacitance, and in applications where ratio accuracy is required, it is desirable to provide the metal bridge in consideration of the physical arrangement of the wiring pattern so that the parasitic capacitance due to the wiring pattern in the multilayer substrate is also the same.

[0016] FIG. 2 is an explanatory diagram of a configuration example of a metal bridge. In FIG. 2, an example of the connection relationship between the metal bridge and the MIM capacitor when the capacitance ratio is 3:2 is conceptually shown. In order to suppress the antenna effect due to the unit capacitance, as shown in FIG. 2(A), it is desirable that metal bridges exist at both ends of the electrodes of the unit capacitance.

[0017] On the other hand, under the condition that only one metal bridge exists for a plurality of unit capacitances as shown in FIG. 2(B), the insulating thin film layer of the MIM capacitor may be damaged due to the antenna effect between the capacitance electrodes connected to each other.

[0018] In addition, to achieve high specific accuracy in both unit capacity and parasitic capacity, a metal bridge structure is required that does not disrupt the high symmetry of the unit capacity in order to cancel out the effects of the process's first-order gradient.

[0019] Therefore, in the following embodiments, a metal bridge structure is provided that exists at both ends of the electrode for each unit capacitance, and does not disrupt the high symmetry of the unit capacitance.

[0020] [2] Embodiment Figure 3 is an overview perspective view of the semiconductor integrated circuit apparatus 10 of the embodiment. In Figure 3, for ease of understanding, the insulating material (insulating layer) and metal shield are omitted from the illustration.

[0021] The main unit capacity 11 includes a top plate 21 formed on the second metal wiring layer ML2 and a bottom plate 22 formed on the first metal wiring layer ML1 and the third metal wiring layer ML3. The fourth metal wiring layer ML4 is equipped with lead-out wiring 31 of the top plate 21 as lead-out metal wiring. The first metal wiring layer ML1 includes lead-out wiring 61 of the bottom plate 22 as lead-out metal wiring.

[0022] Furthermore, the fourth metal wiring layer ML4 is equipped with metal 33 for metal bridges, and the lead wiring 61 is connected to the bottom plate 22 via the metal bridge structure. The lead wiring 31 of the top plate 21 also serves as metal 33 for metal bridges.

[0023] Figures 4 to 7 are diagrams illustrating the configuration of the metal wiring layer. Here, Figure 4 is an explanatory diagram of the fourth metal wiring layer ML4, Figure 5 is an explanatory diagram of the third metal wiring layer ML3, Figure 6 is an explanatory diagram of the second metal wiring layer ML2, and Figure 7 is an explanatory diagram of the first metal wiring layer ML1. Details of each metal wiring layer will be described later.

[0024] Figure 8 is a cross-sectional view of the semiconductor integrated circuit apparatus 10 according to the embodiment shown in Figures 4 to 7. Figure 8(A) is a cross-sectional view of the semiconductor integrated circuit device 10 according to the embodiment shown in Figures 4 to 7, and Figure 5(B) is a cross-sectional view of the semiconductor integrated circuit device 10 according to the embodiment shown in Figures 4 to 7, taken by the arrow BB.

[0025] The semiconductor integrated circuit device 10 comprises a capacitive semiconductor integrated circuit device, and as shown in Figure 8, it includes a main capacitor 11, lead metal wiring, connection parts 14 configured as vias or contacts, a metal shield 15 (15A, 15B, 15C, 15D), and a substrate 16.

[0026] Furthermore, the semiconductor integrated circuit device 10 includes a first metal wiring layer ML1 to a fourth metal wiring layer ML4 that are stacked sequentially from the substrate 16 side, separated by insulating layers (not shown). Each main unit capacity 11 comprises one top plate 21 and two bottom plates 22, each having a rectangular shape in plan view (square shape in the examples shown in Figures 4 to 7).

[0027] Here, for the sake of ease of understanding, we have described the case of one top plate 21 and two bottom plates 22, but it is not limited to this, and other configurations such as two top plates 21 and one bottom plate 22, or one top plate and one bottom plate 22 can also be applied.

[0028] In the semiconductor integrated circuit apparatus 10 of this embodiment, the top plate 21 is formed on the second metal wiring layer ML2, one bottom plate 22 is formed on the first metal wiring layer ML1, and the other bottom plate 22 is formed on the third metal wiring layer ML3.

[0029] Next, we will explain the configuration of the fourth metal wiring layer ML4 shown in Figure 4. As shown in Figure 4, the fourth metal wiring layer ML4 includes lead wiring 31 of the top plate 21 as lead metal wiring, metal 33 for metal bridges, and a metal shield 15A that constitutes the metal shield 15.

[0030] The lead-out wiring 31 of the top plate 21 has a cross shape in plan view. It also has multiple connection points 14C (2 x 4 in the example in Figure 4) configured as vias for connecting to the wiring pattern 35 of the third metal wiring layer ML3.

[0031] As shown in Figure 4, the metal 33 for the metal bridge each has an L-shape in plan view, and four of them are arranged in a rotationally symmetrical manner four times with respect to the rotation axis RX (see Figure 3) along the stacking direction of the metal wiring layers ML1 to ML4.

[0032] Furthermore, the metal 33 for the metal bridge is provided with multiple (2 x 4 in the example of Figure 4) connection points 14A1, 14A2 for connecting to the bottom plate 22, and multiple (1 x 4 in the example of Figure 4) connection points 14A3 configured as vias for connecting to the wiring pattern 37 of the lead wiring 61 of the bottom plate 22 of the third metal wiring layer ML3.

[0033] The metal shield 15A, which constitutes the metal shield 15, has a shape that is rotationally symmetrical four times (L-shaped in plan view in Figure 4), as shown in Figure 4, and is equipped with a plurality of connection parts 14F (8 × 4 in the example in Figure 4) configured as vias.

[0034] Next, we will explain the configuration of the third metal wiring layer ML3 shown in Figure 5. As shown in Figure 5, the third metal wiring layer ML3 comprises a bottom plate 22, a plurality of wiring patterns 34-37, and a metal shield 15B that constitutes the metal shield 15.

[0035] The bottom plate 22 is connected to a plurality of wiring patterns 34 (four in the example in Figure 5) and to the metal bridge 33 of the fourth metal wiring layer ML4 via a plurality of connection points 14A1 configured as vias 14 (2 × 4 in the example in Figure 5).

[0036] Multiple (four in the example in Figure 5) wiring patterns 35 are connected to the lead wiring 31 of the top plate 21 of the fourth metal wiring layer ML4 and the wiring patterns 38 of the second metal wiring layer ML2 via multiple (2 × 4 in the example in Figure 5) connection points 14C configured as vias. Multiple (four in the example in Figure 5) wiring patterns 36 are connected to the metal bridge 33 of the fourth metal wiring layer ML4 (see Figure 4) and the wiring patterns 39 of the second metal wiring layer ML2 (see Figure 6) via multiple (2 × 4 in the example in Figure 5) connection points 14A2 configured as vias.

[0037] Multiple (four in the example in Figure 5) wiring patterns 37 are connected to the metal bridge 33 of the fourth metal wiring layer ML4 (see Figure 4) and the wiring pattern 40 of the second metal wiring layer ML2 (see Figure 6) via multiple (1 x 4 in the example in Figure 5) connection points 14A3 configured as vias.

[0038] The metal shield 15B, which constitutes the metal shield 15, has a shape that is rotationally symmetrical four times (a window frame shape in Figure 5). Furthermore, the metal shield 15B includes a plurality of connection points 14F configured as vias (8 × 4 in the example of Figure 5) that are connected to the metal shield 15A of the fourth metal wiring layer ML4 (see Figure 4) and the metal shield 15C of the second metal wiring layer ML2 (see Figure 6), and a plurality of connection points 14G configured as vias (2 × 4 in the example of Figure 5) that are connected to the metal shield 15C of the second metal wiring layer ML2.

[0039] Next, we will explain the configuration of the second metal wiring layer ML2 shown in Figure 6. As shown in Figure 6, the second metal wiring layer ML2 comprises a top plate 21, a plurality of wiring patterns 38-40, and a metal shield 15C that constitutes the metal shield 15.

[0040] The top plate 21 is connected to multiple (four in the example in Figure 6) wiring patterns 38, and to the wiring patterns 35 of the third metal wiring layer ML3 (see Figure 5) via multiple (2 × 4 in the example in Figure 6) connection points 14C configured as vias.

[0041] Multiple (four in the example in Figure 6) wiring patterns 39 are connected to the wiring patterns 36 of the third metal wiring layer ML3 (see Figure 5) and the wiring patterns 51 of the first metal wiring layer ML1 (see Figure 7) via multiple (2 × 4 in the example in Figure 6) connection points 14A2 configured as vias. Multiple (four in the example in Figure 6) wiring patterns 40 are connected to the wiring pattern 37 of the third metal wiring layer ML3 (see Figure 5) and the wiring pattern 50 of the first metal wiring layer ML1 (see Figure 7) via multiple (1 x 4 in the example in Figure 6) connection points 14A3 configured as vias.

[0042] The metal shield 15C, which constitutes the metal shield 15, has a shape that is rotationally symmetrical four times (window frame shape in Figure 6), and includes a plurality of connection parts 14F (8 × 4 in the example in Figure 6) configured as vias connected to the metal shield 15B of the third metal wiring layer ML3 (see Figure 5) and the metal shield 15D of the first metal wiring layer ML1, and a plurality of connection parts 14G (2 × 4 in the example in Figure 6) configured as vias connected to the metal shield 15B of the third metal wiring layer ML3.

[0043] As shown in Figure 7, the first metal wiring layer ML1 comprises a bottom plate 22, a plurality of wiring patterns 50, 51, and a metal shield 15D that constitutes the metal shield 15.

[0044] The bottom plate 22 is connected to multiple (four in the example in Figure 7) wiring patterns 51 and to the wiring patterns 39 of the second metal wiring layer ML2 (see Figure 6) via multiple (2 × 4 in the example in Figure 7) connection points 14A2 configured as vias.

[0045] Multiple (four in the example in Figure 7) wiring patterns 50 are connected to the wiring patterns 40 of the second metal wiring layer ML2 via multiple (1 × 4 in the example in Figure 7) connection points 14A3 configured as vias. As shown in Figure 7, each of the four wiring patterns 50 has an I-shape in plan view and is arranged symmetrically with respect to the rotation axis RX along the stacking direction of the metal wiring layers ML1 to ML4. Furthermore, the wiring pattern 50 is connected to the lead wiring 61 of the bottom plate 22, which serves as lead metal wiring.

[0046] As described above, the top plate 21 formed on the second metal wiring layer ML2 has electrodes drawn out from the wiring pattern 38 of the second metal wiring layer ML2, the wiring pattern 35 of the third metal wiring layer ML3, and the lead wiring 31 of the fourth metal wiring layer ML4 via the connection portion 14C configured as a via.

[0047] Furthermore, the bottom plate 22 formed on the first metal wiring layer ML1 is connected to the wiring pattern 51 of the first metal wiring layer ML1, and via the connection portion 14A2 configured as a via, to the wiring pattern 39 of the second metal wiring layer ML2, the wiring pattern 36 of the third metal wiring layer ML3, and the metal bridge 33 of the fourth metal wiring layer ML4. The bottom plate 22 formed on the third metal wiring layer ML3 is connected to the wiring pattern 34 of the third metal wiring layer ML3 and to the metal bridge 33 of the fourth metal wiring layer ML4 via the connection portion 14A1 configured as a via. Furthermore, the metal 33 for the metal bridge of the fourth metal wiring layer ML4 is connected to the wiring pattern 37 of the third metal wiring layer ML3, the wiring pattern 40 of the second metal wiring layer ML2, and the wiring pattern 50 of the first metal wiring layer ML1 via the connection part 14A3 configured as a via, and electrodes are drawn out from the lead wiring 61 of the first metal wiring layer ML1.

[0048] As a result, the signals of the semiconductor integrated circuit device 10 can be output to the outside via the lead wiring 31 and lead wiring 61.

[0049] Furthermore, multiple metal shields 15D of the first metal wiring layer ML1 are connected to the substrate 16 by connection parts 14F configured as contacts. As a result, multiple metal shields 15A, 15B, 15C, and multiple metal shields 15D are electrically integrated via connection parts 14F and 14G, which are configured as vias, to form a metal shield 15 that functions as an electromagnetic shield.

[0050] As shown in Figures 4 to 8, in a semiconductor integrated circuit device 10 having capacitive elements, in which multiple metal wiring layers are stacked with an insulating layer in between, a wiring pattern including a wiring pattern constituting a metal bridge structure, vias 14 including vias constituting a metal bridge structure, and vias or contacts connecting the wiring patterns are arranged on the substrate 16 at positions that are four rotationally symmetric with respect to a predetermined rotation axis RX along the stacking direction of the metal wiring layers ML1 to ML4. Therefore, the effective current path length can be easily made the same regardless of which current path is used, without considering wiring routing, and it is possible to construct a unit capacitance with high relative accuracy.

[0051] As described above, this embodiment enables the realization of a layout with high relative accuracy in unit capacitance, making it possible to realize switched capacitor circuits and capacitive D / A converters that require high relative accuracy. Furthermore, according to this embodiment, by arranging a metal bridge while maintaining a shield structure (metal shield) with a unit capacitance, a metal bridge structure can be adopted while maintaining high specific accuracy, thereby suppressing the antenna effect.

[0052] Therefore, the time required to design the layout while taking the effects of antennas into account is eliminated. As a result, the difficulty of designing layouts for capacities requiring high relative accuracy is reduced, and the layout creation time can be shortened. Furthermore, even in applications of capacitance where particularly high specific accuracy is required, such as switched-capacitor circuits and capacitive D / A converters, it is possible to construct switched-capacitor circuits and capacitive D / A converters without a decrease in specific accuracy, as unexpected parasitic capacitances, such as inter-wiring parasitic capacitances, affect the design depending on the layout when the capacitance is realized on the integrated circuit.

[0053] In the above description, we have described a semiconductor integrated circuit device having capacitive elements, in which multiple metal wiring layers are stacked with an insulating layer in between, and in which a member constituting a current channel including a current channel to the capacitive elements is arranged at a position that is four rotationally symmetric with respect to a predetermined rotation axis along the stacking direction of the metal wiring layers ML1 to ML4. Similarly, if the components constituting the current path, including the current path to the capacitive element, are positioned at positions that are rotationally symmetrical n times (n: an integer greater than or equal to 2), the effective length of the current path to the capacitive element that affects the parasitic capacitance can be made more reliably equal, thereby achieving high relative accuracy in both unit capacitance and parasitic capacitance.

[0054] With these configurations, multiple metal wiring layers are stacked with an insulating layer in between, making it possible to arrange metal bridge structures in rotationally symmetrical positions when viewing a semiconductor integrated circuit device with capacitive elements from a planar perspective. Furthermore, the wiring leading to each metal bridge structure and the insulating layers between those wirings can also be arranged rotationally symmetrically. Therefore, even if the metal wiring and insulating layers constituting the capacitive elements are affected by the first-order gradient of the manufacturing process, the symmetry of the capacitive elements cancels out the effect of the first-order gradient, thus improving the relative accuracy.

[0055] In this case, the components constituting the current path include wiring patterns that constitute a metal bridge structure, vias that constitute a metal bridge structure, and vias or contacts that connect the wiring patterns to each other. Therefore, the influence of the first-order gradient of the manufacturing process can be canceled out for the entire semiconductor integrated circuit device, and the high symmetry of the unit capacitance can be maintained.

[0056] Furthermore, by providing metal bridges on both terminals of the capacitive element, the insulating thin film layer of the MIM capacitance is not damaged by the antenna effect between the connected capacitive electrodes during the manufacturing of the semiconductor integrated circuit device, thereby improving the reliability of the semiconductor integrated circuit device equipped with the capacitive element.

[0057] Although the line width of the wiring pattern was not mentioned in the above explanation, it is possible to further improve the specific accuracy by increasing the line width of the wiring pattern drawn from the main capacitor 11, thereby suppressing the effects of line width variations caused by the manufacturing process. Furthermore, since the capacitor formed through the insulating film can be used as the main capacitor 11, it can be applied not only to MIM capacitors but also to PIP capacitors, MOS capacitors, and the like.

[0058] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0059] 10 Semiconductor integrated circuit equipment 11. Main unit capacity 14 Beer 14A1, 14A2, 14A3, 14C connector 14F, 14G connection section 15, 15A~15D Metal Shield 16 circuit boards 21 Top Plate 22 Bottom Plate 31, 61 Output wiring 33 Metal bridge 34-40 Wiring Patterns 50, 51 Wiring Patterns MB Metal Bridge Structure ML1 First Metal Wiring Layer ML2 Second Metal Wiring Layer ML3 Third Metal Wiring Layer ML4 4th Metal Wiring Layer RX rotation axis VIA (Via)

Claims

1. A semiconductor integrated circuit device having capacitive elements, wherein multiple metal wiring layers are stacked with an insulating layer in between, A member constituting a current path including the current path to the capacitive element is positioned at a position that is rotationally symmetrical by n (n: an integer of 2 or more) times with respect to a predetermined rotation axis along the stacking direction of the metal wiring layer. The member includes a wiring pattern that constitutes a metal bridge structure, vias that constitute the metal bridge structure, and vias or contacts that connect the wiring patterns to each other. Semiconductor integrated circuit equipment.

2. The aforementioned member includes m (m: a natural number) types of members, m × n members are arranged in positions that are rotationally symmetrical by n times. The semiconductor integrated circuit apparatus according to claim 1.

3. This includes a member constituting a metal shield having a shape that is rotationally symmetrical n times with respect to the rotation axis, and a member constituting the metal shield positioned at a location that is rotationally symmetrical n times. The semiconductor integrated circuit apparatus according to claim 1.

4. The metal bridge structure is provided on both one terminal and the other terminal of the capacitive element. The semiconductor integrated circuit apparatus according to claim 1.

5. The aforementioned capacitive element is configured as a MIM capacitive element in which a second plate electrode is arranged between a pair of first plate electrodes with an insulator in between. The semiconductor integrated circuit apparatus according to claim 1.

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