Semiconductor equipment

Abstract

To enable normally-off operation.SOLUTION: A semiconductor device performs normally-off driving of a first transistor that performs normally-on driving. The semiconductor device includes a first circuit, a second circuit, and a first diode. The first circuit is connected to power source voltage and ground voltage, detects the power source voltage, and outputs a transition state of the power source voltage. The second circuit is connected to the power source voltage and the ground voltage, is connected to the first circuit and the second transistor, and outputs the driving voltage of the second transistor connected in series to the first transistor on the basis of the output from the first circuit. The first diode has an anode connected to a driving terminal of the first transistor, and a cathode connected to an output terminal of the second transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] Power devices using GaN (gallium nitride) have advantages such as high switching speed, low recovery loss, and fast charge and discharge of output capacitance compared to MOSFETs (Metal - Oxide - Semiconductor Field - Effect Transistors) using Si (silicon). Transistors using GaN are generally often normally - on type, and extensive development is being carried out to utilize these advantages as normally - off type transistors.

[0003] However, circuits for converting to such a normally - off type have problems such as being unable to adjust gate drive capability by the conversion circuit, requiring a dedicated negative power supply circuit and a dedicated gate driver, the gate current loop becoming long via an n - type MOSFET, or a large trade - off between preventing false - on when the gate driver power is off and standby power.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment provides a semiconductor device enabling normally - off operation.

Means for Solving the Problems

[0006] According to one embodiment, the semiconductor device is a semiconductor device that normally drives a normally-on first transistor in a normally-off state, and comprises a first circuit, a second circuit, and a first diode. The first circuit is connected to the power supply voltage and the ground voltage, detects the power supply voltage, and outputs the transition state of the power supply voltage. The second circuit is connected to the power supply voltage, the ground voltage, the first circuit, and the second transistor, and outputs a drive voltage for the second transistor connected in series with the first transistor based on the output of the first circuit. The anode of the first diode is connected to the drive terminal of the first transistor, and the cathode is connected to the output terminal of the second transistor. [Brief explanation of the drawing]

[0007] [Figure 1] A circuit diagram showing an example of a semiconductor device according to one embodiment. [Figure 2] A circuit diagram showing one implementation example of a semiconductor device according to one embodiment. [Figure 3] A diagram showing the on and off states of a transistor according to one embodiment. [Figure 4] A circuit diagram showing one implementation example of a semiconductor device according to one embodiment. [Figure 5] A diagram showing the on and off states of a transistor according to one embodiment. [Figure 6] A circuit diagram showing one implementation example of a semiconductor device according to one embodiment. [Figure 7] A circuit diagram showing one implementation example of a semiconductor device according to one embodiment. [Figure 8] A circuit diagram showing one implementation example of a semiconductor device according to one embodiment. [Figure 9] A circuit diagram showing one implementation example of a semiconductor device according to one embodiment. [Figure 10] A circuit diagram showing an example of a semiconductor device according to one embodiment. [Figure 11] A circuit diagram showing one implementation example of a semiconductor device according to one embodiment. [Figure 12] A circuit diagram showing one implementation example of a semiconductor device according to one embodiment. [Figure 13]A circuit diagram showing one implementation example of a semiconductor device according to one embodiment. [Modes for carrying out the invention]

[0008] Embodiments will be described below with reference to the drawings. In the drawings, unless otherwise specified, D indicates the location of the drain.

[0009] (First Embodiment) Figure 1 is a circuit diagram showing an example of the location of a semiconductor device according to one embodiment. The semiconductor device 1 is a circuit for driving a normally-on type first transistor Q1 in normally-off mode.

[0010] The first transistor Q1 is a power device, for example, made of GaN, and is a normally-on FET.

[0011] The second transistor Q2 is a p-type MOSFET connected in series with the first transistor Q1, sharing a source. Due to the characteristics of this second transistor Q2, the first transistor Q1 operates in normally-off mode.

[0012] Hereinafter, the drains of the first transistor Q1 and the second transistor Q2 are defined as the drain and source of the normally-off transistors, respectively. The semiconductor device 1 solves various problems that occur when the first transistor Q1 is normally-off by controlling the voltage applied to the source and the gate of each transistor.

[0013] When the first transistor Q1 operates normally off via the semiconductor device 1, it is driven according to the voltage applied to its gate and outputs a drain current from the source terminal SOURCE based on the potential difference between the drain terminal DRAIN and the source terminal SOURCE. For example, if an external load is connected to the drain terminal DRAIN, i.e., the drain side of the first transistor Q1, the first transistor Q1 operates as a circuit that switches with respect to this load based on the voltage applied to its gate.

[0014] The semiconductor device 1 is a circuit that controls the voltages of the gate of the first transistor Q1, the gate of the second transistor Q2, and the drain of the second transistor Q2, and is connected to a power supply voltage terminal VDD, a gate voltage application terminal GATE, and a ground terminal GND. This semiconductor device 1 includes a first diode 10, a first circuit 20, and a second circuit 30. Note that the gate voltage application terminal GATE is connected to the gate of the first transistor Q1.

[0015] The power supply voltage terminal VDD is connected to a node shared by the sources of the first transistor Q1 and the second transistor Q2 via the semiconductor device 1, and applies a power supply voltage to the semiconductor device 1. The ground terminal GND sets the ground potential of the semiconductor device 1. In the figure, it is connected to the ground point within the semiconductor device 1, but this form is not limited thereto, and it may be grounded outside the semiconductor device 1. This ground terminal GND is not necessarily actually grounded, and may be connected to a potential of 0V, or may be connected to a predetermined ground potential within the device. It should be understood that the ground terminal GND in the following description can all be interpreted in the same way.

[0016] The first diode 10 is a protection circuit for the first transistor Q1 and the second transistor Q2. The anode of the first diode 10 is connected to the gate of the first transistor Q1, and the cathode is connected to the drain of the second transistor Q2. This first diode 10

[0017] The first circuit 20 is a circuit that detects the voltage of the power supply voltage. The first circuit 20 is connected between the power supply voltage terminal VDD and the ground terminal GND. This first circuit 20 compares the state of the power supply voltage, more specifically, the power supply voltage and the threshold voltage of the first transistor Q1, detects the voltage difference therebetween, and outputs it to the second circuit 30.

[0018] The second circuit 30 is a low-standby power circuit that outputs a voltage to drive the second transistor Q2 in order to operate it properly. The second circuit 30 is connected to the power supply voltage terminal VDD, the ground voltage GND, the first circuit 20, and the gate of the second transistor Q2. When the second circuit 30 receives a signal from the first circuit 20 that detects the voltage state, it drives the second transistor Q2 appropriately.

[0019] When the power supply voltage rises, the first circuit 20 detects that the voltage has become higher than the absolute value of the threshold voltage of the first transistor Q1, that is, that the first transistor Q1 has turned off. The first circuit 20 outputs this voltage fluctuation to the second circuit 30. Upon receiving this signal, the second circuit 30 applies a drive voltage to the gate of the second transistor Q2 to turn on the second transistor Q2 after the first transistor Q1 has turned off.

[0020] Conversely, if the power supply voltage drops, the first circuit 20 outputs to the second circuit 30 that the voltage is dropping when the power supply voltage is higher than the absolute value of the threshold voltage of the first transistor Q1, that is, when the first transistor Q1 is off. Upon receiving this signal, the second circuit 30 applies a drive voltage to the gate of the second transistor Q2 that turns off the second transistor Q2 before the first transistor Q1 turns on.

[0021] By using the first circuit 20 and the second circuit 30 in this manner, even when the voltage applied to the power supply voltage terminal rises or falls with a high slew rate, it is possible to avoid the second transistor Q2 turning on while the first transistor Q1 is turned on. Similarly, even when the power supply voltage is fluctuating in a way that causes it to oscillate near the threshold voltage of the first transistor Q1, it is possible to avoid the state in which both the first transistor Q1 and the second transistor Q2 turn on.

[0022] The following describes some specific implementation examples of semiconductor device 1.

[0023] (Implementation Example 1) Figure 2 is a circuit diagram showing a semiconductor device 1 according to one implementation example. The semiconductor device 1 comprises a first resistor 200, a second diode 201, a third transistor 202, a second resistor 203, a fourth transistor 300, and a third resistor 301. As shown in the figure, as an example, the first resistor 200, the second diode 201, the third transistor 202, and the second resistor 203 are provided as part of the first circuit 20, and the fourth transistor 300 and the third resistor 301 are provided as part of the second circuit 30.

[0024] The first resistor 200 is connected between the power supply voltage terminal VDD and the second diode 201.

[0025] The second diode 201 has its anode connected to the ground terminal GND and its cathode connected to the power supply voltage terminal VDD via the first resistor 200. This second diode 201 is a Zener diode having a Zener voltage that is equal to or greater than the absolute value of the threshold voltage of the first transistor Q1, and lower than the steady-state value Vdd of the power supply voltage (for example, the maximum value of the voltage applied to the power supply, which is about 15V).

[0026] The first resistor 200 and the second diode 201 operate as a circuit that outputs a constant voltage (Zener voltage) from the connection node when a voltage greater than or equal to the Zener voltage of the second diode 201 is applied to the power supply terminal VDD, and as a circuit that outputs a voltage based on the voltage applied to the power supply voltage terminal VDD otherwise.

[0027] The third transistor 202 is, for example, a p-type MOSFET, with its source connected to the power supply voltage terminal VDD, its drain connected to the ground terminal GND via the second resistor 203, and its gate connected to the cathode of the second diode 201. The threshold voltage of this third transistor 202 is negative, and its absolute value is lower than (steady-state value of power supply voltage Vdd) - (Zener voltage of the second diode 201).

[0028] The second resistor 203 is connected between the drain of the third transistor 202 and the ground terminal GND. The current flowing through the third transistor 202 determines the potential of the drain of the third transistor, which is defined by the resistance value of this second resistor 203. For example, the first circuit 20 outputs the voltage across the drain of this third transistor 202.

[0029] The fourth transistor 300 is, for example, a p-type MOSFET, with its source connected to the power supply voltage terminal VDD, its drain connected to the ground terminal GND via the third resistor 301, and its gate connected to the drain of the third transistor 202. The threshold voltage of this fourth transistor 300 is negative, and its absolute value is lower than the steady-state value Vdd of the power supply voltage.

[0030] The third resistor 301 is provided between the drain of the fourth transistor 300 and the ground terminal GND.

[0031] In this configuration, the first circuit 20 outputs a voltage based on the voltage applied to the power supply voltage terminal VDD, and the second circuit 30 outputs a voltage corresponding to the voltage output by the first circuit 20 to the gate of the second transistor Q2.

[0032] Here, we will explain the operation of the first transistor Q1 and the second transistor Q2 when the voltage applied to the power supply voltage terminal VDD fluctuates.

[0033] First, let's explain the case where the voltage applied to the power supply terminal VDD rises from 0 to voltage Vdd. When the voltage applied to the power supply terminal VDD exceeds the threshold voltage of the first transistor Q1, the first transistor Q1 turns off. At this timing, the Zener voltage of the second diode 201 has not been exceeded, so no current flows through the first resistor 200, the gate-source voltage of the third transistor 202 becomes 0, and the third transistor 202 remains in the off state. Then, because no current flows through the second resistor 203, the fourth transistor 300 turns on, and this drain current and the voltage across the third resistor 301 are applied to the gate of the second transistor Q2, and the second transistor Q2 remains in the off state.

[0034] Furthermore, when the voltage applied to the power supply terminal VDD increases and surpasses the Zener voltage of the second diode 201, the gate-source voltage of the third transistor 202 becomes equal to the voltage across the terminals of the first resistor 200. In this state, if the voltage applied to the power supply terminal VDD is lower than the sum of the absolute values ​​of the Zener voltage and the threshold voltage of the third transistor 202, the states of the third transistor 202 and the fourth transistor 300 remain unchanged. That is, the third transistor 202 is off, the fourth transistor 300 is on, and the second transistor Q2 is off.

[0035] Furthermore, when the voltage applied to the power supply voltage terminal VDD increases and exceeds the sum of the absolute values ​​of the Zener voltage and the threshold voltage of the third transistor 202, the gate-source voltage of the third transistor 202 falls below the threshold voltage of the third transistor 202, and the third transistor 202 turns on. When the third transistor 202 turns on, the drain current of the third transistor 202 and the voltage across the second resistor 203 are applied to the gate of the fourth transistor 300.

[0036] In this state, the voltage applied to the gate of the fourth transistor 300 increases as the voltage applied to the power supply terminal VDD increases, gradually turning off the fourth transistor 300. When the voltage applied to the power supply terminal VDD exceeds the absolute value of the threshold voltage of the fourth transistor 300, the fourth transistor 300 turns off. That is, the voltage applied to the gate of the second transistor Q2 decreases as the voltage applied to the power supply terminal VDD increases, and the second transistor Q2 turns on when the voltage falls below the threshold voltage of the second transistor Q2.

[0037] To summarize the above situation, for example, when the voltage applied to the power supply voltage terminal VDD rises from 0 to voltage Vdd, first the first transistor Q1 transitions from on to off, then the third transistor 202 and the fourth transistor 300 transition, and finally the second transistor Q2 transitions from off to on. In this way, a time margin is created between the off state of the first transistor Q1 and the on state of the second transistor Q2, making it possible to configure the system so that these two transistors do not turn on simultaneously.

[0038] Next, we will explain the case where the voltage applied to the power supply voltage terminal VDD drops from voltage Vdd to 0.

[0039] When the voltage applied to the power supply terminal VDD decreases until Vdd - (Zener voltage of the second diode 201), that is, the voltage across the terminals of the first resistor 200, falls below the threshold voltage of the third transistor 202, the third transistor 202 transitions from the ON state to the OFF state.

[0040] As a result, the fourth transistor 300 transitions to the ON state, and when the voltage formed by the drain current of the fourth transistor 300 and the third resistor 301 exceeds the threshold voltage of the second transistor Q2, the second transistor Q2 transitions to the OFF state.

[0041] Subsequently, when the voltage applied to the power supply voltage terminal VDD decreases further and falls below the threshold voltage of the first transistor Q1, the first transistor Q1 turns on.

[0042] To summarize the above situation, for example, when the voltage applied to the power supply voltage terminal VDD drops from voltage Vdd to 0, first the third transistor 202 and the fourth transistor 300 transition their states, then the second transistor Q2 transitions from on to off, and then the first transistor Q1 transitions to the on state. In this way, a time margin is created between the off state of the second transistor Q2 and the on state of the first transistor Q1, making it possible to configure the system so that these two transistors do not turn on simultaneously.

[0043] The driving force for the turn-on and turn-off of the second transistor Q2 when the voltage applied to the power supply voltage terminal VDD rises and falls is determined by the value of the third resistor 301 and the on-resistance value of the fourth transistor 300, respectively. By making the resistance value of the third resistor 301 greater than the on-resistance of the fourth transistor 300, the turn-off of the second transistor Q2 can be made faster than the turn-off.

[0044] Figure 3 shows the voltages of the components in the circuit shown in Figure 2. The solid line shows the voltage applied to the power supply voltage terminal VDD, the dotted line shows the gate-source voltage Vgs1 of the first transistor Q1, and the dashed line shows the gate-source voltage Vgs2 of the second transistor Q2.

[0045] Furthermore, Vth1 is the threshold voltage of the first transistor Q1, and Vth2 is the threshold voltage of the second transistor Q2. Vref is the Zener voltage of the second diode 201, which is the voltage to be detected in the first circuit 20.

[0046] The ON / OFF indicators below show the ON / OFF state of the first transistor Q1 in the upper row and the ON / OFF state of the second transistor Q2 in the lower row.

[0047] As shown in Figure 3, whether the voltage applied to the power supply voltage terminal VDD rises or falls, the timing of the on / off states of the first transistor Q1 and the second transistor Q2 transitions through a state where both transistors are off. Therefore, these two transistors never turn on at the same time.

[0048] In the circuit configuration shown in Figure 2, in the steady state where the first transistor Q1 is in the off state, a voltage Vdd is applied to the gate of the second transistor Q2, making it possible to drive the second transistor Q2 with a low on-resistance.

[0049] As described above, even when the slew rate of the voltage applied to the power supply voltage terminal VDD is high, or when the voltage applied to the power supply voltage terminal VDD oscillates, it is possible to avoid the first transistor Q1 and the second transistor Q2 being turned on simultaneously.

[0050] Furthermore, in the steady state after the power supply voltage has risen, the fourth transistor 300 is in the off state, so no standby current flows, making it possible to achieve both a driving force difference that prevents the first transistor Q1 and the second transistor Q2 from turning on simultaneously, and low power consumption. As a result, the standby power of this circuit as a whole is defined by the current flowing through the first resistor 200 and the second resistor 203, and by making these two resistance values ​​large, it is possible to achieve low power consumption overall. Making the resistance values ​​large means, for example, using resistance values ​​of several tens of kΩ, in which case the power consumption will be about 1 mA at a power supply voltage of about 15 V, making it possible to achieve low current consumption as a transistor driving circuit.

[0051] (Implementation Example 2) Figure 4 is a circuit diagram showing the configuration of the semiconductor device 1 according to Implementation Example 2, which is different from Implementation Example 1 described above. The semiconductor device 1 comprises a fifth transistor 210 and a third diode 211. The fifth transistor 210 and the third diode 211 form the first circuit 20 and the second circuit 30 in Figure 1.

[0052] The fifth transistor 210 is, for example, a normally-on transistor, with its drain connected to the power supply voltage terminal VDD, its source connected to the ground terminal GND via the third diode 211, and its gate connected to the ground terminal GND. This fifth transistor has characteristics such as a negative threshold voltage, whose absolute value is greater than or equal to the absolute value of the threshold voltage of the first transistor Q1, and lower than the voltage Vdd.

[0053] The third diode 211 is, for example, a Zener diode, with its anode connected to the ground terminal GND and its cathode connected to the source of the fifth transistor 210. The Zener voltage of the third diode 211 is greater than or equal to the absolute value of the threshold voltage of the first transistor Q1, and lower than the voltage Vdd - (absolute value of the threshold voltage of the second transistor Q2).

[0054] The connection node between the source of the fifth transistor 210 and the cathode of the third diode 211 is connected to the gate of the second transistor Q2, and the voltage at this node becomes the drive voltage of the second transistor Q2.

[0055] Here, we will explain the operation of the first transistor Q1 and the second transistor Q2 when the voltage applied to the power supply voltage terminal VDD fluctuates.

[0056] First, let's explain the case where the voltage applied to the power supply voltage terminal VDD rises from 0 to voltage Vdd. When the voltage applied to the power supply voltage terminal VDD exceeds the threshold voltage of the first transistor Q1, the first transistor Q1 turns off. At this timing, the fifth transistor 210 is on, so the second transistor Q2 remains in the off state.

[0057] When the voltage applied to the power supply voltage terminal VDD rises further and exceeds the absolute value of the threshold voltage of the fifth transistor 210 and the Zener voltage of the third diode 211, the fifth transistor 210 turns off, and the gate voltage of the second transistor Q2 is raised to the Zener voltage (or a voltage below the Zener voltage).

[0058] When the voltage applied to the power supply voltage terminal VDD rises further and the gate-source voltage of the second transistor Q2 falls below the threshold voltage, the second transistor Q2 turns on.

[0059] To summarize the above situation, for example, when the voltage applied to the power supply voltage terminal VDD rises from 0 to voltage Vdd, first the first transistor Q1 transitions from on to off, and the fifth transistor 210 and the third diode 211 cause the gate of the second transistor Q2 to reach the Zener voltage of the third diode 211 (or a voltage below the Zener voltage), after which the second transistor Q2 transitions from off to on. In this way, a time margin is created between the off state of the first transistor Q1 and the on state of the second transistor Q2, making it possible to configure the system so that these two transistors do not turn on simultaneously.

[0060] Next, we will explain the case where the voltage applied to the power supply voltage terminal VDD drops from voltage Vdd to 0.

[0061] First, when the voltage applied to the power supply voltage terminal VDD falls below the threshold voltage of the fifth transistor 210, the fifth transistor 210 turns on. When the fifth transistor 210 turns on, the drain current causes the gate potential of the second transistor Q2 to exceed the threshold voltage, and the second transistor Q2 turns off.

[0062] Subsequently, the voltage applied to the power supply voltage terminal VDD exceeds the threshold value of the first transistor Q1, causing the first transistor Q1 to turn on.

[0063] To summarize the above situation, for example, when the voltage applied to the power supply voltage terminal VDD drops from voltage Vdd to 0, the fifth transistor 210 turns on first, and accordingly the second transistor Q2 transitions from on to off. After that, the first transistor Q1 transitions from off to on. In this way, a time margin is created between the off state of the first transistor Q1 and the on state of the second transistor Q2, making it possible to configure the system so that these two transistors do not turn on simultaneously.

[0064] The driving force for the turn-on and turn-off of the second transistor Q2 when the voltage applied to the power supply voltage terminal VDD rises and falls is determined by the on-resistance of the fifth transistor 210 and the operating resistance of the third diode 211, respectively. By configuring the operating resistance of the third diode 211 to be greater than the on-resistance of the fifth transistor 210, the turn-off of the second transistor Q2 can be made faster than the turn-off.

[0065] Figure 5 shows the voltages of the components in the circuit shown in Figure 4. The solid line shows the voltage applied to the power supply voltage terminal VDD, the dotted line shows the gate-source voltage Vgs1 of the first transistor Q1, and the dashed line shows the gate-source voltage Vgs2 of the second transistor Q2.

[0066] Furthermore, Vth1 is the threshold voltage of the first transistor Q1, and Vth2 is the threshold voltage of the second transistor Q2. Vref is the Zener voltage of the third diode 211.

[0067] The ON / OFF indicators below show the ON / OFF state of the first transistor Q1 in the upper row and the ON / OFF state of the second transistor Q2 in the lower row.

[0068] As shown in Figure 5, whether the voltage applied to the power supply voltage terminal VDD rises or falls, the timing of the on / off states of the first transistor Q1 and the second transistor Q2 transitions through a state where both transistors are off. Therefore, these two transistors never turn on at the same time.

[0069] In the steady state where the first transistor Q1 is in the off state, a voltage equal to the difference between the power supply voltage VDD and the Zener voltage of the third diode 211 is applied to the gate of the second transistor Q2. Therefore, compared to the circuit configuration in Figure 2, the on-resistance of the second transistor Q2 is higher in the circuit configuration in Figure 4.

[0070] Furthermore, in the steady state after the VDD voltage rises, the first transistor Q1 is in the off state, so no standby current flows, making it possible to achieve both a driving force difference that prevents simultaneous on-up and low power consumption. Compared to implementation example 1, the applied voltage for turning on the second transistor Q2 is lower, so the on-resistance of the second transistor Q2 tends to be higher, but it has the advantage of requiring fewer circuit components and lower power consumption than implementation example 1.

[0071] As described above, even when the slew rate of the voltage applied to the power supply voltage terminal VDD is high, or when the voltage applied to the power supply voltage terminal VDD oscillates, it is possible to avoid the first transistor Q1 and the second transistor Q2 being turned on simultaneously.

[0072] Furthermore, in the steady state after the power supply voltage has risen, the fifth transistor 210 is in the off state, so no standby current flows, making it possible to achieve both a driving force difference that prevents the first transistor Q1 and the second transistor Q2 from turning on simultaneously, and low power consumption. In the configuration shown in Figure 4, the applied voltage to turn on the second transistor Q2 is lower compared to the configuration shown in Figure 2, so the on-resistance of the second transistor Q tends to be higher, but it is possible to use fewer circuit components and lower power consumption than in implementation example 1.

[0073] (Implementation Example 3) Figure 6 is a circuit diagram showing the configuration of the semiconductor device 1 according to implementation example 3. The first circuit 20 includes a reference voltage generation circuit 21 and a voltage comparison circuit 22. The second circuit 30 includes an output buffer 31.

[0074] The reference voltage generation circuit 21 generates a reference voltage Vref. An example is shown in Figure 6, but the circuit is not limited to this example; any circuit that can output a reference voltage Vref will suffice.

[0075] The voltage comparison circuit 22 compares the voltage generated by the reference voltage generation circuit 21 with the voltage applied to the power supply voltage terminal VDD. For example, it is formed by inputting the output of the reference voltage generation circuit 21 and the voltage across multiple resistors that divide the distance between the power supply voltage terminal VDD and the ground terminal GND in a predetermined ratio to the input of a general comparator. The voltage comparison circuit 22 detects a voltage greater than the absolute value of the threshold voltage of the first transistor Q1 and outputs it to the output buffer 31.

[0076] The output buffer 31 controls the output of the voltage comparison circuit 22 and applies it to the gate of the second transistor Q2.

[0077] Figure 7 shows a circuit diagram of an output buffer 31 according to one implementation example. The output buffer 31 comprises, for example, a sixth transistor M1, a seventh transistor M2, a fourth resistor R1, and a fifth resistor R2.

[0078] The sixth transistor M1 is a p-type MOSFET, with its source connected to the power supply voltage terminal VDD and its gate connected to the output of the voltage comparison circuit 22.

[0079] The seventh transistor M2 is an n-type MOSFET, with its source connected to the ground terminal GND and its gate connected to the output of the voltage comparison circuit 22.

[0080] The fourth resistor R1 is connected between the drain and output terminal of the sixth transistor M1.

[0081] The fifth resistor R2 is connected between the drain and output terminal of the seventh transistor M2.

[0082] The resistance value of the fifth resistor R2 is greater than the resistance value of the fourth resistor R1. By setting the resistance values ​​of the fourth resistor R1 and the fifth resistor R2 in this way, the resistance value in the current path when turning on the second transistor Q2 can be made greater than the resistance value in the current path when turning off the second transistor Q2. As a result, it becomes possible to make the drive force for turning off the second transistor Q2 higher than the drive force for turning on the second transistor Q2.

[0083] This resistor configuration makes it possible to avoid the simultaneous turning on of the first transistor Q1 and the second transistor Q2, even when the slew rate of the voltage applied to the power supply voltage terminal VDD is high or when the voltage oscillates.

[0084] Figure 8 shows a circuit diagram illustrating another implementation example of the output buffer 31. The output buffer 31 comprises, for example, an eighth transistor M3 and a ninth transistor M4.

[0085] The eighth transistor M3 is a p-type MOSFET, with its source connected to the power supply voltage terminal VDD and its gate connected to the output of the voltage comparison circuit 22.

[0086] The ninth transistor M4 is an n-type MOSFET, with its source connected to the ground terminal GND, its gate connected to the output of the voltage comparison circuit 22, and its drain connected to the drain of the eighth transistor M8.

[0087] As can be seen from the above, the 8th transistor M3 and the 9th transistor M4 form a CMOS (Complementary MOSFET). In this implementation example, as an example, the gate width of the 8th transistor M3 is made larger than the gate width of the 9th transistor M4.

[0088] By forming such a CMOS, the on-resistance value in the path through which the second transistor Q2 turns on can be made greater than the on-resistance value in the path through which the second transistor Q2 turns off. As a result, it becomes possible to make the drive force for turning off the second transistor Q2 higher than the drive force for turning on the second transistor Q2.

[0089] This configuration makes it possible to avoid the simultaneous turning on of the first transistor Q1 and the second transistor Q2, even when the slew rate of the voltage applied to the power supply voltage terminal VDD is high, or when the voltage oscillates.

[0090] Figure 9 shows another implementation example of the voltage comparison circuit 22. As shown in this figure, a hysteresis comparator may be used as the voltage comparison circuit.

[0091] (Implementation Example 4) Figure 10 is a circuit diagram showing the configuration of the semiconductor device 1 according to implementation example 3. In addition to the first circuit 20 and the second circuit 30 in Figure 1, the semiconductor device 1 further includes a third circuit 40.

[0092] The third circuit 40 is a circuit that, when the VDD power supply has not yet been started and a voltage is applied between the drain terminal DRAIN and the source terminal SOURCE, prevents a charging current from being drawn to the capacitor 50 connected outside the semiconductor device 1 between the power supply voltage and the ground voltage, and also prevents an overvoltage from being applied to the gate of the first transistor Q1.

[0093] When the capacitor 50 is charged, current flows through each component of the semiconductor device 1 based on this charged voltage. For example, this current attempts to flow in the following order: drain terminal DRAIN, first transistor Q1, power supply voltage terminal VDD, capacitor 50, ground terminal GND, body diode of the element that switches the first transistor Q1 in the third circuit 40, first diode 10, and source terminal SOURCE. The third circuit 40 prevents this current from flowing.

[0094] Figure 11 is a circuit diagram showing one implementation example of the third circuit 40. The third circuit 40 comprises a first switch 400, a second switch 401, a sixth resistor 402, a fourth diode 403, and a fifth diode 404.

[0095] The first switch 400 is, for example, a p-type MOSFET, with its source connected to the power supply voltage terminal VDD, its gate connected to the inverter output, and its inverter input connected to the gate voltage application terminal GATE.

[0096] The second switch 401 is, for example, an n-type MOSFET, with its source connected to the ground terminal GND, its gate connected to the inverter output, and its inverter input connected to the gate voltage application terminal GATE.

[0097] The sixth resistor 402 has one end connected to the drain of the first switch 400 and the other end connected to the gate of the first transistor Q1. The sixth resistor 402 acts as a gate resistor that controls the gate current of the first transistor Q1.

[0098] The fourth diode 403 has its anode connected to the anode of the first diode 10 and the gate of the first transistor Q1, and its cathode connected to the power supply voltage terminal VDD.

[0099] The fifth diode 404 has its anode connected to the drain of the first switch 400 and its gate connected to the first transistor Q1 via the sixth resistor 402, and its cathode connected to the drain of the second switch 401.

[0100] In this configuration, the current flowing through the body diode of the second switch 401 for turning off the first transistor Q1 can be prevented by the fifth diode 404 connected between the second switch 401 and the first switch 400 and the sixth resistor 402. Furthermore, the connection of this fifth diode 404 prevents the body diode of the second switch 401 from clamping the gate voltage of the first transistor Q1 when it falls below the ground voltage GND. However, this can be prevented by connecting the fourth diode 403 between the gate of the first transistor Q1 and the power supply voltage terminal VDD.

[0101] As described above, the third circuit 40 in this implementation example makes it possible to prevent both the charging current to the capacitor 50 and the overvoltage of the gate voltage of the first transistor Q1.

[0102] (Implementation Example 5) Figure 12 is a circuit diagram showing another implementation example of the third circuit 40. The third circuit 40 comprises a first switch 400, a second switch 401, a sixth resistor 402, a fourth diode 403, and a sixth diode 405.

[0103] The first switch 400 is, for example, a p-type MOSFET, with its source connected to the power supply voltage terminal VDD, its gate connected to the inverter output, and its inverter input connected to the gate voltage application terminal GATE.

[0104] The second switch 401 is, for example, an n-type MOSFET, with its source connected to the ground terminal GND, its gate connected to the inverter output, and its inverter input connected to the gate voltage application terminal GATE.

[0105] The sixth resistor 402 has one end connected to the drain of the first switch 400 and the other end connected to the gate of the first transistor Q1. The sixth resistor 402 acts as a gate resistor that controls the gate current of the first transistor Q1.

[0106] The fourth diode 403 has its anode connected to the anode of the first diode 10 and the gate of the first transistor Q1, and its cathode connected to the power supply voltage terminal VDD.

[0107] The sixth diode 405 has its anode connected to the gate of the first transistor Q1 and its cathode connected to the drain of the second switch 401.

[0108] The current passing through the body diode of the second switch 401, which turns off the first transistor Q1, can be prevented by the sixth diode 405 connected between the second switch 401 and the gate of the first transistor Q1. In implementation example 4, the gate resistance is present in both the turn-on and turn-off gate current paths of the first transistor Q1, making it difficult to independently adjust the driving force. However, in this implementation example, the sixth diode 405 alone can independently adjust the driving force of the turn-on and turn-off gate current paths of the first transistor Q1, and it is also possible to prevent the charging current of the capacitor, similar to the implementation example above.

[0109] (Implementation Example 6) Figure 13 is a circuit diagram showing another implementation example of the third circuit 40. The third circuit 40 comprises a first switch 400, a second switch 401, a sixth resistor 402, a fourth diode 403, and a third switch 406.

[0110] The first switch 400 is, for example, a p-type MOSFET, with its source connected to the power supply voltage terminal VDD, its gate connected to the inverter output, and its inverter input connected to the gate voltage application terminal GATE.

[0111] The second switch 401 is, for example, an n-type MOSFET, with its source connected back-to-back with the third switch 406, its gate connected to the inverter output, and its inverter input connected to the gate voltage application terminal GATE.

[0112] The sixth resistor 402 has one end connected to the drain of the first switch 400 and the other end connected to the gate of the first transistor Q1. The sixth resistor 402 acts as a gate resistor that controls the gate current of the first transistor Q1.

[0113] The fourth diode 403 has its anode connected to the anode of the first diode 10 and the gate of the first transistor Q1, and its cathode connected to the power supply voltage terminal VDD.

[0114] The third switch 406 is, for example, an n-type MOSFET, with its drain connected to the ground terminal GND, its gate connected to the gate voltage application terminal GATE, and its source connected back-to-back with the source of the second switch 401.

[0115] The current passing through the second switch 401 that turns off the first transistor Q1 can be prevented by forming a bidirectional switch with the third switch 406 connected between the second switch 401 and ground potential. In the aforementioned implementation example 5, when the first transistor Q1 is turned off, the drive force for turning it off is weakened by the forward voltage of the sixth diode 405 in the gate current path. However, with the configuration of this implementation example, when the first transistor Q1 is turned off, this voltage is the product of the on-resistance of the third switch 406 and the gate current. Therefore, by using a switch element with low on-resistance as the third switch 406, the drive force for turning it off can be strengthened.

[0116] As a result, even when a high voltage slew rate is applied between the drain and source of the first transistor Q1, the impedance of the turn-off current path by the second switch 401 and the third switch 406 is kept low, thereby preventing the first transistor Q1 from being accidentally turned on.

[0117] According to the embodiments described above, the first transistor Q1 and the second transistor Q2 can be appropriately controlled without increasing the gate current loop for driving the first transistor Q1, thereby changing the normally-on driven first transistor Q1 to a normally-off driven state. This semiconductor device 1 makes it possible to form a switch that can withstand high voltages when an external load, for example, a high voltage of about 140V to 400V is applied, and that can be safely driven in the normally-off state.

[0118] In the embodiments described above, the second transistor Q2 is provided outside the semiconductor device 1, but the semiconductor device 1 may also be equipped with the second transistor Q2. In this case, the semiconductor device 1 may be connected to the gate and source of the first transistor Q1 and may have an output terminal that outputs the drain current of the first transistor Q1.

[0119] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0120] 1: Semiconductor device, Q1: First transistor, Q2: Second transistor, 10: First diode, 20: 1st circuit, 200: 1st resistor, 201: 2nd diode, 202: 3rd transistor, 203: 2nd resistor, 210: 5th transistor, 211: 3rd diode, 30: 2nd circuit, 300: 4th transistor, 301: 3rd resistor

Claims

1. A semiconductor device for normally-off driving a normally-on type n-type first transistor, wherein the first terminal is connected to the drain terminal, the second terminal is connected to the power supply voltage and the first terminal of a p-type second transistor, and the second terminal of the second transistor is connected to the source terminal, A first diode, whose anode is connected to the gate of the first transistor and whose cathode is connected to the second terminal of the second transistor, A first resistor, one end of which is connected to the power supply voltage, A p-type third transistor, whose gate is connected to the other end of the first resistor and whose first end is connected to the power supply voltage, A second diode is a Zener diode whose anode is connected to the ground voltage, whose cathode is connected to the gate of the third transistor, and which has a Zener voltage that is greater than or equal to the absolute value of the threshold voltage of the first transistor and lower than the steady-state value of the power supply voltage. A second resistor, one end of which is connected to the second terminal of the third transistor and the other end of which is connected to the ground voltage, A p-type fourth transistor, whose gate is connected to the second terminal of the third transistor, whose first terminal is connected to the power supply voltage, and whose second terminal is connected to the gate of the second transistor, A third resistor, one end of which is connected to the second terminal of the fourth transistor and the other end of which is connected to the ground voltage, An n-type first MOSFET is provided, wherein a drive voltage is input to the gate of the first transistor via an inverter to turn it on in normally-off mode, and the second terminal is connected to the ground voltage. A fourth diode, the anode of which is connected to the anode of the first diode and the cathode of which is connected to the first terminal of the first MOSFET, A semiconductor device equipped with the following features.

2. A semiconductor device for normally-off driving a normally-on type n-type first transistor, wherein the first terminal is connected to the drain terminal, the second terminal is connected to the power supply voltage and the first terminal of a p-type second transistor, and the second terminal of the second transistor is connected to the source terminal, A first diode, whose anode is connected to the gate of the first transistor and whose cathode is connected to the second terminal of the second transistor, A normally-on driven n-type fifth transistor, with its first terminal connected to the power supply voltage, its gate connected to the ground voltage, and its second terminal connected to the gate of the second transistor, A third diode is a Zener diode whose anode is connected to the ground voltage, whose cathode is connected to the second terminal of the fifth transistor, and which has a Zener voltage that is greater than or equal to the absolute value of the threshold voltage of the first transistor and lower than the voltage obtained by subtracting the absolute value of the threshold voltage of the second transistor from the power supply voltage. An n-type first MOSFET is provided, wherein a drive voltage is input to the gate of the first transistor via an inverter to turn it on in normally-off mode, and the second terminal is connected to the ground voltage. A fourth diode, the anode of which is connected to the anode of the first diode and the cathode of which is connected to the first terminal of the first MOSFET, A semiconductor device equipped with the following features.

3. A semiconductor device for normally-off driving a normally-on type n-type first transistor, wherein the first terminal is connected to the drain terminal, the second terminal is connected to the power supply voltage and the first terminal of a p-type second transistor, and the second terminal of the second transistor is connected to the source terminal, A reference voltage generation circuit that generates a reference voltage, A voltage comparison circuit compares the aforementioned reference voltage with the power supply voltage. A buffer is connected between the output terminal of the voltage comparison circuit and the gate of the second transistor, A first diode, whose anode is connected to the gate of the first transistor and whose cathode is connected to the second terminal of the second transistor, An n-type first MOSFET is provided, wherein a drive voltage that turns on the first transistor via an inverter in normally-off mode is input to the gate, and the second terminal is connected to the ground voltage. A fourth diode, the anode of which is connected to the anode of the first diode and the cathode of which is connected to the first terminal of the first MOSFET, A semiconductor device equipped with the following features.

4. A semiconductor device for normally-off driving a normally-on type n-type first transistor, wherein the first terminal is connected to the drain terminal, the second terminal is connected to the power supply voltage and the first terminal of a p-type second transistor, and the second terminal of the second transistor is connected to the source terminal, A first circuit connected to the power supply voltage and the ground voltage, which outputs when the power supply voltage has risen above a predetermined voltage and when the power supply voltage has fallen below a predetermined voltage, A second circuit is connected to the power supply voltage, the ground voltage, the first circuit, and the gate of the second transistor, and outputs a voltage to drive the second transistor to turn on after the first transistor is turned off and to turn off the second transistor before the first transistor is turned on, based on the output of the first circuit. A first diode, whose anode is connected to the gate of the first transistor and whose cathode is connected to the second terminal of the second transistor, An n-type first MOSFET is provided, wherein a drive voltage is input to the gate of the first transistor via an inverter to turn it on in normally-off mode, and the second terminal is connected to the ground voltage. A fourth diode, the anode of which is connected to the anode of the first diode and the cathode of which is connected to the first terminal of the first MOSFET, A semiconductor device equipped with the following features.

5. A semiconductor device for normally-off driving a normally-on type n-type first transistor, wherein the first terminal is connected to the drain terminal, the second terminal is connected to the power supply voltage and the first terminal of a p-type second transistor, and the second terminal of the second transistor is connected to the source terminal, A first diode, whose anode is connected to the gate of the first transistor and whose cathode is connected to the second terminal of the second transistor, A first resistor, one end of which is connected to the power supply voltage, A p-type third transistor, whose gate is connected to the other end of the first resistor and whose first end is connected to the power supply voltage, A second diode is a Zener diode whose anode is connected to the ground voltage, whose cathode is connected to the gate of the third transistor, and which has a Zener voltage that is greater than or equal to the absolute value of the threshold voltage of the first transistor and lower than the steady-state value of the power supply voltage. A second resistor, one end of which is connected to the second terminal of the third transistor and the other end of which is connected to the ground voltage, A p-type fourth transistor, whose gate is connected to the second terminal of the third transistor, whose first terminal is connected to the power supply voltage, and whose second terminal is connected to the gate of the second transistor, A third resistor, one end of which is connected to the second terminal of the fourth transistor and the other end of which is connected to the ground voltage, An n-type first MOSFET is provided, wherein a drive voltage is input to the gate of the first transistor via an inverter to turn it on in normally-off mode, and the first terminal is connected to the anode of the first diode. A fifth diode is provided, the anode of which is connected to the second terminal of the first MOSFET and the cathode of which is connected to the ground voltage. A semiconductor device equipped with the following features.

6. A semiconductor device for normally-off driving a normally-on type n-type first transistor, wherein the first terminal is connected to the drain terminal, the second terminal is connected to the power supply voltage and the first terminal of a p-type second transistor, and the second terminal of the second transistor is connected to the source terminal, A first diode, whose anode is connected to the gate of the first transistor and whose cathode is connected to the second terminal of the second transistor, A normally-on driven n-type fifth transistor, with its first terminal connected to the power supply voltage, its gate connected to the ground voltage, and its second terminal connected to the gate of the second transistor, A third diode is a Zener diode whose anode is connected to the ground voltage, whose cathode is connected to the second terminal of the fifth transistor, and which has a Zener voltage that is greater than or equal to the absolute value of the threshold voltage of the first transistor and lower than the voltage obtained by subtracting the absolute value of the threshold voltage of the second transistor from the power supply voltage. An n-type first MOSFET is provided, wherein a drive voltage is input to the gate of the first transistor via an inverter to turn it on in normally-off mode, and the first terminal is connected to the anode of the first diode. A fifth diode is provided, the anode of which is connected to the second terminal of the first MOSFET and the cathode of which is connected to the ground voltage. A semiconductor device equipped with the following features.

7. A semiconductor device for normally-off driving a normally-on type n-type first transistor, wherein the first terminal is connected to the drain terminal, the second terminal is connected to the power supply voltage and the first terminal of a p-type second transistor, and the second terminal of the second transistor is connected to the source terminal, A reference voltage generation circuit that generates a reference voltage, A voltage comparison circuit compares the aforementioned reference voltage with the power supply voltage. A buffer is connected between the output terminal of the voltage comparison circuit and the gate of the second transistor, A first diode, whose anode is connected to the gate of the first transistor and whose cathode is connected to the second terminal of the second transistor, An n-type first MOSFET is provided, wherein a drive voltage is input to the gate of the first transistor via an inverter to turn it on in normally-off mode, and the first terminal is connected to the anode of the first diode. A fifth diode is provided, the anode of which is connected to the second terminal of the first MOSFET and the cathode of which is connected to the ground voltage. A semiconductor device equipped with the following features.

8. A semiconductor device for normally-off driving a normally-on type n-type first transistor, wherein the first terminal is connected to the drain terminal, the second terminal is connected to the power supply voltage and the first terminal of a p-type second transistor, and the second terminal of the second transistor is connected to the source terminal, A first circuit connected to the power supply voltage and the ground voltage, which outputs when the power supply voltage has risen above a predetermined voltage and when the power supply voltage has fallen below a predetermined voltage, A second circuit is connected to the power supply voltage, the ground voltage, the first circuit, and the gate of the second transistor, and outputs a voltage to drive the second transistor to turn on after the first transistor is turned off and to turn off the second transistor before the first transistor is turned on, based on the output of the first circuit. A first diode, whose anode is connected to the gate of the first transistor and whose cathode is connected to the second terminal of the second transistor, An n-type first MOSFET is provided, wherein a drive voltage is input to the gate of the first transistor via an inverter to turn it on in normally-off mode, and the first terminal is connected to the anode of the first diode. A fifth diode is provided, the anode of which is connected to the second terminal of the first MOSFET and the cathode of which is connected to the ground voltage. A semiconductor device equipped with the following features.

9. The first transistor is a FET using GaN (gallium nitride) whose source is connected to the power supply voltage. The second transistor is a p-type MOSFET whose source is connected to the source of the first transistor. The semiconductor device according to any one of claims 1 to 8.

10. A third resistor and a fourth resistor connected in series between the power supply voltage and the ground voltage, A fifth resistor and a switch are connected in series between the node connected to the third resistor and the fourth resistor and the ground voltage, The semiconductor device according to claim 3 or claim 7, wherein the output terminal of the voltage comparison circuit is connected to the control input terminal of the switch.

11. A semiconductor device according to any one of claims 1 to 4, further comprising a sixth resistor connected between the first diode and the fourth diode.

12. The semiconductor device according to any one of claims 5 to 8, wherein the fifth diode is a body diode of a second MOSFET, the gate of which is connected to the gate of the first MOSFET, the first end of which is connected to the second end of the first MOSFET, and the second end of which is connected to the ground voltage.

13. The semiconductor device according to claim 12, wherein the second MOSFET is an n-type MOSFET.

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