Diode wafer and manufacturing method of wafer to be processed

Abstract

To provide high-quality diode wafers and a method for manufacturing processed wafer.SOLUTION: A method determines whether a plurality of raw wafers meet a manufacturing specification. If it is determined that the raw wafer meets the manufacturing specification, the raw wafer is determined as a high-level raw wafer. If it is determined that the raw wafer does not meet the manufacturing specification, the raw wafer is determined as a low-level raw wafer. Next, the method, calculates a ratio of the quantity of low-level raw wafers having problems related to crystal orientation pits to the quantity of all low-level raw wafers, and determines whether this ratio is greater than a predetermined value. If it is determined that the ratio is not greater than the predetermined value, the method removes a partial structure of each of the low-level raw wafers, and smooths the surface of each of the low-level raw wafers. Finally, the method forms a diode structure on the smoothed low-level raw wafer to obtain a diode wafer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a wafer, and more particularly to a method for manufacturing a diode wafer and a processed wafer.

Background Art

[0002] In the semiconductor process, wafers are manufactured from ingots. First, an appropriate material is selected to manufacture an ingot. Common materials include silicon, gallium arsenide, etc. The selected material is put into a high-temperature melting furnace and melted. It is necessary to appropriately control the temperature and gas conditions of the melting furnace so that the material is uniformly melted and reaches the required purity. Among the melted materials, a crystal (usually single-crystal silicon) called a "seed crystal" is gently put in and slowly raised. In the rising process, the crystal grabs the seed crystal from the molten material and forms a single large ingot. The ingot is gradually cooled during the process of being pulled out to form a single-crystal structure. The cooling rate and temperature control during the process are important for the quality of the ingot, ensuring the purity and integrity of the ingot. After the ingot is cooled, it is cut to form wafers of the required diameter. Usually, a diamond cutter or other cutting tools are used for cutting. The cut wafers are subjected to chemical or mechanical treatment to remove surface residues, contaminants, and defects, and make their surfaces flat and clean. Then, the wafers are polished to further improve the surface flatness and optical quality. Finally, the manufactured wafers are washed to remove any residues and contaminants. Then, the wafers are inspected and tested to meet specific quality standards.

Summary of the Invention

Problems to be Solved by the Invention

[0003] In semiconductor manufacturing, A-grade wafers and B-grade wafers define the quality and specifications of wafers. These definitions are typically achieved through consultations between semiconductor manufacturers, the International Organization for Standardization (ISO), and customers. Generally, A-grade wafers have high quality standards in terms of surface flatness, uniformity of wafer thickness, and integrity of the crystal lattice structure. B-grade wafers have relatively lower quality standards, are typically used in general applications, and do not require extremely high performance and reliability. A-grade wafers have a low defect density, meaning there are few defects on the wafer surface or within its volume. B-grade wafers have a high defect density, which means there is a possibility of many defects on the wafer surface or within its volume. A-grade wafers have strict specification controls in terms of size, wafer thickness, wafer flatness, and crystal lattice orientation, ensuring process consistency and repeatability. B-grade wafers have relatively looser specification controls in terms of size, flatness, and crystal lattice orientation, and are not as strict as A-grade wafers. Generally, processed wafers include low-level, mid-level, and high-level wafers. However, the market price of high-grade wafers did not fall easily. For example, diode wafers include low-grade, mid-grade, and high-grade diode wafers. Due to the selling price of the wafers, many low-grade diode wafers used low-quality A-grade wafers, resulting in poor quality. Also, many mid-grade diode wafers used high-quality A-grade wafers, but due to the difference in substrate costs, they could not compete with mid- / low-grade diode wafers.

[0004] Therefore, the inventors believed that the above-mentioned drawbacks could be improved, and after diligent research, they arrived at the proposal of the present invention, a method for manufacturing diode wafers and workpiece wafers that effectively improves the above-mentioned problems through rational design.

[0005] This invention has been made in view of the above circumstances, and its objective is to provide a method for manufacturing diode wafers and processed wafers that can produce high-quality diode wafers and processed wafers at low cost. [Means for solving the problem]

[0006] A method for manufacturing a diode wafer according to one aspect of the present invention involves processing a plurality of raw wafers obtained by slicing from an ingot. The method for manufacturing a diode wafer includes the steps of: determining whether the plurality of raw wafers conform to manufacturing specifications; if it is determined that they conform, the raw wafers are made into high-grade raw wafers; if it is determined that they do not conform, the raw wafers are made into low-grade raw wafers, and the quantity of low-grade raw wafers is multiple; calculating the ratio of the quantity of low-grade raw wafers having problems related to crystal orientation pits (COP) to the total quantity of low-grade raw wafers, and determining whether this ratio is greater than a predetermined value; if it is determined that it is greater, terminating the process; and if it is determined that it is not greater, removing a partial structure from each of the low-grade raw wafers, the partial structure having a fixed thickness; smoothing the surface of each of the low-grade raw wafers from which the structure has been removed; and forming a plurality of diode structures on each of the smoothed low-grade raw wafers to obtain a diode wafer.

[0007] Furthermore, in the method for manufacturing a diode wafer according to the present invention, the items of the manufacturing specifications include electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indicator reading, wafer warpage, partial total indicator reading, and dust count.

[0008] Furthermore, in the method for manufacturing a diode wafer according to the present invention, the defects include chipping, cracks, excess laser engraving, scratches, stains, and fractures in the crystal lattice.

[0009] Furthermore, in the diode wafer manufacturing method according to the present invention, in the step of removing each partial structure of a low-grade raw wafer, a low-grade raw wafer having a thickness greater than a predetermined value is selected, and each partial structure of the selected low-grade raw wafer is removed.

[0010] Furthermore, in the diode wafer manufacturing method according to the present invention, an etching process and a mirror finishing process are sequentially performed on each surface of the low-grade raw wafer from which the structure has been removed, thereby smoothing each surface of the low-grade raw wafer from which the structure has been removed.

[0011] Furthermore, in the diode wafer manufacturing method according to the present invention, a grinding process and a mirror finishing process are sequentially performed on each surface of the low-grade raw wafer from which the structure has been removed, thereby smoothing each surface of the low-grade raw wafer from which the structure has been removed.

[0012] Furthermore, in the diode wafer manufacturing method according to the present invention, the diode wafer manufacturing method further includes the step of roughening the surface of each of the smoothed low-grade raw wafers. In the step of forming a plurality of diode structures on each of the smoothed low-grade raw wafers to obtain a diode wafer, the plurality of diode structures are formed on each of the roughened low-grade raw wafers to obtain a diode wafer.

[0013] Furthermore, in the diode wafer manufacturing method according to the present invention, each surface of the smoothed low-grade raw wafer is roughened by bench etching or spin etching.

[0014] Furthermore, in the method for manufacturing a diode wafer according to the present invention, the method for manufacturing a diode wafer further includes the step of forming a metal conductive layer on the surface of the diode wafer.

[0015] Furthermore, in the method for manufacturing a diode wafer according to the present invention, the diode structure comprises a doping well region, a first high-concentration doped region, and a second high-concentration doped region. The doping well region and the first high-concentration doped region have a first conductivity type, and the doping well region is located on a smoothed low-level raw wafer. The first high-concentration doped region is located in the doping well region. The second high-concentration doped region has a second conductivity type opposite to the first conductivity type, and the second high-concentration doped region is located in the doping well region.

[0016] Another aspect of the present invention relates to a method for manufacturing a wafer to be processed, which involves processing a plurality of raw wafers obtained by slicing from an ingot. The method for manufacturing a wafer to be processed includes the steps of: determining whether the plurality of raw wafers conform to manufacturing specifications; if they conform, making the raw wafers high-grade raw wafers; if they do not conform, making the raw wafers low-grade raw wafers, with a quantity of multiple low-grade raw wafers; calculating the ratio of the quantity of low-grade raw wafers having problems related to crystal-oriented pits (COP) to the total quantity of low-grade raw wafers, and determining whether this ratio is greater than a predetermined value; if it is greater, terminating the process; and if it is not greater, removing the partial structure of each low-grade raw wafer, the partial structure having a fixed thickness; and smoothing the surface of each of the low-grade raw wafers from which the structure has been removed to obtain a wafer to be processed.

[0017] Furthermore, in the method for manufacturing a wafer according to the present invention, the items of the manufacturing specifications include electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indicator readings, wafer warpage, some total indicator readings, and dust count.

[0018] Furthermore, in the method for manufacturing a wafer according to the present invention, the defects include chipping, cracks, excess laser engraving, scratches, stains, and fractures in the crystal lattice.

[0019] Furthermore, in the method for manufacturing a wafer to be processed according to the present invention, in the step of removing each partial structure of a low-grade raw wafer, a low-grade raw wafer having a thickness greater than a predetermined value is selected, and each partial structure of the selected low-grade raw wafer is removed.

[0020] Furthermore, in the method for manufacturing a wafer to be processed according to the present invention, an etching process and a mirror finishing process are sequentially performed on each surface of the low-grade raw wafer from which the structure has been removed, thereby smoothing each surface of the low-grade raw wafer from which the structure has been removed.

[0021] Furthermore, in the method for manufacturing a wafer to be processed according to the present invention, a grinding process and a mirror finishing process are sequentially performed on each surface of the low-grade raw wafer from which the structure has been removed, thereby smoothing each surface of the low-grade raw wafer from which the structure has been removed.

[0022] Furthermore, in the method for manufacturing a wafer to be processed according to the present invention, the method for manufacturing a wafer to be processed further includes the step of roughening each surface of the smoothed low-grade raw wafer.

[0023] Also, in the method for manufacturing a wafer to be processed according to the present invention, the surface of each of the smoothed lower-level raw wafers is roughened by bench etching or spin etching.

Effect of the Invention

[0024] As described above, the method for manufacturing a diode wafer and a wafer to be processed selects lower-level raw wafers of suitable quality based on the presence of crystal oriented pits (COP), and manufactures high-quality diode wafers and wafers to be processed at low cost.

[0025] From the descriptions in the following specification and drawings, at least the following matters will become clear.

Brief Description of the Drawings

[0026] [Figure 1] It is a flowchart showing a method for manufacturing a diode wafer according to an embodiment of the present invention. [Figure 2] It is a cross-sectional view showing the configuration of a diode wafer according to an embodiment of the present invention. [Figure 3] It is a flowchart showing a method for manufacturing a wafer to be processed according to an embodiment of the present invention.

Mode for Carrying Out the Invention

[0027] Hereinafter, embodiments of the present invention will be described while disclosing the drawings. In the drawings and the specification, the same reference numerals indicate the same or similar members. In the drawings, for the sake of simplicity or display convenience, the shape and thickness may be enlarged for display. It should be noted that elements not disclosed in the drawings or described in the specification are obvious to those skilled in the art. Those skilled in the art can make various changes and improvements based on the content of the present invention. Unless otherwise specified, conditional statements or words such as "can" or "might" are often intended to express features, components, or steps that are present in this embodiment but may also be interpreted as unnecessary. In other embodiments, these features, components, or steps may not be necessary. In this specification, the phrase "one embodiment" or "example" refers to a specific element, structure, or feature relating to at least one embodiment. Therefore, the phrase "one embodiment" or "example" in this specification does not necessarily refer to the same embodiment. Furthermore, specific components, structures, and features described in multiple embodiments can be appropriately combined. Within this specification and the scope of this patent application, certain terms are used to refer to specific components. However, a person skilled in the art will understand that the same component may be referred to by different terms. The specification and the scope of the patent application distinguish components based on functional differences rather than differences in name. The term “inclusion” within this specification and the scope of the patent application is an open-ended term and should be interpreted as “including, but not limited to.” Furthermore, “connection” or “bonding” within this specification includes all direct and indirect means of connection. Thus, where it is stated in this specification that a first element is connected to a second element, it means that the first element may be directly connected to the second element by an electrical or signaling connection such as wireless transmission or optical transmission, or it may be indirectly connected to the second element electrically or signaling by some other element or means of connection. The following is merely illustrative, and it will be understood by those skilled in the art that various modifications are possible, and that such modifications also fall within the scope of the present invention. The scope of the present invention is defined by the appended claims. In the specification and claims, "one" and "the foregoing" refer to "one or at least one" element or component unless otherwise specified. Also, singular articles include the meaning of multiple elements or components unless it is clearly indicated as plural from the surrounding sentences. In addition, "inside" includes the meaning of "inside" and "on top" unless otherwise specified. Unless otherwise specified, the terms used in the specification and claims have the same meaning as understood by those skilled in the art. In addition, some specific terms will be clearly defined and explained below. The terms used in the specification are merely illustrative and do not limit the scope of the present invention. Furthermore, the present invention is not limited to the following embodiments. The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0028] In the specification and claims, when it is stated that the first member is located on the second member, it means that the first member is connected, joined, or bonded to the second member above the second member, or connected to the second member, and the first member is directly located on the second member, and is directly connected, joined, or bonded to the second member, and other members may exist between the first member and the second member. Relatively, when it is stated that the first member is directly located on the second member, it means that the first member is directly connected, joined, bonded, or bonded to the second member, and no other members exist between the first member and the second member.

[0029] The following description provides a method for manufacturing diode wafers and workpiece wafers. This method involves selecting high-quality, low-grade raw wafers based on issues related to crystal-oriented pits (COP), thereby enabling the low-cost production of high-quality diode wafers and workpiece wafers.

[0030] Figure 1 is a flowchart showing a method for manufacturing a diode wafer according to one embodiment of the present invention. Next, an example of a specific embodiment of the method for manufacturing a diode wafer according to the present invention will be described with reference to Figure 1. Multiple raw wafers obtained by slicing from an ingot are processed. These wafers have their surfaces smoothed through grinding, etching, and mirror finishing processes. While silicon wafers are used as an example of raw wafers, the present invention is not limited thereto. First, as shown in step S10, it is determined whether the multiple raw wafers conform to the manufacturing specifications. If it is determined that the raw wafers conform to the manufacturing specifications, the raw wafers are made into high-grade raw wafers, as shown in step S12. If it is determined that the raw wafers do not conform to the manufacturing specifications, the raw wafers are made into low-grade raw wafers, as shown in step S14. For example, the manufacturing specifications include, but are not limited to, electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indicator readings, wafer warp, some total indicator readings, and dust count. Defects include, but are not limited to, chipping, cracks, excess laser engraving, scratches, stains, and crystal lattice fractures. Total thickness deviation is defined as the difference between the maximum and minimum distances from the thickness of the reference plane in the context in which the wafer is clamped. It is generally expressed in micrometers (μm), and a common expression is, for example, ≤15μm. The total indicator reading is defined as the difference between the maximum and minimum distances between the wafer surface and the reference plane, with the smallest plane formed by the sum of the intercepts of all points within the appropriate mass area of ​​the wafer surface being used as the reference plane when the wafer is clamped. Wafer warpage is defined as the difference between the minimum and maximum distances between the wafer surface being measured and the reference plane, usually with the back surface of the wafer being used as the reference plane when the wafer is not clamped. Wafer warpage includes both concave and convex conditions, with a negative curvature for concave conditions and a positive curvature for convex conditions.Generally, measurements are expressed in micrometers, with a common expression being, for example, ≤30 μm. Some total indicator readings are defined as the difference between the maximum and minimum distances between the wafer surface and the reference plane, where the smallest plane formed by the sum of the intercepts of all points within a defined area on the wafer surface is the reference plane in the context of the wafer clamping situation. Table 1 provides the manufacturing specifications. A raw wafer is considered a low-grade raw wafer if it is determined not to meet one of the manufacturing specifications. A raw wafer is considered a high-grade raw wafer if it is determined to meet all of the manufacturing specifications. Furthermore, a raw wafer is considered a low-grade raw wafer if defects, black film, or color film are observed. A raw wafer is considered a high-grade raw wafer if no defects, black film, or color film are observed.

[0031] [Table 1]

[0032] Generally, the quantity of low-grade raw wafers obtained by cutting from an ingot is always multiple. Step S18 is performed after step S14. In step S18, the ratio of the quantity of low-grade raw wafers having problems related to crystal-oriented pits (COP) to the total quantity of low-grade raw wafers is calculated, and it is determined whether this ratio is greater than a predetermined value. Crystal-oriented pits cannot be easily removed in etching, grinding, or mirror-finishing processes, and crystal-oriented pits are observed using tools such as optical microscopes or electron microscopes. Problems related to crystal-oriented pits are defined as the inability of the corresponding low-grade raw wafer to pass the COP specification inspection set in the inspection equipment. For example, if the quantity of crystal-oriented pits on one low-grade raw wafer is greater than the set value, this low-grade raw wafer cannot pass the COP specification inspection set in the inspection equipment. If the quantity of selected low-grade raw wafers having problems related to crystal-oriented pits is 64, the total quantity of selected low-grade raw wafers is 100, and the ratio is 0.64. The appearance of crystal orientation pits indicates the presence of holes that should not be there during diode manufacturing and wafer etching. Diode manufacturing requires processing of silicon wafers. During processing, processes such as ion implantation or diffusion are performed using the silicon wafer as a substrate. In areas with holes, the silicon wafer is absent. Therefore, it cannot withstand the necessary processes, causing the electrical characteristics of the diode itself to drift, leading to defects and a decrease in yield. Furthermore, diode manufacturing sometimes requires drilling and filling with necessary materials. If the COP (Chip-on-Chip) is poor, there is a very high probability of excessive dust being present after drilling, causing problems in subsequent processes. This then leads to drift in the electrical characteristics of the diode itself, resulting in defects and a decrease in yield. Therefore, a suitable silicon wafer substrate supports the diode and prevents material problems from reducing the overall process yield.In other words, if the number of selected low-level raw wafers having problems related to crystal orientation pits is greater than a predetermined value relative to the total number of selected low-level raw wafers, it indicates that the yield of diode wafers manufactured from this lot of low-level raw wafers has decreased significantly, and the process proceeds to step S20, ending the entire flowchart. If the number of selected low-level raw wafers having problems related to crystal orientation pits is not greater than a predetermined value relative to the total number of selected low-level raw wafers, it indicates that the yield of diode wafers manufactured from this lot of low-level raw wafers has increased significantly, and that low-level raw wafers are inexpensive and have a very high market value. That is, if the result of the judgment in step S18 is negative, the process proceeds to step S22. In step S22, low-level raw wafers with a thickness greater than a predetermined value are selected, and each partial structure of the selected low-level raw wafer is removed. Since this partial structure has a fixed thickness, the observed crystal orientation pits are removed. This fixed thickness is determined by the depth at which the observed crystal orientation pits are located. For example, if an observed crystal orientation pit is located at a depth of 7 micrometers from the surface, it indicates that the fixing thickness is 7 micrometers.

[0033] Step S24 is performed after step S22. In step S24, each surface of the destructured low-grade raw wafer is smoothed to remove surface stains, chemical films, or scratches to the extent that the flatness and number of fine particles of the surface of the low-grade raw wafer are determined. In some embodiments of the present invention, an etching process and a polishing process are sequentially performed on each surface of the destructured low-grade raw wafer to smooth each surface of the destructured low-grade raw wafer. Alternatively, a grinding process and a mirror-finishing process are sequentially performed on each surface of the destructured low-grade raw wafer to smooth each surface of the destructured low-grade raw wafer.

[0034] Step S26 is performed after step S24. In step S26, the surface of each smoothed low-grade raw wafer is roughened to improve the stability for bonding the metal layer. The surface of each smoothed low-grade raw wafer is roughened by bench etching or spin etching. Then, in step S28, multiple diode structures are formed on each of the roughened low-grade raw wafers to obtain a diode wafer. Finally, as shown in step S30, a metal conductive layer is formed on the surface of the diode wafer, and the metal conductive layer serves as the electrode of the diode. Step S30 is followed by step S20. These steps do not necessarily have to be performed in the order shown in Figure 1 if substantially the same results are to be obtained.

[0035] Figure 2 is a cross-sectional view showing the configuration of a diode wafer according to one embodiment of the present invention. As shown in the figure, each of the diode structures 10 comprises a doping well region 100, a first high-concentration doped region 102, and a second high-concentration doped region 104. The doping well region 100 and the first high-concentration doped region 102 have a first conductivity type, and the second high-concentration doped region 104 has a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is n type, the second conductivity type is p type. If the first conductivity type is p type, the second conductivity type is n type. The doping well region 100 is located on the roughened low-grade raw wafer 11. The first high-concentration doped region 102 is located on the doping well region 100, and the second high-concentration doped region 104 is located on the doping well region 100. The metal conductive layer 12 is located on the surface of the roughened low-grade raw wafer 11.

[0036] In the example shown in Figure 1, the step of selecting a low-grade raw wafer with a thickness greater than a predetermined value may be omitted, and in step S22, each partial structure of the low-grade raw wafer is removed. Step S26 may also be omitted. If step S26 is omitted, in step S28, multiple diode structures are formed on each of the smoothed low-grade raw wafers to obtain a diode wafer. Step S30 may be performed as needed or omitted. If step S30 is omitted, step S20 is performed directly after the completion of step S28.

[0037] Figure 3 is a flowchart showing a method for manufacturing a wafer according to one embodiment of the present invention. Next, an example of a specific embodiment of the method for manufacturing a wafer according to the present invention will be described with reference to Figure 3. Multiple raw wafers obtained by slicing from an ingot are processed. These wafers have their surfaces smoothed through grinding, etching, and mirror finishing processes. While silicon wafers are used as an example of raw wafers, the present invention is not limited thereto. Steps S32, S34, S36, S40, S42, and S44 in Figure 3 are the same as steps S10, S12, S14, S18, S20, and S22 in Figure 1, respectively, and similar points will not be explained. After the completion of step S44, step S46 is performed. In step S46, the surface of each of the low-level raw wafers from which the structure has been removed is smoothed to obtain a wafer to be manufactured. Any semiconductor component, such as diodes or elements of microelectromechanical systems (MEMS), can be formed on the wafer to be manufactured. In step S46, an etching process and a mirror finishing process are sequentially performed on each surface of the low-grade raw wafer from which the structure has been removed to smooth each surface of the low-grade raw wafer from which the structure has been removed. Alternatively, a grinding process and a mirror finishing process are sequentially performed on each surface of the low-grade raw wafer from which the structure has been removed to smooth each surface of the low-grade raw wafer from which the structure has been removed. Next, step S48 is performed to roughen each surface of the smoothed low-grade raw wafer to improve the stability for bonding the metal layer. Each surface of the smoothed low-grade raw wafer is roughened by bench etching or spin etching. After the completion of step S48, step S42 is performed.

[0038] In the example shown in Figure 3, the step of selecting a low-grade raw wafer with a thickness greater than a predetermined value may be omitted, and in step S44, each partial structure of the low-grade raw wafer is removed. Also, step S48 may be performed as needed or omitted. If step S48 is omitted, step S42 is performed directly after the completion of step S46.

[0039] According to the above-described embodiment, the method for manufacturing diode wafers and workpiece wafers produces high-quality diode wafers and workpiece wafers at low cost by selecting high-quality low-grade raw wafers based on problems related to crystal orientation pits.

[0040] The present invention is not limited to the embodiments described above, but rather within the scope of the claims. Various modifications are possible, and the technical means disclosed in different embodiments can be combined as appropriate. Embodiments obtained by combining these embodiments are also included within the technical scope of the present invention. This falls within the scope of protection of the present invention. The invention described in the original claims of this application is listed below. [Note 1] A method for manufacturing diode wafers, which involves processing multiple raw wafers obtained by slicing from an ingot, A step of determining whether the plurality of raw wafers conform to the manufacturing specifications, If it is determined that it is suitable, the raw wafer is made into a high-grade raw wafer, If it is determined that the wafer does not conform, the raw wafer is designated as a low-grade raw wafer, and the quantity of the low-grade raw wafers is multiple. The steps include: calculating the ratio of the quantity of low-grade raw wafers having problems related to crystal orientation pits (COP) to the total quantity of low-grade raw wafers, and determining whether the ratio is greater than a predetermined value; If it is determined to be large, the step to terminate is, If it is determined that the size is not large, the step is to remove each of the partial structures of the low-grade raw wafer, the partial structures having a fixed thickness, The steps include smoothing each surface of the lower-grade raw wafer from which the structure has been removed, A method for manufacturing a diode wafer, comprising the steps of: forming a plurality of diode structures on each of the smoothed low-level raw wafers to obtain a diode wafer. [Note 2] The method for manufacturing a diode wafer as described in Appendix 1, characterized in that the items of the manufacturing specifications include electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indicator reading, wafer warpage, partial total indicator reading, and dust count. [Note 3] The method for manufacturing a diode wafer according to Appendix 2, characterized in that the defects include chipping, cracking, excess laser engraving, scratching, staining, and fractures in the crystal lattice. [Note 4] The method for manufacturing a diode wafer according to Appendix 1, characterized in that, in the step of removing the partial structure of each of the low-grade raw wafers, a low-grade raw wafer having a thickness greater than a predetermined value is selected, and the partial structure of each of the selected low-grade raw wafers is removed. [Note 5] The method for manufacturing a diode wafer according to Appendix 1, characterized in that, in the step of smoothing each surface of the low-grade raw wafer from which the structure has been removed, an etching process and a mirror finishing process are sequentially performed on each surface of the low-grade raw wafer from which the structure has been removed, thereby smoothing each surface of the low-grade raw wafer from which the structure has been removed. [Note 6] A method for manufacturing a diode wafer according to Appendix 1, characterized in that, in the step of smoothing each surface of the low-grade raw wafer from which the structure has been removed, a grinding process and a mirror finishing process are sequentially performed on each surface of the low-grade raw wafer from which the structure has been removed, thereby smoothing each surface of the low-grade raw wafer from which the structure has been removed. [Note 7] A method for manufacturing a diode wafer according to Appendix 1, further comprising the step of roughening the surface of each of the smoothed low-grade raw wafers, forming a plurality of diode structures on each of the smoothed low-grade raw wafers, and obtaining the diode wafer, characterized in that the plurality of diode structures are formed on each of the roughened low-grade raw wafers, and the diode wafer is obtained. [Note 8] The method for manufacturing a diode wafer according to Appendix 7, characterized in that the surfaces of each of the smoothed low-grade raw wafers are roughened by bench etching or spin etching. [Note 9] The method for manufacturing a diode wafer according to Appendix 7, further comprising the step of forming a metal conductive layer on the surface of the diode wafer. [Note 10] The diode structure is A doping well region having a first conductivity type, wherein the doping well region is located on the smoothed low-level raw wafer, A first high-concentration doped region having the first conductivity type, wherein the first high-concentration doped region is located in the doping well region, A method for manufacturing a diode wafer according to Appendix 1, characterized in that it comprises a second highly concentrated doped region having a second conductivity type opposite to the first conductivity type, wherein the second highly concentrated doped region is located in the doping well region. [Note 11] A method for manufacturing a wafer to be processed, which involves processing multiple raw wafers obtained by slicing from an ingot, A step of determining whether the plurality of raw wafers conform to the manufacturing specifications, If it is determined that it is suitable, the steps are to make the raw wafer a high-grade raw wafer, If it is determined that the wafer is not suitable, the raw wafer is designated as a lower-grade raw wafer, and the quantity of the lower-grade raw wafers is multiple. A step of calculating the ratio of the quantity of low-grade raw wafers having problems related to crystal orientation pits (COP) to the total quantity of low-grade raw wafers, and determining whether the ratio is greater than a predetermined value, If it is determined to be large, the step to terminate is, If it is determined that the size is not large, the step is to remove each of the partial structures of the low-grade raw wafer, the partial structures having a fixed thickness, A method for manufacturing a wafer to be processed, comprising the steps of smoothing each surface of the low-grade raw wafers from which the structure has been removed to obtain a wafer to be processed. [Note 12] The method for manufacturing a wafer according to Appendix 11, characterized in that the items of the manufacturing specifications include electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indicator readings, wafer warpage, some total indicator readings, and dust count. [Note 13] The method for manufacturing a wafer to be processed according to Appendix 12, characterized in that the defects include chipping, cracking, excess laser engraving, scratching, staining, and fractures in the crystal lattice. [Note 14] The method for manufacturing a wafer to be processed according to Appendix 11, characterized in that, in the step of removing the partial structure of each of the low-grade raw wafers, a low-grade raw wafer having a thickness greater than a predetermined value is selected, and the partial structure of each of the selected low-grade raw wafers is removed. [Note 15] The method for manufacturing a wafer to be processed according to Appendix 11, characterized in that, in the step of smoothing each surface of the low-grade raw wafer from which the structure has been removed, an etching process and a mirror finishing process are sequentially performed on each surface of the low-grade raw wafer from which the structure has been removed, thereby smoothing each surface of the low-grade raw wafer from which the structure has been removed. [Note 16] The method for manufacturing a wafer to be processed according to Appendix 11, characterized in that, in the step of smoothing each surface of the low-grade raw wafer from which the structure has been removed, a grinding process and a mirror finishing process are sequentially performed on each surface of the low-grade raw wafer from which the structure has been removed, thereby smoothing each surface of the low-grade raw wafer from which the structure has been removed. [Note 17] The method for manufacturing a wafer to be processed according to Appendix 11, further comprising the step of roughening each of the smoothed low-grade raw wafers. [Note 18] The method for manufacturing a wafer to be processed according to Appendix 17, characterized in that each of the smoothed low-grade raw wafers is roughened by bench etching or spin etching. [Explanation of symbols]

[0041] 1 Diode wafer 10 Diode Structure 100 Doping well area 102 First High-Concentration Doped Area 104 Second High-Concentration Doping Region 11. Low-grade raw wafers 12 Metal conductive layer

Claims

1. A method for manufacturing diode wafers, which involves processing multiple raw wafers obtained by slicing from an ingot, A step of determining whether the plurality of raw wafers conform to the manufacturing specifications, If it is determined that it is suitable, the raw wafer is made into a high-grade raw wafer, If it is determined that it does not conform, the raw wafer is designated as a low-grade raw wafer, and the quantity of the low-grade raw wafers is multiple. The steps include: calculating the ratio of the quantity of low-grade raw wafers having problems related to crystal orientation pits (COP) to the total quantity of low-grade raw wafers, and determining whether the ratio is greater than a predetermined value; If it is determined to be large, the step to terminate is, If it is determined that the size is not large, the partial structure having the problem related to the crystal orientation pit of each of the low-grade raw wafers is removed, the partial structure having a fixed thickness, and the fixed thickness is determined by the depth of the crystal orientation pit from the surface of the low-grade raw wafer, The steps include smoothing each surface of the lower-grade raw wafer from which the partial structure has been removed, A method for manufacturing a diode wafer, comprising the steps of: forming a plurality of diode structures on each of the smoothed low-level raw wafers to obtain a diode wafer.

2. The method for manufacturing a diode wafer according to claim 1, characterized in that the items of the manufacturing specifications include electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indicator reading, wafer warpage, partial total indicator reading, and dust count.

3. The method for manufacturing a diode wafer according to claim 2, characterized in that the defects include chipping, cracking, excess laser engraving, scratching, staining, and fractures in the crystal lattice.

4. The method for manufacturing a diode wafer according to claim 1, characterized in that, in the step of removing the partial structure of each of the low-grade raw wafers, a low-grade raw wafer having a thickness greater than a predetermined value is selected, and the partial structure of each of the selected low-grade raw wafers is removed.

5. The method for manufacturing a diode wafer according to Claim 1, characterized in that, in the step of smoothing each of the surfaces of the lower-grade raw wafers from which the partial structure has been removed, an etching process and a mirror finishing process are sequentially performed on each of the surfaces of the lower-grade raw wafers from which the partial structure has been removed, thereby smoothing each of the surfaces of the lower-grade raw wafers from which the partial structure has been removed.

6. The method for manufacturing a diode wafer according to Claim 1, characterized in that, in the step of smoothing each surface of the lower-grade raw wafer from which the partial structure has been removed, a grinding process and a mirror finishing process are sequentially performed on each surface of the lower-grade raw wafer from which the partial structure has been removed, thereby smoothing each surface of the lower-grade raw wafer from which the partial structure has been removed.

7. A method for manufacturing a diode wafer according to claim 1, further comprising the step of roughening the surface of each of the smoothed low-grade raw wafers, forming a plurality of diode structures on each of the smoothed low-grade raw wafers, and obtaining the diode wafer, characterized in that the plurality of diode structures are formed on each of the roughened low-grade raw wafers, and the diode wafer is obtained.

8. The method for manufacturing a diode wafer according to claim 7, characterized in that each of the smoothed low-grade raw wafers is roughened by bench etching or spin etching.

9. The method for manufacturing a diode wafer according to claim 7, further comprising the step of forming a metal conductive layer on the surface of the diode wafer.

10. The diode structure is A doping well region having a first conductivity type, wherein the doping well region is located on the smoothed low-level raw wafer, A first high-concentration doped region having the first conductivity type, wherein the first high-concentration doped region is located in the doping well region, A method for manufacturing a diode wafer according to claim 1, comprising a second highly concentrated doped region having a second conductivity type opposite to the first conductivity type, wherein the second highly concentrated doped region is located in the doping well region.

11. A method for manufacturing a wafer to be processed, which involves processing multiple raw wafers obtained by slicing from an ingot, A step of determining whether the plurality of raw wafers conform to the manufacturing specifications, If it is determined that it is suitable, the steps are to make the raw wafer a high-grade raw wafer, If it is determined that the wafer is not suitable, the raw wafer is designated as a lower-grade raw wafer, and the quantity of the lower-grade raw wafers is multiple. A step of calculating the ratio of the quantity of low-grade raw wafers having problems related to crystal orientation pits (COP) to the total quantity of low-grade raw wafers, and determining whether the ratio is greater than a predetermined value, If it is determined to be large, the step to terminate is, If it is determined that the size is not large, the partial structure having the problem related to the crystal orientation pit of each of the low-grade raw wafers is removed, the partial structure having a fixed thickness, and the fixed thickness is determined by the depth of the crystal orientation pit from the surface of the low-grade raw wafer, A method for manufacturing a wafer to be processed, comprising the step of smoothing each surface of the lower-grade raw wafer from which the partial structure has been removed to obtain a wafer to be processed.

12. The method for manufacturing a wafer according to claim 11, characterized in that the items of the manufacturing specifications include electrical resistance, defects, black film, color film, wafer thickness, wafer crystal growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indicator readings, wafer warpage, some total indicator readings, and dust count.

13. The method for manufacturing a wafer to be processed according to claim 12, characterized in that the defects include chipping, cracking, excess laser engraving, scratching, staining, and fractures in the crystal lattice.

14. The method for manufacturing a wafer to be processed according to claim 11, characterized in that, in the step of removing the partial structure of each of the low-grade raw wafers, a low-grade raw wafer having a thickness greater than a predetermined value is selected, and the partial structure of each of the selected low-grade raw wafers is removed.

15. The method for manufacturing a wafer to be processed according to claim 11, characterized in that, in the step of smoothing each surface of the lower-grade raw wafer from which the partial structure has been removed, an etching process and a mirror finishing process are sequentially performed on each surface of the lower-grade raw wafer from which the partial structure has been removed, thereby smoothing each surface of the lower-grade raw wafer from which the partial structure has been removed.

16. The method for manufacturing a wafer to be processed according to claim 11, characterized in that, in the step of smoothing each of the surfaces of the lower-grade raw wafers from which the partial structure has been removed, a grinding process and a mirror finishing process are sequentially performed on each of the surfaces of the lower-grade raw wafers from which the partial structure has been removed, thereby smoothing each of the surfaces of the lower-grade raw wafers from which the partial structure has been removed.

17. The method for manufacturing a wafer to be processed according to claim 11, further comprising the step of roughening each of the smoothed low-grade raw wafers.

18. The method for manufacturing a wafer to be processed according to claim 17, characterized in that each of the smoothed low-grade raw wafers is roughened by bench etching or spin etching.

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