Semiconductor equipment

Abstract

To reduce an area required for installation of elements for controlling a power semiconductor element.SOLUTION: A semiconductor device includes: a power semiconductor element; a control chip including a plurality of terminals including a first terminal and a second terminal, the control chip controlling the power semiconductor element using a power supply voltage supplied to the second terminal; a first conductor for supplying a predetermined control voltage to the first terminal; and a semiconductor chip 30[k] including a diode D[k] used for boot strap operation generating the power supply voltage. The semiconductor chip 30[k] includes: a semiconductor substrate 31 which has a first face F1 and a second face F2 located opposite each other and in which pn junction of the diode D[k] is formed by a p-type semiconductor region 31p on the first face F1 and an n-type semiconductor region 31n on the second face F2; an anode 32 formed on the first face F1 and joined to the surface of the first conductor; and a cathode formed on the second face F2 and electrically connected to the second terminal via first wiring.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a semiconductor chip.

Background Art

[0002] For example, in a power conversion device using a power semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor), a bootstrap operation for generating a power supply voltage for controlling the power semiconductor device from a predetermined control voltage is executed. Patent Document 1 discloses a configuration that uses a resistor element and a diode connected in series with each other for the bootstrap operation.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the technology of Patent Document 1, for example, a sufficient area is required to install a large number of elements for controlling a power semiconductor device, such as the aforementioned resistor element and diode. In view of the above circumstances, one aspect of the present disclosure aims to reduce the area required for installing elements for controlling a power semiconductor device.

Means for Solving the Problems

[0005] In order to solve the above problems, a semiconductor device according to one aspect of the present disclosure includes a power semiconductor device, a plurality of terminals including a first terminal and a second terminal, a control chip that controls the power semiconductor device using a power supply voltage supplied to the second terminal, a first conductor for supplying a predetermined control voltage to the first terminal, A first wiring for supplying the aforementioned power supply voltage to the second terminal,The semiconductor chip comprises a semiconductor chip including a diode used in a bootstrap operation to generate the power supply voltage, the semiconductor chip including a first surface and a second surface located on opposite sides of each other, wherein a pn junction of the diode is formed by a p-type semiconductor region of the first surface and an n-type semiconductor region of the second surface, and the semiconductor chip includes an anode formed on the first surface and joined to the surface of the first conductor, and a cathode formed on the second surface and electrically connected to the second terminal via a first wiring.

[0006] A semiconductor chip according to one aspect of the present disclosure includes a diode, which is electrically connected between a first terminal, to which a predetermined control voltage is supplied, and a second terminal, to which a power supply voltage is supplied, and is used in a bootstrap operation to generate the power supply voltage, among a plurality of terminals of a control chip for controlling a power semiconductor element, the semiconductor chip comprising a semiconductor substrate including a first surface and a second surface located on opposite sides of each other, wherein a pn junction of the diode is formed by a p-type semiconductor region of the first surface and an n-type semiconductor region of the second surface, an anode formed on the first surface and bonded to the surface of the first conductor, and a cathode formed on the second surface and electrically connected to the second terminal via a first wiring.

[0007] A semiconductor chip according to one aspect of the present disclosure is a semiconductor chip including a diode used in a bootstrap operation to generate a power supply voltage for a control chip that controls a power semiconductor element, and comprises a semiconductor substrate including a first surface and a second surface located on opposite sides of each other, wherein a pn junction of the diode is formed by a p-type semiconductor region of the first surface and an n-type semiconductor region of the second surface; an anode including a metal film formed of nickel or a nickel alloy on the first surface; a cathode including a metal film formed of aluminum or an aluminum alloy on the second surface; and a current-limiting resistor element electrically connected to the cathode. [Brief explanation of the drawing]

[0008] [Figure 1]This is a circuit diagram illustrating the electrical configuration of a semiconductor device according to the first embodiment. [Figure 2] This is a plan view of a semiconductor chip including a diode. [Figure 3] This is a cross-sectional view along line III-III in Figure 2. [Figure 4] This is a plan view of a semiconductor device. [Figure 5] Figure 4 is a cross-sectional view of the VV line. [Figure 6] This is a magnified plan view of the vicinity of a semiconductor chip in a semiconductor device. [Figure 7] This is a cross-sectional view of a semiconductor chip in a proportional relationship. [Figure 8] This is a magnified planar view of the vicinity of a semiconductor chip in a proportional relationship. [Figure 9] This is an enlarged plan view of the vicinity of the semiconductor chip in the second embodiment. [Figure 10] This is a plan view of the semiconductor device in the third embodiment. [Figure 11] This is an enlarged plan view of the vicinity of the semiconductor chip in the third embodiment. [Figure 12] This is an enlarged plan view of the vicinity of the semiconductor chip in the fourth embodiment. [Figure 13] This is a cross-sectional view of a semiconductor chip in a modified example. [Modes for carrying out the invention]

[0009] The embodiments for implementing this disclosure will be described with reference to the drawings. Note that the dimensions and scale of the elements in each drawing may differ from those of the actual product. Furthermore, the embodiments described below are illustrative examples of embodiments that may be envisioned when implementing this disclosure. Therefore, the scope of this disclosure is not limited to the embodiments exemplified below.

[0010] A: First Embodiment Figure 1 is a circuit diagram illustrating the electrical configuration of the semiconductor device 100. The semiconductor device 100 is an intelligent power module used as a three-phase inverter circuit to drive an electric motor M, such as a three-phase motor. A control device 102 is connected to the semiconductor device 100. The control device 102 is, for example, an external MPU (Micro Processing Unit) that controls the operation of the semiconductor device 100.

[0011] In the following explanation, any one AC phase in the motor M is identified by the symbol k. That is, the symbol k means one of the U phase, V phase, or W phase (k=U,V,W). For example, the symbol [k] added to the reference code means that it is an element of each AC phase of the motor M. As illustrated in Figure 1, the semiconductor device 100 is equipped with a plurality of connection terminals T for external connection (Tin_H[k], Tin_L[k], Tout[k], Tc_H, Tc_L, Tg, Tp, Tn[k], Tbs[k]).

[0012] The semiconductor device 100 has three drive chips 21[k](21[U],21[V],21[W]) and three drive chips 22[k](22[U],22[V], 22[W] The motor comprises a drive chip 21[k], a drive chip 22[k], and a semiconductor chip 30[k] for each of the three phases (U phase, V phase, W phase) of the motor M.

[0013] Each of the drive chips 21[k] and 22[k] is a reverse conducting (RC)-IGBT including an IGBT (Insulated Gate Bipolar Transistor) and a FWD (Free Wheeling Diode), and has a main electrode E, a main electrode C, and a control electrode G. The main electrode E and the main electrode C are electrodes to which a current to be controlled is input or output. The main electrode C also functions as the cathode of the FWD, and the main electrode E also functions as the anode of the FWD. The control electrode G is a gate electrode to which a drive voltage for controlling the on / off of the IGBT is applied. Note that the drive chips 21[k] and 22[k] are an example of a "power semiconductor device".

[0014] The pair of the drive chips 21[k] and 22[k] constitutes a half-bridge circuit corresponding to one AC phase of the motor M. The drive chips 21[k] and 22[k] are connected in series between a connection terminal Tp and a connection terminal Tn[k]. A connection point between the drive chip 21[k] and the drive chip 22[k] is electrically connected to a connection terminal Tout[k]. The connection terminal Tout[k] is an output terminal for supplying power to one AC phase of the motor M. A high-potential-side power supply voltage is supplied from an external power supply 103 to the connection terminal Tp. A low-potential-side power supply voltage (ground voltage) is supplied to each connection terminal Tn[k]. Note that the three connection terminals Tn[k] may be replaced with one terminal common to the three phases.

[0015] The control chip 41 is a HVIC (High Voltage IC) that controls each of the high-potential-side drive chips 21[k]. Note that in the first embodiment, a form in which the control chip 41 is constituted by one chip is illustrated, but the control chip 41 may be constituted by three chips corresponding to different AC phases. As illustrated in FIG. 1, the control chip 41 includes a plurality of terminals H (Hin[k], Hout[k], Hb[k], Hs[k], Hc, Hg). That is, the control chip 41 includes an input terminal Hin[k], an output terminal Hout[k], a power supply terminal Hb[k], and a power supply terminal Hs[k] for each AC phase of the motor M.

[0016] The control signal supplied from the control device 102 to the connection terminal Tin_H[k] is input to the input terminal Hin[k]. The control signal is a signal for controlling each drive chip 21[k]. A high-potential power supply voltage Vb[k] is supplied to the power supply terminal Hb[k], and a low-potential power supply voltage Vs[k] is supplied to the power supply terminal Hs[k]. The control chip 41 operates with the power supply voltages supplied to the power supply terminal Hb[k] and the power supply terminal Hs[k], and outputs a drive voltage corresponding to the control signal supplied to the input terminal Hin[k] to the output terminal Hout[k]. The output terminal Hout[k] is electrically connected to the control electrode G of the IGBT in the drive chip 21[k]. As understood from the above description, the control chip 41 controls the drive chip 21[k] using the power supply voltage Vb[k] supplied to the power supply terminal Hb[k]. The power supply terminal Hb[k] is an example of the "second terminal".

[0017] Further, the control chip 41 includes a voltage terminal Hc and a ground terminal Hg. A control voltage Vcc is supplied to the voltage terminal Hc from the external power supply 104 via the connection terminal Tc_H. The control voltage Vcc is a predetermined DC voltage used for the operation of the control chip 41. Also, the control voltage Vcc is used for the bootstrap operation that generates the power supply voltage Vb[k] of the control chip 41. On the other hand, the ground terminal Hg is grounded. Note that the voltage terminal Hc is an example of the "first terminal".

[0018] The control chip 42 is a LVIC (Low Voltage IC) that controls each low-potential drive chip 22[k]. In the first embodiment, a form in which the control chip 42 is composed of one chip is illustrated, but the control chip 42 may be composed of three chips corresponding to different AC phases of the electric motor M. Also, the control chip 41 and the control chip 42 may be composed of a single chip. As illustrated in FIG. 1, the control chip 42 includes a plurality of terminals L (Lin[k], Lout[k], Lc, Lg). That is, the control chip 42 includes an input terminal Lin[k] and an output terminal Lout[k] for each AC phase of the electric motor M.

[0019] The control signal supplied from the control device 102 to the connection terminal Tin_L[k] is input to the input terminal Lin[k]. The control signal is a signal for controlling each drive chip 22[k]. The control chip 42 outputs a drive voltage corresponding to the control signal supplied to the input terminal Lin[k] to the output terminal Lout[k]. The output terminal Lout[k] is electrically connected to the control electrode G of the IGBT in the drive chip 22[k]. In other words, the control chip 42 controls each drive chip 22[k].

[0020] Furthermore, the control chip 42 is equipped with a voltage terminal Lc and a ground terminal Lg. A control voltage Vcc is supplied to the voltage terminal Lc from the external power supply 104 via the connection terminal Tc_L. Note that the control voltage Vcc supplied to the control chip 41 and the control voltage Vcc supplied to the control chip 42 may be different. On the other hand, the ground terminal Lg is grounded.

[0021] As illustrated in Figure 1, the power terminal Hb[k] of the control chip 41 is electrically connected to the connection terminal Tbs[k]. A capacitive element B[k] is electrically connected between the connection terminal Tbs[k] and the connection terminal Tout[k]. The capacitive element B[k] is a bootstrap capacitor externally connected to the semiconductor device 100. Each capacitive element B[k] comprises a first electrode b1 and a second electrode b2. The first electrode b1 is electrically connected to the connection terminal Tbs[k], and the second electrode b2 is electrically connected to the connection terminal Tout[k].

[0022] Each semiconductor chip 30[k] is connected between the connection terminal Tc_H and the connection terminal Tbs[k]. That is, the semiconductor chip 30[k] is connected between the voltage terminal Hc and the power supply terminal Hb[k] in the control chip 41. The semiconductor chip 30[k] is used in the bootstrap operation described above.

[0023] As illustrated in Figure 1, the semiconductor chip 30[k] comprises a diode D[k] and a resistor R[k] connected in series with each other. Diode D[k] is a bootstrap diode that constitutes a charging path (charging path α) for charging the capacitive element B[k] during bootstrap operation. The resistor R[k] limits the current flowing through diode D[k] during bootstrap operation. The anode of each diode D[k] is electrically connected to the connection terminal Tc_H and the voltage terminal Hc. The cathode of diode D[k] is electrically connected to one end of the resistor R[k]. The other end of the resistor R[k] is electrically connected to the connection terminal Tbs[k] and the power supply terminal Hb[k].

[0024] In the above configuration, the bootstrap operation is performed by controlling the drive chip 22[k] to the ON state while keeping the drive chip 21[k] in the OFF state. When the drive chip 22[k] is controlled to the ON state, the charging path α shown in Figure 1 is formed. In Figure 1, only the charging path α via the semiconductor chip 30[V] is shown for convenience, but the same charging paths α are formed for the U phase and W phase as well.

[0025] The charging path α is a current path that passes through the following in the order listed above: connection terminal Tc_H, diode D[k], resistor R[k], connection terminal Tbs[k], capacitive element B[k], connection terminal Tout[k], driver chip 22[k], and connection terminal Tn[k]. The capacitive element B[k] is charged by the charging path α. Specifically, the voltage across the capacitive element B[k] is maintained at the control voltage Vcc by charging via the charging path α. Therefore, the power supply voltage Vb[k] supplied to the power supply terminal Hb[k] is set to a voltage that is higher by the control voltage Vcc compared to the power supply voltage Vs[k] at the power supply terminal Hs[k]. As described above, the bootstrap operation is an operation that generates the power supply voltage Vb[k] using a bootstrap circuit including the semiconductor chip 30[k] and the capacitive element B[k].

[0026] Figure 2 is a plan view of the semiconductor chip 30[k]. Figure 3 is a cross-sectional view taken along line III-III in Figure 2. In the following explanation, we assume that the X, Y, and Z axes are mutually orthogonal, as illustrated in Figures 2 and 3. One direction along the X axis is denoted as the X1 direction, and the opposite direction is denoted as the X2 direction. Similarly, one direction along the Y axis is denoted as the Y1 direction, and the opposite direction is denoted as the Y2 direction. Likewise, one direction along the Z axis is denoted as the Z1 direction, and the opposite direction is denoted as the Z2 direction. Furthermore, viewing any element of the semiconductor device 100 along the Z axis (Z1 or Z2 direction) will be referred to as "planar view" below.

[0027] In actual use, the semiconductor device 100 can be installed in any direction; however, for convenience, in the following explanation, we will assume that the Z1 direction is downward and the Z2 direction is upward. Therefore, any surface of the semiconductor device 100 facing the Z1 direction may be referred to as the "bottom surface," and any surface of the same element facing the Z2 direction may be referred to as the "top surface."

[0028] As illustrated in Figures 2 and 3, the semiconductor chip 30[k] comprises a rectangular semiconductor substrate 31 in plan view. The semiconductor substrate 31 is a plate-shaped member formed of a semiconductor material such as silicon. The semiconductor substrate 31 in the first embodiment is a p-type semiconductor substrate.

[0029] The semiconductor substrate 31 comprises a first surface F1 and a second surface F2. The first surface F1 and the second surface F2 are main surfaces located on opposite sides of the semiconductor substrate 31. Specifically, the first surface F1 faces in the Z1 direction, and the second surface F2 faces in the Z2 direction. That is, the first surface F1 corresponds to the bottom surface of the semiconductor substrate 31, and the second surface F2 corresponds to the top surface of the semiconductor substrate 31.

[0030] A p-type semiconductor region 31p is formed on the first surface F1, where holes move as majority carriers. On the other hand, an n-type semiconductor region 31n is formed on the second surface F2, where electrons move as majority carriers. The p-type semiconductor region 31p and the n-type semiconductor region 31n are joined to each other inside the semiconductor substrate 31. The p-type semiconductor region 31p of the first surface F1 and the n-type semiconductor region 31n of the second surface F2 form a pn junction of the diode D[k]. Therefore, the first surface F1 is located on the anode side of the diode D[k], and the second surface F2 is located on the cathode side of the diode D[k].

[0031] An anode 32 is formed on the first surface F1. The anode 32 of the first embodiment is formed on the first surface F1 to The conductive film is formed to make contact and covers the entire surface F1. However, the anode 32 may cover only a portion of the first surface F1. The anode 32 is formed from a low-resistance metal material. The anode 32 may be composed of a single layer or of a laminate of multiple metal films made of different materials. As will be described in detail later, the anode 32 is joined to the metal die pad 65 by a conductive bonding material such as solder or conductive paste. Therefore, it is desirable that the anode 32 includes a metal film made of nickel or a nickel alloy, which has high bonding properties with bonding materials.

[0032] On the second surface F2, the first insulating layer 33, the resistive layer 34, and the second insulating layer 35 are stacked in the order described above. That is, the first insulating layer 33 is formed on the second surface F2, the resistive layer 34 is formed on the first insulating layer 33, and the second insulating layer 35 is formed on the resistive layer 34. Therefore, the first insulating layer 33 is located between the second surface F2 and the resistive layer 34, and the resistive layer 34 is located between the first insulating layer 33 and the second insulating layer 35. The first insulating layer 33 is an example of an "insulating layer".

[0033] The first insulating layer 33 and the resistive layer 34 are formed in a circular shape on the second surface F2 in a plan view. The first insulating layer 33 is an insulating film that covers the second surface F2. Specifically, the first insulating layer 33 is, for example, an oxide film formed by the oxidation of the semiconductor substrate 31. The resistive layer 34 is a highly resistive conductive film that covers the first insulating layer 33. Specifically, the resistive layer 34 is formed of a material with a higher resistivity compared to the cathode 36 and anode 32. For example, the resistive layer 34 is made of polysilicon. The aforementioned resistive element R[k] is composed of the resistive layer 34.

[0034] The second insulating layer 35 is an insulating film that covers the entire area of ​​the second surface F2. The first insulating layer 33 and the resistive layer 34 are covered by the second insulating layer 35. The second insulating layer 35 is an oxide film formed from an insulating material such as silicon oxide.

[0035] A cathode 36 and a connecting electrode 37 are formed on the second insulating layer 35. The cathode 36 and the connecting electrode 37 are formed collectively by patterning a conductive film that covers the entire area of ​​the second insulating layer 35. Therefore, the cathode 36 and the connecting electrode 37 are formed from a common conductive material and have approximately the same film thickness. For example, the cathode 36 and the connecting electrode 37 are formed from a low-resistance metallic material. The cathode 36 may be composed of a single layer or of a laminate of multiple metallic films made of different materials. As will be described in detail later, a wire Qb[k] is bonded to the connecting electrode 37. Therefore, it is desirable that the cathode 36 and the connecting electrode 37 include a metallic film made of aluminum or an aluminum alloy, which is suitable for connecting the wire Qb[k]. The cathode 36 and the connecting electrode 37 may be formed from different materials in separate processes.

[0036] The connecting electrode 37 is a circular electrode formed in the center of the second surface F2. Specifically, the connecting electrode 37 is formed so as to overlap the resistive layer 34 in a plan view. On the other hand, the cathode 36 is an electrode formed in a shape that surrounds the connecting electrode 37 in a plan view. That is, the cathode 36 has a circular opening that encloses the connecting electrode 37. A predetermined distance is ensured between the outer edge of the connecting electrode 37 and the inner edge of the cathode 36. The cathode 36 includes an inner region that overlaps the resistive layer 34 in a plan view and an outer region that does not overlap the resistive layer 34. As can be understood from the above description, the cathode 36 of the diode D[k] is formed on the second surface F2.

[0037] A protective layer 38 is formed on the second surface F2. Note that the protective layer 38 is partially shown in Figure 2. The protective layer 38 is an insulating coating that covers the cathode 36 and the connecting electrode 37. The protective layer 38 is made of an insulating resin material, such as epoxy resin. The protective layer 38 includes a covering portion 381 that covers the cathode 36 and the connecting electrode 37, and a partition portion 382 that fills the gap between the cathode 36 and the connecting electrode 37. The cathode 36 and the connecting electrode 37 are electrically insulated by the partition portion 382. A circular opening 383 is formed in the area of ​​the covering portion 381 that is located inside the partition portion 382 in a plan view. The connecting electrode 37 is exposed through the opening 383 of the protective layer 38. The connecting electrode 37 is connected to the semiconductor chip 30 [k] It functions as a connection terminal for electrically connecting to other elements.

[0038] As illustrated in Figures 2 and 3, conduction holes h1, h2, and h3 are formed in the second insulating layer 35. Conduction hole h1 is a through-hole formed in an annular shape in the region of the second insulating layer 35 that is outside the resistive layer 34 in a plan view. The cathode 36 conducts to the second surface F2 (n-type semiconductor region 31n) through conduction hole h1. As can be understood from the above explanation, the anode 32, the p-type semiconductor region 31p, the n-type semiconductor region 31n, and the cathode 36 are stacked in the Z2 direction in the above order to form a diode D[k].

[0039] Each of the conduction holes h2 and h3 is an annular through-hole formed in the region of the second insulating layer 35 that overlaps with the resistive layer 34 in a plan view. Conduction hole h2 is formed in the region outside the partition wall 382, ​​and conduction hole h3 is formed in the region inside the partition wall 382. The cathode 36 is conductive to the resistive layer 34 through the conduction hole h2. That is, as illustrated in Figure 1, the current-limiting resistor R[k] is electrically connected to the cathode 36 of the diode D[k]. The connecting electrode 37 is also conductive to the resistive layer 34 through the conduction hole h3. As can be understood from the above explanation, the resistive element R[k], which is composed of the resistive layer 34, is interposed between the cathode 36 of the diode D[k] and the connecting electrode 37. Note that the connecting electrode 37 may also be referred to as the cathode 36 of the diode D[k].

[0040] As described above, according to the first embodiment, the current flowing through the diode D[k] during bootstrap operation can be limited by the current-limiting resistor R[k]. In the first embodiment, the resistor R[k] is formed by a resistor 34 laminated on the second surface F2 of the semiconductor substrate 31 via a first insulating layer 33. That is, the current-limiting resistor R[k] can be easily formed by laminating the first insulating layer 33 and the resistor 34 on the second surface F2. Furthermore, since the resistor R[k] and the diode D[k] are formed integrally, the configuration of the semiconductor device 100 is simplified compared to a configuration in which the resistor R[k] and the diode D[k] are separate components.

[0041] Figure 4 is a plan view of the semiconductor device 100 in the first embodiment. Figure 5 is a cross-sectional view of the line VV in Figure 4. As can be seen from Figures 4 and 5, the direction of the X axis corresponds to the longitudinal direction of the semiconductor device 100 (i.e., the direction of the longer side of the rectangle that constitutes the outer shape), and the direction of the Y axis corresponds to the short side of the semiconductor device 100 (i.e., the direction of the shorter side of the rectangle that constitutes the outer shape).

[0042] As illustrated in Figures 4 and 5, the semiconductor device 100 comprises a housing 50 that houses the elements illustrated in Figure 1. The housing 50 comprises a resin case 51, a support plate 52, and a sealing resin 53. The resin case 51 is a rectangular frame-shaped structure formed of a resin material. The housing 50 is formed from various resin materials such as PPS (polyphenylene sulfide) resin, PBT (polybutylene terephthalate) resin, PBS (poly butylene succinate) resin, PA (polyamide) resin, or ABS (acrylonitrile-butadiene-styrene) resin.

[0043] As illustrated in Figure 5, the support plate 52 is a plate-shaped member composed of a laminate of an insulating layer 521 and a heat sink 522. The insulating layer 521 is formed of a resin material such as epoxy resin and covers the upper surface of the heat sink 522. The heat sink 522 is a plate-shaped member formed of a metal material with high thermal conductivity such as aluminum or copper. The support plate 52 is fixed to the resin case 51 so as to close the opening of the resin case 51. Three drive chips 21[k](21[U],21[V],21[W]), three drive chips 22[k](22[U],22[V],22[W]), three semiconductor chips 30[k](30[U],30[V],30[W]), a control chip 41, and a control chip 42 are housed in the space surrounded by the resin case 51 with the support plate 52 as the bottom surface. A main electrode E and a control electrode G are formed on the upper surface of the drive chip 21[k] and the drive chip 22[k], respectively, and a main electrode C is formed on the lower surface of each.

[0044] The sealing resin 53 is a resin that fills the space inside the resin case 51 and seals the elements housed in that space. The sealing resin 53 is formed from various resin materials, such as silicone gel or epoxy resin. In addition to the resin material, the sealing resin 53 may also contain various insulating fillers such as silicon oxide or aluminum oxide.

[0045] A lead frame 60 is installed in the housing 50. The lead frame 60 is wiring formed from a low-resistance metal material such as copper or a copper alloy. The lead frame 60 is formed integrally with the resin case 51, for example by insert molding. The lead frame 60 is a conductor containing multiple leads. Each of the aforementioned connection terminals T is the end of the multiple leads that is exposed to the outside from the housing 50.

[0046] As illustrated in Figure 4, the housing 50 includes an element region 55, a terminal region 56, and a control region 57 in a plan view. Each of the element region 55, terminal region 56, and control region 57 is an elongated region along the X-axis. The element region 55 is located between the terminal region 56 and the control region 57.

[0047] Of the multiple connection terminals T, some connection terminals T (Tin_H[k], Tin_L[k], Tc_H, Tc[L], Tg, Tbs[k]) related to the operation of control chips 41 and 42 are control terminals that protrude in the Y1 direction from the side of the control area 57 and are arranged at intervals from each other along the X axis. On the other hand, some connection terminals T (Tout[k], Tp, Tn[k]) related to the power supplied to the electric motor M are terminals that protrude in the Y2 direction from the side of the terminal area 56 and are arranged at intervals from each other along the X axis.

[0048] As illustrated in Figure 4, the lead frame 60 includes one die pad 61 and three die pads 62[k]. Die pad 61 and each die pad 62[k] are metal plates located within the element region 55 in a plan view. Three drive chips 21[k] are mounted on die pad 61. One drive chip 22[k] is mounted on each die pad 62[k]. Conductive bonding materials such as solder or metal sintered material are used to mount the drive chips 21[k] and 22[k]. As can be understood from the above explanation, three drive chips 21[k] and three drive chips 22[k] are installed in the element region 55. Note that the three die pads 62[k] may be replaced with single die pads.

[0049] The lead frame 60 includes leads extending from the connection terminal Tp and each of the connection terminals Tout[k] and Tn[k]. The connection terminal Tp is connected to the die pad 61 via the lead. Therefore, the main electrode C on the lower surface of each drive chip 21[k] is electrically connected to the connection terminal Tp. Each connection terminal Tout[k] is connected to the die pad 62[k] via the lead. In addition, each connection terminal Tout[k] is electrically connected by a wire to the main electrode E on the upper surface of the drive chip 21[k]. Therefore, as illustrated in Figure 1, the main electrode E of the drive chip 21[k] and the main electrode C on the lower surface of the drive chip 22[k] are electrically connected to the connection terminal Tout[k]. In addition, each connection terminal Tn[k] is electrically connected by a wire to the main electrode E on the upper surface of the drive chip 22[k].

[0050] Furthermore, as illustrated in Figure 4, the lead frame 60 includes die pads 63, 64, and 65, and three connecting pads 66[k]. Die pads 63, 64, and 65, and each connecting pad 66[k] are metal plates located within the control region 57 in a plan view.

[0051] The lead frame 60 includes leads extending from each control connection terminal T (Tin_H[k], Tin_L[k], Tc_H, Tc_L, Tg, Tbs[k]) related to the operation of the control chip 42. Each of the die pads 63 and 64 is connected to the connection terminal Tg via a lead. Furthermore, die pads 63 and 64 are interconnected via leads. Therefore, a ground voltage is supplied to die pads 63 and 64 from each connection terminal Tg. Note that die pads 63 and 64, the connection terminal Tg, and the leads connecting each of the above elements (63, 64, Tg) may be formed integrally.

[0052] The control chip 41 is bonded to the surface of the die pad 63. An insulating adhesive is used to mount the control chip 41. Therefore, the underside of the control chip 41 and the die pad 63 are electrically insulated. Note that the die pad 63 is an example of a "third conductor". Note that some or all of the die pads 63 and 64, the connection terminal Tg, and the leads connecting each of the above elements (63, 64, Tg) may be considered as the "third conductor".

[0053] Multiple terminals H are formed on the upper surface of the control chip 41. Each terminal H of the control chip 41 is electrically connected to the drive chip 21[k] or the connection terminal T by a wire. For example, the output terminal Hout[k] of the control chip 41 is connected to the control electrode G on the upper surface of the drive chip 21[k], and the power terminal Hs[k] is connected to the main electrode E on the upper surface of the drive chip 21[k]. In addition, the voltage terminal Hc is connected to a lead connected to the connection terminal Tc_H, and the ground terminal Hg is connected to a lead connected to the connection terminal Tg.

[0054] As described above, in the first embodiment, the control chip 41 is bonded to the surface of the die pad 63 to which the ground voltage is supplied. That is, the control chip 41 is installed so as to overlap the die pad 63 in a plan view. Therefore, the ground terminal Hg of the control chip 41 to which the ground voltage is supplied can be easily connected to the die pad 63.

[0055] As illustrated in Figure 4, the control chip 42 is bonded to the surface of the die pad 64. An insulating adhesive is used to mount the control chip 42. Therefore, the lower surface of the control chip 42 is electrically insulated from the die pad 64. Multiple terminals L are formed on the upper surface of the control chip 42. Each terminal L of the control chip 42 is electrically connected to the drive chip 22[k] or the connection terminal T by a wire. For example, the output terminal Lout[k] of the control chip 42 is connected to the control electrode G on the upper surface of the drive chip 22[k]. The voltage terminal Lc is connected to a lead connected to the connection terminal Tc_L, and the ground terminal Lg is connected to a lead connected to the connection terminal Tg.

[0056] The die pad 65 is connected to the connection terminal Tc_H via a lead. Therefore, the die pad 65 is supplied with a control voltage Vcc from the connection terminal Tc_H. The die pad 65 is a conductor for supplying the control voltage Vcc to the voltage terminal Hc of the control chip 41. The die pad 65, the connection terminal Tc_H, and the lead connecting them (65, Tc_H) may be formed integrally. Note that the die pad 65 is an example of a "first conductor". The die pad 65, the connection terminal Tc_H, and the lead connecting them (65, Tc_H) may all or part of be considered the "first conductor".

[0057] Each connection pad 66[k] is connected to a connection terminal Tbs[k] via a lead. The three connection pads 66[k] are arranged spaced apart from each other along the X-axis. Specifically, the three connection pads 66[k] are arranged along the periphery of the housing 50 located in the Y1 direction. As mentioned above, a capacitive element B[k] is connected to the connection terminal Tbs[k]. That is, a capacitive element B[k] is externally connected to each connection pad 66[k]. Each connection pad 66[k] and each connection terminal Tbs[k], and the lead connecting them (66[k],Tbs[k]) may be formed integrally. Note that the connection pad 66[k] and the connection terminal Tbs[k] are examples of a "second conductor". Some or all of the connection pad 66[k], the connection terminal Tbs[k], and the lead connecting them (66[k],Tbs[k]) may be the "second conductor".

[0058] As illustrated in Figure 4, the die pad 63 is located between the drive chip 21[k] and the die pad 65 in a plan view. Specifically, the die pad 63 (control chip 41) is located between the arrangement of three drive chips 21[k] and the die pad 65. The die pad 65 is located between the die pad 63 and the connection pad 66[k] in a plan view. Specifically, the die pad 65 is located between the arrangement of three connection pads 66[k] and the die pad 63 (control chip 41).

[0059] Figure 6 is an enlarged plan view of the vicinity of each semiconductor chip 30[k] in the semiconductor device 100. Note that elements shown in Figure 4 that are not relevant to the following explanation are omitted in Figure 6 for convenience. As illustrated in Figure 6, the ground terminal Hg on the upper surface of the control chip 41 is electrically connected to the die pad 63 via wire Qg. Also, the voltage terminal Hc on the upper surface of the control chip 41 is electrically connected to the die pad 65 via wire Qc.

[0060] As illustrated in Figure 6, the die pad 65 includes a first portion 651 and three second portions 652[k] (652[U], 652[V], 652[W]). The first portion 651 is a portion that extends linearly along the X-axis. Each second portion 652[k] is a rectangular portion that protrudes in the Y1 direction from the periphery of the first portion 651 located in the Y1 direction. Each second portion 652[k] can also be described as a portion that protrudes from the periphery of the first portion 651 on the opposite side from the control chip 41 and the die pad 63. The three second portions 652[k] are arranged at intervals from each other along the X-axis.

[0061] Three semiconductor chips 30[k] are placed on the die pad 65. Each semiconductor chip 30[k] is placed in a position corresponding to the second portion 652[k] in a plan view. Specifically, a portion of the semiconductor chip 30[k] located in the Y1 direction overlaps with the second portion 652[k] in a plan view. That is, the semiconductor chip 30[k] overlaps with the first portion 651 and the second portion 652[k] in a plan view. With the above configuration, the first portion of the die pad 65 in a plan view 651 The second portion 652[k] protruding from the first portion ensures sufficient space for the semiconductor chip 30[k] to be installed. It is also conceivable that the entire semiconductor chip 30[k] may overlap the second portion 652[k].

[0062] As can be understood from the above explanation, the three semiconductor chips 30[k] are arranged with a gap between them along the X-axis. The three semiconductor chips 30[k] are located between the arrangement of the three driver chips 21[k] and the arrangement of the three connection pads 66[k]. Specifically, the three semiconductor chips 30[k] are placed between the control chip 41 and the arrangement of the three connection pads 66[k].

[0063] The semiconductor chip 30[k] is bonded to the die pad 65 with its anode 32 facing the die pad 65. That is, the anode 32 located on the underside of the semiconductor chip 30[k] is bonded to the surface of the die pad 65. For example, the semiconductor chip 30[k] is bonded to the die pad 65 using a conductive bonding material such as solder or conductive paste. Therefore, the anode 32 of the semiconductor chip 30[k] is electrically connected to the die pad 65 (and further to the connection terminal Tc_H). In other words, by mounting the semiconductor chip 30[k] on the die pad 65, the anode 32 and the die pad 65 are electrically connected. Also, when the semiconductor chip 30[k] is mounted on the die pad 65, the connection electrode 37 of the semiconductor chip 30[k] faces in the Z2 direction. That is, the connection electrode 37 is located on the upper surface of the semiconductor chip 30[k].

[0064] As illustrated in Figure 6, the power terminal Hb[k] of the control chip 41 and the connection electrode 37 and connection pad 66[k] of the semiconductor chip 30[k] are electrically connected by a wire Qb[k]. The wire Qb[k] is a linear conductor formed by wire bonding. Each wire Qb[k] consists of a first wiring Qb1 and a second wiring Qb2.

[0065] The first wiring Qb1 is a wiring that electrically connects the power terminal Hb[k] of the control chip 41 to the connecting electrode 37 of the semiconductor chip 30[k]. Specifically, one end of the first wiring Qb1 is joined to the surface of the power terminal Hb[k], and the other end of the first wiring Qb1 is joined to the surface of the connecting electrode 37. In other words, the power terminal Hb[k] and the cathode 36 of the diode D[k] are electrically connected via the first wiring Qb1.

[0066] The second wiring Qb2 is a wiring that electrically connects the connection electrode 37 and the connection pad 66[k] of the semiconductor chip 30[k]. Specifically, one end of the second wiring Qb2 is joined to the surface of the connection electrode 37, and the other end of the second wiring Qb2 is joined to the surface of the connection pad 66[k]. That is, the connection pad 66[k] and the cathode 36 of the diode D[k] are electrically connected via the second wiring Qb2. With this configuration, a capacitive element B[k] with a desired capacitance externally connected to the semiconductor device 100 can be used for bootstrap operation. The first wiring Qb1 and the second wiring Qb2 are wirings for supplying a power supply voltage Vb[k] to the power supply terminal Hb[k] of the control chip 41.

[0067] In the first embodiment, the portion to which the first wiring Qb1 and the second wiring Qb2 are interconnected (connection portion) is a stitch formed on the surface of the connection electrode 37 of the semiconductor chip 30[k]. That is, the first wiring Qb1 and the second wiring Qb2 are interconnected via a stitch on the second surface F2 of the semiconductor chip 30[k]. Specifically, the end of the first wiring Qb1 joined to the connection electrode 37 and the end of the second wiring Qb2 joined to the same connection electrode 37 constitute a stitch on the second surface F2. As can be understood from the above description, the power terminal Hb[k] of the control chip 41, the connection electrode 37 (cathode 36 of the diode D[k]) and the connection pad 66[k] of the semiconductor chip 30[k] are electrically connected to each other by stitch bonding. That is, in a series of steps to form the wire Qb[k], the first wiring Qb1 and the second wiring Qb2 are formed continuously.

[0068] Incidentally, in addition to the above-mentioned configurations illustrated in Figures 2 and 3, the configuration of the diode D[k] used in the bootstrap operation can also be envisioned as the form illustrated in Figure 7 (hereinafter referred to as "proportional"). Figure 7 is a cross-sectional view of the semiconductor chip 90[k] in the proportional configuration. The proportional semiconductor chip 90[k] comprises an n-type semiconductor substrate 91 including a first surface F1 and a second surface F2. An n-type semiconductor region 91n is formed on the first surface F1 of the semiconductor substrate 91, and a p-type semiconductor region 91p is formed on the second surface F2 of the semiconductor substrate 91. The pn junction of the diode D[k] is formed by the junction of the p-type semiconductor region 91p on the second surface F2 and the n-type semiconductor region 91n on the first surface F1. A cathode 92 is formed on the first surface F1, and an anode 93 is formed on the second surface F2. In other words, the direction of the diode D[k] is opposite between the first embodiment and the proportional configuration.

[0069] Figure 8 is an enlarged plan view of the vicinity of each semiconductor chip 90[k] in the proportional relationship. As illustrated in Figure 8, the control region 57 of the semiconductor device 100 involved in the proportional relationship is equipped with die pad 63, die pad 65, and three connection pads 66[k]. A control chip 41 is mounted on die pad 63.

[0070] As described above, in the proportional semiconductor chip 90[k], a cathode 92 to be connected to the connection terminal Tbs[k] is formed on the lower surface, and an anode 93 to be connected to the connection terminal Tc_H is formed on the upper surface. Therefore, each semiconductor chip 90[k] is joined to the connection pad 66[k]. That is, the cathode 92 formed on the first surface F1 is joined to the surface of the connection pad 66[k]. In addition, the power terminal Hb[k] of the control chip 41 is electrically connected to the connection pad 66[k] via wire q1. Therefore, the connection pad 66[k] needs to have sufficient area for the installation of the semiconductor chip 90[k] and for the connection of wire q1. Also, the voltage terminal Hc on the upper surface of the control chip 41 is electrically connected to the anode 93 on the upper surface of the semiconductor chip 90[k] via wire q2. Therefore, wire q1 and wire q2 are separate wires.

[0071] In contrast to the proportional arrangement described above, in the first embodiment, the anode 32 of the diode D[k] is formed on the first surface F1 of the semiconductor substrate 31, and the anode 32 is joined to the die pad 65 for supplying a control voltage Vcc to the control chip 41. That is, the diode D[k] is installed so that the anode 32 faces the die pad 65. On the other hand, the cathode 36 formed on the second surface F2 of the semiconductor substrate 31 is electrically connected to the power terminal Hb[k] of the control chip 41 via the wire Qb[k]. As a result of the semiconductor chip 30[k] adopting the above configuration, in the first embodiment, the semiconductor chip 30[k] is directly mounted on the die pad 65. That is, there is no need to join the semiconductor chip 30[k] to the connection pad 66[k], so the area of ​​the connection pad 66[k] is reduced compared to the proportional arrangement. Therefore, according to the first embodiment, the control area 57 can be reduced compared to the proportional arrangement in which each semiconductor chip 90[k] is mounted on the connection pad 66[k]. In other words, according to the first embodiment, the semiconductor device 100 can be miniaturized compared to proportional miniaturization.

[0072] On the other hand, assuming that the size of the semiconductor device 100 is maintained at the same level as in the proportional design, the element area 55 can be expanded by the amount by which the control area 57 is reduced. Therefore, according to the first embodiment, compared to the proportional design, it is possible to install large drive chips 21[k] and 22[k] capable of controlling large currents in the element area 55. In other words, according to the first embodiment, it is possible to improve power density. As described above, according to the first embodiment, it is possible to achieve both miniaturization of the semiconductor device 100 and improvement of power density.

[0073] Furthermore, in the proportional connection, it is necessary to separately form wire q1 for connecting the power terminal Hb[k] and the connection pad 66[k], and wire q2 for connecting the anode 93 and the die pad 65 (voltage terminal Hc). In contrast to the proportional connection, in the first embodiment, the power terminal Hb[k], diode D[k], and connection pad 66[k] are electrically connected by a single wire Qb[k] stitched on the semiconductor chip 30[k]. Therefore, according to the first embodiment, the process of electrically connecting the power terminal Hb[k], diode D[k], and connection pad 66[k] can be simplified compared to the proportional connection.

[0074] Furthermore, in the first embodiment, the drive chip 21[k], die pad 63, die pad 65, and each connection pad 66[k] are arranged in the above order in the Y1 direction in a plan view. Therefore, the power terminal Hb[k] of the control chip 41 bonded to the die pad 63 and the semiconductor chip 30 bonded to the die pad 65 [k] This allows for efficient connection to the connection pad 66[k].

[0075] B: Second Embodiment A second embodiment of this disclosure will now be described. In each of the embodiments described below, elements whose function is the same as in the first embodiment will use the same reference numerals as in the description of the first embodiment, and their detailed descriptions will be omitted as appropriate.

[0076] Figure 9 is an enlarged plan view of the vicinity of each semiconductor chip 30[k] in the semiconductor device 100 of the second embodiment. As illustrated in Figure 9, the control chip 41 of the second embodiment is equipped with a grounding terminal Hg. The grounding terminal Hg of the second embodiment is a terminal formed on the side of the control chip 41 facing the die pad 63 (i.e., the bottom surface). Similar to the first embodiment, a grounding voltage is supplied to the die pad 63.

[0077] In the first embodiment, as described above, the control chip 41 is joined to the die pad 63 with an insulating adhesive. In the second embodiment, the control chip 41 is joined to the die pad 63 with a conductive bonding material such as solder or conductive paste. Therefore, the grounding terminal Hg on the lower surface of the control chip 41 is electrically connected to the die pad 63. That is, a ground voltage is supplied to the grounding terminal Hg of the control chip 41 via the die pad 63. Except for the fact that the grounding terminal Hg on the lower surface of the control chip 41 is joined to the die pad 63, the second embodiment is the same as the first embodiment.

[0078] The same effects as in the first embodiment are achieved in the second embodiment. Furthermore, in the second embodiment, the grounding terminal Hg of the control chip 41 and the die pad 63 can be electrically connected by a simple process of joining the control chip 41 to the die pad 63 with a conductive bonding material. In other words, the aforementioned wire Qg (Figure 6) that electrically connects the grounding terminal Hg and the die pad 63 is unnecessary. However, in the second embodiment as in the first embodiment, wire Qg may be installed.

[0079] C: Third Embodiment Figure 10 is a plan view of the semiconductor device 100 in the third embodiment. As illustrated in Figure 10, the die pad 63 illustrated in the first embodiment is omitted in the third embodiment. The control chip 41, which is mounted on the die pad 63 in the first embodiment, is mounted on the die pad 65 in the third embodiment. That is, the die pad 65 of the third embodiment is mounted with the control chip 41 and three semiconductor chips 30[k](30[U], 30[V], 30[W]).

[0080] As illustrated in Figure 10, the die pad 65 is located between the drive chip 21[k] and the connection pad 66[k] in a plan view. That is, the drive chip 21[k], the die pad 65, and the connection pad 66[k] are arranged in the above order in the Y1 direction in a plan view. Specifically, the die pad 65 (control chip 41) is located between the arrangement of three drive chips 21[k] and the arrangement of three connection pads 66[k].

[0081] Figure 11 is an enlarged plan view of the vicinity of each semiconductor chip 30[k] in the semiconductor device 100. Note that elements shown in Figure 10 that are not relevant to the following explanation are omitted in Figure 11 for convenience. As illustrated in Figure 11, the ground terminal Hg formed on the upper surface of the control chip 41 is electrically connected to a lead connected to the connection terminal Tg via wire Qg. Also, the voltage terminal Hc of the control chip 41 is electrically connected to the die pad 65 via wire Qc.

[0082] The die pad 65 includes a first portion 651 and three second portions 652[k], similar to the first embodiment. The first portion 651 is a rectangular portion that is elongated in the direction of the X axis. Each second portion 652[k] is a rectangular portion that protrudes in the Y1 direction from the periphery of the first portion 651 located in the Y1 direction, similar to the first embodiment. Each semiconductor chip 30[k] is positioned in a location corresponding to the second portion 652[k] in a plan view. Specifically, each semiconductor chip 30[k] overlaps the first portion 651 and the second portion 652[k] in a plan view. Thus, the three semiconductor chips 30[k] are arranged spaced apart from each other along the X axis. Similar to the first embodiment, the three semiconductor chips 30[k] are located between the arrangement of three driver chips 21[k] and the arrangement of three connection pads 66[K].

[0083] Similar to the first embodiment, the semiconductor chip 30[k] is bonded to the surface of the die pad 65 by a conductive bonding material such as solder or conductive paste. Thus, the anode 32 of the semiconductor chip 30[k] is electrically connected to the die pad 65 (and further to the connection terminal Tc_H).

[0084] Furthermore, the control chip 41 is bonded to the surface of the first portion 651 of the die pad 65. That is, the control chip 41 is bonded to the die pad 65 in a plan view. Installation An insulating adhesive is used to mount the control chip 41. Therefore, the underside of the control chip 41 and the die pad 65 are electrically insulated.

[0085] The third embodiment is the same as the first embodiment except that the control chip 41 is bonded to the die pad 65. For example, in the third embodiment, as in the first embodiment, the power terminal Hb[k] of the control chip 41 and the connection electrode 37 and connection pad 66[k] of the semiconductor chip 30[k] are electrically connected by a wire Qb[k] composed of a first wiring Qb1 and a second wiring Qb2.

[0086] The same effects as in the first embodiment are achieved in the third embodiment. In the third embodiment, the control chip 41 is bonded to the surface of the die pad 65 to which the control voltage Vcc is supplied. That is, there is no need to form the die pad 63 at a distance from the die pad 65. Therefore, compared to the first embodiment in which the die pad 63 is formed separately from the die pad 65, the control area 57 can be reduced more effectively. In other words, miniaturization of the semiconductor device 100 and improvement of power density can be achieved at a high level. In addition, since the control chip 41 is bonded to the die pad 65, there is also the advantage that the voltage terminal Hc to which the control voltage Vcc is supplied on the control chip 41 can be easily connected to the die pad 65.

[0087] Furthermore, in the third embodiment, the drive chip 21[k], die pad 65, and connection pad 66[k] are arranged in the above order in the Y1 direction in a plan view. Therefore, the voltage terminal Hc of the control chip 41 bonded to the die pad 65, the semiconductor chip 30[k] (diode D[k]) bonded to the die pad 65, and the connection pad 66[k] can be efficiently connected.

[0088] D: Fourth Embodiment Figure 12 is an enlarged plan view of the vicinity of each semiconductor chip 30[k] in the semiconductor device 100 of the fourth embodiment. As illustrated in Figure 12, the control chip 41 of the fourth embodiment is equipped with a voltage terminal Hc. The voltage terminal Hc of the fourth embodiment is a terminal formed on the side of the control chip 41 facing the die pad 65 (i.e., the bottom surface). Similar to the third embodiment, a control voltage Vcc is supplied to the die pad 65. The voltage terminal Hc of the fourth embodiment is an example of a "third terminal".

[0089] In the third embodiment, the control chip 41 is bonded to the die pad 65 with an insulating adhesive. In the fourth embodiment, the control chip 41 is bonded to the die pad 65 with a conductive bonding material such as solder or conductive paste. Therefore, the voltage terminal Hc on the lower surface of the control chip 41 is electrically connected to the die pad 65. That is, the control voltage Vcc is supplied to the voltage terminal Hc of the control chip 41 via the die pad 65. Except for the fact that the voltage terminal Hc on the lower surface of the control chip 41 is bonded to the die pad 65, this is the same as the third embodiment.

[0090] The same effects as in the third embodiment are achieved in the fourth embodiment. Furthermore, in the fourth embodiment, the voltage terminal Hc of the control chip 41 and the die pad 65 can be electrically connected by a simple process of joining the control chip 41 to the die pad 65 with a conductive bonding material. In other words, the aforementioned wire Qc (Figure 11) that electrically connects the voltage terminal Hc and the die pad 65 is unnecessary. However, in the fourth embodiment as in the third embodiment, wire Qc may be installed.

[0091] E: Variation The following are examples of specific modifications that may be added to each of the embodiments exemplified above. Two or more embodiments may be arbitrarily selected from the above embodiments and the following modifications, and combined as appropriate, within the bounds of mutual consistency.

[0092] (1) In the embodiments described above, the semiconductor chip 30[k] is shown to include a resistive element R[k], but as illustrated in Figure 13, the resistive element R[k] may be omitted from the semiconductor chip 30[k]. In the configuration of Figure 13, the cathode 36 is formed on the second surface F2 of the semiconductor substrate 31 so as to be in contact with the second surface F2. The resistive element R[k] is externally connected to the semiconductor device 100 together with the capacitive element B[k].

[0093] The anode 32 on the first surface F1 is bonded to the surface of the die pad 65, as in the embodiments described above. On the other hand, the cathode 36 on the second surface F2 is electrically connected to the power terminal Hb[k] of the control chip 41 via the first wiring Qb1 of the wire Qb[k], and is also electrically connected to the connection pad 66[k] via the second wiring Qb2 of the same wire Qb[k].

[0094] As can be understood from the above examples, in one embodiment of this disclosure, the cathode 36 of the diode D[k] is electrically connected to the power supply terminal Hb[k]. Whether the cathode 36 is indirectly connected to the power supply terminal Hb[k] via a resistive element R[k] (Figure 3) or directly connected to the power supply terminal Hb[k] (Figure 13) is irrelevant in this disclosure.

[0095] (2) In the embodiments described above, the housing 50 is shown as comprising a resin case 51, a support plate 52, and a sealing resin 53. However, the configuration of the housing 50 is not limited to these examples. For example, a fully molded type housing 50 in which the resin case 51 and the sealing resin 53 are integrated may also be used. In the fully molded type housing 50, an insulating layer 521 may also be integrated in addition to the resin case 51 and the support plate 52. In the fully molded type housing 50, the resin case 51 and the sealing resin 53 (and furthermore, the insulating layer 521) are formed collectively from various resin materials such as epoxy resin. In addition, the sealing resin 53 in the embodiments described above and the fully molded type housing 50 in this modified example may include various insulating fillers such as silicon oxide or aluminum oxide in addition to the resin material. In the housing 50 exemplified in the embodiments described above and in this modified example, the heat sink 522 may be omitted.

[0096] (3) In the above-described embodiments, the connection between the first wiring Qb1 and the second wiring Qb2 is shown as a stitch, but the first wiring Qb1 and the second wiring Qb2 may be separate wirings.

[0097] (4) In the above-described embodiments, the semiconductor substrate 31 of the semiconductor chip 30[k] is shown as a p-type semiconductor substrate as an example, but the conductivity type of the semiconductor substrate 31 is not limited to the above examples. For example, an n-type semiconductor substrate may be used as the semiconductor substrate 31, and a p-type semiconductor region 31p may be formed on the first surface F1. As can be understood from the above description, the conductivity type of the semiconductor substrate 31 itself is arbitrary as long as the pn junction of the diode D[k] is formed by the p-type semiconductor region 31p on the first surface F1 and the n-type semiconductor region 31n on the second surface F2.

[0098] (5) In each of the above embodiments, RC-IGBTs including IGBTs and FWDs were exemplified as drive chips 21[k] and 22[k], but drive chip 21[k] or drive chip 22[k] may consist of an IGBT chip and an FWD chip. Also, the IGBT may be replaced with other transistors such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). In the embodiment employing MOSFETs, the main electrode C is one of the source electrode and the drain electrode, and the main electrode E is the other of the source electrode and the drain electrode.

[0099] E: Addendum From the various forms exemplified above, the following configurations can be identified, for example.

[0100] A semiconductor device according to one aspect of the present disclosure (Aspect 1) comprises a power semiconductor element, a control chip having a plurality of terminals including a first terminal and a second terminal and controlling the power semiconductor element using a power supply voltage supplied to the second terminal, a semiconductor chip including a first conductor for supplying a predetermined control voltage to the first terminal, a first wiring for supplying the power supply voltage to the second terminal, and a diode used in a bootstrap operation to generate the power supply voltage, wherein the semiconductor chip includes a first surface and a second surface located on opposite sides of each other, and a pn junction of the diode is formed by a p-type semiconductor region of the first surface and an n-type semiconductor region of the second surface, an anode formed on the first surface and bonded to the surface of the first conductor, and a cathode formed on the second surface and electrically connected to the second terminal via the first wiring.

[0101] In the above embodiment, the anode of the diode is formed on the first surface of the semiconductor substrate, and the anode of the diode is joined to the first conductor for supplying a control voltage to the first terminal of the control chip. That is, the diode is installed so that the anode faces the first conductor. On the other hand, the cathode formed on the second surface of the semiconductor substrate is electrically connected to the second terminal of the control chip via wiring such as a wire. With the above configuration, compared to a configuration in which the anode formed on the second surface of the semiconductor substrate is connected to the first conductor by a wire, the area required to install the elements for controlling the power semiconductor device (control chip, first conductor, and diode) is reduced. This reduction in area makes it possible to achieve both miniaturization of the semiconductor device and improvement of power density by increasing the size of the power semiconductor device.

[0102] "Bootstrap operation" is an operation that generates the power supply voltage of a control chip by charging a capacitive element (bootstrap capacitor) through a charging path from the first conductor via a diode. In other words, the power supply voltage is generated by bootstrap operation using the control voltage. For example, bootstrap operation can generate a power supply voltage that is higher by the control voltage than the potential of the main electrode (e.g., emitter) of a power semiconductor element.

[0103] "An anode is formed on the first surface" means that part or all of the anode overlaps the first surface in a plan view (i.e., the anode is formed above the first surface). Therefore, in addition to configurations in which the anode is directly formed on the first surface and in contact with the first surface, configurations in which other elements are interposed between the anode and the first surface also satisfy the requirement that "an anode is formed on the first surface."

[0104] The same applies to the relationship between the cathode and the second surface. That is, "a cathode is formed on the second surface" means that part or all of the cathode overlaps with the second surface in a plan view (i.e., the cathode is formed above the second surface). Therefore, in addition to configurations in which the cathode is directly formed on the second surface and comes into contact with it, configurations in which other elements are interposed between the cathode and the second surface also satisfy the requirement that "a cathode is formed on the second surface."

[0105] The statement that element A is "electrically connected" to element B includes not only configurations in which elements A and B are directly connected, but also configurations in which another conductor is interposed between elements A and B. For example, a configuration in which the cathode of a diode is electrically connected to the second terminal includes not only configurations in which the cathode of the diode is directly connected to the second terminal, but also configurations in which the cathode of the diode is indirectly connected to the second terminal via another conductor (e.g., a resistive element).

[0106] In a specific example of Embodiment 1 (Embodiment 2), the device further comprises a second conductor to which a capacitive element used in the bootstrap operation is externally connected, and a second wiring that electrically connects the cathode and the second conductor. In this embodiment, the second terminal of the control chip is electrically connected to the second conductor via the first wiring, the cathode of the diode, and the second wiring. Therefore, a capacitive element with a desired capacitance externally connected to the semiconductor device can be used in the bootstrap operation.

[0107] In a specific example of Embodiment 2 (Embodiment 3), the connection between the first wiring and the second wiring is a stitch on the second surface. In this embodiment, the second conductor for external connection, the cathode of the diode, and the second terminal of the control chip are electrically connected to each other by stitch bonding. Therefore, compared to a configuration in which the first wiring and the second wiring are installed individually, the process of electrically connecting the second conductor, the cathode, and the second terminal is simplified.

[0108] In a specific example of Embodiment 2 or Embodiment 3 (Embodiment 4), the system further comprises a third conductor to which a ground voltage is supplied, and the control chip is bonded to the surface of the third conductor. In the above embodiments, the control chip is bonded to the surface of the third conductor to which the ground voltage is supplied. That is, the control chip is installed so as to overlap the third conductor in a plan view. Therefore, the terminal to which the ground voltage is supplied among the multiple terminals of the control chip can be easily connected to the third conductor.

[0109] In a specific example of Embodiment 4 (Embodiment 5), the control chip further includes a grounding terminal formed on the surface facing the third conductor, and the control chip is joined to the third conductor by a conductive bonding material. According to the above embodiment, the grounding terminal of the control chip and the third conductor can be electrically connected by a simple process of joining the control chip to the third conductor with a conductive bonding material.

[0110] In a specific example of Embodiment 4 or Embodiment 5 (Embodiment 6), the third conductor is located between the power semiconductor element and the first conductor in a plan view, and the first conductor is located between the third conductor and the second conductor in a plan view. According to the above embodiments, the power semiconductor element, the third conductor, the first conductor and the second conductor are arranged in the above order in a plan view. Therefore, the second terminal of the control chip joined to the third conductor, the semiconductor chip joined to the first conductor and the second conductor can be efficiently connected.

[0111] In a specific example of Embodiment 2 or Embodiment 3 (Embodiment 7), the control chip is bonded to the surface of the first conductor. In the above embodiments, the control chip is bonded to the surface of the first conductor. That is, the control chip is installed so as to overlap the first conductor in a plan view. Therefore, compared to a configuration in which the control chip does not overlap the first conductor in a plan view, the area required to install the elements for controlling the power semiconductor device (control chip, first conductor, and diode) can be reduced more effectively.

[0112] In a specific example of Embodiment 7 (Embodiment 8), the control chip further includes a third terminal formed on the surface facing the first conductor, and the control chip is joined to the first conductor by a conductive bonding material. According to the above embodiment, the third terminal of the control chip and the first conductor can be electrically connected by a simple process of joining the control chip to the first conductor with a conductive bonding material.

[0113] In a specific example of Embodiment 7 or Embodiment 8 (Embodiment 9), the first conductor is located between the power semiconductor element and the second conductor in a plan view. According to the above embodiments, the power semiconductor element, the first conductor, and the second conductor are arranged in the above order in a plan view. Therefore, the second terminal of the control chip joined to the first conductor, the semiconductor chip joined to the first conductor, and the second conductor can be efficiently connected.

[0114] In any specific example of Embodiments 1 to 9 (Embodiment 10), the first conductor includes a first portion and a second portion that protrudes from the periphery of the first portion in a plan view, and at least a portion of the semiconductor chip overlaps with the second portion in a plan view. In the above embodiment, the second portion of the first conductor that protrudes from the periphery of the first portion in a plan view provides sufficient space for the semiconductor chip to be installed.

[0115] In any specific example of Embodiments 1 to 10 (Embodiment 11), the semiconductor chip further includes a current-limiting resistor electrically connected to the cathode. According to the above embodiments, the current flowing through the diode during bootstrap operation can be limited by the current-limiting resistor.

[0116] In a specific example of Embodiment 11 (Embodiment 12), the semiconductor chip further includes an insulating layer formed on the second surface and a resistive layer formed on the insulating layer, and the resistive element is composed of the resistive layer. According to the above embodiment, a resistive element for current limiting can be easily formed by laminating an insulating layer and a resistive layer on the second surface.

[0117] A semiconductor chip according to one aspect of the present disclosure (Aspect 13) includes a diode, which is electrically connected between a first terminal, to which a predetermined control voltage is supplied, and a second terminal, to which a power supply voltage is supplied, and is used in a bootstrap operation to generate the power supply voltage, among a plurality of terminals of a control chip for controlling a power semiconductor element, the semiconductor chip comprising a semiconductor substrate including a first surface and a second surface located on opposite sides of each other, wherein a pn junction of the diode is formed by a p-type semiconductor region of the first surface and an n-type semiconductor region of the second surface, and an anode formed on the first surface and bonded to the surface of the first conductor, and a cathode formed on the second surface and electrically connected to the second terminal via a first wiring.

[0118] In a specific example of Embodiment 13 (Embodiment 14), the anode includes a metal film formed of nickel or a nickel alloy, and the cathode includes a metal film formed of aluminum or an aluminum alloy. According to the above embodiments, the anode can be well bonded to a conductive bonding material such as solder or conductive paste. Also, a wire can be well bonded to the cathode.

[0119] In a specific example of Embodiment 13 or Embodiment 14 (Embodiment 15), the current-limiting resistor element is further electrically connected to the cathode. According to the above embodiments, the current flowing through the diode during bootstrap operation can be limited by the current-limiting resistor element.

[0120] Incidentally, when mounting the semiconductor chip used in the aforementioned bootstrap operation, one configuration is envisioned in which one of the anodes and cathodes is bonded to a conductive bonding material such as solder or conductive paste, and a wire is bonded to the other of the anode and cathode. In this configuration, the bondability of the anode or cathode to the conductive bonding material and wire becomes a challenge.

[0121] From the viewpoint of solving the above problems, a semiconductor chip according to one aspect of the present disclosure (Aspect 16) is a semiconductor chip including a diode used in a bootstrap operation to generate a power supply voltage for a control chip that controls a power semiconductor element, and comprises a semiconductor substrate including a first surface and a second surface located on opposite sides of each other, wherein the pn junction of the diode is formed by a p-type semiconductor region of the first surface and an n-type semiconductor region of the second surface; an anode including a metal film formed of nickel or a nickel alloy on the first surface; a cathode including a metal film formed of aluminum or an aluminum alloy on the second surface; and a current-limiting resistor element electrically connected to the cathode. According to the above aspect, the anode can be well bonded to a conductive bonding material such as solder or conductive paste. Also, a wire can be well bonded to the cathode.

[0122] In a specific example of Embodiment 15 or Embodiment 16 (Embodiment 17), the device further comprises an insulating layer formed on the second surface and a resistive layer formed on the insulating layer, wherein the resistive element is composed of the resistive layer. According to the above embodiments, a resistive element for current limiting can be easily formed by laminating an insulating layer and a resistive layer on the second surface. [Explanation of Symbols]

[0123] 100...Semiconductor device, 102...Control device, 103,104...External power supply, 21[k](21[U],21[V],21[W])...Driver chip, 22[k](22[U],22[V],22[W])...Driver chip, 30[k](30[U],30[V],30[W])...Semiconductor chip, 31...Semiconductor substrate, 31n...n-type semiconductor region, 31p...p-type semiconductor region F1...First surface, F2...Second surface, 32...Anode, 33...First insulating layer, 34...Resistive layer, 35...Second insulating layer, 36...Cathode, 37...Connecting electrode, 38...Protective layer, 381...Coating part, 382...Partition part, 383...Opening, 41...Control chip, 42...Control chip, 50...Housing, 51...Resin case, 52...Support plate, 521...Insulating layer, 522...Heat sink, 53...Sealing resin, 55...Element Sub-region, 56... Terminal region, 57... Control region, 60... Lead frame, 61~65... Die pad, 66[k](66[U],66[V],66[W])... Connection pad, 651... First part, 652[k](652[U],652[V],652[W])... Second part, D[k](D[U],D[V],D[W])... Diode, R[k](R[U],R[V] ,R[W])...resistive element, B[k](B[U],B[V],B[W])...capacitive element, H(Hin[k],Hout[k],Hb[k],Hs[k],Hc,Hg)...terminal, L( Lin[k],Lout[k],Lc,Lg)...terminal, Lc...voltage terminal, Qb,Qc,Qg...wire, Qb1...first wiring, Qb2...second wiring, R[k](R[U],R[V],R [W] )...Resistance element, T(Tin_H[k],Tin_L[k],Tout[k],Tc_H,Tc_L,Tg,Tp,Tn[k],Tbs[k])...Connection terminal, α...Charging path.

Claims

1. Power semiconductor elements and A control chip comprising a plurality of terminals including a first terminal and a second terminal, which controls the power semiconductor element using the power supply voltage supplied to the second terminal, A first conductor for supplying a predetermined control voltage to the first terminal, A first wiring for supplying the aforementioned power supply voltage to the second terminal, A semiconductor chip including a diode used in a bootstrap operation to generate the aforementioned power supply voltage, A second conductor to which a capacitive element used in the bootstrap operation is externally connected, Second wiring and It is equipped with, The aforementioned semiconductor chip is A semiconductor substrate comprising a first surface and a second surface located on opposite sides of each other, wherein the pn junction of the diode is formed by the p-type semiconductor region of the first surface and the n-type semiconductor region of the second surface, an anode formed on the first surface and joined to the surface of the first conductor, A cathode formed on the second surface and electrically connected to the second terminal via the first wiring, The second wiring electrically connects the cathode and the second conductor. The connection between the first wiring and the second wiring is a stitch on the second surface. Semiconductor equipment.

2. It further comprises a third conductor to which a ground voltage is supplied, The control chip is bonded to the surface of the third conductor. The semiconductor device according to claim 1.

3. The control chip further includes a grounding terminal formed on the surface facing the third conductor, The control chip is joined to the third conductor by a conductive bonding material. The semiconductor device according to claim 2.

4. The third conductor is located between the power semiconductor element and the first conductor in a plan view. The first conductor is located between the third conductor and the second conductor in a plan view. A semiconductor device according to claim 2 or claim 3.

5. The control chip is bonded to the surface of the first conductor. The semiconductor device according to claim 1.

6. The control chip further includes a third terminal formed on the surface facing the first conductor, The control chip is joined to the first conductor by a conductive bonding material. The semiconductor device according to claim 5.

7. The first conductor is located between the power semiconductor element and the second conductor in a plan view. A semiconductor device according to claim 5 or claim 6.

8. The first conductor is Part 1 and, Including a second portion that protrudes from the periphery of the first portion in a plan view, At least a portion of the semiconductor chip overlaps the second portion in a plan view. A semiconductor device according to any one of claims 1 to 7.

9. The semiconductor chip further includes a current-limiting resistor element electrically connected to the cathode. A semiconductor device according to any one of claims 1 to 8.

10. The aforementioned semiconductor chip is An insulating layer formed on the second surface, The present invention further includes a resistive layer formed on the insulating layer, The resistive element is composed of the resistive layer. The semiconductor device according to claim 9.

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