Information processing device, information processing system, information processing method, and information processing program

Abstract

To provide an information processing apparatus, an information processing system, an addition and subtraction apparatus, a multiplication apparatus, an information processing method, and an information processing program capable of calculating a large-scale matrix at high speed.SOLUTION: An information processing apparatus 10 comprises: an acquisition unit 10a for acquiring addition and subtraction operation performance of one or more addition and subtraction apparatuses 2j that perform addition and subtraction and multiplication operation performance of one or more multiplication apparatuses 3i that perform multiplication; a calculation unit 10b for calculating a matrix size that makes the processing time for performing one submatrix multiplication equal to the processing time for performing submatrix addition and subtraction a predetermined number of times as a critical matrix size NC; and a selection unit 10c for selecting the number of times of divisions n in the matrix to be calculated using the calculated critical matrix size NC.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to an information processing device, an information processing system, an addition / subtraction device, a multiplication device, an information processing method, and an information processing program. [Background technology]

[0002] Patent Document 1 describes a parallel computer having multiple processor elements, a control device, a first communication channel connecting them, and a second communication channel connecting adjacent processor elements other than the first communication channel. The parallel computer in Patent Document 1 performs matrix multiplication calculations without requiring expensive semiconductor devices or complex networks.

[0003] Patent Document 2 describes an information processing device in which an accelerator unit can be detached from the main unit. The information processing device in Patent Document 2 sets the drive voltage or drive frequency for driving the main unit-side arithmetic unit and the accelerator-side arithmetic unit according to performance information.

[0004] Patent Document 3 describes a multiply-accumulate circuit that includes a multiplier and an adder for performing matrix calculations. In the multiply-accumulate circuit of Patent Document 3, the multiplier performs the multiplication in parallel of a subrow vector obtained by dividing the rows of matrix A and a subcolumn vector obtained by dividing the columns of matrix B, and the adder adds the results of the multiplication.

[0005] Patent Document 4 describes a method for processing data signals received via a communication channel, which involves inverting a matrix having multiple components that represent the characteristics of the communication channel, and then processing the data using the inverted matrix. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 09-062656 [Patent Document 2] Japanese Patent Publication No. 2003-015785 [Patent Document 3] Japanese Patent Publication No. 2009-245381 [Patent Document 4] Special Publication No. 2009-527182 [Overview of the project] [Problems that the invention aims to solve]

[0007] For example, there is a need to rapidly compute large matrices used in processing data signals in information processing devices.

[0008] In view of the above-mentioned problems, the purpose of this disclosure is to provide an information processing device, an information processing system, an addition / subtraction device, a multiplication device, an information processing method, and an information processing program that can calculate large matrices at high speed. [Means for solving the problem]

[0009] An information processing device according to one embodiment includes: an acquisition unit that acquires the addition and subtraction calculation performance of one or more addition and subtraction devices that perform addition and subtraction, and the multiplication calculation performance of one or more multiplication devices that perform multiplication; a calculation unit that calculates a matrix size as a critical matrix size such that the processing time for one multiplication of a submatrix is ​​equal to the processing time for performing addition and subtraction of the submatrix a predetermined number of times; and a selection unit that selects the number of divisions of the matrix to be calculated using the calculated critical matrix size.

[0010] An information processing system according to one embodiment comprises one or more addition / subtraction devices that perform addition and subtraction, one or more multiplication devices that perform multiplication, and an information processing device connected to the addition / subtraction devices and the multiplication devices, wherein the information processing device includes an acquisition unit that acquires the addition / subtraction calculation performance of the addition / subtraction devices and the multiplication calculation performance of the multiplication devices, a calculation unit that calculates a matrix size as a critical matrix size such that the processing time for one multiplication of a submatrix is ​​equal to the processing time for performing addition and subtraction of the submatrix a predetermined number of times, and a selection unit that selects the number of divisions of the matrix to be calculated using the calculated critical matrix size.

[0011] An addition / subtraction device according to one embodiment is connected to an information processing device having an acquisition unit that acquires the addition / subtraction operation performance and the multiplication operation performance of one or more multipliers that perform multiplication; a calculation unit that calculates a matrix size as a critical matrix size at which the processing time for one multiplication of a submatrix is ​​equal to the processing time for performing addition or subtraction of the submatrix a predetermined number of times; and a selection unit that uses the calculated critical matrix size to select the number of divisions in the matrix to be calculated, and has the addition / subtraction operation performance to perform addition and subtraction.

[0012] A multiplication device according to one embodiment is connected to an information processing device having the following: an acquisition unit that acquires the multiplication operation performance and the addition / subtraction operation performance of one or more addition / subtraction devices that perform addition and subtraction; a calculation unit that calculates a matrix size as a critical matrix size at which the processing time for one multiplication of a submatrix and the processing time for performing addition and subtraction of the submatrix a predetermined number of times are equal; and a selection unit that uses the calculated critical matrix size to select the number of divisions in the matrix to be calculated, and has the multiplication operation performance to perform multiplication.

[0013] An information processing method according to one embodiment includes the steps of: obtaining the addition and subtraction calculation performance of one or more addition and subtraction devices that perform addition and subtraction, and the multiplication calculation performance of one or more multiplication devices that perform multiplication; calculating a matrix size as a critical matrix size such that the processing time for one multiplication of a submatrix is ​​equal to the processing time for performing addition and subtraction of the submatrix a predetermined number of times; and selecting the number of divisions of the matrix to be calculated using the calculated critical matrix size.

[0014] An information processing program according to one embodiment causes a computer to perform the following steps: acquire the addition and subtraction calculation performance of one or more addition and subtraction devices that perform addition and subtraction, and the multiplication calculation performance of one or more multiplication devices that perform multiplication; calculate a critical matrix size such that the processing time for one multiplication of a submatrix is ​​equal to the processing time for performing addition and subtraction of the submatrix a predetermined number of times; and use the calculated critical matrix size to select the number of divisions for the matrix to be calculated. [Effects of the Invention]

[0015] According to this disclosure, it is possible to provide an information processing device, an information processing system, an addition / subtraction device, a multiplication device, an information processing method, and an information processing program that can compute large matrices at high speed. [Brief explanation of the drawing]

[0016] [Figure 1] This figure illustrates the matrix multiplication formulas for a normal matrix and a matrix multiplication formula using the Strassen algorithm according to Embodiment 1. [Figure 2] This figure illustrates the relationship between the conventional matrix multiplication formula and the matrix multiplication formula using the Strassen algorithm according to Embodiment 1. [Figure 3] This figure illustrates the calculation of the number of divisions for matrix multiplication using the Strassen algorithm according to Embodiment 1. [Figure 4] This is a diagram illustrating an information processing system according to Embodiment 1. [Figure 5] This is a block diagram illustrating an addition / subtraction management device in the information processing system according to Embodiment 1. [Figure 6] This is a block diagram illustrating an addition / subtraction device in the information processing system according to Embodiment 1. [Figure 7] This is a block diagram illustrating a multiplication management device in the information processing system according to Embodiment 1. [Figure 8] This is a block diagram illustrating a multiplication device in the information processing system according to Embodiment 1. [Figure 9] This is a block diagram illustrating an information processing device in the information processing system according to Embodiment 1. [Figure 10] This is a flowchart illustrating an example of the information processing method according to Embodiment 1. [Figure 11] This is a block diagram illustrating an information processing device according to Embodiment 2. [Figure 12] This is a flowchart illustrating an example of the information processing method according to Embodiment 2. [Modes for carrying out the invention]

[0017] The embodiments will be described below with reference to the drawings. For clarity of explanation, the following descriptions and drawings have been omitted and simplified as appropriate. In addition, the same elements are denoted by the same reference numerals in each drawing, and redundant explanations have been omitted where necessary.

[0018] (Embodiment 1) The information processing system and information processing device according to Embodiment 1 will now be described. The information processing system and information processing device of this embodiment perform high-speed calculation of large matrix multiplication using a matrix partitioning algorithm. Matrix multiplication is one of the basic linear algebra calculations and occupies an important position in numerical calculations in many scientific and technological fields. With the progress of scientific and technological fields, the need for multiplication of large matrices is increasing. One example of an algorithm that speeds up multiplication of large matrices is the Strassen algorithm.

[0019] To speed up the multiplication of large matrices using the Strassen algorithm, it is conceivable to use multiple machines. Matrix calculations can be accelerated by performing parallel computation of addition, subtraction, or multiplication of submatrices, taking into account the data dependencies of each operation on the submatrices. As the matrices to be multiplied become larger, the memory requirements and the need for parallelism necessitate the use of multiple machines.

[0020] Industrial applications of the Strassen algorithm include methods for processing data signals, data processing units, and computer program products, as described in Patent Document 4. Below, the Strassen algorithm will be explained as an example of multiplication of large matrices using a matrix partitioning algorithm. Then, the information processing system will be explained, and the addition / subtraction management device, addition / subtraction device, multiplication management device, multiplication device, and information processing device that constitute the information processing system will be described. After that, the information processing method will be explained.

[0021] <Strassen Algorithm> FIG. 1 is a diagram illustrating a normal matrix multiplication formula and a matrix multiplication formula by the Strassen algorithm according to Embodiment 1. FIG. 2 is a diagram illustrating the relationship between the normal matrix multiplication formula and the matrix multiplication formula by the Strassen algorithm according to Embodiment 1. As shown in FIGS. 1 and 2, in normal matrix multiplication, the multiplication of submatrices is performed 8 times, and the addition and subtraction of submatrices are performed 4 times. Specifically, as shown below, in the multiplication of matrix A and matrix B in equation (1), the multiplications included twice in each of equations (2) to (5) (a total of 8 multiplications), and the addition and subtraction included once in each of equations (2) to (5) (a total of 4 addition and subtraction) are performed.

[0022] C = AB (1)

[0023] C 12 , 12 , 22 , 12 , 22 , 12 , 21 , 11 , , 11 , 22 , 22 , , , 22 , , , <​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​(8) S4=A 12 -A 21 (9) S5=B 12 -B 11 (10) S6=B 22 -S5(11) S7=B 22 -B 12 (12) S8 = S6 - A 21 (13) M1=S2S6(14) M2=A 11 B 11 (15) M3=A 12 B 21 (16) M4=S3S7(17) M5=S1S5(18) M6=S4B 22 (19) M7=A 22 S8(20) V1 = M1 + M2 (21) V2 = V1 + M4(22) V3 = M5 + M6 (23) C 11 =M2+M3(24) C 12 =V1+V3(25) C 21 =V2-M7(26) C 22 =V2+M5(27)

[0025] Therefore, matrix multiplication using the Strassen algorithm reduces the number of submatrix multiplications from 8 to 7 compared to ordinary matrix multiplication. On the other hand, it increases the number of submatrix additions and subtractions from 4 to 15. Thus, multiplication using the Strassen algorithm reduces the number of submatrix multiplications.

[0026] For an N x N square matrix, the number of numerical operations in matrix multiplication is N. 3 It increases in the order of n. In contrast, the number of numerical operations in matrix addition and subtraction is N 2It increases by an order of magnitude. Therefore, the larger the matrix size, the faster the Strassen algorithm becomes compared to ordinary matrix multiplication.

[0027] The Strassen algorithm is a divide-and-conquer method. The Strassen algorithm can be applied again to the multiplication of submatrices M1 to M7 shown in Figure 1 and equations (14) to (20) above. Furthermore, the Strassen algorithm can be applied again to the multiplication of those submatrices, i.e., the grandchild submatrices. By repeatedly performing this division, further speed improvements are possible. After n divisions, the speed improvement (also called the speed-up rate) of the calculation using the Strassen algorithm compared to normal matrix multiplication is approximately (8 / 7). n Therefore, the speedup rate increases as the number of divisions n increases. Here, 8 is the number of submatrix multiplications in normal matrix multiplication, and 7 is the number of submatrix multiplications in the Strassen algorithm.

[0028] However, as the matrix is ​​repeatedly partitioned, the size of the submatrices decreases. Therefore, the advantage of the Strassen algorithm, which reduces the number of submatrix multiplications and increases the number of additions and subtractions, is lost. Consequently, the number of partitions cannot be increased indefinitely.

[0029] To further speed up large-scale matrix multiplication using the Strassen algorithm, it is conceivable to use multiple machines (also called devices). Matrix calculations can be accelerated by performing addition, subtraction, or multiplication of submatrices in parallel using multiple machines. In this case, it is preferable to perform parallel calculations on multiple machines suitable for each operation, taking into account the data dependencies of each operation on the submatrices shown in Figures 1 and 2.

[0030] Furthermore, as the size of the multiplication matrix increases, the memory requirements also increase, making parallel computing on multiple machines necessary. However, until now, there has been no method to predict the optimal number of partitions—a speed-up technique specific to the Strassen algorithm—when using multiple machines in this way.

[0031] To select the optimal number of divisions, it is necessary to find the size of the submatrix at which the advantages of the Strassen algorithm disappear, that is, the critical matrix size at which the speedup rate of multiplication by the Strassen algorithm compared to ordinary multiplication becomes 1.0. For example, the critical matrix size can be found by experimentation. However, this becomes a very time-consuming task when using multiple machines. In particular, if the machine available varies each time depending on the machine's availability, the critical matrix size will differ each time. For example, if there are many machines with high performance in addition and subtraction and few machines with high performance in multiplication, it is necessary to increase the number of divisions to reduce the cost of multiplication. Conversely, if the opposite is true, it is necessary to decrease the number of divisions to reduce the increase in the cost of addition and subtraction.

[0032] This embodiment determines the optimal number of divisions when using multiple machines with different computing performance, for example, for multiplication of large matrices using the Strassen algorithm. This enables high-speed computation of large matrices.

[0033] As mentioned earlier, as the partitioning is repeated, the size of the submatrices gradually decreases. This eliminates the advantage of the Strassen algorithm, which reduces the number of submatrix multiplications and increases the number of additions and subtractions. First, we find the matrix size at which this advantage disappears, i.e., the critical matrix size N at which matrix multiplication by the Strassen algorithm is faster than standard matrix multiplication. C This is calculated using the computing power of the machine being used. Below, the critical matrix size N C The selection method will be explained in detail.

[0034] Matrix multiplication using the Strassen algorithm involves one less submatrix multiplication and 11 more additions / subtractions compared to standard matrix multiplication. Critical matrix size N C This matrix size is selected so that the processing time for one submatrix multiplication is equal to the processing time for eleven submatrix additions and subtractions.

[0035] Therefore, first, in order to calculate the processing time for addition, subtraction, and multiplication, the computational performance of the arithmetic units used for addition, subtraction, and multiplication is obtained. At that time, the settings for how the arithmetic units will be used in parallel for each of the addition, subtraction, and multiplication operations are set. In addition, the number of times each arithmetic unit will sequentially perform addition, subtraction, or multiplication is set. Note that the arithmetic unit that performs addition and subtraction is called the addition / subtraction unit, and the arithmetic unit that performs multiplication is called the multiplication unit.

[0036] Based on the above settings, the processing time for one submatrix multiplication and the processing time for eleven submatrix additions and subtractions are expressed as functions of matrix size N. The critical matrix size N is defined as the size at which the processing time for one submatrix multiplication and the processing time for eleven submatrix additions and subtractions are equal. C This is derived as follows. The formula used for the calculation is equation (28) below.

[0037] JPEG0007848495000001.jpg26168 Herein lies the following: R mi This indicates the multiplication performance of each multiplier. R sj This indicates the addition and subtraction performance of each addition and subtraction device. x i , y j This indicates the number of sequential operations for each multiplier and each addition / subtraction device.

[0038] Multiplication using the Strassen algorithm reduces the number of submatrix multiplications from 8 to 7 compared to normal multiplication. On the other hand, the number of submatrix additions and subtractions increases by 11. The left side of equation (28) is the computation time reduction due to reducing the number of square matrix multiplications from 8 to 7. The right side of equation (28) is the computation time increase due to increasing the number of additions and subtractions of the same matrix by 11. (2N C -1)N C 2 is, N C Row N C This is the number of operations performed in the multiplication of a square matrix of columns. The right-hand side is N. C 2 This represents the number of operations performed in addition and subtraction. On both sides of equation (28), these operations are divided by the processing performance (processing speed) of the arithmetic unit used.

[0039] When arithmetic units used for matrix multiplication or addition / subtraction perform operations in parallel, their performance is added together. If a single arithmetic unit performs matrix multiplication or addition / subtraction x times sequentially, its performance becomes 1 / x. Equation (28) is given for matrix size N. C This demonstrates that matrix multiplication using the Strassen algorithm is equivalent in speed to regular matrix multiplication.

[0040] Next, N calculated using equation (28) C Using this method, the fastest number of divisions is selected as shown in Figure 3. Figure 3 is an example of how the number of divisions for matrix multiplication is calculated using the Strassen algorithm according to Embodiment 1. As shown in Figure 3, if the initial matrix is ​​N rows and N columns, after n divisions, the size of the submatrix is ​​N / 2 n Therefore, the optimal number of divisions is N / 2. n is N C That's all for N C This is the closest result. In this way, data on the computational performance of the arithmetic units to be used is given. It may be decided which submatrix multiplication or which addition / subtraction operations of the Strassen algorithm those arithmetic units will be assigned to. This allows for the selection of the optimal number of divisions for the combination of arithmetic units.

[0041] <Information Processing System> Next, an information processing system for selecting the number of divisions for multiplication of a large matrix will be described. Figure 4 is a configuration diagram illustrating an information processing system according to Embodiment 1. As shown in Figure 4, the information processing system 1 comprises an information processing device 10, an addition / subtraction management device 20, one or more addition / subtraction devices 21-2j, a multiplication management device 30, and one or more multiplication devices 31-3i. One or more addition / subtraction devices 21-2j are collectively referred to as addition / subtraction device 2j. One or more multiplication devices 31-3i are collectively referred to as multiplication device 3i. The information processing device 10, the addition / subtraction management device 20, the addition / subtraction device 2j, the multiplication management device 30, and the multiplication device 3i each have the functions of an information processing means, an addition / subtraction management means, an addition / subtraction means, a multiplication management means, and a multiplication means, respectively.

[0042] The information processing device 10 is connected to the addition / subtraction management device 20 via a communication line capable of transmitting information. The addition / subtraction management device 20 is connected to one or more addition / subtraction devices 2j via a communication line capable of transmitting information. Therefore, the information processing device 10 is connected to one or more addition / subtraction devices 2j via the addition / subtraction management device 20. In addition, the information processing device 10 is connected to the multiplication management device 30 via a communication line capable of transmitting information. The multiplication management device 30 is connected to one or more multiplication devices 3i via a communication line capable of transmitting information. Therefore, the information processing device 10 is connected to one or more multiplication devices 3i via the multiplication management device 30. Each configuration will be described below.

[0043] <Addition / subtraction management device> Figure 5 is a block diagram illustrating an addition / subtraction management device 20 in an information processing system 1 according to Embodiment 1. As shown in Figure 5, the addition / subtraction management device 20 comprises an acquisition unit 20a, a storage unit 20b, and a transmission unit 20c. The acquisition unit 20a, storage unit 20b, and transmission unit 20c each function as an acquisition means, a storage means, and a transmission means, respectively.

[0044] The acquisition unit 20a acquires the results of pre-measured addition and subtraction calculation performance of each addition and subtraction device 2j from each addition and subtraction device 2j. The storage unit 20b stores an addition and subtraction list file LF20 which lists the addition and subtraction calculation performance of each addition and subtraction device 2j. The addition and subtraction list file LF20 records the number of each addition and subtraction device 2j, the operation it is responsible for, the type of operation (multiplication or addition / subtraction), and its calculation performance. The transmission unit 20c transmits the addition and subtraction calculation performance and calculation results of each addition and subtraction device 2j to the information processing device 10.

[0045] <Addition / subtraction device> Figure 6 is a block diagram illustrating an addition / subtraction device 2j in an information processing system 1 according to Embodiment 1. As shown in Figure 6, the addition / subtraction device 2j comprises an acquisition unit 2ja, a calculation unit 2jb, and a transmission unit 2jc. The acquisition unit 2ja, the calculation unit 2jb, and the transmission unit 2jc each function as an acquisition means, a calculation means, and a transmission means, respectively.

[0046] The acquisition unit 2ja acquires the submatrix to be operated on from the information processing device 10 via the addition / subtraction management device 20. The calculation unit 2jb performs addition and subtraction on the submatrix. The transmission unit 2jc transmits the calculation performance and the calculation result of the addition and subtraction to the information processing device 10 via the addition / subtraction management device 20.

[0047] The addition / subtraction device 2j is preferably one with excellent addition / subtraction calculation performance. For example, one addition / subtraction device 21 may be connected to the addition / subtraction management device 20. In this case, the addition / subtraction device 21 is S1 to S8, V1 to V3 and C as shown in Figure 2 and equations (6) to (13) and (21) to (27). 11 ~C 22 The calculations are assigned to the addition / subtraction devices 2j. Note that the number of addition / subtraction devices 2j connected to the addition / subtraction management device 20 is not limited to one, but may be multiple. In addition, the addition / subtraction devices 2j may obtain the submatrices to be operated on directly from the information processing device 10 without going through the addition / subtraction management device 20. The addition / subtraction devices 2j may also transmit the calculation performance and results of the addition / subtraction calculations directly to the information processing device 10 without going through the addition / subtraction management device 20.

[0048] <Multiplication Management Device> Figure 7 is a block diagram illustrating a multiplication management device 30 in an information processing system 1 according to Embodiment 1. As shown in Figure 7, the multiplication management device 30 comprises an acquisition unit 30a, a storage unit 30b, and a transmission unit 30c. The acquisition unit 30a, storage unit 30b, and transmission unit 30c each function as an acquisition means, storage means, and transmission means, respectively.

[0049] The acquisition unit 30a acquires the results of a prior measurement of the multiplication performance of each multiplier 3i from each multiplier 3i. The storage unit 30b stores a multiplication list file LF30 which lists the multiplication performance of each multiplier 3i. The multiplication list file LF30 records the number of each multiplier 3i, the operation it is responsible for, the type of operation (multiplication or addition / subtraction), and its performance. The transmission unit 30c transmits the multiplication performance and calculation results of each multiplier 3i to the information processing device 10.

[0050] <Multiplier> Figure 8 is a block diagram illustrating a multiplier 3i in the information processing system 1 according to Embodiment 1. As shown in Figure 8, the multiplier 3i comprises an acquisition unit 3ia, a calculation unit 3ib, and a transmission unit 3ic. The acquisition unit 3ia, calculation unit 3ib, and transmission unit 3ic each function as an acquisition means, calculation means, and transmission means, respectively.

[0051] The acquisition unit 3ia acquires the submatrix to be calculated from the information processing device 10 via the multiplication management device 30. The calculation unit 3ib performs multiplication of the submatrix. The transmission unit 3ic transmits the calculation capability and the calculation result of the multiplication to the information processing device 10 via the multiplication management device 30.

[0052] The multiplier 3i is preferably one with excellent multiplication performance. For example, seven multipliers 31 to 37 may be connected to the multiplication management device 30. In this case, the multipliers 31 to 37 are assigned to the calculations M1 to M7 shown in Figure 2. Note that the number of multipliers 3i connected to the multiplication management device 30 is not limited to seven. Also, the multiplier 3i may obtain the submatrix to be calculated directly from the information processing device 10 without going through the multiplication management device 30. The multiplier 3i may also transmit the multiplication performance and the multiplication result directly to the information processing device 10 without going through the multiplication management device 30.

[0053] <Information Processing Device> Figure 9 is a block diagram illustrating an information processing device 10 in an information processing system 1 according to Embodiment 1. As shown in Figure 9, the information processing device 10 includes an acquisition unit 10a, a calculation unit 10b, and a selection unit 10c. The acquisition unit 10a, the calculation unit 10b, and the selection unit 10c each have the functions of an acquisition means, a calculation means, and a selection means, respectively.

[0054] The acquisition unit 10a acquires the addition and subtraction calculation performance of one or more addition and subtraction devices 2j that perform addition and subtraction, and the multiplication calculation performance of one or more multiplication devices 3i that perform multiplication. Specifically, the acquisition unit 10a acquires the calculation performance of the addition and subtraction devices 2j and the multiplication devices 3i from the list file LF20 of the addition and subtraction management device 20 and the list file LF30 of the multiplication management device 30. Alternatively, the acquisition unit 10a may acquire the calculation performance of the addition and subtraction devices 2j and the multiplication devices 3i directly from the addition and subtraction devices 2j and the multiplication devices 3i.

[0055] The calculation unit 10b determines a critical matrix size N such that the processing time for one submatrix multiplication is approximately equal to the processing time for a predetermined number of submatrix additions and subtractions. C The calculation is performed as follows: Specifically, the calculation unit 10b uses the addition and subtraction calculation performance of the addition and subtraction device 2j and the multiplication calculation performance of the multiplication device 3i to calculate the critical matrix size N using equation (28) described above. C Calculate.

[0056] The selection unit 10c is the calculated critical matrix size N.C From this, the number of divisions in the matrix to be calculated is selected. For example, if the number of divisions in the N x N matrix to be calculated is n, the selection unit 10c determines the number of divisions n as N / (2 n ) but the critical matrix size N C The critical matrix size N is as described above. C Select the number of divisions n that is closest to the desired result.

[0057] The selection unit 10c may set an upper limit when selecting the number of divisions n. Critical matrix size N C When the process is divided up to a certain point, the calculations performed by the arithmetic units, such as the addition / subtraction unit 2j and the multiplication unit 3i, may include calculations where the speed improvement rate is 1.0x. In this case, the addition / subtraction unit 2j and the multiplication unit 3i will perform unnecessary calculations. Therefore, a threshold for the speed improvement rate may be set to prevent the arithmetic units from performing unnecessary calculations. For example, the threshold for the speed improvement rate may be set to 1.01x, and if the speed improvement rate falls below this threshold, the number of divisions may not be increased. In this way, the selection unit 10c may select the number of divisions n based on the speed improvement rate.

[0058] The information processing device 10, addition / subtraction management device 20, addition / subtraction device 2j, multiplication management device 30, and multiplication device 3i described above are information processing devices including computers such as server devices and personal computers. Each of these devices has a control unit, a communication unit, a storage unit, and an interface unit. The control unit, communication unit, storage unit, and interface unit each have the functions of control means, communication means, storage means, and interface means, respectively.

[0059] The control unit includes, for example, a processor such as a CPU (Central Processing Unit), MPU (Micro Processing Unit), ECU (Electronic Control Unit), FPGA (Field-Programmable Gate Array), or ASIC (Application Specific Integrated Circuit). The control unit functions as a computing device that performs control processing and arithmetic processing. The control unit also controls the operation of the communication unit, storage unit, interface unit, and each component necessary for executing the functions of each device.

[0060] Each component of each device can be realized, for example, by executing a program controlled by the control unit. More specifically, each component can be realized by the control unit executing a program stored in the memory unit. Alternatively, each component may be realized by recording the necessary programs on any non-volatile recording medium and installing them as needed. Furthermore, each component is not limited to being realized by software programs, but may also be realized by any combination of hardware, firmware, and software.

[0061] The communication unit performs the necessary communications for each device to perform information processing. The storage unit is, for example, ROM (Read Only Memory) or RAM (Random Access Memory). The storage unit has the function of storing control programs and arithmetic programs executed by the control unit. The storage unit also has the function of temporarily storing processing data.

[0062] The interface unit is, for example, a user interface. The interface unit has an input device such as a keyboard, touch panel, or mouse, and an output device such as a display or speaker. The interface unit accepts data input operations from the user (operator, etc.) and outputs information to the user.

[0063] <Specific Example I> Below, we present two specific examples, I and II, of numerical calculations to derive the optimal number of divisions n. First, let's explain example I. For example, consider two types of multipliers, 31 and 32, for matrix multiplication. Assume that the calculation speeds of each multiplier, 31 and 32, are given by equations (29) and (30) below.

[0064] R m1 = 7.8 × 10 12 FLOPS (29) R m2 = 7.8 × 10 12 FLOPS (30)

[0065] For example, consider one type of addition / subtraction device 21 as a device for matrix addition and subtraction. Assume the calculation speed of the addition / subtraction device 21 is as follows (31).

[0066] R s1 = 3.75 × 10 10 FLOPS (31)

[0067] These values ​​are based on a given processing speed (e.g., NVIDIA GPU V100 and P100). We also consider the case where the Strassen algorithm is applied to the multiplication of an 8000x8000 square matrix.

[0068] Each multiplier 31 and 32 is used for multiplication of submatrices, and the addition / subtraction device 21 is used for addition and subtraction of submatrices. Standard matrix multiplication involves multiplication of eight submatrices. Multipliers 31 and 32 sequentially calculate four and three multiplications in parallel. As a result, the critical matrix size N is obtained. C It can be calculated using the following equation (32).

[0069] (8 / (R m1 / 4+R m2 / 4)-7 / (R m1 / 4+R m2 / 3))(2N C -1) =11 / R s1 (32)

[0070] The critical matrix size N is obtained from the above formula C = 263. 8000×(1 / 2 4 ) = 500 > the critical matrix size N C is. At this critical matrix size N C and above, a matrix of N = 8000 can be divided into 4 parts. The optimal number of divisions is 4. The speed-up rate is approximately given by the following equation (33).

[0071] (8 / 7) 4 = 1.71 (33)

[0072] However, this speed-up rate takes into account the computing speed of the computing device used. It ignores the effects of other factors, such as the time taken to allocate and release memory and the transfer of data between devices.

[0073] <Specific Example II> Next, Specific Example II will be described. For example, consider multiplication devices 31 to 34 as devices for matrix multiplication. Assume that the computing speeds of multiplication devices 31 and 32 are R m1 , and the computing speeds of multiplication devices 33 and 34 are R m2 . Also, assume that the computing speed of addition / subtraction device 21 as a device for matrix addition / subtraction is R s1 . Consider the case of applying the Strassen algorithm to the multiplication of an 8000-by-8000 square matrix.

[0074] Each of the multiplication devices 31 to 34 is used for multiplying submatrices, and the addition / subtraction device 21 is used for adding / subtracting submatrices. The critical matrix size N C is obtained from the following equation (34).

[0075] (8 / (R m1 / 2 + R m1 / 2 + R m2 / 2 + R m2 / 2) - 7 / (R m1 / 2 + R m1 / 2 + R m2 / 2 + R m2 / 2))(2N C - 1) = 11 / R s1(34)

[0076] From the above equation, the critical matrix size N C =866 is obtained. The critical matrix size N is this. C Based on the above, a matrix of N=8000 can be partitioned three times. The optimal number of partitions is three. The speedup rate is approximately given by equation (35) below.

[0077] (8 / 7) 3 =1.47 (35)

[0078] While using more multipliers 3i than in Example I, the speedup rate is lower. This is because a similar number of multipliers 3i were used for standard multiplication. The computation time for Example II is shorter than that for Example I.

[0079] <Information Processing Methods> Next, an information processing method using the information processing device 10 will be described. Figure 10 is a flowchart illustrating an information processing method according to Embodiment 1. As shown in Figure 10, the information processing method comprises an acquisition step STEP 11, a calculation step STEP 12, and a selection step STEP 13.

[0080] First, in acquisition step STEP 11, the addition and subtraction calculation performance of one or more addition and subtraction devices 2j and the multiplication calculation performance of one or more multiplication devices 3i are acquired. Specifically, the acquisition unit 10a of the information processing device 10 is instructed to acquire the calculation performance of the addition and subtraction devices 2j and the multiplication devices 3i from the list file LF20 of the addition and subtraction management device 20 and the list file LF30 of the multiplication management device 30.

[0081] Next, in calculation step STEP12, the critical matrix size N is determined such that the processing time for one submatrix multiplication is equal to the processing time for a predetermined number of submatrix additions and subtractions. C The calculation is performed as follows. For example, if the predetermined number of times is set to 11, the calculation unit 10b calculates the critical matrix size N using the above-mentioned equation (28). C You may also have it calculated.

[0082] Next, in the selection step STEP13, the calculated critical matrix size N C The number of partitions in the matrix to be calculated is selected using this method. Specifically, the selection unit 10c is set to the critical matrix size N C Using this method, the number of divisions n in the N x N matrix to be calculated is N / (2 n ) but the critical matrix size N C The critical matrix size N is as described above. C The selection may be made from the number of divisions n closest to the desired result. Furthermore, the selection unit 10c may be made to select the number of divisions n based on the speed improvement rate. In this way, information processing is performed to compute large matrices at high speed.

[0083] Next, the effects of this embodiment will be explained. The information processing device 10 of this embodiment uses an addition / subtraction device 2j and a multiplication device 3i for multiplying large matrices using the Strassen algorithm. In this process, the number of divisions n of the Strassen algorithm is determined based on the computational performance of each device. This allows the addition / subtraction device 2j and the multiplication device 3i to be used in an optimal state for multiplying large matrices. Therefore, large matrices can be calculated at high speed. For example, in multiplying large matrices that require multiple arithmetic devices, the optimal number of divisions n can be selected depending on the availability of the assigned arithmetic device. Therefore, large matrix multiplication can be accelerated, and the efficiency of numerical calculations can be improved.

[0084] Note that the algorithm for partitioning into submatrices described above is not limited to the Strassen algorithm. Any other algorithm is acceptable as long as partitioning into submatrices changes the number of additions, subtractions, and multiplications compared to normal matrix multiplication. In that case, when partitioning into submatrices, the critical matrix size N is determined by considering the relationship between the increase and decrease of additions and subtractions and the increase and decrease of multiplications, so that the processing time for one submatrix multiplication is equal to the processing time for a predetermined number of submatrix additions and subtractions. C It may also be calculated as follows.

[0085] (Embodiment 2) Next, Embodiment 2 will be described. Figure 11 is a block diagram illustrating an information processing device according to Embodiment 2. As shown in Figure 11, the information processing device 40 of this embodiment further includes a splitting unit 10d, a transfer unit 10e, a determination unit 10f, and an integration unit 10g. The splitting unit 10d, the transfer unit 10e, the determination unit 10f, and the integration unit 10g each function as a splitting means, a transfer means, a determination means, and an integration means, respectively.

[0086] The division unit 10d divides the matrix into submatrices. The transfer unit 10e transfers the divided submatrices to the multiplier 3j and the addition / subtraction unit 2i. The determination unit 10f determines whether to subdivide again. The integration unit 10g integrates the calculation results of the multiplier 3j and the addition / subtraction unit 2i.

[0087] Next, an information processing method using the information processing device 10 will be described. Figure 12 is a flowchart illustrating an information processing method according to Embodiment 2. As shown in Figure 12, in addition to the acquisition step STEP 21, calculation step STEP 22, and selection step STEP 23, the information processing method of this embodiment includes a division step STEP 24, a transfer step STEP 25, a calculation result acquisition step STEP 26, a judgment step STEP 27, a calculation result acquisition step STEP 28, and an integration step STEP 29.

[0088] First, in acquisition step STEP21, similar to acquisition step STEP11, the acquisition unit 10a is instructed to acquire the addition and subtraction performance of the addition and subtraction device 2j and the multiplication performance of the multiplication device 3i.

[0089] Next, in calculation step STEP22, similar to calculation step STEP12, the calculation unit 10b is instructed to determine the critical matrix size N such that the processing time for one submatrix multiplication is equal to the processing time for a predetermined number of submatrix additions and subtractions. C It will be calculated as follows.

[0090] Next, in selection step STEP23, similar to selection step STEP13, the calculated critical matrix size N is entered into the selection unit 10c.C This is used to select the number of divisions n in the matrix to be calculated. As mentioned above, a threshold may be set for the speed improvement rate, and an upper limit may be set on the number of divisions.

[0091] Next, in the division step STEP24, the division unit 10d is instructed to divide the matrix to be calculated into submatrices. The division unit 10d may also be instructed to store the number of divisions performed.

[0092] Next, in the transfer step STEP25, the transfer unit 10e is instructed to transfer the divided submatrices to the addition / subtraction unit 2j and the multiplication unit 3i. Each arithmetic unit that receives the transferred submatrices performs calculations S1 to S8 to prepare the divisible M1 to M7.

[0093] Next, in the calculation result acquisition step STEP26, the acquisition unit 10a is instructed to acquire the calculation result.

[0094] Next, in the decision step STEP27, the decision unit 10f is asked to decide whether to perform further division. The decision unit 10f makes a decision by comparing the selected number of divisions n with the number of divisions stored. If the decision unit 10f determines that further division should be performed (YES), the process returns to step STEP24, and steps STEP24 to STEP27 are repeated.

[0095] In the decision step STEP27, if the decision unit 10f determines NO, meaning that no further subdivision is to be performed, then in step STEP28, the acquisition unit 10a is instructed to acquire the calculation result. The calculation result is obtained from M1-M7, V1-V3, and C performed by each calculation unit. 11 ~C 22 This is the calculation result up to that point.

[0096] Next, in integration step STEP29, the integration unit 10g is instructed to integrate the calculation results of the addition / subtraction device 2j and the multiplication device 3i. Specifically, the integration unit 10g is instructed to integrate the calculation results C11 to C22 of the calculated submatrices. In this way, information processing is performed to compute large matrices at high speed.

[0097] Next, the effects of this embodiment will be explained. In this embodiment, the information processing device 40 divides the matrix to be calculated into submatrices by a number of divisions n selected by the device. Then, the divided submatrices are used for calculations by the addition / subtraction device 2j and the multiplication device 3i. Therefore, large matrices can be calculated at high speed. Other configurations and effects are described in Embodiment 1.

[0098] It should be noted that the present invention is not limited to the embodiments described above, and can be modified as appropriate without departing from the spirit of the invention. For example, combinations of the configurations of Embodiments 1 and 2 are also included within the scope of the technical concept of the embodiments. Furthermore, information processing programs that cause a computer to execute information processing methods are also included within the scope of the technical concept of the embodiments.

[0099] Some or all of the above embodiments may also be described as follows, but are not limited to the following:

[0100] (Note A1) One or more addition and subtraction devices that perform addition and subtraction, One or more multipliers that perform multiplication, An information processing device connected to the addition / subtraction device and the multiplication device, Equipped with, The aforementioned information processing device is An acquisition unit that acquires the addition and subtraction calculation performance of the addition and subtraction device and the multiplication calculation performance of the multiplication device, A calculation unit calculates the critical matrix size, which is the matrix size at which the processing time for one multiplication of a submatrix is ​​equal to the processing time for performing a predetermined number of additions and subtractions of the submatrixes. A selection unit that selects the number of divisions in the matrix to be calculated using the calculated critical matrix size, Having, Information processing system. (Appendix A2) When the predetermined number of times is set to 11, the calculation unit calculates the critical matrix size N using the following equation (A). C Calculate JPEG0007848495000002.jpg26167 Here, R mi This indicates the multiplication performance of each multiplier, R sj This indicates the addition and subtraction calculation performance of each addition and subtraction device. x i , y j This indicates the number of sequential operations for each multiplier and each addition / subtraction device. The information processing system described in Appendix A1. (Note A3) The selection unit determines the size of the critical matrix, N, which is the size of the critical matrix calculated by the selection unit. C Using this, the number of divisions n in the N x N matrix that is the subject of the calculation is N / (2 n ) is the N C That concludes the above N C Select from the aforementioned n that is closest to it. The information processing system described in Appendix A1 or A2. (Note A4) The selection unit selects n based on the speed improvement rate. The information processing system described in Appendix A3. (Note A5) The aforementioned information processing device is A division unit that divides the aforementioned matrix into the aforementioned submatrices, A transfer unit that transfers the divided submatrices to the addition / subtraction device and the multiplication device, An integration unit that integrates the calculation results of the addition / subtraction device and the multiplication device, It further possesses, An information processing system described in any one of the items A1 to A4 in the appendix. (Note B1) An acquisition unit that acquires the performance of addition and subtraction operations and the multiplication operation performance of one or more multiplication devices that perform multiplication, A calculation unit calculates the critical matrix size, which is the matrix size at which the processing time for one multiplication of a submatrix is ​​equal to the processing time for performing a predetermined number of additions and subtractions of the submatrixes. A selection unit that selects the number of divisions in the matrix to be calculated using the calculated critical matrix size, It is connected to an information processing device having, Having the performance for performing addition and subtraction calculations, Addition and subtraction device. (Note B2) When the predetermined number of times is set to 11, the calculation unit calculates the critical matrix size N using the following equation (A). C Calculate JPEG0007848495000003.jpg26167 Here, R mi This indicates the multiplication performance of each multiplier, R sj This indicates the addition and subtraction calculation performance of each addition and subtraction device. x i , y j This indicates the number of sequential operations for each multiplier and each addition / subtraction device. The addition and subtraction device described in Appendix B1. (Note B3) The selection unit determines the size of the critical matrix, N, which is the size of the critical matrix calculated by the selection unit. C Using this, the number of divisions n in the N x N matrix that is the subject of the calculation is N / (2 n ) is the N C That concludes the above N C Select from the aforementioned n that is closest to it. Addition and subtraction devices as described in Appendix B1 or B2. (Note B4) The selection unit selects n based on the speed improvement rate. The addition and subtraction device described in Appendix B3. (Note B5) The aforementioned information processing device is A division unit that divides the aforementioned matrix into the aforementioned submatrices, A transfer unit that transfers the divided submatrices to the addition / subtraction device and the multiplication device, An integration unit that integrates the calculation results of the addition / subtraction device and the multiplication device, It further possesses, An addition / subtraction device as described in any one of the appendices B1 to B4. (Note C1) An acquisition unit that acquires the multiplication performance and the addition / subtraction performance of one or more addition / subtraction devices that perform addition and subtraction, A calculation unit calculates the critical matrix size, which is the matrix size at which the processing time for one multiplication of a submatrix is ​​equal to the processing time for performing a predetermined number of additions and subtractions of the submatrixes. A selection unit that selects the number of divisions in the matrix to be calculated using the calculated critical matrix size, It is connected to an information processing device having, Having the performance of performing multiplication operations, Multiplication device. (Note C2) When the predetermined number of times is set to 11, the calculation unit calculates the critical matrix size N using the following equation (A). C Calculate JPEG0007848495000004.jpg26167 Here, R mi This indicates the multiplication performance of each multiplier, R sj This indicates the addition and subtraction calculation performance of each addition and subtraction device. x i , y j This indicates the number of sequential operations for each multiplier and each addition / subtraction device. The multiplication device described in Appendix C1. (Note C3) The selection unit determines the size of the critical matrix, N, which is the size of the critical matrix calculated by the selection unit. C Using this, the number of divisions n in the N x N matrix that is the subject of the calculation is N / (2 n ) is the N C That concludes the above N C Select from the aforementioned n that is closest to it. The multiplication device described in Appendix C1 or C2. (Note C4) The selection unit selects n based on the speed improvement rate. The multiplication device described in Appendix C3. (Note C5) The aforementioned information processing device is A division unit that divides the aforementioned matrix into the aforementioned submatrices, A transfer unit that transfers the divided submatrices to the addition / subtraction device and the multiplication device, An integration unit that integrates the calculation results of the addition / subtraction device and the multiplication device, It further possesses, A multiplier described in any one of the appendices C1 to C4. (Note D1) A step of obtaining the addition and subtraction calculation performance of one or more addition and subtraction devices that perform addition and subtraction, and the multiplication calculation performance of one or more multiplication devices that perform multiplication, A step of calculating the critical matrix size such that the processing time for one multiplication of a submatrix is ​​equal to the processing time for a predetermined number of additions and subtractions of the submatrixes, The steps include selecting the number of partitions in the matrix to be calculated using the calculated critical matrix size, An information processing method equipped with [a specific feature / feature]. (Note D2) In the step of calculating, When the predetermined number of times is set to 11, the critical matrix size N is calculated using equation (A) below. C To calculate, JPEG0007848495000005.jpg26167 Here, R mi This indicates the multiplication performance of each multiplier, R sj This indicates the addition and subtraction calculation performance of each addition and subtraction device. x i , y j This indicates the number of sequential operations for each multiplier and each addition / subtraction device. The information processing method described in Appendix D1. (Note D3) In the step of selecting, The calculated critical matrix size is N C Using this, the number of divisions n in the N x N matrix that is the subject of the calculation is N / (2 n ) is the N C That concludes the above N C Select from the aforementioned n that is closest to it. The information processing method described in Appendix D1 or D2. (Note D4) In the step of selecting, Based on the rate of speed improvement, the aforementioned n is selected. The information processing method described in Appendix D3. (Note D5) The steps of dividing the matrix into the submatrices, The steps include transferring the divided submatrices to the addition / subtraction device and the multiplication device, A step of integrating the calculation results of the addition / subtraction device and the multiplication device, It also has, The information processing method described in any one of the appendices D1 to D4. (Note E1) A step of obtaining the addition and subtraction calculation performance of one or more addition and subtraction devices that perform addition and subtraction, and the multiplication calculation performance of one or more multiplication devices that perform multiplication, A step of calculating the critical matrix size such that the processing time for one multiplication of a submatrix is ​​equal to the processing time for a predetermined number of additions and subtractions of the submatrixes, The steps include selecting the number of partitions in the matrix to be calculated using the calculated critical matrix size, An information processing program that causes a computer to execute something. (Note E2) In the step of calculating, When the predetermined number of times is set to 11, the critical matrix size N is calculated using equation (A) below. C To calculate, JPEG0007848495000006.jpg26167 Here, R mi This indicates the multiplication performance of each multiplier, R sj This indicates the addition and subtraction calculation performance of each addition and subtraction device. x i , y j This indicates the number of sequential operations for each multiplier and each addition / subtraction device. The information processing program described in Appendix E1. (Note E3) In the step of selecting, The calculated critical matrix size is N C Using this, the number of divisions n in the N x N matrix that is the subject of the calculation is N / (2 n ) is the N C That concludes the above N C Select from the aforementioned n that is closest to it. The information processing program described in Appendix E1 or E2. (Note E4) In the step of selecting, Based on the rate of speed improvement, the aforementioned n is selected. The information processing program described in Appendix E3. (Note E5) The steps of dividing the matrix into the submatrices, The steps include transferring the divided submatrices to the addition / subtraction device and the multiplication device, A step of integrating the calculation results of the addition / subtraction device and the multiplication device, An information processing program described in any one of the appendices E1 to E2, which is further executed by a computer.

[0101] The program, when loaded into a computer, includes a set of instructions (or software code) for causing the computer to perform one or more of the functions described in the embodiments. The program may be stored on a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other memory technologies, CD-ROM, digital versatile disc (DVD), Blu-ray® disc or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. The program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrically, optically, acoustically or otherwise propagating signals. [Explanation of Symbols]

[0102] 1. Information Processing System 10, 40 Information Processing Devices 10a Acquisition part 10b Calculation part 10c selection section 10d Divided section 10e Transfer section 10f Judgment section 10g integration part 20 Addition / subtraction management device 20a Acquisition Department 20b Storage section 20c Transmitter 21, 2j addition / subtraction device 2ja acquisition department 2jb calculation section 2JC Transmitter 30 Multiplication Management Device 30a Acquisition part 30b Storage section 30c Transmitter 31, 3i Multiplier 3ja acquisition department 3jb calculation section 3JC Transmitter LF20 Addition / Subtraction List File LF30 Multiplication List File

Claims

1. An acquisition unit that acquires the addition and subtraction calculation performance of one or more addition and subtraction devices that perform addition and subtraction, and the multiplication calculation performance of one or more multiplication devices that perform multiplication, A calculation unit calculates the critical matrix size such that the processing time for one multiplication of a submatrix is ​​equal to the processing time for a predetermined number of additions and subtractions of the submatrix, A selection unit that selects the number of divisions in the matrix to be calculated using the calculated critical matrix size, Equipped with an information processing device.

2. When the predetermined number of times is set to 11, the calculation unit calculates the critical matrix size N using the following equation (A). Ｃ Calculate Here, R ｍｉ This indicates the multiplication performance of each multiplier, R ｓｊ This indicates the addition and subtraction calculation performance of each addition and subtraction device. x ｉ , y ｊ This indicates the number of sequential operations for each multiplier and each addition / subtraction device. The information processing apparatus according to claim 1.

3. The selection unit uses N, which is the calculated critical matrix size, to select n, which is the number of divisions in the N×N matrix that is the calculation target, from the n where N / (2 Ｃ is greater than or equal to N ｎ and closest to N Ｃ among them. Ｃ ​ The information processing apparatus according to claim 1 or 2.

4. The selection unit selects n based on the speed improvement rate. The information processing apparatus according to claim 3.

5. A division unit that divides the aforementioned matrix into the aforementioned submatrices, A transfer unit that transfers the divided submatrices to the addition / subtraction device and the multiplication device, An integration unit that integrates the calculation results of the addition / subtraction device and the multiplication device, It also has, The information processing apparatus according to any one of claims 1 to 4.

6. One or more addition and subtraction devices that perform addition and subtraction, One or more multipliers that perform multiplication, An information processing device connected to the addition / subtraction device and the multiplication device, Equipped with, The aforementioned information processing device is An acquisition unit that acquires the addition and subtraction calculation performance of the addition and subtraction device and the multiplication calculation performance of the multiplication device, A calculation unit calculates the critical matrix size such that the processing time for one multiplication of a submatrix is ​​equal to the processing time for a predetermined number of additions and subtractions of the submatrix, A selection unit that selects the number of divisions in the matrix to be calculated using the calculated critical matrix size, Having, Information processing system.

7. A computer acquires the addition and subtraction calculation performance of one or more addition and subtraction devices that perform addition and subtraction, and the multiplication calculation performance of one or more multiplication devices that perform multiplication. The computer calculates the critical matrix size such that the processing time for one multiplication of a submatrix is ​​equal to the processing time for a predetermined number of additions and subtractions of the submatrixes. The computer selects the number of divisions in the matrix to be calculated using the calculated critical matrix size, An information processing method equipped with [a specific feature / feature].

8. A step of obtaining the addition and subtraction calculation performance of one or more addition and subtraction devices that perform addition and subtraction, and the multiplication calculation performance of one or more multiplication devices that perform multiplication, A step of calculating the critical matrix size such that the processing time for one multiplication of a submatrix is ​​equal to the processing time for a predetermined number of additions and subtractions of the submatrixes, The steps include selecting the number of partitions in the matrix to be calculated using the calculated critical matrix size, An information processing program that causes a computer to execute something.

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