Semiconductor optical element

Abstract

To diffuse stress generated in a semiconductor multilayer.SOLUTION: An uppermost layer 24 contains Au. A lowermost layer 26 is formed of a material with an adhesion to a semiconductor multilayer 16 higher than that of Au. A multistep structure includes three or more sections S that overlap with an optical waveguide 18, are adjacent in a direction where the optical waveguide 18 extends, and have different thicknesses. An adjacent pair among the three or more sections S includes one with a small thickness that is close to an end surface of the semiconductor multilayer 16, and the other with a large thickness that is apart from the end surface of the semiconductor multilayer 16. The three or more sections S include a first section S1 with the minimum thickness including at least the lowermost layer 26, a second section S2 adjacent to the first section S1 including at least a stress relief layer 30 formed of a material with a Young's modulus less than or equal to that of Au in addition to the lowermost layer 26, and a third section S3 with the maximum thickness including all the layers from the uppermost layer 24 to the lowermost layer 26.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor optical device.

Background Art

[0002] A stacked structure of a plurality of metals is applied to the electrodes of a semiconductor optical device. For example, an electrode structure having a three-layer structure of a Ti layer, a Pt layer, and an Au layer in this order from the closest to the semiconductor multilayer is known (Patent Document 1). The bottom layer is for forming an ohmic contact between the semiconductor multilayer and the electrode, the top layer is for electrical and thermal conduction with the outside and for mixing of the solder material and the electrode, and the intermediate layer is for preventing mixing of the solder material and the semiconductor multilayer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Since there is a difference in the coefficient of thermal expansion between the electrode and the semiconductor multilayer, stress may occur in the semiconductor multilayer, which may cause a decrease in reliability. As a countermeasure, Patent Document 1 discloses an electrode having a two-stage structure in which the top layer (Au layer) has receded. Since it has a two-stage structure, the stress of the semiconductor multilayer can be reduced at the end face of the device. However, since the top layer (Au layer) has receded, the stress increases inside rather than at the end face of the device.

[0005] The present disclosure aims to disperse the stress generated in the semiconductor multilayer.

Means for Solving the Problems

[0006] The semiconductor optical element comprises a semiconductor multilayer configured to include an optical waveguide, and multilayer and multi-stage electrodes in contact with the upper surface of the semiconductor multilayer, wherein the uppermost layer of the multilayer is made of Au, the lowermost layer of the multilayer is made of a material that has higher adhesion to the semiconductor multilayer than Au, the multi-stage structure is made of three or more adjacent sections of different thicknesses that overlap the optical waveguide and extend in the direction of the optical waveguide, a pair of adjacent sections of the three or more sections consisting of one that is close to the end face of the semiconductor multilayer and has a small thickness, and the other that is farther from the end face of the semiconductor multilayer and has a large thickness, the three or more sections include a first section which consists of at least the bottom layer and has the smallest thickness, a second section which is adjacent to the first section and consists of at least the bottom layer plus a stress relaxation layer made of a material with a Young's modulus less than or equal to Au, and a third section which consists of all layers from the uppermost layer to the bottommost layer and has the largest thickness. [Brief explanation of the drawing]

[0007] [Figure 1] This is a plan view of a semiconductor optical device according to the first embodiment. [Figure 2] Figure 1 is a cross-sectional view of the semiconductor optical device shown along line II-II. [Figure 3] This is a magnified view of the multi-stage structure of the electrode. [Figure 4] This is a cross-sectional view of the electrode according to Comparative Example 1. [Figure 5] This is a cross-sectional view of the electrode according to Comparative Example 2. [Figure 6] This is a cross-sectional view of the electrode according to Comparative Example 3. [Figure 7] This is a cross-sectional view of the electrode according to Modified Example 1. [Figure 8] This is a cross-sectional view of the electrode according to modified example 2. [Figure 9] This is a cross-sectional view of the electrode according to modified example 3. [Figure 10] This is a cross-sectional view of the electrode according to modified example 4. [Figure 11] This is a plan view of a semiconductor optical device according to the second embodiment. [Figure 12] Figure 11 is a cross-sectional view of the semiconductor optical device shown along line XII-XII. [Figure 13] Figure 11 is a cross-sectional view of the semiconductor optical device shown along line XIII-XIII. [Figure 14] Figure 11 is a cross-sectional view of the semiconductor optical device shown along the line XIV-XIV. [Figure 15] This is a plan view of a semiconductor optical element according to the third embodiment. [Figure 16] Figure 15 is a cross-sectional view of a semiconductor optical device taken along the line XVI-XVI. [Figure 17] Figure 15 is a cross-sectional view of the semiconductor optical device shown along line XVII-XVII. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described specifically and in detail below with reference to the drawings. Components denoted by the same reference numerals in all figures have the same or equivalent function, and repeated explanations will be omitted. Note that the size of the figures does not necessarily correspond to the magnification.

[0009] [First Embodiment] Figure 1 is a plan view of a semiconductor optical element according to the first embodiment. Figure 2 is a cross-sectional view of the semiconductor optical element shown in Figure 1, taken along line II-II. Semiconductor optical elements have the function of guiding, emitting, absorbing, or amplifying light, and are, for example, bulk waveguides, lasers, optical modulators, or optical amplifiers. Figure 2 shows a cross-section of an end-face emitting laser along the optical axis, with light being emitted from at least one of the end faces perpendicular to the optical axis.

[0010] [Semiconductor multilayer] The semiconductor optical element has a semiconductor multilayer 16 in which a lower cladding layer 10, an optical functional layer 12, and an upper cladding layer 14 are laminated. The optical functional layer 12 forms at least a part of an optical waveguide 18. The optical functional layer 12 is, for example, a multiple quantum well layer and functions as an active layer (light emitting layer) in a laser. Alternatively, the optical functional layer 12 may be a bulk semiconductor layer. The lower cladding layer 10 may be a semiconductor substrate or may be a semiconductor layer different from the semiconductor substrate. Other layers such as a contact layer and an optical confinement layer may be included in the semiconductor multilayer 16.

[0011] [Electrode] The semiconductor optical element includes an electrode 20 and a back surface electrode 22. The electrode 20 and the back surface electrode 22 are formed by metal evaporation. The metal constituting the back surface electrode 22 includes, for example, AuGe and Ni. On the upper surface of the semiconductor multilayer 16, the portion other than the electrode 20 may be a semiconductor surface or an insulator film (for example, silicon oxide) formed by a plasma CVD (Chemical Vapor Deposition) method or a thermal CVD method may be formed. The electrode 20 is in contact with the upper surface of the semiconductor multilayer 16.

[0012] [Multilayer structure] [Top layer] The electrode 20 has a multilayer structure. The top layer 24 of the multilayer structure is thicker (for example, 600 nm) than other layers in order to perform wire bonding or physically contact the mounting surface of a submount. The top layer 24 is composed of Au. Since Au has a larger thermal expansion coefficient than semiconductors such as InP, it can cause stress in the semiconductor multilayer 16.

[0013] [Bottom layer] The bottom layer 26 of the multilayer structure is composed of a material (for example, Ti, Mo) having higher adhesion to the semiconductor multilayer 16 than Au, thereby enabling ohmic contact. The thickness of the bottom layer 26 is, for example, 100 nm.

[0014] [Barrier layer] The multilayer structure includes a barrier layer 28. The barrier layer 28 consists of a material that prevents metal diffusion throughout the electrode 20, between the uppermost layer 24 and the bottommost layer 26. The material that prevents metal diffusion is, for example, Pt, W, Cr, Pd, or Ta. The barrier layer 28 is in contact with the bottommost layer 26. The thickness of the barrier layer 28 is, for example, 100 nm.

[0015] [Multi-stage structure] The electrode 20 has a multi-stage structure. The multi-stage structure consists of three or more sections S. The three or more sections S overlap the optical waveguide 18, are adjacent to each other in the direction in which the optical waveguide 18 extends, and have different thicknesses. One of a pair of adjacent sections S is close to the end face (device end face) of the semiconductor multilayer 16 and has a small thickness. The other of a pair of adjacent sections S is further away from the end face of the semiconductor multilayer 16 and has a large thickness.

[0016] [Section 1] Figure 3 is an enlarged view of the multi-stage structure of the electrode 20. Three or more sections S include a first section S1. The first section S1 consists of at least the bottom layer 26. Here, the first section S1 includes the bottom layer 26 and a barrier layer 28. The end faces of the layers constituting the first section S1 coincide with the side faces (device end faces) of the semiconductor multilayer 16.

[0017] The first section S1 has a first thickness t1. The first thickness t1 is the smallest among the thicknesses of the three or more sections S. In order to suppress the influence of stress caused by the first section S1, the first thickness t1 is smaller than the thickness of the top layer 24. Preferably, the first thickness t1 is half or less the thickness of the top layer 24.

[0018] [Section 2] Three or more sections S include a second section S2. The second section S2 is adjacent to the first section S1. The thickness of the second section S2 beyond the first section S1 is the second thickness t2.

[0019] The second section S2 consists of at least the bottom layer 26 (for example, the bottom layer 26 and the barrier layer 28), plus a stress relaxation layer 30 made of a material with a Young's modulus less than or equal to that of Au. The stress relaxation layer 30 is part of the top layer 24 (the part that makes up the bottom surface). The stress relaxation layer 30 is made of Au and has excellent heat dissipation properties. Since the stress relaxation layer 30 has the same or less Young's modulus as the Au that makes up the top layer 24, it mitigates the transmission of expansion or contraction of the top layer 24, which is included in the third section S3 described later, to the semiconductor layer 16.

[0020] The stress relaxation layer 30 is thinner than the overall thickness of the top layer 24 in order to suppress the effects of stress caused by it. Preferably, the stress relaxation layer 30 is less than half the thickness of the top layer 24. The second thickness t2 of the stress relaxation layer 30 is, for example, 100 nm.

[0021] The distance between the tip of the second section S2 and the tip of the first section S1 is, for example, 10 μm. The tip of the second section S2 is located inside the side surface of the semiconductor multilayer 16. In other words, the distance from the tip of the second section S2 to the side surface of the semiconductor multilayer 16 is greater than the distance from the tip of the first section S1 to the side surface of the semiconductor multilayer 16.

[0022] [Section 3] Three or more sections S include a third section S3. The third section S3 consists of all layers from the top layer 24 to the bottom layer 26 and has the greatest thickness among the three or more sections S. The thickness of the third section S3 that exceeds that of the second section S2 is the third thickness t3. At least one of the first thickness t1 and the second thickness t2 is less than or equal to half of the third thickness t3.

[0023] The tip of the third section S3 is located further inside the upper surface of the semiconductor multilayer 16 than the tip of the second section S2. The distance from the tip of the third section S3 to the side surface of the semiconductor multilayer 16 is greater than the distance from the tip of the second section S2 to the side surface of the semiconductor multilayer 16. The distance between the tip of the first section S1 and the tip of the third section S3 is, for example, 20 μm.

[0024] From a stress perspective, a larger distance between the tips of the first section S1, the second section S2, and the third section S3 is preferable. However, each layer constituting the electrode 20 also plays a role as a heat dissipation layer, so a smaller area (volume) is undesirable. In particular, the amount of heat generated is large near the tips of the first section S1, the second section S2, and the third section S3. From a heat dissipation perspective, it is preferable that the second section S2 and the third section S3 are close to the sides of the semiconductor multilayer 16. For example, the distance between the tip of the first section S1 and the tip of the second section S2 may be 5 μm, and the distance between the tip of the first section S1 and the tip of the third section S3 may be 10 μm.

[0025] The distance between the tip of the first section S1 and the tips of the second section S2 and the third section S3 should be determined from the viewpoint of stress and heat dissipation. As a minimum distance, from the viewpoint of manufacturing variations, it is preferable that the distance between the tip of the first section S1 and the tip of the second section S2 be 2 μm, and the distance between the tip of the first section S1 and the tip of the third section S3 be 4 μm or more.

[0026] [Comparative Example] Figure 4 is a cross-sectional view of the electrode according to Comparative Example 1. In Comparative Example 1, the leading edges of the uppermost layer 4, the bottommost layer 6, and the barrier layer 8 are aligned with the side surface of the semiconductor multilayer 2. As a result, stress concentrates on the side surface of the semiconductor multilayer 2.

[0027] Figure 5 is a cross-sectional view of the electrode according to Comparative Example 2. In Comparative Example 2, the entire uppermost layer 4 is within the range of the third section S3. In other words, the uppermost layer 4 is separated from the side surface of the semiconductor multilayer 2. Therefore, the stress generated on the side surface of the semiconductor multilayer 2 is reduced. However, directly below the leading edge of the uppermost layer 4, the stress generated in the semiconductor multilayer 2 is greater than in Comparative Example 1.

[0028] Figure 6 is a cross-sectional view of the electrode according to Comparative Example 3. In Comparative Example 3, the edge of the uppermost layer 4 is in two stages, and the thin tip is aligned with the side surface of the semiconductor multilayer 2, so the stress generated on the side surface of the semiconductor multilayer 2 is smaller than in Comparative Example 1. However, since a part of the uppermost layer 4 is aligned with the side surface of the semiconductor multilayer 2, the stress generated on the side surface of the semiconductor multilayer 2 is larger than in Comparative Example 2.

[0029] [effect] In this embodiment, since the electrode 20 has a multi-stage structure, the stress generated in the semiconductor multilayer 16 can be distributed. For example, the tips of the second section S2 and the third section S3 do not coincide with the side surface (end face) of the semiconductor multilayer 16. In particular, the uppermost layer 24 made of Au, which is the source of strong stress generation, does not coincide with the side surface. Therefore, the stress generated on the side surface can be reduced.

[0030] Since the stress relaxation layer 30 is a metal with a Young's modulus equal to or less than that of Au, the expansion or contraction of the uppermost layer 24 of the third section S3 is mitigated from being transmitted to the semiconductor multilayer 16, thereby reducing the effect of stress on the semiconductor multilayer 16. In particular, because the tip of the second section S2 and the tip of the third section S3 do not coincide, the stress exerted directly below the tip of the third section S3 is reduced, thereby reducing the stress applied to the inside of the device. Furthermore, since the uppermost layer 24, which is the Au layer, does not coincide with the side surface, the Au layer is not cut when the semiconductor multilayer 16 is cut, resulting in superior cleavage.

[0031] [Manufacturing method] The multi-layer structure of the electrode 20 can be formed by the following procedure from the standpoint of mass production. First, a semiconductor multilayer 16 is formed, and then a metal multilayer from the bottom layer 26 to the top layer 24 is deposited onto the entire upper surface of the semiconductor multilayer 16. Then, the metal multilayer is etched so as to preserve the overall planar shape of the electrode 20.

[0032] Next, an etching mask covering the planar shape of the second section S2 and the third section S3 is formed by applying the lithography method. Then, selective etching is performed, in which etching proceeds on the uppermost layer 24 but slowly on the layer directly below it. As a result, the uppermost layer 24 is removed in the first section S1, and the leading edge of the second section S2 is formed. In other words, a step is formed between the first section S1 and the second section S2.

[0033] Next, the uppermost layer 24 in the second section S2 is etched again through an etching mask that covers the area that will become the third section S3 but does not cover the second section S2. However, by controlling the etching rate and etching time, a portion of the uppermost layer 24 is left intact instead of being completely removed. This forms the tip of the third section S3 and creates a step between the second section S2 and the third section S3. Together with the previously formed step, a multi-stage structure is formed.

[0034] [Example 1] Figure 7 is a cross-sectional view of the electrode according to Modification 1. In Modification 1, the stress relaxation layer 130 of the second section S2 is a separate layer from the top layer 124. The stress relaxation layer 130 is made of a metal (e.g., In) with a Young's modulus smaller than that of the Au that constitutes the top layer 124. Because the stress relaxation layer 130 is made of a metal with a Young's modulus smaller than that of Au, the transmission of expansion or contraction of the top layer 124 to the semiconductor multilayer 116 is mitigated, and the stress generated in the semiconductor multilayer 116 can be reduced.

[0035] [Differentiation 2] Figure 8 is a cross-sectional view of the electrode according to Modified Example 2. In Modified Example 2, the stress relaxation layer 230 of the second section S2 is a separate layer (non-contact layer) from the top layer 224, but is made of the same Au as the top layer 224. The thickness of the stress relaxation layer 230 is 100 nm. The stress relaxation layer 230 reduces the influence that the tip of the third section S3 has on the semiconductor multilayer 216 due to expansion or contraction.

[0036] The multilayer structure of electrode 220 includes a partial barrier layer 232 made of a material that prevents metal diffusion in at least the third section S3 (e.g., the second section S2 and the third section S3), except for the first section S1. The thickness of the partial barrier layer 232 is 100 nm. The partial barrier layer 232 is also included in the second section S2. The material that prevents metal diffusion is Pt, W, Cr, Pd, or Ta.

[0037] The layer constituting the upper surface of the second section S2 is not limited to the partial barrier layer 232, but may be any other layer. For example, it may be a Ti layer. The partial barrier layer 232 and the Ti layer may be stacked between the uppermost layer 224 and the stress relaxation layer 230. However, it is preferable that the second thickness t2 of the second section S2 be less than or equal to half of the third thickness t3 so as not to increase the stress generated in the semiconductor multilayer 216 directly beneath its leading edge.

[0038] In the second modification, the process of forming the stepped shape becomes easier. First, a metal multilayer is deposited over the entire upper surface of the semiconductor multilayer 216. Then, the unnecessary portion is removed from the metal multilayer in the first section S1. In the second section S2 and the third section S3, the entire layer of the metal multilayer is left.

[0039] Next, the region that will become the third section S3 is masked, and etching is performed with a solution that etches only Au. If the layer constituting the upper surface of the second section S2 is composed of a partial barrier layer 232 (e.g., Pt) or Ti, etching will not proceed. This makes selective etching possible without time control, allowing unwanted parts of the second section S2 to be removed, and enabling large-area and efficient manufacturing.

[0040] [Difference 3] Figure 9 is a cross-sectional view of the electrode according to Modification 3. In Modification 3, the barrier layer 328 is thin (e.g., 50 nm). This reduces the influence of the tip of the first section S1 on the side surface of the semiconductor multilayer 316. However, controlling the thin film thickness is difficult, and it can become too thin or result in areas that are not densely formed. As a result, reliability decreases when Au diffuses into the semiconductor multilayer 316.

[0041] Therefore, in Modification 3, the multilayer structure includes a partial barrier layer 332 in at least the third section S3 (for example, only the third section S3), excluding the first section S1. The partial barrier layer 332 is made of a material that prevents metal diffusion. The material that prevents metal diffusion is Pt, W, Cr, Pd, or Ta. The thickness of the partial barrier layer 332 is 100 nm. By providing the partial barrier layer 332, the effect of preventing the Au constituting the uppermost layer 324 above it from diffusing into the layer below can be enhanced. This makes it possible to sufficiently suppress the diffusion of Au constituting the uppermost layer 324.

[0042] In the third section S3, the thickness of the top layer 324 is 600 nm, but the third thickness t3 is increased due to the addition of a partial barrier layer 332. This increases the influence of expansion or contraction in the third section S3. However, the stress relaxation layer 330 in the second section S2 distributes the stress, reducing its impact on the semiconductor multilayer 316. The stress relaxation layer 330 in the second section S2 is a separate layer from the top layer 324.

[0043] [Differentiation Example 4] Figure 10 is a cross-sectional view of the electrode according to Modification 4. In Modification 4, the first section S1 includes a portion of the uppermost layer 424. The portion of the uppermost layer 424 included in the first section S1 has the effect of improving heat dissipation on and near the side of the semiconductor multilayer 416, thereby improving its characteristics. In other words, Modification 4 achieves high heat dissipation and reliability.

[0044] On the other hand, if a portion of the uppermost layer 424 included in the first section S1 is too thick, it can cause stress and degrade reliability. Therefore, a portion of the uppermost layer 424 included in the first section S1 is less than half the thickness of a portion of the uppermost layer 424 included in the second section S2 (for example, 25 nm). The thickness of the bottom layer 426 and the barrier layer 428 are both 100 nm.

[0045] [Second Embodiment] Figure 11 is a plan view of a semiconductor optical element according to the second embodiment. Figure 12 is a cross-sectional view of the semiconductor optical element shown in Figure 11 along the line XII-XII. Figure 13 is a cross-sectional view of the semiconductor optical element shown in Figure 11 along the line XIII-XIII. Figure 14 is a cross-sectional view of the semiconductor optical element shown in Figure 11 along the line XIV-XIV.

[0046] The semiconductor optical device is a distributed feedback semiconductor laser (DFB laser) having a ridge waveguide structure. The optical functional layer 512, which constitutes at least a portion of the optical waveguide 518, is, for example, a multiple quantum well layer and functions as an active layer (light-emitting layer).

[0047] The semiconductor multilayer 516 includes a lower cladding layer 510, an optical functional layer 512, and an upper cladding layer 514. The lower cladding layer 510 and the upper cladding layer 514 are made of InP, and the optical functional layer 512 is made of InGaAsP. The lower cladding layer 510 may be a semiconductor substrate or a semiconductor layer separate from the semiconductor substrate. A diffraction grating layer (not shown) having a diffraction grating structure made of InGaAsP is placed between the optical functional layer 512 and the lower cladding layer 510. The diffraction grating layer may also be placed between the optical functional layer 512 and the upper cladding layer 514.

[0048] An optical confinement layer (not shown) made of InGaAsP is disposed between the optical functional layer 512 and the diffraction grating layer, and between the optical functional layer 512 and the upper cladding layer 514. The optical functional layer 512 and the optical confinement layer are not limited to InGaAsP, but may also be InGaAlAs. The semiconductor multilayer 516 may also include a contact layer.

[0049] The semiconductor multilayer 516 includes a mesa structure that forms an optical waveguide 518. The optical waveguide 518 has a ridge waveguide type mesa structure (hereinafter referred to as the ridge structure). The ridge structure may include a part of the upper cladding layer 514, a part of the optical functional layer 512, and a part of the lower cladding layer 510.

[0050] The electrode 520 includes a main electrode 534 positioned above the optical waveguide 518 along the optical waveguide 518, and a pad electrode 536 drawn out from the main electrode 534, which are continuous and integrated. A wire that transmits an external electrical signal is bonded to the pad electrode 536. By applying a voltage between the electrode 520 and the back electrode 522, the semiconductor optical element outputs laser light from the end face of the element.

[0051] In areas where electrodes 520 are not located, the semiconductor multilayer 516 is covered with an insulating layer 538. The insulating layer 538 is, for example, silicon oxide. Except for the electrical connection between the main electrode 534 and the semiconductor multilayer 516 (directly above the optical waveguide 518), the insulating layer 538 is also located below a portion of the electrode 520.

[0052] The main electrode 534 has a multi-stage structure on the upper surface of the ridge structure. The main electrode 534 also has a multi-stage structure on the side of the ridge structure or on both sides of the ridge structure, preventing stress concentration in the semiconductor multilayer 516 in these regions as well. The details of the multi-stage structure described in the above embodiment are applicable here.

[0053] Semiconductor optical devices can be manufactured by the following method: Crystal growth is performed on a semiconductor substrate using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy, thereby growing the lower cladding layer 510, the optical functional layer 512, and the upper cladding layer 514, respectively. Subsequently, an etching mask is formed to cover the optical waveguide 518 (mesa structure), and etching (dry etching or wet etching) is performed to form a ridge-type optical waveguide 518.

[0054] To protect the surface of the semiconductor multilayer 516, an insulating layer 538 (e.g., silicon oxide) is formed over the entire surface using plasma CVD or thermal CVD. Then, the insulating layer 538 is etched through an etching mask having an opening in the region directly above the optical waveguide 518 (electrical connection area). Subsequently, a metal multilayer is formed by vapor deposition, starting from the side closest to the semiconductor multilayer 516.

[0055] Next, etching is performed using an etching resist that covers only the region that will become the third section S3, thereby forming the surface shape of the third section S3 from the uppermost layer 524. However, instead of completely removing the region other than the third section S3, that region is thinned and left intact by etch-back.

[0056] Next, etching is performed using an etching resist that covers only the areas that will become the second section S2 and the third section S3, thereby forming the surface shape of the second section S2 (stress relaxation layer 530) from the top layer 524. However, instead of completely removing the areas other than the second section S2 and the third section S3, those areas are thinned and left intact by etch-back.

[0057] Next, etching is performed using an etching resist that covers only the regions that will become the first section S1, the second section S2, and the third section S3, to form the surface shape of the first section S1 (layer 526 consisting of the bottom layer and a barrier layer). However, the etching is performed so as not to extend to the layer below layer 526 (insulating layer 538).

[0058] [Third Embodiment] Figure 15 is a plan view of a semiconductor optical element according to the third embodiment. Figure 16 is a cross-sectional view of the semiconductor optical element shown in Figure 15, taken along the line XVI-XVI. Figure 17 is a cross-sectional view of the semiconductor optical element shown in Figure 15, taken along the line XVII-XVII.

[0059] The semiconductor optical device is an optical modulator (for example, an electro-absorption modulator) that converts continuous light input from one end face into modulated light. The optical functional layer 612, which constitutes at least a portion of the optical waveguide 618, is, for example, a multiple quantum well layer and functions as an optical absorption layer.

[0060] The semiconductor multilayer 616 includes a mesa structure that forms an optical waveguide 618. The optical waveguide 618 has a mesa structure. In Figure 15, the mesa structure is shown by a dashed line. The mesa structure includes a portion of the lower cladding layer 610, the optical functional layer 612, and the upper cladding layer 614. Both sides of the mesa structure are embedded with semiconductor embedding layers 642. The lower cladding layer 610 and the upper cladding layer 614 are made of InP, and the optical functional layer 612 is made of InGaAsP. Optical confinement layers (not shown) made of InGaAsP are placed between the optical functional layer 612 and the lower cladding layer 610, and between the optical functional layer 612 and the upper cladding layer 614.

[0061] The optical waveguide 618 includes a non-absorbent material layer 640 (window structure). The non-absorbent material layer 640 has the effect of reducing the reflection at the optical emission end face that returns to the optical functional layer 612. The non-absorbent material layer 640 has a larger band gap than the optical functional layer 612. The non-absorbent material layer 640 is adjacent to the optical functional layer 612 in the optical waveguide direction. The non-absorbent material layer 640 constitutes a part of the side surface (device end face) of the semiconductor multilayer 616.

[0062] The semiconductor optical element comprises an electrode 620 and a back electrode 622. The electrode 620 includes a main electrode 634 positioned above the optical waveguide 618 along the optical waveguide 618, and a pad electrode 636 drawn out from the main electrode 634, which are continuous and integrated. A wire that transmits an external electrical signal is bonded to the pad electrode 636. By applying a voltage between the electrode 620 and the back electrode 622, the semiconductor optical element modulates light incident from the end face.

[0063] The main electrode 634 has a multi-stage structure on the upper surface of the ridge structure. The details of the multi-stage structure described in the above-described embodiment are applicable here. Since there is no need to input electricity to the non-absorbent material layer 640, above the non-absorbent material layer 640, the electrode 620 does not reach the edge (device end face) of the upper surface of the semiconductor multilayer 616. On the side where the non-absorbent material layer 640 is located, the leading edge of the first section S1 is located inward from the side surface of the semiconductor multilayer 616. The end faces of the layers constituting the first section S1 are away from the side surface of the semiconductor multilayer 616. The portion of the electrode 620 directly above the non-absorbent material layer 640 is insulated from the semiconductor multilayer 616 via the insulating layer 638. The configuration of the electrode 620 is merely an example, and other structures shown in other embodiments may also be used.

[0064] [Summary of the Embodiment] (1) The semiconductor optical element has a semiconductor multilayer 16 configured to include an optical waveguide 18, and electrodes 20 having a multilayer structure and a multi-stage structure that are in contact with the upper surface of the semiconductor multilayer 16, the uppermost layer 24 of the multilayer structure being made of Au, the lowermost layer 26 of the multilayer structure being made of a material that has higher adhesion to the semiconductor multilayer 16 than Au, and the multi-stage structure being made of three or more adjacent sections S of different thicknesses that overlap the optical waveguide 18 and are adjacent to each other in the direction in which the optical waveguide 18 extends, and pairs of adjacent sections S The semiconductor multilayer 16 consists of one side that is close to the edge and has a small thickness, and the other side that is far from the edge and has a large thickness, and the three or more sections S include a first section S1 which is composed of at least the bottom layer 26 and has the smallest thickness, a second section S2 which is adjacent to the first section S1 and consists of at least the bottom layer 26 plus a stress relaxation layer 30 made of a material with a Young's modulus of Au or less, and a third section S3 which is composed of all layers from the top layer 24 to the bottom layer 26 and has the largest thickness.

[0065] (2) The semiconductor optical element described in (1), wherein the stress relaxation layer 30 of the second section S2 may be part of the uppermost layer 24.

[0066] (3)(2) The semiconductor optical element described in (2), wherein the first section S1 may further include other parts of the uppermost layer 424.

[0067] (4)(3) The semiconductor optical element described in (3), wherein the other part of the uppermost layer 424 included in the first section S1 may be less than or equal to half the thickness of the part of the uppermost layer 424 included in the second section S2.

[0068] (5)(1) The semiconductor optical element described in (1) is such that the stress relaxation layer 130 of the second section S2 is a different layer from the uppermost layer 124.

[0069] (6) A semiconductor optical element according to any one of (1) to (5), wherein the first section S1 has a first thickness t1, the thickness of the second section S2 beyond the first section S1 is a second thickness t2, the thickness of the third section S3 beyond the second section S2 is a third thickness t3, and at least one of the first thickness t1 and the second thickness t2 may be half or less of the third thickness t3.

[0070] (7) A semiconductor optical device according to any one of (1) to (6), wherein the multilayer structure may include a barrier layer 28 made of a material that prevents metal diffusion between the uppermost layer 24 and the lowermost layer 26, extending over three or more sections S.

[0071] (8)(7) The semiconductor optical element is described above, and the barrier layer 28 may be a layer that is in contact with the bottom layer 26.

[0072] A semiconductor optical device according to (9), (7), or (8), wherein the multilayer structure may include a partial barrier layer 232 made of a material that prevents metal diffusion in at least the third section S3, excluding the first section S1.

[0073] The semiconductor optical device described in (10)(9) is also included in the second section S2, wherein the partial barrier layer 232 is also included in the second section S2.

[0074] A semiconductor optical device according to any one of items (11)(7) to (10), wherein the material for preventing metal diffusion may be Pt, W, Cr, Pd, or Ta.

[0075] (12) A semiconductor optical device according to any one of items (1) to (11), wherein the bottom layer 26 may be made of Ti or Mo.

[0076] (13) A semiconductor optical element according to any one of items (1) to (12), wherein the layer constituting the upper surface of the second section S2 may be made of Pt or Ti.

[0077] (14) A semiconductor optical element according to any one of items (1) to (13), wherein the end face of the layer constituting the first section S1 may coincide with the side surface of the semiconductor multilayer 16.

[0078] (15) A semiconductor optical element according to any one of items (1) to (13), wherein the end face of the layer constituting the first section S1 may be separated from the side surface of the semiconductor multilayer 616.

[0079] A semiconductor optical element according to any one of items (16)(1) to (15), wherein the semiconductor multilayer 516 may include a mesa structure that forms an optical waveguide 518.

[0080] (17) A semiconductor optical device according to any one of items (1) to (16), wherein the semiconductor multilayer 16 may include an active layer or an optical absorption layer that constitutes at least a part of the optical waveguide 18.

[0081] The semiconductor optical element described in (18)(17) is wherein the optical waveguide 618 includes a non-absorbing material layer 640 having a band gap larger than that of the active layer or the optical absorption layer, and the non-absorbing material layer 640 is adjacent to the active layer or the optical absorption layer in the optical waveguide direction, and the portion of the electrode 620 directly above the non-absorbing material layer 640 may be insulated from the semiconductor multilayer 616 via an insulating layer 638. The semiconductor optical element described in (19)(16), wherein the electrode 520 may be the multi-stage structure on the upper surface of the mesa structure. A semiconductor optical element as described in (20)(16), wherein the electrode 520 may have the multi-stage structure on the side surface of the mesa structure.

[0082] The present invention is not limited to the embodiments described above, and various modifications are possible. For example, the configurations described in the embodiments can be replaced with substantially the same configuration, a configuration that produces the same effect, or a configuration that can achieve the same purpose. [Explanation of Symbols]

[0083] 2 Semiconductor multilayer, 4 Top layer, 6 Bottom layer, 8 Barrier layer, 10 Lower cladding layer, 12 Optical functional layer, 14 Upper cladding layer, 16 Semiconductor multilayer, 18 Optical waveguide, 20 Electrode, 22 Back electrode, 24 Top layer, 26 Bottom layer, 28 Barrier layer, 30 Stress relaxation layer, 116 Semiconductor multilayer, 124 Top layer, 130 Stress relaxation layer, 216 Semiconductor multilayer, 220 Electrode, 224 Top layer, 230 Stress relaxation layer, 232 Partial barrier layer, 316 Semiconductor multilayer, 324 Top layer, 328 Barrier layer, 330 Stress relaxation layer, 332 Partial barrier layer, 416 Semiconductor multilayer, 424 Top layer, 426 Bottom layer, 428 Barrier layer, 510 Lower cladding layer, 512 Optical functional layer, 514 516 Upper cladding layer, 518 Semiconductor multilayer, 518 Optical waveguide, 520 Electrode, 522 Back electrode, 524 Top layer, 526 Layer, 534 Main electrode, 536 Pad electrode, 538 Insulating layer, 610 Lower cladding layer, 612 Optical functional layer, 614 Upper cladding layer, 616 Semiconductor multilayer, 618 Optical waveguide, 620 Electrode, 622 Back electrode, 634 Main electrode, 636 Pad electrode, 638 Insulating layer, 640 Non-absorbent material layer, 642 Embedding layer, S Section, S1 First section, S2 Second section, S3 Third section.

Claims

1. A semiconductor multilayer configured to include an optical waveguide, A multilayer and multi-stage electrode that contacts the upper surface of the semiconductor multilayer, It has, The uppermost layer of the aforementioned multilayer structure is made of Au, The bottom layer of the aforementioned multilayer structure is composed of a material that has higher adhesion to the semiconductor multilayer than Au. The multi-stage structure is composed of three or more sections of different thicknesses that overlap the optical waveguide and are adjacent to each other in the direction in which the optical waveguide extends. A pair of adjacent sections of the three or more sections consists of one section that is close to the end face of the semiconductor multilayer and has a small thickness, and the other section that is further away from the end face of the semiconductor multilayer and has a large thickness. The three or more sections mentioned above are: A first section comprising at least the bottom layer and having the minimum thickness, A second section adjacent to the first section is composed of a stress relaxation layer made of a material with a Young's modulus of Au or less, in addition to the bottommost layer, The third section, which consists of all layers from the uppermost layer to the lowermost layer and has the greatest thickness, Includes, The stress relaxation layer in the second section is a semiconductor optical element that is part of the uppermost layer.

2. A semiconductor optical element according to claim 1, The first section further comprises a semiconductor optical element including another portion of the uppermost layer.

3. A semiconductor optical element according to claim 2, A semiconductor optical element in which the other part of the uppermost layer included in the first section has a thickness of less than or equal to half the thickness of the part of the uppermost layer included in the second section.

4. A semiconductor optical element according to any one of claims 1 to 3, The first section has a first thickness, The thickness of the second section that exceeds the thickness of the first section is the second thickness, The thickness of the third section exceeding that of the second section is the third thickness. A semiconductor optical element in which at least one of the first thickness and the second thickness is half or less of the third thickness.

5. A semiconductor multilayer configured to include an optical waveguide, A multilayer and multi-stage electrode that contacts the upper surface of the semiconductor multilayer, It has, The uppermost layer of the aforementioned multilayer structure is made of Au, The bottom layer of the aforementioned multilayer structure is composed of a material that has higher adhesion to the semiconductor multilayer than Au. The multi-stage structure is composed of three or more sections of different thicknesses that overlap the optical waveguide and are adjacent to each other in the direction in which the optical waveguide extends. A pair of adjacent sections of the three or more sections consists of one section that is close to the end face of the semiconductor multilayer and has a small thickness, and the other section that is further away from the end face of the semiconductor multilayer and has a large thickness. The three or more sections mentioned above are: A first section comprising at least the bottom layer and having the minimum thickness, A second section adjacent to the first section is composed of a stress relaxation layer made of a material with a Young's modulus of Au or less, in addition to the bottommost layer, The third section, which consists of all layers from the uppermost layer to the lowermost layer and has the greatest thickness, Includes, The multilayer structure includes a semiconductor optical element comprising a barrier layer made of a material that prevents metal diffusion between the uppermost layer and the lowermost layer, and throughout the three or more sections.

6. A semiconductor optical element according to claim 5, The barrier layer is a semiconductor optical element that is in contact with the bottom layer.

7. A semiconductor optical element according to claim 5 or 6, The multilayer structure is a semiconductor optical element in which at least the third section, excluding the first section, includes a partial barrier layer made of a material that prevents metal diffusion.

8. A semiconductor optical element according to claim 7, The aforementioned partial barrier layer is a semiconductor optical element also included in the second section.

9. A semiconductor optical element according to any one of claims 5 to 8, The material that prevents the aforementioned metal diffusion is a semiconductor optical element, wherein the material is Pt, W, Cr, Pd, or Ta.

10. A semiconductor optical element according to any one of claims 1 to 9, The bottom layer is a semiconductor optical element made of Ti or Mo.

11. A semiconductor optical element according to any one of claims 1 to 10, The layer constituting the upper surface of the second section is a semiconductor optical element made of Pt or Ti.

12. A semiconductor optical element according to any one of claims 1 to 11, The end face of the layer constituting the first section is a semiconductor optical element that coincides with the side surface of the semiconductor multilayer.

13. A semiconductor optical element according to any one of claims 1 to 11, A semiconductor optical element in which the end face of the layer constituting the first section is separated from the side surface of the semiconductor multilayer.

14. A semiconductor optical element according to any one of claims 1 to 13, The semiconductor multilayer includes a semiconductor optical element with a mesa structure that serves as an optical waveguide.

15. A semiconductor optical element according to any one of claims 1 to 14, The semiconductor multilayer includes a semiconductor optical element comprising an active layer or an optical absorbing layer that constitutes at least a portion of the optical waveguide.

16. A semiconductor optical element according to claim 15, The optical waveguide includes a non-absorbing material layer with a band gap larger than that of the active layer or the light-absorbing layer. The non-absorbing material layer is adjacent to the active layer or the light-absorbing layer in the optical wave-guiding direction, The portion of the electrode directly above the non-absorbing material layer is insulated from the semiconductor multilayer via an insulating layer, forming a semiconductor optical element.

17. A semiconductor optical element according to claim 14, The electrode is a semiconductor optical element having the multi-stage structure on the upper surface of the mesa structure.

18. A semiconductor optical element according to claim 14, The electrode is a semiconductor optical element having the multi-stage structure on the side of the mesa structure.

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