Signal processing circuit

Abstract

In this signal processing circuit (1), an input circuit (2) generates an input signal (SIN) by binarizing an external input wave (EW). A digital filter circuit (4) samples the input signal (SIN) on the basis of a clock signal (CLK), and removes noise included in the input signal (SIN) on the basis of a plurality of sampling values. A counter circuit (5) counts the number of pulses included in the input signal (SIN) from which the noise has been removed by the digital filter circuit (4). A clock supply circuit (3) which generates the clock signal (CLK) selectively outputs one of a phase synchronization circuit output and a timer circuit output as the clock signal (CLK).

Description

Technical Field

[0001] This disclosure relates to a signal processing circuit.

Background Art

[0002] Japanese Patent Application Laid-Open No. 3-195112 (Patent Document 1) discloses a counter unit provided with a filter circuit on the input side to remove noise from an input signal.

[0003] Particularly in the case of this document, instead of adopting a CR configuration for the configuration that determines the time constant of the filter circuit, it has a configuration that can be set by a program. Specifically, by dividing the input clock at the set division ratio, a clock signal used in the filter circuit is generated.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Simply dividing the input clock by a division circuit as described in the above Patent Document 1 has a limited setting range for the clock frequency. This disclosure has been made in consideration of the above background art, and one of its purposes is to expand the setting range of the time constant of the filter circuit compared to the prior art.

Means for Solving the Problems

[0006] One embodiment of the signal processing circuit comprises an input circuit, a digital filter circuit, a counter circuit, and a clock supply circuit that generates a clock signal. The input circuit generates an input signal by binarizing an external input wave. The digital filter circuit samples the input signal based on the clock signal and removes noise contained in the input signal based on a plurality of sampling values ​​that are continuous in time series. The counter circuit counts the number of pulses contained in the input signal from which noise has been removed by the digital filter circuit. The clock supply circuit comprises a phase-locking circuit that multiplies and divides the frequency of the original oscillator, and a timer circuit that outputs a square wave that inverts when the count of the reference signal matches a set value. The clock supply circuit selects and outputs either the output of the phase-locking circuit or the output of the timer circuit as the clock signal. [Effects of the Invention]

[0007] According to the above embodiment, by selecting either the output of the phase-locking circuit or the output of the timer circuit as the clock signal and outputting it to the digital filter circuit, the setting range of the time constant of the filter circuit can be expanded compared to before. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram showing an example configuration of the signal processing circuit of Embodiment 1. [Figure 2] Figure 1 is a circuit diagram showing an example of the configuration of a digital filter circuit. [Figure 3] Figure 2 is a circuit diagram showing a modified example of the digital filter circuit. [Figure 4] This block diagram shows an example configuration of the clock supply circuit shown in Figure 1. [Figure 5] Figure 4 is a block diagram showing an example of the configuration of a phase-locked circuit. [Figure 6] Figure 4 is a block diagram showing an example of the timer circuit configuration. [Figure 7] This is a block diagram showing a first modified example of the clock supply circuit shown in Figure 4. [Figure 8]This block diagram shows a second modified example of the clock supply circuit shown in Figure 4. [Figure 9] This is a block diagram showing an example of the configuration of the signal processing circuit of Embodiment 2. [Figure 10] This is a block diagram showing an example of the configuration of a digital filter circuit in Figure 9. [Figure 11] This is a block diagram showing a modified example of the signal processing circuit in Figure 9. [Figure 12] Figure 11 is a block diagram showing an example of the configuration of a digital filter circuit. [Figure 13] This is a block diagram showing an example of the configuration of the signal processing circuit according to Embodiment 3. [Figure 14] Figure 13 is a block diagram showing an example configuration of a digital filter circuit and a clock buffer circuit. [Modes for carrying out the invention]

[0009] Each embodiment will be described in detail below with reference to the drawings. Note that identical or corresponding parts are denoted by the same or similar reference numerals, and their descriptions will not be repeated.

[0010] Embodiment 1. [Overall configuration of the signal processing circuit] Figure 1 is a block diagram showing an example configuration of the signal processing circuit 1 of Embodiment 1. Referring to Figure 1, the signal processing circuit 1 comprises an input circuit 2, a clock supply circuit 3, a digital filter circuit 4, and a counter circuit 5. The signal processing circuit is mounted on, for example, a microcontroller.

[0011] Input circuit 2 generates a digital input signal SIN having high and low logic values ​​by binarizing the external input wave EW. The input signal SIN contains noise that partially inverts the logic value due to noise contained in the external input wave EW. The input signal SIN may also contain chattering. The input signal SIN is input to digital filter circuit 4.

[0012] The clock supply circuit 3 generates a clock signal CLK having a set frequency based on a reference clock. The clock signal CLK is input to the digital filter circuit 4.

[0013] The digital filter circuit 4 samples the input signal SIN for each period of the clock signal CLK. The digital filter circuit 4 determines the logical value of the input signal SIN at the current sampling time based on the logical values of the input signal SIN at a plurality of consecutive sampling times including the current sampling time in a time series.

[0014] For example, when all of the input signals SIN at the plurality of sampling times are at a high level, the digital filter circuit 4 sets the input signal SIN at the current sampling time to the high level, and when all of the input signals SIN at the plurality of sampling times are at a low level, the digital filter circuit 4 sets the input signal SIN at the current sampling time to the low level. When the input signals SIN at the plurality of sampling times include both high and low levels, the logical value at the sampling time immediately before the current sampling time is maintained as it is. The digital filter circuit 4 may perform signal processing based on a majority vote instead of the signal processing based on such total agreement.

[0015] By performing the above-described signal processing on the input signal SIN, the digital filter circuit 4 generates an output signal SOUT from which noise and chattering included in the input signal SIN are removed. The output signal SOUT is input to the counter circuit 5.

[0016] The counter circuit 5 counts the number of pulses included in the output signal SOUT output from the digital filter circuit 4.

[0017] [Configuration Example of Digital Filter Circuit] FIG. 2 is a circuit diagram showing a configuration example of the digital filter circuit 4 in FIG. 1. Referring to FIG. 2, the digital filter circuit 4 is constituted by a logic circuit and includes a shift register 10 and a logic operation circuit 11.

[0018] The shift register 10 includes n stages of D flip-flops DF1 to DFn connected in series. Figure 2 shows the case where n=4. The input signal SIN is input to the D terminal of the first stage D flip-flop DF1. The output of the Q terminal of the i-1 stage D flip-flop DFi-1 is input to the D terminal of the i-1 stage D flip-flop DFi-1. The outputs Q1 to Qn of the Q terminals of each stage of D flip-flops DF1 to DFn are input to the logic circuit 11.

[0019] Furthermore, the clock signal CLK is input to the clock terminal of each stage of D flip-flops DF1 to DFn. By changing the period of the clock signal CLK, the sampling period of the input signal SIN can be changed. Note that each of the D flip-flops DF1 to DFn may also be provided with a reset terminal, which is not shown in the diagram.

[0020] The logic circuit 11 includes an AND circuit 12, a NOR circuit 13, and an RS (Reset-Set) flip-flop 14. The AND circuit 12 calculates the logical AND of the outputs Q1 to Qn of the Q terminals of the D flip-flops DF1 to DFn in each stage. The NOR circuit 13 calculates the negation of the logical OR of the outputs Q1 to Qn of the Q terminals of the D flip-flops DF1 to DFn in each stage. The result of the AND circuit 12 is input to the S terminal of the RS flip-flop 14. The result of the NOR circuit 13 is input to the R terminal of the RS flip-flop 14. The output signal SOUT of the digital filter circuit 4 is output from the Q terminal of the RS flip-flop 14.

[0021] According to the configuration of the logic circuit 11 described above, when the outputs Q1 to Qn of the Q terminals of the D flip-flops DF1 to DFn in each stage are all at a high level ("1"), "1" is input to the S terminal and "0" is input to the R terminal of the RS flip-flop 14. As a result, the RS flip-flop 14 enters a set state and outputs a high-level output signal SOUT.

[0022] When the outputs Q1 to Qn of the Q terminals of the D flip-flops DF1 to DFn in each stage are all at a low level ("0"), a "1" is input to the R terminal and a "0" is input to the S terminal of the RS flip-flop 14. As a result, the RS flip-flop 14 enters a reset state, and a low-level output signal SOUT is output.

[0023] When the outputs Q1 to Qn of the Q terminals of the D flip-flops DF1 to DFn in each stage contain a mix of "1" and "0", "0" is input to both the S terminal and R terminal of the RS flip-flop 14. As a result, the output of the RS flip-flop 14 retains its current state.

[0024] Figure 3 is a circuit diagram showing a modified version of the digital filter circuit 4 in Figure 2. In the digital filter circuit 4A of Figure 3, the logic operation circuit 11 in Figure 2 is changed to logic operation circuit 11A. For simplicity, the following explanation assumes that the number of stages n of the shift register 10 is 4.

[0025] The logic circuit 11A in Figure 3 differs from the logic circuit 11 in Figure 2 in that it further includes a NOT gate 21 and an RS flip-flop 22. Furthermore, the configurations of the AND gate 12 and NOR gate 13 in Figure 2 are described in more detail in the logic circuit 11A in Figure 3.

[0026] Specifically, AND gate 12 includes AND gates 15, 16, and 17. AND gate 15 calculates the logical AND of the outputs Q1 and Q2 of the first and second stage D flip-flops DF1 and DF2. AND gate 16 calculates the logical AND of the outputs Q3 and Q4 of the third and fourth stage D flip-flops DF3 and DF4. AND gate 17 calculates the logical AND of the result of AND gate 15 and the result of AND gate 16. The result of AND gate 17 is input to the S terminal of RS flip-flop 14 as the result of AND gate 12.

[0027] Furthermore, the NOR circuit 13 includes OR circuits 18, 19 and NOR circuit 20. OR circuit 18 calculates the logical OR of the outputs Q1 and Q2 of the first and second stage D flip-flops DF1 and DF2. OR circuit 19 calculates the logical OR of the outputs Q3 and Q4 of the third and fourth stage D flip-flops DF3 and DF4. NOR circuit 20 calculates the negation of the logical OR of the result of OR circuit 18 and the result of OR circuit 19. The result of NOR circuit 20 is input to the R terminal of RS flip-flop 14 as the result of NOR circuit 13.

[0028] The S terminal of RS flip-flop 22 receives the result of AND circuit 15, which is an intermediate step in the logical AND operation of AND circuit 12. The R terminal of RS flip-flop 22 receives the negation of the result of OR circuit 18, which is an intermediate step in the logical OR operation of NOR circuit 13.

[0029] According to the above configuration, the logic circuit 11A in Figure 3 outputs both an output signal SOUT based on the logic value of the input signal SIN at four consecutive sampling times, including the current sampling time, and an output signal SOUT' based on the logic value of the input signal SIN at two consecutive sampling times, including the current sampling time. Therefore, these output signals SOUT and SOUT' are signals obtained by performing a logic operation on sampling values ​​with different numbers of sampling points. The counter circuit 5 in Figure 1 can selectively use these output signals SOUT and SOUT'.

[0030] [Example of a clock supply circuit configuration] Figure 4 is a block diagram showing an example configuration of the clock supply circuit 3 in Figure 1. Referring to Figure 4, the clock supply circuit 3 includes a phase-locked loop (PLL) 30 and a timer circuit 31. The clock supply circuit 3 outputs the clock signal CLK as one of the output signals selected from the phase-locked loop 30 and the timer circuit 31.

[0031] The phase-locking circuit 30 generates a signal with a frequency obtained by multiplying and dividing the fundamental oscillation frequency generated by the reference oscillator. The timer circuit 31 counts the pulse signal generated by the reference oscillator and generates a square wave that inverts when the count value equals a set value. By using the phase-locking circuit 30 and the timer circuit 31 together, the frequency of the clock signal CLK can be set over an extremely wide range.

[0032] When the phase-locking circuit 30 outputs a clock signal CLK, the output terminal of the timer circuit 31 is set to high impedance. This prevents any influence on the phase-locking circuit 30. Conversely, when the timer circuit 31 outputs a clock signal CLK, the output terminal of the phase-locking circuit 30 is set to high impedance.

[0033] Figure 5 is a block diagram showing an example configuration of the phase-locked circuit 30 shown in Figure 4. Referring to Figure 5, the phase-locked circuit 30 includes a reference oscillator 40, a frequency divider 41, a phase comparator 42, a low-pass filter 43, a voltage-controlled oscillator 44, and a frequency divider 45.

[0034] The reference oscillator 40 generates a reference signal having an excitation frequency. The frequency divider 41 divides the excitation frequency by 1 / M. The phase comparator 42 detects the phase difference between the reference signal divided by the frequency divider 41 and the clock signal CLK1 divided by the frequency divider 45. The low-pass filter 43 removes ripple from the DC signal output from the phase comparator 42. The voltage-controlled oscillator 44 generates a clock signal CLK1 having a frequency corresponding to the magnitude of the DC signal that has passed through the low-pass filter 43. The frequency divider 45 divides the clock signal CLK1 by 1 / N.

[0035] Through the feedback control described above, the phase-locking circuit 30 can stably generate a clock signal CLK1 having a frequency that is N / M times the excitation frequency.

[0036] Figure 6 is a block diagram showing an example configuration of the timer circuit 31 shown in Figure 4. The timer circuit 31 includes a counter 50, a data register 51, a comparator 52, and an output circuit 53.

[0037] The counter 50 counts the reference signal output from the reference oscillator 54 in one cycle. The data register 51 stores the count value set by the CPU (Central Processing Unit) 55. The comparator 52 compares the current count value of the counter 50 with the count value stored in the data register 51 and activates its output when they match. When the output of the comparator 52 is activated, the count value of the counter 50 is reset. The output circuit 53 outputs a signal to the outside in response to the activation of the output of the comparator 52. For example, the output circuit 53 outputs a square wave that is inverted at the timing when the output of the comparator 52 is activated as the clock signal CLK2.

[0038] According to the configuration of the timer circuit 31 described above, clock signals CLK with various frequencies can be generated by changing the count value set in the data register 51.

[0039] The phase-lock circuit 30 and the timer circuit 31 are used in different ways. When the frequency generated by the reference oscillator 40 and its frequency division in the phase-lock circuit 30 can be selected as the clock signal CLK, this is selected. On the other hand, when it is desired to use a frequency that cannot be realized by the phase-lock circuit 30, i.e., a frequency that does not correspond to the reference oscillator 40 and its frequency division, the output of the timer circuit 31 (such as the rising edge) is selected as the frequency of the clock signal CLK. This allows the window length of the digital filter circuit 4 (the period containing multiple consecutive sampling values ​​in time series) to be changed over a wide range and with fine adjustment.

[0040] [Modified Clock Supply Circuit] Figure 7 is a block diagram showing a first modified example of the clock supply circuit 3 in Figure 4. In the configuration of the clock supply circuit 3 in Figure 4, there was only one port provided for outputting the clock signal CLK, which was selected from the output signal of the phase synchronization circuit 30 and the output signal of the timer circuit 31.

[0041] In contrast, the clock supply circuit 3 in Figure 7 is provided with a port 60 for outputting the output signal of the phase synchronization circuit 30 and a port 61 for outputting the output signal of the timer circuit 31. When the output signal of the phase synchronization circuit 30 is used as the clock signal CLK, the output signal of the phase synchronization circuit 30 is output from port 60. When the output signal of the timer circuit 31 is used as the clock signal CLK, the output signal of the timer circuit 31 is output from port 61.

[0042] Figure 8 is a block diagram showing a second modified example of the clock supply circuit 3 in Figure 4. In the configuration of Figure 8, a first clock supply circuit 3A equipped with a phase-locking circuit 30 and a second clock supply circuit 3B equipped with a timer circuit 31 are provided. When the output signal of the phase-locking circuit 30 is used as the clock signal CLK, the output signal of the phase-locking circuit 30 is output from the first clock supply circuit 3A. When the output signal of the timer circuit 31 is used as the clock signal CLK, the output signal of the timer circuit 31 is output from the second clock supply circuit 3B.

[0043] The decision of which of the clock supply circuits 3A and 3B outputs the clock signal CLK may be controlled by mutual communication or by a higher-level control system.

[0044] Furthermore, the distinction between the first clock supply circuit 3A and the second clock supply circuit 3B is for convenience only; therefore, clock supply circuits 3A and 3B can be considered together as a single clock supply circuit 3. In this case, the modified example in Figure 8 can be considered substantially the same as the clock supply circuit 3 in Figures 4 and 7.

[0045] [Summary of Embodiment 1] As described above, the digital filter circuit 4 samples the input signal SIN based on the clock signal CLK and removes noise contained in the input signal SIN based on a series of consecutive sampled values.

[0046] For the purposes of this explanation, the period containing multiple consecutive sample values ​​in the above time series is referred to as the window length (or time constant) of the digital filter circuit 4. The window length is expressed as the product of the number of sampling points and the sampling period. The window length must be set to be sufficiently shorter than the pulse width of the external input wave EW or input signal SIN.

[0047] To change the window length, (i) the sampling period is changed by changing the frequency of the clock signal CLK, or (ii) the number of sampling points is changed by changing the number of data used for processing from the output of each stage of the shift register 10.

[0048] As explained with reference to Figures 4 to 6, in order to increase the frequency of the clock signal CLK and shorten the sampling period, the division ratio M of the frequency divider 41 and the division ratio N of the frequency divider 45 are increased in the phase-locking circuit 30. Alternatively, the count value set in the data register 51 in the timer circuit 31 is changed to a smaller value. In order to decrease the frequency of the clock signal CLK and lengthen the sampling period, the division ratio M of the frequency divider 41 and the division ratio N of the frequency divider 45 are increased in the phase-locking circuit 30. Alternatively, the count value set in the data register 51 in the timer circuit 31 is changed to a larger value.

[0049] Furthermore, as explained with reference to Figure 3, the number of sampling points used for signal processing in the logic circuit 11A can be changed. This makes it possible to change the window length.

[0050] According to the signal processing circuit 1 of this embodiment, by changing the frequency of the clock signal CLK used for signal processing by using the phase-locking circuit 30 and the timer circuit 31 in combination as described above, the window length (i.e., time constant) of the digital filter circuit 4 can be changed over a wider range than in the conventional method.

[0051] Embodiment 2. In Embodiment 2, the digital filter circuit 4 allows the output signal of the D flip-flop DF at an intermediate stage of the shift register 10 to be output directly to the counter circuit 5 without performing filtering by the window length configured in the logic operation circuit 11. If the window length of the digital filter circuit 4 cannot be sufficiently shortened compared to the period of the input signal SIN even when the excitation frequency is multiplied using the phase-locking circuit 30, the digital filter circuit 4 outputs the output signal of the D flip-flop DF at an intermediate stage of the shift register 10 directly without performing filtering by the window length configured in the logic operation circuit 11. The following explanation will be given with reference to the drawings.

[0052] Figure 9 is a block diagram showing an example configuration of the signal processing circuit 1A of Embodiment 2. In the signal processing circuit 1A of Figure 9, a digital filter circuit 4B is provided in place of the digital filter circuit 4 of Figure 1. The digital filter circuit 4B outputs the output Qi of one of the D flip-flops DFi that constitute the shift register 10, along with the filtered output signal SOUT.

[0053] The counter circuit 5 performs counting on the selected signal from the output signals SOUT and Qi output from the digital filter circuit 4B. The other configurations in Figure 9 are the same as in Figure 1, so the same or corresponding parts are denoted by the same reference numerals and the explanation is not repeated.

[0054] Figure 10 is a block diagram showing an example configuration of the digital filter circuit 4B in Figure 9. The digital filter circuit 4A in Figure 10 differs from the digital filter circuit 4 in Figure 2 in that it further includes a terminal for outputting the output signal Q1 of the first-stage D flip-flop DF1 that constitutes the shift register 10. Other aspects of Figure 10 are the same as in Figure 2, so the same or corresponding parts are denoted by the same reference numerals and their descriptions are not repeated.

[0055] Figure 11 is a block diagram showing a modified version of the signal processing circuit 1A in Figure 9. In the signal processing circuit 1B of Figure 11, a digital filter circuit 4C is provided in place of the digital filter circuit 4 in Figure 1. The digital filter circuit 4C outputs the filtered output signal SOUT along with the output signals Q1 to Qn of all the D flip-flops DF1 to DFn that constitute the shift register 10.

[0056] The counter circuit 5 performs counting on a selected signal from the output signals SOUT, Q1 to Qn output from the digital filter circuit 4C. The other configurations in Figure 11 are the same as in Figure 1, so the same or corresponding parts are denoted by the same reference numerals and the explanation is not repeated.

[0057] Figure 12 is a block diagram showing an example configuration of the digital filter circuit 4C in Figure 11. In Figure 11, the case where the number of stages n=4 in the shift register 10 is shown.

[0058] The digital filter circuit 4C in Figure 12 differs from the digital filter circuit 4 in Figure 2 in that it further includes four terminals for outputting the output signals Q1 to Q4 of the D flip-flops DF1 to DF4 that constitute the shift register 10. Other aspects of Figure 12 are the same as those in Figure 2, so the same or corresponding parts are denoted by the same reference numerals and their descriptions are not repeated.

[0059] Embodiment 3. In Embodiment 3, the digital filter circuit 4 is configured to output the input signal SIN as is without performing any filtering. If the window length of the digital filter circuit 4 cannot be sufficiently shortened compared to the period of the input signal SIN, even if the excitation frequency is multiplied using the phase-locking circuit 30, the digital filter circuit 4 will output the input signal SIN as is without performing any filtering. This allows the counter circuit 5 to receive signals with even less delay and shorter window lengths. The following explanation will be given with reference to the drawings.

[0060] Figure 13 is a block diagram showing an example configuration of the signal processing circuit 1C of Embodiment 3. The signal processing circuit 1C in Figure 13 differs from the signal processing circuit 1 in Figure 1 in that it further includes a clock buffer circuit 6. The input signal SIN from the input circuit 2 is input to both the digital filter circuit 4 and the clock buffer circuit 6. As described in Embodiment 1, the digital filter circuit 4 outputs an output signal SOUT, which is the input signal SIN that has been filtered, to the counter circuit 5. The clock buffer circuit 6 outputs a signal shaped according to the input signal SIN as an output signal SOUT_Buff to the counter circuit 5.

[0061] The counter circuit 5 performs counting on a selected signal from the output signal SOUT from the digital filter circuit 4 and the output signal SOUT_Buff from the clock buffer circuit 6. Other aspects of Figure 13 are the same as in Figure 1, so the same or corresponding parts are denoted by the same reference numerals and the explanation is not repeated.

[0062] Figure 14 is a block diagram showing an example configuration of the digital filter circuit 4 and clock buffer circuit 6 in Figure 13. Since the digital filter circuit 4 in Figure 14 is the same as the digital filter circuit 4 in Figure 2, the same reference numerals are used for the same or corresponding parts, and the explanation will not be repeated. The clock buffer circuit 6 in Figure 14 is connected in parallel with the digital filter circuit 4 between the input circuit 2 and the counter circuit 5 in Figure 13. The clock buffer circuit 6 has a Schmitt trigger function.

[0063] Instead of the digital filter circuit 4 in Figure 14, any of the digital filter circuits 4A in Figure 3, 4B in Figure 10, or 4C in Figure 12 may be used. When using the digital filter circuit 4B in Figure 10, the counter circuit 5 performs counting on a selected signal from among the output signal Qi of the D flip-flop DFi, the output signal SOUT of the logic circuit 11, and the output signal SOUT_Buff of the clock buffer circuit 6. When using the digital filter circuit 4C in Figure 12, the counter circuit 5 performs counting on a selected signal from among the output signals Q1 to Q4 of the D flip-flops DF1 to DF4 that constitute the shift register 10, the output signal SOUT of the logic circuit 11, and the output signal SOUT_Buff of the clock buffer circuit 6.

[0064] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this application is indicated by the claims and not by the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of Symbols]

[0065] 1,1A,1B,1C Signal processing circuit, 2 Input circuit, 3,3A,3B Clock supply circuit, 4,4A,4B,4C Digital filter circuit, 5 Counter circuit, 6 Clock buffer circuit, 10 Shift register, 11,11A Logic operation circuit, 12,15,16,17 AND circuit, 13,20 NOR circuit, 14,22 RS flip-flop, 18,19 OR circuit, 21 NOT circuit, 30 Phase synchronous circuit, 31 Timer circuit, 40,54 Reference oscillator, 41,45 Frequency divider, 42 Phase comparator, 43 Low-pass filter, 44 Voltage-controlled oscillator, 50 Counter, 51 Data register, 52 Comparator, 53 Output circuit, CLK,CLK1,CLK2 Clock signal, DF1~DF4 D flip-flop, EW External input wave, Q1~Q4 Output of D flip-flop, SOUT Output signal, SOUT_Buff output signal, SIN input signal.

Claims

1. A signal processing circuit, An input circuit that generates an input signal by binarizing an external input wave, The system includes a digital filter circuit that samples the input signal based on a clock signal and removes noise contained in the input signal based on a plurality of sampling values ​​that are continuous in time series within a time window, The aforementioned digital filter circuit comprises a shift register and a logic circuit, The shift register includes n stages (where n is an integer of 2 or more) of D flip-flops connected in series that operate in synchronization with the clock signal, and the input signal is input to the first stage D flip-flop. The logic circuit determines its own output signal for each period of the clock signal based on the logic value of each output signal of the n stages of D flip-flops, and the output signal of the logic circuit corresponds to the signal from which the noise contained in the input signal has been removed. The digital filter circuit outputs the output signal of at least one of the n stages of D flip-flops together with the output signal of the logic circuit. The aforementioned signal processing circuit further, A counter circuit configured to count the number of pulses of a selected signal from the output signal of the at least one D flip-flop and the output signal of the logic circuit, The system includes a clock supply circuit that generates the aforementioned clock signal, The aforementioned clock supply circuit is A phase-locked circuit that multiplies and divides the frequency of the original vibration, It includes a timer circuit that outputs a square wave that inverts when the count of the reference signal matches the set value. The clock supply circuit selects and outputs either the output of the phase synchronization circuit or the output of the timer circuit as the clock signal. The window length of the time window is adjusted to a shorter window length as the period of the input signal becomes shorter. The counter circuit is a signal processing circuit that counts the number of pulses of the output signal of the logic circuit until the window length of the time window, which is adjusted according to the period of the input signal, reaches a lower limit, and when the window length of the time window reaches the lower limit, it counts the number of pulses of the output signal of the at least one D flip-flop.

2. The signal processing circuit further includes a clock buffer circuit connected in parallel with the digital filter circuit between the input circuit and the counter circuit, The clock buffer circuit outputs a signal shaped according to the input signal to the counter circuit. The signal processing circuit according to claim 1, wherein the counter circuit is configured to count the number of pulses of a signal selected from the output signal of the at least one D flip-flop, the output signal of the logic circuit, and the output signal of the clock buffer circuit.

3. An input circuit that generates an input signal by binarizing an external input wave, A digital filter circuit that samples the input signal based on a clock signal and removes noise contained in the input signal based on a plurality of sampling values ​​that are consecutive in time series within a time window, A clock buffer circuit that outputs a signal shaped according to the input signal, A counter circuit that counts the number of pulses contained in a selected signal from the input signal from which noise has been removed by the digital filter circuit and the input signal from which noise has been removed by the clock buffer circuit, The system includes a clock supply circuit that generates the aforementioned clock signal, The aforementioned clock supply circuit is A phase-locked circuit that multiplies and divides the frequency of the original vibration, It includes a timer circuit that outputs a square wave that inverts when the count of the reference signal matches the set value. The clock supply circuit selects and outputs either the output of the phase synchronization circuit or the output of the timer circuit as the clock signal. The window length of the time window is adjusted to a shorter window length as the period of the input signal becomes shorter. The counter circuit is a signal processing circuit that counts the number of pulses of the input signal from which noise has been removed by the digital filter circuit until the window length of the time window, which is adjusted according to the period of the input signal, reaches a lower limit, and when the window length of the time window reaches the lower limit, it counts the number of pulses of the input signal that has been shaped by the clock buffer circuit.

4. The aforementioned digital filter circuit comprises a shift register and a logic circuit, The shift register includes n stages (where n is an integer of 2 or more) of D flip-flops connected in series that operate in synchronization with the clock signal, and the input signal is input to the first stage D flip-flop. The signal processing circuit according to claim 3, wherein the logic operation circuit determines the output signal of the digital filter circuit for each period of the clock signal based on the logic values ​​of the output signals of each of the n stages of D flip-flops.

5. The logic circuit includes an RS (Reset-Set) flip-flop, and the output signal of the RS flip-flop is input to the counter circuit as the output signal of the digital filter circuit. The aforementioned logic circuit is When the outputs of all n stages of D flip-flops are "1", input "1" to the set terminal and "0" to the reset terminal of the RS flip-flop. When the outputs of all n stages of D flip-flops are "0", input "1" to the reset terminal and "0" to the set terminal of the RS flip-flop. The signal processing circuit according to any one of claims 1, 2, and 4, wherein when the outputs of the n-stage D flip-flops contain a mixture of "1" and "0", "0" is input to the set terminal and reset terminal of the RS flip-flop, respectively.

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