Gate driver, isolation module, low-voltage circuit unit, and high-voltage circuit unit

Abstract

This gate driver (10) comprises: a low voltage circuit (20) that operates when a first voltage (V1) is applied; a high voltage circuit (30) that operates when a second voltage (V2) higher than the first voltage (V1) is applied; a transformer (40A) having a first coil (41A) and a second coil (42A) arranged facing each other with an insulating layer therebetween; and a capacitor (50A) connected in series with the transformer (40A). The low voltage circuit (20) and the high voltage circuit (30) are connected via the transformer (40A) and the capacitor (50A) and transmit signals via the transformer (40A) and the capacitor (50A).

Description

Technical Field

[0001] The present disclosure relates to a gate driver, an isolation module, a low-voltage circuit unit, and a high-voltage circuit unit.

Background Art

[0002] As a gate driver for driving a switching element such as a transistor, for example, an isolated gate driver is known. For example, Patent Document 1 describes a semiconductor integrated circuit as an isolated gate driver including a transformer having a primary-side first coil and a secondary-side second coil.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, since the ground of the first coil and the ground of the second coil are provided independently, for example, the ground potential of the first coil and the ground potential of the second coil may be different. In this case, there is a risk of a short-circuit abnormality (insulation breakdown) in which the first coil and the second coil of the transformer are short-circuited due to the strong electric field that may occur between these ground potentials. Such a problem can also occur in an insulation structure other than the transformer, for example, an insulation structure using a capacitor.

Means for Solving the Problems

[0005] A gate driver according to one aspect of the present disclosure is a gate driver for applying a drive voltage signal to the gate of a switching element, comprising: a low-voltage circuit that operates when a first voltage is applied; a high-voltage circuit that operates when a second voltage higher than the first voltage is applied; a transformer; and a capacitor connected in series with the transformer, wherein the low-voltage circuit and the high-voltage circuit are connected via the transformer and the capacitor, and signals are transmitted via the transformer and the capacitor.

[0006] In this configuration, both the transformer and the capacitor connected in series with the transformer insulate the low-voltage circuit from the high-voltage circuit. Therefore, even if dielectric breakdown occurs in one of the transformer or capacitor due to a short circuit, the other transformer or capacitor can maintain the insulation between the low-voltage and high-voltage circuits. Thus, safety can be improved.

[0007] An isolation module according to one aspect of the present disclosure is an isolation module used to isolate a low-voltage circuit and a high-voltage circuit included in a gate driver that applies a drive voltage signal to the gate of a switching element, comprising a transformer and a capacitor connected in series with the transformer, wherein the low-voltage circuit and the high-voltage circuit are connected via the transformer and the capacitor, and the transformer and the capacitor are used to transmit signals between the low-voltage circuit and the high-voltage circuit.

[0008] In this configuration, both the transformer and the capacitor connected in series with the transformer insulate the low-voltage circuit from the high-voltage circuit. Therefore, even if dielectric breakdown occurs in one of the transformer or capacitor due to a short circuit, the other transformer or capacitor can maintain the insulation between the low-voltage and high-voltage circuits. Thus, safety can be improved. [Effects of the Invention]

[0009] The gate driver, isolation module, low-voltage circuit unit, and high-voltage circuit unit described above can improve safety. [Brief explanation of the drawing]

[0010] [Figure 1] A schematic circuit diagram of the gate driver of the first embodiment. [Figure 2] A plan view showing the internal configuration of the gate driver of the first embodiment. [Figure 3] A schematic cross-sectional view showing a portion of the cross-sectional structure of line 3-3 in Figure 2. [Figure 4] A plan view showing the internal configuration of the gate driver of the second embodiment. [Figure 5] A schematic cross-sectional view showing a portion of the cross-sectional structure of line 5-5 in Figure 4. [Figure 6] A schematic circuit diagram of the gate driver of the third embodiment. [Figure 7] A schematic cross-sectional view of the gate driver of the third embodiment. [Figure 8] A plan view showing the internal configuration of the gate driver of the fourth embodiment. [Figure 9] A schematic cross-sectional view showing a portion of the cross-sectional structure of line 9-9 in Figure 8. [Figure 10] A schematic circuit diagram of the gate driver according to the fifth embodiment. [Figure 11] A schematic cross-sectional view of the gate driver of the fifth embodiment. [Figure 12] A schematic circuit diagram of the gate driver according to the sixth embodiment. [Figure 13] A schematic cross-sectional view of the insulating module of the sixth embodiment. [Figure 14] A schematic circuit diagram of the gate driver according to the seventh embodiment. [Figure 15] A schematic cross-sectional view of the low-voltage circuit unit of the seventh embodiment. [Figure 16] A schematic circuit diagram of the gate driver according to the eighth embodiment. [Figure 17] A schematic cross-sectional view of the high-voltage circuit unit of the eighth embodiment. [Figure 18]Schematic cross-sectional view of a gate driver of a modified example. [Figure 19] Schematic cross-sectional view of a gate driver of a modified example. [Figure 20] Schematic cross-sectional view of a gate driver of a modified example. [Figure 21] Schematic circuit diagram of a gate driver of a modified example. [Figure 22] Schematic circuit diagram of a gate driver of a modified example.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the gate driver will be described with reference to the drawings. The embodiments shown below illustrate configurations and methods for embodying the technical idea, and do not limit the materials, shapes, structures, arrangements, dimensions, etc. of each component to those described below.

[0012] [First Embodiment] Referring to FIGS. 1 to 3, the gate driver 10 of the first embodiment will be described. FIG. 1 schematically shows an example of the circuit configuration of the gate driver 10.

[0013] As shown in FIG. 1, the gate driver 10 applies a drive voltage signal to the gate of the switching element, and is applied, for example, to an inverter device 500 mounted on an electric vehicle or a hybrid vehicle. The inverter device 500 includes a pair of switching elements 501 and 502 connected in series to each other, a gate driver 10, and an ECU 503 that controls the gate driver 10. The switching element 501 is, for example, a high-side switching element connected to a drive power source, and the switching element 502 is a low-side switching element. Examples of the switching elements 501 and 502 include transistors such as SiMOSFET, SiCMOSFET, and IGBT. The gate driver 10 of the first embodiment applies a drive voltage signal to the gate of the switching element 501. In the following description, the case where MOSFETs are used for the switching elements 501 and 502 will be described.

[0014] A gate driver 10 is provided for each switching element 501 and 502, and drives the switching elements 501 and 502 individually. In the first embodiment, for the sake of explanation, the gate driver 10 that drives the switching element 501 will be described.

[0015] The gate driver 10 includes a low-voltage circuit 20 to which a first voltage V1 is applied, a high-voltage circuit 30 to which a second voltage V2 higher than the first voltage V1 is applied, a transformer 40, and a capacitor 50. The first voltage V1 and the second voltage V2 are DC voltages.

[0016] In the first embodiment, the gate driver 10 is configured such that, based on a control signal from an external control unit (ECU) 503, a signal is transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 via a transformer 40 and a capacitor 50, and a drive voltage signal is output from the high-voltage circuit 30. Here, the control signal from the ECU 503 corresponds to an external command.

[0017] The signals transmitted from the low-voltage circuit 20 to the high-voltage circuit 30, that is, the signals output from the low-voltage circuit 20, are, for example, signals for driving the switching element 501, and examples include the set signal and the reset signal. The set signal is a signal that transmits the rising edge of the control signal from the ECU 503, and the reset signal is a signal that transmits the falling edge of the control signal from the ECU 503. The set signal and the reset signal can also be said to be signals for generating the drive voltage signal for the switching element 501. For this reason, the set signal and the reset signal correspond to the first signal.

[0018] In detail, the low-voltage circuit 20 is a circuit that operates when a first voltage V1 is applied. The low-voltage circuit 20 is electrically connected to the ECU 503 and generates set signals and reset signals based on control signals input from the ECU 503. For example, the low-voltage circuit 20 generates a set signal in response to the rising edge of the control signal, and a reset signal in response to the falling edge of the control signal. The low-voltage circuit 20 then transmits the generated set signals and reset signals to the high-voltage circuit 30.

[0019] The high-voltage circuit 30 is a circuit that operates when a second voltage V2 is applied. The high-voltage circuit 30 is electrically connected to the gate of the switching element 501, and based on the set signal and reset signal received from the low-voltage circuit 20, it generates a drive voltage signal to drive the switching element 501 and applies that drive voltage signal to the gate of the switching element 501. In other words, the high-voltage circuit 30 also generates a drive voltage signal to apply to the gate of the switching element 501 based on the first signal output from the low-voltage circuit 20. More specifically, the high-voltage circuit 30 generates a drive voltage signal to turn on the switching element 501 based on the set signal and applies it to the gate of the switching element 501. On the other hand, the high-voltage circuit 30 generates a drive voltage signal to turn off the switching element 501 based on the reset signal and applies that drive voltage signal to the gate of the switching element 501. In this way, the on / off state of the switching element 501 is controlled by the gate driver 10.

[0020] The high-voltage circuit 30 includes, for example, an RS-type flip-flop circuit to which a set signal and a reset signal are input, and a driver unit that generates a drive voltage signal based on the output signal of the RS-type flip-flop circuit. However, the specific circuit configuration of the high-voltage circuit 30 is arbitrary.

[0021] Both the transformer 40 and the capacitor 50 are located between the low-voltage circuit 20 and the high-voltage circuit 30. That is, the low-voltage circuit 20 and the high-voltage circuit 30 are electrically connected via the transformer 40 and the capacitor 50. In the first embodiment, the capacitor 50 is circuit-wise located between the transformer 40 and the high-voltage circuit 30, and the transformer 40 and the capacitor 50 are connected in series.

[0022] In the gate driver 10 of the first embodiment, the low-voltage circuit 20 and the high-voltage circuit 30 are isolated by a transformer 40 and a capacitor 50. Specifically, the transformer 40 and capacitor 50 restrict the transmission of DC voltage between the low-voltage circuit 20 and the high-voltage circuit 30, while allowing the transmission of various signals such as set signals and reset signals.

[0023] In other words, the state in which the low-voltage circuit 20 and the high-voltage circuit 30 are isolated means that the transmission of DC voltage between the low-voltage circuit 20 and the high-voltage circuit 30 is blocked, while the transmission of signals between the low-voltage circuit 20 and the high-voltage circuit 30 is permitted.

[0024] The dielectric strength of the gate driver 10 is, for example, 2500 Vrms or more and 7500 Vrms or less. The dielectric strength of the gate driver 10 in the first embodiment is approximately 3750 Vrms. However, the specific value of the dielectric strength of the gate driver 10 is not limited to this and is arbitrary.

[0025] In the first embodiment, the dielectric strength of the transformer 40 is, for example, 2500 Vrms or more and 7500 Vrms or less. However, the dielectric strength of the transformer 40 may be 2500 Vrms or more and 5700 Vrms or less. However, it is not limited to this, and the dielectric strength of the transformer 40 is arbitrary.

[0026] The dielectric strength of the capacitor 50 is set to be greater than or equal to that of the transformer 40, for example. For example, the dielectric strength of the capacitor 50 is 200 Vrms or more and 5700 Vrms or less, preferably 600 Vrms or more and 5700 Vrms or less. However, as can be seen from the range of the dielectric strength of the capacitor 50, the dielectric strength of the capacitor 50 is not limited to being greater than or equal to that of the transformer 40, and the dielectric strength of the capacitor 50 may be lower than that of the transformer 40.

[0027] In the first embodiment, the ground of the low-voltage circuit 20 and the ground of the high-voltage circuit 30 are provided independently. Hereinafter, the ground potential of the low-voltage circuit 20 will be referred to as the first reference potential, and the ground potential of the high-voltage circuit 30 will be referred to as the second reference potential. In this case, the first voltage V1 is the voltage from the first reference potential, and the second voltage V2 is the voltage from the second reference potential. The first voltage V1 is, for example, 4.5V or more and 5.5V or less, and the second voltage V2 is, for example, 9V or more and 24V or less.

[0028] The following provides a detailed description of transformer 40 and capacitor 50. The gate driver 10 of the first embodiment includes two transformers 40 and two capacitors 50 to correspond to the transmission of two types of signals from the low-voltage circuit 20 to the high-voltage circuit 30. Specifically, the gate driver 10 includes a transformer 40 and capacitor 50 used for transmitting a set signal, and a transformer 40 and capacitor 50 used for transmitting a reset signal.

[0029] For the sake of explanation, the transformer 40 and capacitor 50 used to transmit the set signal will be referred to as transformer 40A and capacitor 50A, and the transformer 40 and capacitor 50 used to transmit the reset signal will be referred to as transformer 40B and capacitor 50B. In other words, transformer 40 can be said to include transformer 40A and transformer 40B, and capacitor 50 can be said to include capacitor 50A and capacitor 50B.

[0030] The gate driver 10 includes a low-voltage signal line 21A connecting the low-voltage circuit 20 and the transformer 40A, and a low-voltage signal line 21B connecting the low-voltage circuit 20 and the transformer 40B. Therefore, the low-voltage signal line 21A is a signal line through which a set signal is transmitted, and the low-voltage signal line 21B is a signal line through which a reset signal is transmitted.

[0031] The gate driver 10 includes a high-voltage signal line 31A connecting transformer 40A and high-voltage circuit 30, and a high-voltage signal line 31B connecting transformer 40B and high-voltage circuit 30. Therefore, high-voltage signal line 31A is a signal line through which a set signal is transmitted, and high-voltage signal line 31B is a signal line through which a reset signal is transmitted.

[0032] In the first embodiment, the transformer 40A and the capacitor 50A are connected in series by the high-voltage signal line 31A, and the capacitor 50A is connected to the high-voltage circuit 30 by the high-voltage signal line 31A. Therefore, it can be said that the transformer 40A and the high-voltage circuit 30 are electrically connected via the capacitor 50A. In addition, the transformer 40B and the capacitor 50B are connected in series by the high-voltage signal line 31B, and the capacitor 50B is connected to the high-voltage circuit 30 by the high-voltage signal line 31B. Therefore, it can be said that the transformer 40B and the high-voltage circuit 30 are electrically connected via the capacitor 50B.

[0033] The set signal output from the low-voltage circuit 20 is transmitted to the high-voltage circuit 30 via transformer 40A and capacitor 50A. The reset signal output from the low-voltage circuit 20 is transmitted to the high-voltage circuit 30 via transformer 40B and capacitor 50B.

[0034] The transformer 40A includes a first coil 41A and a second coil 42A that is insulated from the first coil 41A and is magnetically coupled to it. The first coil 41A is connected to the low-voltage circuit 20 by the low-voltage signal line 21A, while also being connected to the ground of the low-voltage circuit 20. In other words, the first end of the first coil 41A is electrically connected to the low-voltage circuit 20, and the second end of the first coil 41A is electrically connected to the ground of the low-voltage circuit 20. Therefore, the potential at the second end of the first coil 41A becomes the first reference potential. The first reference potential is, for example, 0V.

[0035] The second coil 42A is connected to the high-voltage circuit 30 by the high-voltage signal line 31A, while also being connected to the ground of the high-voltage circuit 30. In other words, the first end of the second coil 42A is electrically connected to the high-voltage circuit 30, and the second end of the second coil 42A is electrically connected to the ground of the high-voltage circuit 30. Therefore, the potential at the second end of the second coil 42A becomes the second reference potential.

[0036] Here, since the ground of the high-voltage circuit 30 is connected to the source of the switching element 501, the second reference potential fluctuates with the driving of the inverter device 500 and may exceed, for example, 600V.

[0037] Capacitor 50A has an insulated first electrode 51A and a second electrode 52A. The first electrode 51A is electrically connected to transformer 40A, and the second electrode 52A is electrically connected to high-voltage circuit 30. More specifically, the first electrode 51A is connected to the second coil 42A by a high-voltage signal line 31A, and the second electrode 52A is connected to the high-voltage circuit 30 by a high-voltage signal line 31A.

[0038] The transformer 40B has a first coil 41B which is electrically connected to the low-voltage circuit 20 by a low-voltage signal line 21B, and a second coil 42B which is insulated from the first coil 41B and is magnetically coupled. The second coil 42B is electrically connected to the high-voltage circuit 30 via a capacitor 50B.

[0039] Capacitor 50B has an insulated first electrode 51B and a second electrode 52B. The first electrode 51B is electrically connected to transformer 40B, and the second electrode 52B is electrically connected to the high-voltage circuit 30. Since transformer 40B and capacitor 50B are the same as transformer 40A and capacitor 50A, a detailed explanation is omitted.

[0040] The structure of the gate driver 10 will be described below using Figures 2 and 3. Figure 2 shows an example of a plan view showing the internal configuration of the gate driver 10, and Figure 3 shows a cross-sectional view taken along line 3-3 in Figure 2.

[0041] Note that in Figure 1, the circuit configuration of the gate driver 10 is shown in a simplified manner, so the number of external terminals of the gate driver 10 in Figure 2 is greater than the number of external terminals of the gate driver 10 in Figure 1. Here, the number of external terminals of the gate driver 10 refers to the number of external electrodes that can connect the gate driver 10 to external electronic components such as the ECU 503 and the switching element 501 (see Figure 1). Also, the number of signal lines (the number of wires W described later) that transmit signals from the low-voltage circuit 20 to the high-voltage circuit 30 in the gate driver 10 in Figure 2 is greater than the number of signal lines of the gate driver 10 in Figure 1.

[0042] As shown in Figure 2, the gate driver 10 is a semiconductor device in which multiple semiconductor chips are packaged together, and is mounted on a circuit board provided in, for example, an inverter device 500. Note that each switching element 501, 502 is mounted on a separate mounting board from the circuit board. A cooler is attached to this mounting board.

[0043] The gate driver 10 is packaged in an SO-based format, and in the first embodiment, it is packaged in an SOP format. The gate driver 10 comprises a low-voltage circuit chip 60, a high-voltage circuit chip 70, and a transformer chip 80 as semiconductor chips, a low-voltage lead frame 90 on which the low-voltage circuit chip 60 is mounted, a high-voltage lead frame 100 on which the high-voltage circuit chip 70 is mounted, and a sealing resin 110 that seals parts of each lead frame 90, 100 and each chip 60, 70, 80. In Figure 2, the sealing resin 110 is shown as a dashed line for the purpose of illustrating the internal structure of the gate driver 10. The package format of the gate driver 10 can be arbitrarily changed.

[0044] The sealing resin 110 is made of an electrically insulating material, for example, a black epoxy resin. The sealing resin 110 is formed in the shape of a rectangular plate with the z direction as the thickness direction. The sealing resin 110 has four resin sides 111 to 114. In detail, the sealing resin 110 has resin sides 111 and 112 as end faces in the x direction, and resin sides 113 and 114 as end faces in the y direction. The x and y directions are perpendicular to the z direction. The x and y directions are orthogonal to each other. In the following description, "plan view" means viewing from the z direction.

[0045] The low-voltage lead frame 90 and the high-voltage lead frame 100 are each made of a conductor, and in the first embodiment, they are made of Cu (copper). Each lead frame 90, 100 is provided spanning both the inside and outside of the sealing resin 110.

[0046] The low-voltage lead frame 90 includes a low-voltage die pad 91 located within the sealing resin 110, and a plurality of low-voltage leads 92 arranged to span both the inside and outside of the sealing resin 110. Each low-voltage lead 92 constitutes an external terminal that electrically connects to an external electronic device such as an ECU 503 (see Figure 1).

[0047] The low-voltage die pad 91 is mounted on a low-voltage circuit chip 60 and a transformer chip 80. In a plan view, the low-voltage die pad 91 is positioned such that its center in the y-direction is closer to the resin side surface 113 than the center of the sealing resin 110 in the y-direction. In the first embodiment, the low-voltage die pad 91 is not exposed from the sealing resin 110. In a plan view, the shape of the low-voltage die pad 91 is rectangular, with the x-direction being the longer side and the y-direction being the shorter side.

[0048] Multiple low-pressure leads 92 are arranged spaced apart from each other in the x-direction. Each of the low-pressure leads 92 located at both ends in the x-direction is integrated with the low-pressure die pad 91. A portion of each low-pressure lead 92 protrudes outward from the resin side surface 113 toward the sealing resin 110.

[0049] The high-voltage lead frame 100 includes a high-voltage die pad 101 located within the sealing resin 110, and a plurality of high-voltage leads 102 arranged to span both the inside and outside of the sealing resin 110. Each high-voltage lead 102 constitutes an external terminal that electrically connects to external electronic equipment such as the gate of a switching element 501 (see Figure 1).

[0050] A high-voltage circuit chip 70 is mounted on the high-voltage die pad 101. In a plan view, the high-voltage die pad 101 is positioned closer to the resin side surface 114 than the low-voltage die pad 91 in the y-direction. In the first embodiment, the high-voltage die pad 101 is not exposed from the sealing resin 110. In a plan view, the shape of the high-voltage die pad 101 is rectangular, with the x-direction being the longer side and the y-direction being the shorter side.

[0051] The low-pressure die pad 91 and the high-pressure die pad 101 are spaced apart in the y-direction. Therefore, the y-direction can also be described as the direction in which the two die pads 91 and 101 are aligned. The y-direction dimensions of the low-voltage die pad 91 and the high-voltage die pad 101 are determined by the size and number of semiconductor chips to be mounted. In the first embodiment, the low-voltage die pad 91 is mounted with a low-voltage circuit chip 60 and a transformer chip 80, and the high-voltage die pad 101 is mounted with a high-voltage circuit chip 70. Therefore, the y-direction dimension of the low-voltage die pad 91 is larger than that of the high-voltage die pad 101.

[0052] Multiple high-voltage leads 102 are arranged spaced apart from each other in the x-direction. One pair of the multiple high-voltage leads 102 is integrated with the high-voltage die pad 101. A portion of each high-voltage lead 102 protrudes outward from the resin side surface 114 toward the sealing resin 110.

[0053] In the first embodiment, the number of high-voltage leads 102 is the same as the number of low-voltage leads 92. As can be seen from Figure 2, the multiple low-voltage leads 92 and the multiple high-voltage leads 102 are arranged in a direction (x direction) perpendicular to the arrangement direction (y direction) of the low-voltage die pads 91 and high-voltage die pads 101. Note that the number of high-voltage leads 102 and the number of low-voltage leads 92 can be changed arbitrarily.

[0054] In the first embodiment, the low-pressure die pad 91 is supported by a pair of low-pressure leads 92 integrated with the low-pressure die pad 91, and the high-pressure die pad 101 is supported by a pair of high-pressure leads 102 integrated with the high-pressure die pad 101. Therefore, each die pad 91, 101 is not provided with suspension leads exposed on the resin side surfaces 111, 112. As a result, the creepage distance between the low-pressure lead frame 90 and the high-pressure lead frame 100 can be made large.

[0055] The low-voltage circuit chip 60, the high-voltage circuit chip 70, and the transformer chip 80 are arranged spaced apart from each other in the y-direction. In other words, in a plan view, the low-voltage circuit chip 60, the high-voltage circuit chip 70, and the transformer chip 80 are also arranged spaced apart from each other in the direction of arrangement of both die pads 91 and 101. In the first embodiment, the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70 are arranged in the y-direction from the resin side surface 113 toward the resin side surface 114.

[0056] Furthermore, considering that each lead 92,102 is arranged in the x-direction, the x-direction can also be said to be the arrangement direction of each lead 92,102, and the y-direction can be said to be perpendicular to the arrangement direction of each lead 92,102 in a plan view. For this reason, the low-voltage circuit chip 60, the high-voltage circuit chip 70, and the transformer chip 80 can be said to be spaced apart from each other in a direction perpendicular to the arrangement direction of each lead 92,102 in a plan view. And, in a plan view, it can be said that the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70 are arranged in the order of low-voltage lead 92 to high-voltage lead 102.

[0057] The low-voltage circuit chip 60 includes the low-voltage circuit 20 shown in Figure 1. In plan view, the low-voltage circuit chip 60 has a rectangular shape with a short side and a long side. In plan view, the low-voltage circuit chip 60 is mounted on the low-voltage die pad 91 such that the long side is along the x-direction and the short side is along the y-direction. As shown in Figure 3, the low-voltage circuit chip 60 has a main chip surface 60s and a back surface 60r that face opposite each other in the z-direction. The back surface 60r of the low-voltage circuit chip 60 is bonded to the low-voltage die pad 91 by a conductive bonding material SD such as solder or Ag (silver) paste.

[0058] As shown in Figure 2, the main surface 60s of the low-voltage circuit chip 60 has a plurality of first electrode pads 61, a plurality of second electrode pads 62, and a plurality of third electrode pads 63 formed thereon. Each electrode pad 61 to 63 is electrically connected to the low-voltage circuit 20 shown in Figure 1.

[0059] Multiple first electrode pads 61 are positioned closer to the low-voltage leads 92 than to the center of the chip main surface 60s in the y-direction. Multiple first electrode pads 61 are arranged in the x-direction. Multiple second electrode pads 62 are positioned at the ends of the chip main surface 60s in the y-direction that are closer to the transformer tip 80. Multiple second electrode pads 62 are arranged in the x-direction. Multiple third electrode pads 63 are positioned at both ends of the chip main surface 60s in the x-direction.

[0060] The transchip 80 includes the transchip 40 shown in Figure 1. In plan view, the shape of the transchip 80 is rectangular with a short side and a long side. In the first embodiment, in plan view, the transchip 80 is mounted on the low-pressure die pad 91 such that the long side is along the x-direction and the short side is along the y-direction.

[0061] The transformer chip 80 is positioned adjacent to the low-voltage circuit chip 60 in the y-direction. The transformer chip 80 is positioned closer to the high-voltage circuit chip 70 than to the low-voltage circuit chip 60.

[0062] As shown in Figure 3, the trans tip 80 has a main tip surface 80s and a back tip surface 80r that face opposite each other in the z direction. The back tip surface 80r of the trans tip 80 is bonded to the low-pressure die pad 91 by a conductive bonding material SD.

[0063] As shown in Figure 2, the main surface 80s of the transformer chip 80 has a plurality of first electrode pads 81 and a plurality of second electrode pads 82 formed thereon. The plurality of first electrode pads 81 are located, for example, at the ends of the main surface 80s in the y-direction that are closer to the low-voltage circuit chip 60. The plurality of first electrode pads 81 are arranged in the x-direction. The plurality of second electrode pads 82 are located near the center of the main surface 80s in the y-direction. The plurality of second electrode pads 82 are arranged in the x-direction.

[0064] In order to set the dielectric strength of the gate driver 10 to a predetermined dielectric strength, it is necessary to separate the low-voltage die pad 91 and the high-voltage die pad 101, where each lead frame 90, 100 is closest, by a predetermined distance or more. For this reason, in a plan view, the distance between the high-voltage circuit chip 70 and the transformer chip 80 is greater than the distance between the low-voltage circuit chip 60 and the transformer chip 80.

[0065] As shown in Figure 3, the transformer chip 80 includes both transformers 40A and 40B (see Figure 1), and more specifically, both transformers 40A and 40B are integrated into a single chip. The transformer chip 80 has an insulating layer 83, and both coils 41A and 42A of transformer 40A are embedded in the insulating layer 83 and are positioned opposite each other, spaced apart in the z direction, via the insulating layer 83. The insulating layer 83 may be one layer or multiple layers.

[0066] Each coil 41A, 42A consists of a conductor layer embedded in the insulating layer 83. In the first embodiment, the second coil 42A is positioned away from the low-voltage die pad 91 relative to the first coil 41A.

[0067] The first coil 41A is electrically connected to the first electrode pad 81. The second coil 42A is electrically connected to the second electrode pad 82. The relative positions of the two coils 41A and 42A can be changed as needed.

[0068] Although not shown in the diagram, transformer 40B has the same configuration as transformer 40A. Therefore, the first coil 41B of transformer 40B is electrically connected to a first electrode pad 81 that is different from the first electrode pad 81 that is electrically connected to the first coil 41A. The second coil 42B is electrically connected to a second electrode pad 82 that is different from the second electrode pad 82 that is electrically connected to the second coil 42A.

[0069] The high-voltage circuit chip 70 includes a high-voltage circuit 30. As shown in Figure 2, the shape of the high-voltage circuit chip 70 in plan view is rectangular with a short side and a long side. In plan view, the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101 such that the long side is along the x-direction and the short side is along the y-direction. As shown in Figure 3, the high-voltage circuit chip 70 has a chip main surface 70s and a chip back surface 70r that face opposite each other in the z-direction. The chip back surface 70r of the high-voltage circuit chip 70 is bonded to the high-voltage die pad 101 by a conductive bonding material SD.

[0070] As shown in Figure 3, the capacitors 50A and 50B of the first embodiment (see Figure 1) are incorporated into a high-voltage circuit chip 70. More specifically, the high-voltage circuit chip 70 has an insulating layer 74, and both capacitors 50A and 50B are embedded within this insulating layer 74. In the first embodiment, the insulating layer 74 is made of a dielectric material. The insulating layer 74 is made of, for example, SiO2.

[0071] The high-voltage circuit 30 is located closer to the back surface 70r of the high-voltage circuit chip 70 than to the insulating layer 74. In the first embodiment, the capacitor 50A is located in the portion of the high-voltage circuit chip 70 that is close to the transformer chip 80 in the y-direction.

[0072] In the first embodiment, as shown in Figure 3, the capacitor 50A is positioned closer to the main surface 70s of the chip than the high-voltage circuit 30 within the high-voltage circuit chip 70. Also, in a plan view, the capacitor 50A is positioned to overlap with the high-voltage circuit 30. Note that the position of the capacitor 50A within the high-voltage circuit chip 70 can be arbitrarily changed.

[0073] The first electrode 51A and the second electrode 52A of capacitor 50A are each formed as flat plates facing each other in a direction perpendicular to the z direction. The first electrode 51A and the second electrode 52A are positioned opposite each other in the z direction, spaced apart, via an insulating layer 74. An insulating layer 74 is interposed between the first electrode 51A and the second electrode 52A within the high-voltage circuit chip 70. In the first embodiment, the first electrode 51A is positioned closer to the main surface 70s of the chip than the second electrode 52A. Although not shown in the figures, the arrangement configuration of capacitor 50B within the high-voltage circuit chip 70 is the same as that of capacitor 50A. Thus, the second electrodes 52A and 52B of capacitors 50A and 50B are electrically connected to the high-voltage circuit 30 within the high-voltage circuit chip 70. In other words, capacitors 50A and 50B are electrically connected to the high-voltage circuit 30 within the high-voltage circuit chip 70.

[0074] As shown in Figure 2, the main surface 70s of the high-voltage circuit chip 70 has a plurality of first electrode pads 71, a plurality of second electrode pads 72, and a plurality of third electrode pads 73 formed thereon. The plurality of first electrode pads 71 ​​are located at the end of the main surface 70s in the y-direction that is closer to the transformer chip 80. The plurality of first electrode pads 71 ​​are arranged in the x-direction. The plurality of second electrode pads 72 are located at the end of the main surface 70s in the y-direction that is further from the transformer chip 80. The plurality of second electrode pads 72 are arranged in the x-direction. The plurality of third electrode pads 73 are located at both ends of the main surface 70s in the x-direction.

[0075] Multiple first electrode pads 71 ​​are electrically connected to capacitors 50A and 50B (see Figure 1). More specifically, some of the multiple first electrode pads 71 ​​are electrically connected to the first electrode 51A of capacitor 50A (see Figure 1). Another portion of the multiple first electrode pads 71 ​​are electrically connected to the first electrode 51B of capacitor 50B (see Figure 1). Each of the multiple second electrode pads 72 and the multiple third electrode pads 73 is electrically connected to the high-voltage circuit 30 (see Figure 1).

[0076] Multiple wires W are connected to each of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70. Each wire W is a bonding wire formed by a wire bonding apparatus and consists of a conductor such as Au (gold), Al (aluminum), or Cu.

[0077] The low-voltage circuit chip 60 is electrically connected to the low-voltage lead frame 90 by wire W. More specifically, the multiple first electrode pads 61 and multiple low-voltage leads 92 of the low-voltage circuit chip 60 are connected by wire W. The multiple third electrode pads 63 of the low-voltage circuit chip 60 and a pair of low-voltage leads 92 integrated with the low-voltage die pad 91 are connected by wire W. As a result, the low-voltage circuit 20 (see Figure 1) and the multiple low-voltage leads 92 (external electrodes of the gate driver 10 that are electrically connected to the ECU 503) are electrically connected. In the first embodiment, the pair of low-voltage leads 92 integrated with the low-voltage die pad 91 constitute the ground terminal, and the low-voltage circuit 20 and the low-voltage die pad 91 are electrically connected by wire W, so that the low-voltage die pad 91 is at the same potential as the ground of the low-voltage circuit 20.

[0078] The low-voltage circuit chip 60 and the transformer chip 80 are electrically connected by wire W. Specifically, the multiple second electrode pads 62 of the low-voltage circuit chip 60 and the multiple first electrode pads 81 of the transformer chip 80 are connected by wire W. This electrically connects the low-voltage circuit 20 to the first coils 41A and 41B of the transformers 40A and 40B (see Figure 1).

[0079] Furthermore, the first coils 41A and 41B are electrically connected to the low-voltage die pad 91 via the first electrode pad 81, the wire W connecting the low-voltage circuit chip 60 and the transformer chip 80, the second electrode pad 62, the low-voltage circuit 20, the third electrode pad 63, and the wire W connected to the third electrode pad 63. This electrically connects the first coils 41A and 41B of the transformers 40A and 40B to the ground of the low-voltage circuit 20.

[0080] The transformer chip 80 and the high-voltage circuit chip 70 are electrically connected by wire W. More specifically, the multiple second electrode pads 82 of the transformer chip 80 and the multiple first electrode pads 71 ​​of the high-voltage circuit chip 70 are connected by wire W. As a result, the second coil 42A of the transformer 40A and the first electrode 51A of the capacitor 50A (both shown in Figure 1) are electrically connected, and the second coil 42B of the transformer 40B and the first electrode 51B of the capacitor 50B (both shown in Figure 1) are electrically connected.

[0081] Furthermore, in the first embodiment, the second electrode 52A of the capacitor 50A is electrically connected to the high-voltage circuit 30 within the high-voltage circuit chip 70. In other words, the portion of the high-voltage signal line 31A that connects the second electrode 52A to the high-voltage circuit 30 is incorporated into the high-voltage circuit chip 70. The same applies to the high-voltage signal line 31B.

[0082] Each of the high-voltage circuit chip 70 and the multiple high-voltage leads 102 of the high-voltage lead frame 100 are electrically connected by a wire W. More specifically, the multiple second electrode pads 72 and multiple third electrode pads 73 of the high-voltage circuit chip 70 are connected to the multiple high-voltage leads 102 by a wire W. As a result, the high-voltage circuit 30 and the multiple high-voltage leads 102 (external electrodes of the gate driver 10 that are electrically connected to the inverter device 500, such as the switching element 501) are electrically connected. In the first embodiment, a pair of high-voltage leads 102 integrated with the high-voltage die pad 101 constitute the ground terminal, and the high-voltage circuit 30 and the high-voltage die pad 101 are electrically connected by a wire W, so that the high-voltage die pad 101 is at the same potential as the ground of the high-voltage circuit 30.

[0083] Furthermore, the second coils 42A and 42B of transformers 40A and 40B (see Figure 1) are electrically connected to the ground of the high-voltage circuit 30. In detail, each coil 42A and 42B is electrically connected to the high-voltage die pad 101 via a second electrode pad 82, a wire W connecting the transformer chip 80 and the high-voltage circuit chip 70, a first electrode pad 71, the high-voltage circuit 30, a third electrode pad 73, and a wire W connected to the third electrode pad 73 that is connected to the high-voltage lead 102 integrated with the high-voltage die pad 101.

[0084] Next, the operation of the gate driver 10 of the first embodiment will be described. In the gate driver 10 of the first embodiment, the ground potential of the high-voltage circuit 30 may be higher than the ground potential of the low-voltage circuit 20. In this case, there is a risk that current will flow from the ground of the high-voltage circuit 30 to the ground of the low-voltage circuit 20. To suppress this current flow from the high-voltage circuit 30 to the low-voltage circuit 20, an insulating transformer 40 is provided between the low-voltage circuit 20 and the high-voltage circuit 30.

[0085] Here, if a voltage higher than the dielectric strength of the transformer 40 is applied, there is a risk of dielectric breakdown, which is an abnormality in which the first coil 41A (41B) and the second coil 42A (42B) will short-circuit. In this case, even if dielectric breakdown occurs in the transformer 40 due to a short circuit between the first coil 41A (41B) and the second coil 42A (42B), the capacitor 50 connected in series with the transformer 40 will maintain the insulation between the low-voltage circuit 20 and the high-voltage circuit 30. In other words, the capacitor 50 functions as additional insulation to the transformer 40, which provides the basic insulation.

[0086] According to the gate driver 10 of the first embodiment, the following effects can be obtained. (1-1) The gate driver 10 includes a low-voltage circuit 20 to which a first voltage V1 is applied, a high-voltage circuit 30 to which a second voltage V2 higher than the first voltage V1 is applied, a transformer 40 having first coils 41A, 41B and second coils 42A, 42B arranged opposite each other via an insulating layer 83, and a capacitor 50 connected in series with the transformer 40. The low-voltage circuit 20 and the high-voltage circuit 30 transmit signals via the transformer 40 and the capacitor 50.

[0087] In this configuration, both the transformer 40 and the capacitor 50 connected in series with the transformer 40 insulate the low-voltage circuit 20 from the high-voltage circuit 30. Therefore, even if dielectric breakdown occurs in the transformer 40 due to a short circuit between the first coil 41A (41B) and the second coil 42A (42B), the capacitor 50 can maintain insulation between the low-voltage circuit 20 and the high-voltage circuit 30. Thus, safety can be improved.

[0088] (1-2) Capacitor 50A has a first electrode 51A and a second electrode 52A. The first electrode 51A is electrically connected to transformer 40A, and the second electrode 52A is electrically connected to high-voltage circuit 30. Capacitor 50B has a first electrode 51B and a second electrode 52B. The first electrode 51B is electrically connected to transformer 40B, and the second electrode 52B is electrically connected to high-voltage circuit 30. With this configuration, even if dielectric breakdown occurs in transformer 40A due to a short circuit between the first coil 41A and the second coil 42A, capacitor 50A can provide insulation on the high-voltage circuit 30 side of transformer 40A, and even if dielectric breakdown occurs in transformer 40B due to a short circuit between the first coil 41B and the second coil 42B, capacitor 50B can provide insulation on the high-voltage circuit 30 side of transformer 40B. Therefore, it is possible to suppress the application of high voltages, such as the drain voltage of the switching element 501, to the low-voltage lead frame 90 due to the dielectric breakdown of transformers 40A and 40B.

[0089] (1-3) The gate driver 10 comprises a low-voltage circuit chip 60 including a low-voltage circuit 20, a high-voltage circuit chip 70 including a high-voltage circuit 30, and a transformer chip 80 including transformers 40A and 40B. With this configuration, since the transformer chip 80 is provided separately from the low-voltage circuit chip 60 and the high-voltage circuit chip 70, a common transformer chip 80 can be used for different low-voltage circuit chips 60 and high-voltage circuit chips 70. This reduces manufacturing costs when manufacturing multiple types of gate drivers in which at least one of the low-voltage circuit chip 60 and the high-voltage circuit chip 70 is different.

[0090] (1-4) Capacitors 50A and 50B are integrated into the high-voltage circuit chip 70. This configuration reduces the number of semiconductor chips in the gate driver 10 compared to when capacitors 50A and 50B are configured as separate chips. Therefore, the size of the gate driver 10 can be suppressed.

[0091] Furthermore, since the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101, even if dielectric breakdown occurs in the transformer 40 due to a short circuit between the first coil 41A (41B) and the second coil 42A (42B), the high voltage is unlikely to reach the low-voltage lead frame 90. This suppresses the application of high voltage to the low-voltage lead frame 90.

[0092] (1-5) Within the high-voltage circuit chip 70, capacitors 50A and 50B are positioned so as to overlap with the high-voltage circuit 30 in a plan view. This configuration makes it possible to suppress the increase in size of the high-voltage circuit chip 70.

[0093] (1-6) Capacitors 50A and 50B are located near the transformer chip 80 on the high-voltage circuit chip 70. This configuration allows for shorter conductive paths between transformer 40A and capacitor 50A, and between transformer 40B and capacitor 50B. Therefore, the inductance caused by the length of these conductive paths can be reduced.

[0094] (1-7) The transformer chip 80 is positioned between the low-voltage circuit chip 60 and the high-voltage circuit chip 70. With this configuration, when connecting adjacent chips 60, 70, and 80 in the arrangement direction (y-direction) with wire W, the wire W does not need to cross any particular chip when electrically connecting these chips 60, 70, and 80, thus simplifying the connection structure of the wire W.

[0095] (1-8) The dielectric strength of the capacitor 50 is set to be greater than or equal to the dielectric strength of the transformer 40. With this configuration, even if dielectric breakdown occurs in the transformer 40 due to a short circuit between the first coil 41A (41B) and the second coil 42A (42B), the insulation between the low-voltage circuit 20 and the high-voltage circuit 30 can be maintained without stopping the operation of the inverter device 500.

[0096] [Second Embodiment] The gate driver 10 of the second embodiment will be described with reference to Figures 4 and 5. The gate driver 10 of the second embodiment differs from the gate driver 10 of the first embodiment mainly in that the capacitor 50 is not incorporated into the high-voltage circuit chip 70, but is provided as a separate capacitor chip 120 as a semiconductor chip. In the following description, the differences from the gate driver 10 of the first embodiment will be mainly described, and components common to the gate driver 10 of the first embodiment will be given the same reference numerals and their descriptions will be omitted. Note that in Figure 4, the sealing resin 110 is shown with a dashed line for the purpose of explaining the internal structure of the gate driver 10.

[0097] As shown in Figure 4, the gate driver 10 comprises a low-voltage circuit chip 60, a high-voltage circuit chip 70, a transformer chip 80, and a capacitor chip 120. These chips 60, 70, 80, and 120 are sealed by a sealing resin 110. The low-voltage circuit chip 60, the high-voltage circuit chip 70, the transformer chip 80, and the capacitor chip 120 are arranged spaced apart from each other in the y-direction. These chips 60, 70, 80, and 120 can also be said to be arranged in the direction of the arrangement of the low-voltage die pad 91 and the high-voltage die pad 101.

[0098] In the second embodiment, the low-voltage circuit chip 60, transformer chip 80, capacitor chip 120, and high-voltage circuit chip 70 are arranged in the order from the low-voltage lead 92 to the high-voltage lead 102. In other words, in a plan view, the transformer chip 80 and capacitor chip 120 are located between the low-voltage circuit chip 60 and the high-voltage circuit chip 70. In a plan view, the transformer chip 80 is located between the low-voltage circuit chip 60 and the capacitor chip 120, and the capacitor chip 120 is located between the transformer chip 80 and the high-voltage circuit chip 70.

[0099] Both the low-voltage circuit chip 60 and the transformer chip 80 are mounted on the low-voltage die pad 91 of the low-voltage lead frame 90, as in the first embodiment. In the second embodiment, both the capacitor chip 120 and the high-voltage circuit chip 70 are mounted on the high-voltage die pad 101 of the high-voltage lead frame 100. To ensure space for mounting the capacitor chip 120, the y-direction length of the high-voltage die pad 101 in the second embodiment is longer than that of the high-voltage die pad 101 in the first embodiment. In one example, the y-direction length of the high-voltage die pad 101 is equal to the y-direction length of the low-voltage die pad 91.

[0100] In plan view, the capacitor chip 120 has a rectangular shape with a long side and a short side. In plan view, the capacitor chip 120 is mounted on the high-voltage die pad 101 such that the long side is aligned with the x-direction and the short side is aligned with the y-direction. As shown in Figure 5, the capacitor chip 120 has a main chip surface 120s and a back surface 120r that face opposite each other in the z-direction. The capacitor chip 120 is bonded to the high-voltage die pad 101 by a conductive bonding material SD.

[0101] As shown in Figure 4, the main surface 120s of the capacitor chip 120 has a plurality of first electrode pads 121 and a plurality of second electrode pads 122 formed thereon. The plurality of first electrode pads 121 are located near the transformer chip 80 on the main surface 120s. The plurality of first electrode pads 121 are arranged in the x direction. The plurality of second electrode pads 122 are located near the high-voltage circuit chip 70 on the main surface 120s. The plurality of second electrode pads 122 are arranged in the x direction.

[0102] As shown in Figure 5, the capacitor chip 120 includes both capacitors 50A and 50B (see Figure 1), and more specifically, both capacitors 50A and 50B are packaged together. The capacitor chip 120 has an insulating layer 123, and both electrodes 51A and 52A of capacitor 50A are embedded in the insulating layer 123 and are positioned opposite each other, spaced apart in the z direction, via the insulating layer 123. In the second embodiment, the first electrode 51A is positioned further away from the high-voltage die pad 101 than the second electrode 52A. In the second embodiment, the insulating layer 123 is made of a dielectric material. The insulating layer 123 is made of, for example, SiO2. The insulating layer 123 may be one layer or multiple layers. Although not shown, the arrangement of capacitor 50B within the capacitor chip 120 is the same as that of capacitor 50A.

[0103] Both capacitors 50A and 50B are electrically connected to a first electrode pad 121 and a second electrode pad 122 within the capacitor chip 120. In one example, as shown in Figure 5, the first electrode pad 121 is electrically connected to the first electrode 51A of capacitor 50A. The second electrode pad 122 is electrically connected to the second electrode 52A of capacitor 50A.

[0104] Although not shown in the diagram, another first electrode pad 121 is electrically connected to the first electrode 51B of the capacitor 50B. Another second electrode pad 122 is electrically connected to the second electrode 52B of the capacitor 50B. The arrangement of electrodes 51B and 52B is the same as that of electrodes 51A and 52A.

[0105] The capacitor chip 120 is electrically connected to both the transformer chip 80 and the high-voltage circuit chip 70 by wire W. Specifically, the second electrode pad 82 of the transformer chip 80 and the first electrode pad 121 of the capacitor chip 120 are connected by wire W, and the second electrode pad 122 of the capacitor chip 120 and the first electrode pad 71 of the high-voltage circuit chip 70 are connected by wire W. This electrically connects the transformer 40, the capacitor 50, and the high-voltage circuit 30.

[0106] According to the gate driver 10 of the second embodiment, in addition to the effects of (1-1), (1-2), and (1-8) of the first embodiment, the following effects can be obtained. (2-1) The gate driver 10 includes a low-voltage circuit chip 60 containing a low-voltage circuit 20, a high-voltage circuit chip 70 containing a high-voltage circuit 30, a transformer chip 80 containing a transformer 40, and a capacitor chip 120 containing a capacitor 50. The low-voltage circuit chip 60, the transformer chip 80, the capacitor chip 120, and the high-voltage circuit chip 70 are arranged in that order.

[0107] With this configuration, by connecting adjacent chips 60, 70, 80, and 120 in the arrangement direction (y-direction) with wire W, when electrically connecting these chips 60, 70, 80, and 120, the wire W does not need to cross over a predetermined chip, thus simplifying the connection structure of the wire W.

[0108] In addition, since a transformer chip 80 and a capacitor chip 120 are provided separately from the low-voltage circuit chip 60 and the high-voltage circuit chip 70, a common transformer chip 80 and a common capacitor chip 120 can be used for different low-voltage circuit chips 60 and high-voltage circuit chips 70. This reduces manufacturing costs when manufacturing multiple types of gate drivers in which at least one of the low-voltage circuit chip 60 and the high-voltage circuit chip 70 is different.

[0109] (2-2) The gate driver 10 comprises a low-voltage die pad 91 on which a low-voltage circuit chip 60 is mounted, and a high-voltage die pad 101 on which a high-voltage circuit chip 70 is mounted. The transformer chip 80 is mounted on the low-voltage die pad 91, and the capacitor chip 120 is mounted on the high-voltage die pad 101.

[0110] When forming the encapsulating resin 110, as the area of ​​each die pad 91, 101 in a plan view increases, voids are more likely to form in the vicinity of each die pad 91, 101 in the encapsulating resin 110. For this reason, if both the transformer chip 80 and the capacitor chip 120 are mounted on the low-pressure die pad 91, the area of ​​the low-pressure die pad 91 becomes excessively large, and there is a risk that voids will form in the vicinity of the low-pressure die pad 91.

[0111] In this regard, according to the gate driver 10 of the second embodiment, since the transformer chip 80 and the capacitor chip 120 are mounted on the low-pressure die pad 91 and the high-pressure die pad 101 respectively, it is possible to suppress the one of the low-pressure die pad 91 and the high-pressure die pad 101 from becoming excessively large. Therefore, it is possible to suppress the generation of voids in the sealing resin 110 caused by the area of ​​one of the die pads 91 and 101 becoming excessively large.

[0112] [Third Embodiment] The gate driver 10 of the third embodiment will be described with reference to Figures 6 and 7. The gate driver 10 of the third embodiment differs from the gate driver 10 of the first embodiment mainly in the location where the capacitor 50 is provided. In the following description, the differences from the first embodiment will be mainly described, and components common to the gate driver 10 of the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0113] As shown in Figure 6, unlike in the first embodiment, capacitor 50 is circuit-wise located between the low-voltage circuit 20 and the transformer 40. More specifically, capacitor 50A is circuit-wise located between the low-voltage circuit 20 and the transformer 40A, and capacitor 50B is circuit-wise located between the low-voltage circuit 20 and the transformer 40B. In the third embodiment, transformer 40A and capacitor 50A are connected in series. Transformer 40B and capacitor 50B are connected in series.

[0114] In the third embodiment, the transformer 40A and the capacitor 50A are connected in series by the low-voltage signal line 21A, and the capacitor 50A is connected to the low-voltage circuit 20 by the low-voltage signal line 21A. Therefore, it can be said that the low-voltage circuit 20 and the transformer 40A are electrically connected via the capacitor 50A. Also, the transformer 40B and the capacitor 50B are connected in series by the low-voltage signal line 21B, and the capacitor 50B is connected to the low-voltage circuit 20 by the low-voltage signal line 21B. Therefore, it can be said that the low-voltage circuit 20 and the transformer 40B are electrically connected via the capacitor 50B. In the third embodiment, the capacitor 50A is not provided between the transformer 40A and the high-voltage circuit 30 in terms of the circuit, and the capacitor 50B is not provided between the transformer 40B and the high-voltage circuit 30 in terms of the circuit.

[0115] As shown in Figure 7, the gate driver 10 comprises a low-voltage circuit chip 60, a high-voltage circuit chip 70, and a transformer chip 80. The arrangement of these chips 60, 70, and 80, and the configuration of each lead frame 90, 100 are the same as in the first embodiment. As shown in Figure 7, the transformer chip 80 is mounted on the low-voltage die pad 91 of the low-voltage lead frame 90.

[0116] In the third embodiment, capacitors 50A and 50B (see Figure 6) are incorporated into a low-voltage circuit chip 60. Specifically, the low-voltage circuit chip 60 has an insulating layer 64, within which both capacitors 50A and 50B are embedded. The first electrode 51A and the second electrode 52A are positioned opposite each other and spaced apart in the z-direction via the insulating layer 64. In the third embodiment, capacitors 50A and 50B are positioned in the y-direction within the low-voltage circuit chip 60 in a portion close to the transformer chip 80. In the third embodiment, the insulating layer 64 is made of a dielectric material. The insulating layer 64 is made of, for example, SiO2.

[0117] In the third embodiment, the capacitor 50 is positioned closer to the main surface 60s of the low-voltage circuit chip 60 than to the low-voltage circuit 20. More specifically, as shown in Figure 7, both electrodes 51A and 52A of the capacitor 50A are positioned closer to the main surface 60s of the low-voltage circuit chip 60 than to the low-voltage circuit 20. In a plan view, the capacitors 50A and 50B are positioned in a location that overlaps with the low-voltage circuit 20 within the low-voltage circuit chip 60. The positioning of the capacitors 50A and 50B within the low-voltage circuit chip 60 can be arbitrarily changed.

[0118] Capacitor 50 is electrically connected to both the low-voltage circuit 20 and the second electrode pad 62 of the low-voltage circuit chip 60 within the low-voltage circuit chip 60. More specifically, as shown in Figure 7, the first electrode 51A of capacitor 50A is electrically connected to the low-voltage circuit 20 within the low-voltage circuit chip 60. The second electrode 52A of capacitor 50A is electrically connected to the second electrode pad 62 within the low-voltage circuit chip 60.

[0119] Although not shown in the diagram, capacitor 50B has the same configuration as capacitor 50A. Both electrodes 51B and 52B of capacitor 50B are also positioned closer to the main surface 60s of the low-voltage circuit chip 60 than the low-voltage circuit 20, and are electrically connected to both the low-voltage circuit 20 and the second electrode pad 62 of the low-voltage circuit chip 60.

[0120] Similar to the first embodiment, the second electrode pad 62 is connected to the first electrode pad 81 of the transformer chip 80 by a wire W. More specifically, the second electrode pad 62, which is electrically connected to the second electrode 52A of the capacitor 50A, and the first electrode pad 81, which is electrically connected to the first coil 41A of the transformer 40A, are connected by a wire W. Although not shown, the second electrode pad 62, which is electrically connected to the second electrode 52B of the capacitor 50B, and the first electrode pad 81, which is electrically connected to the first coil 41B of the transformer 40B, are also connected by a wire W.

[0121] According to the gate driver 10 of the third embodiment, in addition to the effects of (1-1), (1-3), (1-7), and (1-8) of the first embodiment, the following effects can be obtained. (3-1) The first electrode 51A of capacitor 50A is electrically connected to the low-voltage circuit 20, and the second electrode 52A of capacitor 50A is electrically connected to transformer 40A. The first electrode 51B of capacitor 50B is electrically connected to the low-voltage circuit 20, and the second electrode 52B of capacitor 50B is electrically connected to transformer 40B. With this configuration, even if dielectric breakdown occurs in transformer 40A due to a short circuit between the first coil 41A and the second coil 42A, capacitor 50A can maintain insulation between the low-voltage circuit 20 and the high-voltage circuit 30. Similarly, even if dielectric breakdown occurs in transformer 40B due to a short circuit between the first coil 41B and the second coil 42B, capacitor 50B can maintain insulation between the low-voltage circuit 20 and the high-voltage circuit 30. Therefore, the application of high voltage to the low-voltage circuit 20 due to the dielectric breakdown of transformers 40A and 40B is suppressed, and thus the application of high voltage to the low-voltage lead frame 90 can be suppressed.

[0122] (3-2) Capacitors 50A and 50B are incorporated into the low-voltage circuit chip 60. This configuration allows for a reduction in the number of semiconductor chips within the gate driver 10 compared to the case where capacitors 50A and 50B are configured as separate chips. Therefore, the size of the gate driver 10 can be suppressed.

[0123] (3-3) Within the low-voltage circuit chip 60, capacitors 50A and 50B are positioned so as to overlap with the low-voltage circuit 20 in a plan view. This configuration makes it possible to suppress the increase in size of the low-voltage circuit chip 60.

[0124] (3-4) Capacitors 50A and 50B are located near the transformer chip 80 on the low-voltage circuit chip 60. This configuration allows for shorter conductive paths between capacitor 50A and transformer 40A, and between capacitor 50B and transformer 40B. Therefore, the inductance caused by the length of these conductive paths can be reduced.

[0125] [Fourth Embodiment] The gate driver 10 of the fourth embodiment will be described with reference to Figures 8 and 9. The gate driver 10 of the fourth embodiment differs from the gate driver 10 of the third embodiment mainly in that the capacitor 50 is not incorporated into the low-voltage circuit chip 60, but is provided as a separate capacitor chip 120 as a semiconductor chip. In the following description, the differences from the gate driver 10 of the third embodiment will be mainly described, and components common to the gate driver 10 of the third embodiment will be given the same reference numerals and their descriptions will be omitted. Note that in Figure 8, the sealing resin 110 is shown with a dashed line for the purpose of explaining the internal structure of the gate driver 10.

[0126] As shown in Figure 8, the gate driver 10 comprises a low-voltage circuit chip 60, a high-voltage circuit chip 70, a transformer chip 80, and a capacitor chip 120. These chips 60, 70, 80, and 120 are sealed by a sealing resin 110. The low-voltage circuit chip 60, the high-voltage circuit chip 70, the transformer chip 80, and the capacitor chip 120 are arranged spaced apart from each other in the y-direction. These chips 60, 70, 80, and 120 can also be said to be arranged in the direction of the arrangement of the low-voltage die pad 91 and the high-voltage die pad 101.

[0127] In the fourth embodiment, the low-voltage circuit chip 60, capacitor chip 120, transformer chip 80, and high-voltage circuit chip 70 are arranged in that order from the low-voltage lead 92 to the high-voltage lead 102. In other words, in a plan view, the capacitor chip 120 and transformer chip 80 are located between the low-voltage circuit chip 60 and the high-voltage circuit chip 70, and the capacitor chip 120 is located between the low-voltage circuit chip 60 and the transformer chip 80.

[0128] In the fourth embodiment, the low-voltage circuit chip 60, capacitor chip 120, and transformer chip 80 are mounted on the low-voltage die pad 91 of the low-voltage lead frame 90. The capacitor chip 120 is bonded to the low-voltage die pad 91 by a conductive bonding material SD (see Figure 9). The shape and orientation of the capacitor chip 120 in plan view are the same as in the second embodiment. In order to secure space for mounting the capacitor chip 120, the length of the low-voltage die pad 91 in the y-direction in the fourth embodiment is longer than the length of the low-voltage die pad 91 in the y-direction in the third embodiment. In the transformer chip 80, the first coil 41A is sufficiently far from the low-voltage die pad 91 to maintain insulation between the transformer chip 80 and the low-voltage die pad 91.

[0129] The high-voltage die pad 101 of the high-voltage lead frame 100 is equipped only with a high-voltage circuit chip 70. The high-voltage die pad 101 of the fourth embodiment is the same as the high-voltage die pad 101 of the first embodiment.

[0130] The capacitor chip 120 is electrically connected to both the low-voltage circuit chip 60 and the transformer chip 80 by wire W. Specifically, the first electrode pad 121 of the capacitor chip 120 is connected to the second electrode pad 62 of the low-voltage circuit chip 60 by wire W. The second electrode pad 122 of the capacitor chip 120 is connected to the first electrode pad 81 of the transformer chip 80 by wire W.

[0131] As shown in Figure 9, the first electrode pad 121 to which the first electrode 51A of capacitor 50A is electrically connected and the second electrode pad 62 to which the low-voltage circuit 20 is electrically connected are connected by wire W, so the first electrode 51A of capacitor 50A and the low-voltage circuit 20 are electrically connected. The second electrode pad 122 to which the second electrode 52A of capacitor 50A is electrically connected and the second electrode pad 62 to which the first coil 41A of transformer 40A is electrically connected are connected by wire W, so the second electrode 52A of capacitor 50A and the first coil 41A of transformer 40A are electrically connected.

[0132] Although not shown in the diagram, similar to capacitor 50A, the first electrode 51B of capacitor 50B is electrically connected to the low-voltage circuit 20, and the second electrode 52B of capacitor 50B is electrically connected to the first coil 41B of transformer 40B.

[0133] According to the gate driver 10 of the fourth embodiment, in addition to the effects of (3-1) of the third embodiment, the following effects can be obtained. (4-1) The gate driver 10 includes a low-voltage circuit chip 60 including a low-voltage circuit 20, a high-voltage circuit chip 70 including a high-voltage circuit 30, a transformer chip 80 including a transformer 40, and a capacitor chip 120 including a capacitor 50. The low-voltage circuit chip 60, capacitor chip 120, transformer chip 80, and high-voltage circuit chip 70 are arranged in that order. With this configuration, the same effects as in (2-1) of the second embodiment can be obtained.

[0134] [Fifth Embodiment] The gate driver 10 of the fifth embodiment will be described with reference to Figures 10 and 11. The gate driver 10 of the fifth embodiment differs from the gate driver 10 of the first embodiment in that it has a double insulation structure using multiple transformers. In the following description, the differences from the first embodiment will be described, and components common to the gate driver 10 of the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0135] As shown in Figure 10, transformer 40A of transformer 40 has a first transformer 43A and a second transformer 44A connected in series with each other. Transformer 40B has a first transformer 43B and a second transformer 44B connected in series with each other. Thus, since each of transformers 40A and 40B has a double insulation structure, the dielectric strength of the gate driver 10 is higher than in the first to fourth embodiments, for example, to about 5000 Vrms.

[0136] The first transformer 43A is electrically connected to the low-voltage circuit 20. The first transformer 43A includes a first coil 45A and a second coil 46A that is insulated from the first coil 45A and is magnetically coupled to it.

[0137] The second transformer 44A is electrically connected to the high-voltage circuit 30. It can also be said that the second transformer 44A is located on the signal line connecting the first transformer 43A and the high-voltage circuit 30. The second transformer 44A has a first coil 47A and a second coil 48A that is insulated from the first coil 47A and is magnetically coupled to it.

[0138] The first coil 45A is electrically connected to the low-voltage circuit 20 by the low-voltage signal line 21A, while also being connected to the ground of the low-voltage circuit 20. In other words, the first end of the first coil 45A is electrically connected to the low-voltage circuit 20, and the second end of the first coil 45A is electrically connected to the ground of the low-voltage circuit 20. Therefore, the potential at the second end of the first coil 45A becomes the first reference potential. The first reference potential is, for example, 0V.

[0139] The second coil 46A is connected to the first coil 47A of the second transformer 44A. In one example, the second coil 46A and the first coil 47A are connected to each other in an electrically floating state. That is, the first end of the second coil 46A is connected to the first end of the first coil 47A, and the second end of the second coil 46A is connected to the second end of the first coil 47A. In this way, the second coil 46A and the first coil 47A act as relay coils that relay the transmission of the set signal from the first coil 45A to the second coil 48A.

[0140] The second coil 48A is electrically connected to the high-voltage circuit 30 via a capacitor 50A through a high-voltage signal line 31A, while also being connected to the ground of the high-voltage circuit 30. In other words, the first end of the second coil 48A is electrically connected to the high-voltage circuit 30 via capacitor 50A, and the second end of the second coil 48A is electrically connected to the ground of the high-voltage circuit 30. Therefore, the potential at the second end of the second coil 48A becomes the second reference potential. The second reference potential fluctuates with the driving of the inverter device 500, and is, for example, 600V or higher.

[0141] Similar to the first embodiment, the capacitor 50A is provided on the high-voltage signal line 31A. The capacitor 50A is provided between the second transformer 44A and the high-voltage circuit 30. In other words, the capacitor 50A is provided on the high-voltage signal line 31A that connects the second transformer 44A and the high-voltage circuit 30. The capacitor 50A is connected in series with the second transformer 44A. The first electrode 51A of the capacitor 50A is electrically connected to the second coil 48A, and the second electrode 52A of the capacitor 50A is electrically connected to the high-voltage circuit 30.

[0142] The first transformer 43B of transformer 40B has a first coil 45B electrically connected to the low-voltage circuit 20, and a second coil 46B that is insulated from the first coil 45B and can be magnetically coupled.

[0143] The second transformer 44B of transformer 40B has a first coil 47B electrically connected to the high-voltage circuit 30, and a second coil 48B that is insulated from the first coil 47B and magnetically coupled. Since transformer 40B and capacitor 50B are the same as transformer 40A and capacitor 50A, a detailed explanation is omitted.

[0144] As shown in Figure 11, the gate driver 10 comprises a low-voltage circuit chip 60, a high-voltage circuit chip 70, a first transformer chip 80A, and a second transformer chip 80B. The low-voltage circuit chip 60, the high-voltage circuit chip 70, the first transformer chip 80A, and the second transformer chip 80B are arranged spaced apart from each other in the y-direction. These chips 60, 70, 80A, and 80B can also be said to be arranged in the direction of the arrangement of the low-voltage die pad 91 and the high-voltage die pad 101.

[0145] In the fifth embodiment, the low-voltage circuit chip 60, the first transformer chip 80A, the second transformer chip 80B, and the high-voltage circuit chip 70 are arranged in that order from the low-voltage lead 92 to the high-voltage lead 102 (see Figure 2). In other words, in a plan view, each transformer chip 80A, 80B is positioned between the low-voltage circuit chip 60 and the high-voltage circuit chip 70.

[0146] In the fifth embodiment, both the low-voltage circuit chip 60 and the first transformer chip 80A are mounted on the low-voltage die pad 91 of the low-voltage lead frame 90. Both the high-voltage circuit chip 70 and the second transformer chip 80B are mounted on the high-voltage die pad 101 of the high-voltage lead frame 100.

[0147] The first transformer chip 80A includes the first transformer 43A of transformer 40A and the first transformer 43B of transformer 40B (see Figure 10), and more specifically, both transformers 43A and 43B are packaged together. In other words, the first transformer chip 80A includes the transformers 40A and 40B, which are circuit-wise positioned closer to the low-voltage circuit 20 than to the high-voltage circuit 30.

[0148] As shown in Figure 11, the first transformer chip 80A has an insulating layer 83, similar to the transformer chip 80 of the first embodiment. Both coils 45A and 46A of the first transformer 43A are embedded in the insulating layer 83 and are positioned opposite each other, spaced apart in the z direction, via the insulating layer 83. The insulating layer 83 may be one layer or multiple layers.

[0149] Both coils 45A and 46A consist of a conductor layer embedded in the insulating layer 83. In the fifth embodiment, the second coil 46A is positioned away from the low-voltage die pad 91 relative to the first coil 45A. The first coil 45A is electrically connected to the first electrode pad 81A, and the second coil 46A is electrically connected to the second electrode pad 82A. Although not shown in the figures, the arrangement configuration of the first transformer 43B within the first transformer chip 80A is the same as that of the first transformer 43A.

[0150] The second transformer chip 80B includes the second transformer 44A of transformer 40A and the second transformer 44B of transformer 40B (see Figure 10), and more specifically, both transformers 44A and 44B are packaged together. In other words, the second transformer chip 80B includes the transformers 40A and 40B that are circuit-wise positioned closer to the high-voltage circuit 30 than to the low-voltage circuit 20.

[0151] As shown in Figure 11, the second transformer chip 80B has an insulating layer 83, similar to the transformer chip 80 of the first embodiment. Both coils 47A and 48A of the second transformer 44A are embedded in the insulating layer 83 and are positioned opposite each other, spaced apart in the z direction, via the insulating layer 83. The insulating layer 83 may be one layer or multiple layers.

[0152] Both coils 47A and 48A consist of a conductor layer embedded in the insulating layer 83. In the fifth embodiment, the first coil 47A is positioned away from the high-voltage die pad 101 relative to the second coil 48A. The first coil 47A is electrically connected to the first electrode pad 81B, and the second coil 48A is electrically connected to the second electrode pad 82B. Although not shown in the figures, the arrangement configuration of the second transformer 44B within the second transformer chip 80B is the same as that of the second transformer 44A.

[0153] The low-voltage circuit chip 60 and the first transformer chip 80A are connected by a wire W. More specifically, the second electrode pad 62 of the low-voltage circuit chip 60 and the first electrode pad 81A of the first transformer chip 80A are connected by a wire W. As a result, the low-voltage circuit 20 and the first coil 45A of the first transformer 43A are electrically connected, and the low-voltage circuit 20 and the first coil 45B of the first transformer 43B are electrically connected.

[0154] The first transformer chip 80A and the second transformer chip 80B are connected by a wire W. More specifically, the second electrode pad 82A of the first transformer chip 80A and the first electrode pad 81B of the second transformer chip 80B are connected by a wire W. As a result, the second coil 46A of the first transformer 43A and the first coil 47A of the second transformer 44A are electrically connected, and the second coil 46B of the first transformer 43B and the first coil 47B of the second transformer 44B (see Figure 10) are electrically connected.

[0155] The second transformer chip 80B and the high-voltage circuit chip 70 are connected by wire W. More specifically, the second electrode pad 82B of the second transformer chip 80B and the first electrode pad 71 of the high-voltage circuit chip 70 are connected by wire W. As a result, the second coil 48A of the second transformer 44A and the first electrode 51A of the capacitor 50A are electrically connected, and the second coil 48B of the second transformer 44B and the first electrode 51B of the capacitor 50B (see Figure 10) are electrically connected.

[0156] According to the gate driver 10 of the fifth embodiment, in addition to the effects (1-1) to (1-8) of the first embodiment, the following effects can be obtained. (5-1) Transformer 40A has a first transformer 43A and a second transformer 44A connected in series with each other. Transformer 40B has a first transformer 43B and a second transformer 44B connected in series with each other. With this configuration, the signal line transmitting the set signal has a double insulation structure between the low-voltage circuit 20 and the high-voltage circuit 30 due to the first transformer 43A and the second transformer 44A, and the signal line transmitting the reset signal has a double insulation structure between the low-voltage circuit 20 and the high-voltage circuit 30 due to the first transformer 43B and the second transformer 44B, thereby improving the dielectric strength of the gate driver 10.

[0157] [Sixth Embodiment] The gate driver 10 of the sixth embodiment will be described with reference to Figures 12 and 13. The gate driver 10 of the sixth embodiment differs from the gate driver 10 of the second embodiment mainly in that the gate driver 10 is composed of multiple packages. In the following description, the differences from the second embodiment will be described, and components common to the gate driver 10 of the second embodiment will be denoted by the same reference numerals, and their descriptions will be omitted.

[0158] As shown in Figure 12, the circuit configuration of the gate driver 10 in the sixth embodiment is the same as the circuit configuration of the gate driver 10 in the first embodiment. The gate driver 10 includes a low-voltage circuit module 200, a high-voltage circuit module 210, and an isolation module 220.

[0159] The low-voltage circuit module 200 includes a low-voltage circuit 20. In one example, although not shown, the low-voltage circuit module 200 includes a low-voltage circuit chip including the low-voltage circuit 20, a low-voltage lead frame including a low-voltage die pad on which the low-voltage circuit chip is mounted, and a sealing resin that seals a portion of the low-voltage lead frame and the low-voltage circuit chip.

[0160] The high-voltage circuit module 210 includes a high-voltage circuit 30. In one example, although not shown, the high-voltage circuit module 210 includes a high-voltage circuit chip including the high-voltage circuit 30, a high-voltage lead frame including a high-voltage die pad on which the high-voltage circuit chip is mounted, and a sealing resin that seals a portion of the high-voltage lead frame and the high-voltage circuit chip.

[0161] The isolation module 220 enables the transmission of set and reset signals from the low-voltage circuit 20 to the high-voltage circuit 30, while insulating the low-voltage circuit 20 from the high-voltage circuit 30. In other words, the isolation module 220 is used to isolate the low-voltage circuit 20 and the high-voltage circuit 30 included in the gate driver 10. The isolation module 220 includes a transformer 40 and a capacitor 50. The transformer 40 and capacitor 50 are used to transmit signals (set and reset signals) between the low-voltage circuit 20 and the high-voltage circuit 30, as in the first embodiment. As shown in Figure 12, the isolation module 220 is circuit-wise positioned between the low-voltage circuit 20 and the high-voltage circuit 30. Therefore, the low-voltage circuit 20 and the high-voltage circuit 30 are connected via the transformer 40 and capacitor 50.

[0162] Figure 13 shows an example of a schematic cross-sectional structure of the isolation module 220. As shown in Figure 13, the isolation module 220 comprises a transformer chip 80, a capacitor chip 120, a low-voltage lead frame 221, a high-voltage lead frame 222, and a sealing resin 223 that seals the transformer chip 80, the capacitor chip 120, and a portion of each lead frame 221, 222.

[0163] Each lead frame 221, 222 is made of a conductor, and in the sixth embodiment, it is made of Cu. Each lead frame 221, 222 is provided spanning both the inside and outside of the sealing resin 223. The low-voltage lead frame 221 is a lead frame electrically connected to the low-voltage circuit 20 (see Figure 12), and has a low-voltage die pad 221a located within the sealing resin 223, and a plurality of low-voltage leads 221b located both inside and outside the sealing resin 223. Each low-voltage lead 221b constitutes an external terminal electrically connected to the low-voltage circuit 20.

[0164] The high-voltage lead frame 222 is a lead frame electrically connected to the high-voltage circuit 30 (see Figure 12), and has a high-voltage die pad 222a located within the sealing resin 223, and a plurality of high-voltage leads 222b located both inside and outside the sealing resin 223. Each high-voltage lead 222b constitutes an external terminal electrically connected to the high-voltage circuit 30.

[0165] In the sixth embodiment, the transformer chip 80 is mounted on the low-voltage die pad 221a, and the capacitor chip 120 is mounted on the high-voltage die pad 222a. In the sixth embodiment, the low-voltage die pad 221a corresponds to the first die pad, and the high-voltage die pad 222a corresponds to the second die pad. Also, the low-voltage lead 221b corresponds to the first lead, and the high-voltage lead 222b corresponds to the second lead.

[0166] In the sixth embodiment, the transformer chip 80 and the capacitor chip 120 are arranged in the order of low-voltage lead 221b to high-voltage lead 222b. In the gate driver 10, the first coils 41A and 41B of transformers 40A and 40B (see Figure 12) are electrically connected to the low-voltage circuit 20, while also being connected to the ground of the low-voltage circuit 20. In other words, the first ends of the first coils 41A and 41B are electrically connected to the low-voltage circuit 20, and the second ends of the first coils 41A and 41B are connected to the ground of the low-voltage circuit 20.

[0167] The first electrode pad 81 of the transformer tip 80 and the low-voltage lead 221b are connected by a wire W. This electrically connects the first coil 41A of the transformer 40A to the low-voltage lead 221b. Although not shown, the first coil 41B of the transformer 40B is electrically connected to another low-voltage lead 221b. Also not shown, the first coils 41A and 41B of transformers 40A and 40B are connected by a wire W to the low-voltage lead 221b which is integrated with the low-voltage die pad 221a.

[0168] In the gate driver 10, the second coils 42A and 42B of transformers 40A and 40B (see Figure 12) are electrically connected to capacitors 50A and 50B, while also being connected to the ground of the high-voltage circuit 30. In other words, the first ends of the second coils 42A and 42B are electrically connected to capacitors 50A and 50B, and the second ends of the second coils 42A and 42B are connected to the ground of the high-voltage circuit 30.

[0169] The second electrode pad 82 of the transformer chip 80 and the first electrode pad 121 of the capacitor chip 120 are connected by wire W. This electrically connects the second coil 42A of the transformer 40A and the first electrode 51A of the capacitor 50A (see Figure 12). Although not shown, the second coil 42B of the transformer 40B and the first electrode 51B of the capacitor 50B (see Figure 12) are also electrically connected. Although not shown, the second coils 42A and 42B of the transformers 40A and 40B are electrically connected by wire W to the high-voltage lead 222b, which is integrated with the high-voltage die pad 222a.

[0170] According to the sixth embodiment, in addition to the effects of (1-1), (1-2), and (1-8) of the first embodiment, the following effects can be obtained. (6-1) The transformer 40 and capacitor 50 are contained in an isolation module 220, which is a semiconductor module separate from the low-voltage circuit module 200 and the high-voltage circuit module 210.

[0171] This configuration allows a common isolation module 220 to be used for different low-voltage circuit modules 200 and high-voltage circuit modules 210. This reduces manufacturing costs when producing multiple types of gate drivers, at least one of which is different from the other.

[0172] [Seventh Embodiment] The gate driver 10 of the seventh embodiment will be described with reference to Figures 14 and 15. The gate driver 10 of the seventh embodiment differs from the gate driver 10 of the second embodiment mainly in that the gate driver 10 is composed of multiple packages. In the following description, the differences from the second embodiment will be described, and components common to the gate driver 10 of the second embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0173] As shown in Figure 14, the circuit configuration of the gate driver 10 in the seventh embodiment is the same as the circuit configuration of the gate driver 10 in the first embodiment. The gate driver 10 comprises a low-voltage circuit unit 300 and a high-voltage circuit module 310. The high-voltage circuit module 310 has the same configuration as the high-voltage circuit module 210 in the sixth embodiment (see Figure 12).

[0174] The low-voltage circuit unit 300 includes a low-voltage circuit 20, a transformer 40, and a capacitor 50. The low-voltage circuit unit 300 enables the transmission of set signals and reset signals from the low-voltage circuit 20 to the high-voltage circuit 30, while isolating the low-voltage circuit 20 from the high-voltage circuit 30.

[0175] Figure 15 shows an example of a schematic cross-sectional structure of the low-voltage circuit unit 300. As shown in Figure 15, the low-voltage circuit unit 300 comprises a low-voltage circuit chip 60 including the low-voltage circuit 20, a transformer chip 80, a capacitor chip 120, a low-voltage lead frame 301, a high-voltage lead frame 302, and a sealing resin 320 that seals parts of each chip 60, 80, 120 and each lead frame 301, 302. Therefore, it can also be said that the low-voltage circuit unit 300 comprises an insulating module including the transformer 40 and the capacitor 50. In other words, it can also be said that the low-voltage circuit unit 300 comprises an insulating module and the low-voltage circuit 20 (see Figure 14). This insulating module can also be said to comprise the transformer chip 80 and the capacitor chip 120.

[0176] Each lead frame 301, 302 is made of a conductor, and in the seventh embodiment, it is made of Cu. Each lead frame 301, 302 is provided spanning both the inside and outside of the sealing resin 320. The low-voltage lead frame 301 is a lead frame electrically connected to the low-voltage circuit 20, and includes a low-voltage die pad 301a located within the sealing resin 320, and a plurality of low-voltage leads 301b located both inside and outside the sealing resin 320. Each low-voltage lead 301b constitutes an external terminal electrically connected to the low-voltage circuit 20.

[0177] The high-voltage lead frame 302 is a lead frame electrically connected to the high-voltage circuit 30 (see Figure 14), and has a plurality of high-voltage leads 302a arranged across the inside and outside of the sealing resin 320. Each high-voltage lead 302a constitutes an external terminal electrically connected to the high-voltage circuit 30.

[0178] In the seventh embodiment, the low-voltage circuit chip 60, the transformer chip 80, and the capacitor chip 120 are mounted on the low-voltage die pad 301a. The low-voltage circuit chip 60, the transformer chip 80, and the capacitor chip 120 are spaced apart from each other in the y-direction. In the seventh embodiment, the low-voltage circuit chip 60, the transformer chip 80, and the capacitor chip 120 are arranged in that order from the low-voltage lead 301b toward the high-voltage lead 302a. In the case of the capacitor chip 120, the second electrode 52A is sufficiently far from the low-voltage die pad 301a to maintain insulation between the capacitor chip 120 and the low-voltage die pad 301a.

[0179] The connection configuration of the low-voltage circuit chip 60, transformer chip 80, and capacitor chip 120 by wire W is the same as in the second embodiment. The second electrode pad 122 of the capacitor chip 120 is connected to a plurality of high-voltage leads 302a by wire W. According to the seventh embodiment, the effects of (1-1), (1-2), and (1-8) of the first embodiment are obtained.

[0180] [Eighth Embodiment] The gate driver 10 of the eighth embodiment will be described with reference to Figures 16 and 17. The gate driver 10 of the eighth embodiment differs from the gate driver 10 of the second embodiment mainly in that the gate driver 10 is composed of multiple packages. In the following description, the differences from the second embodiment will be described, and components common to the gate driver 10 of the second embodiment will be denoted by the same reference numerals, and their descriptions will be omitted.

[0181] As shown in Figure 16, the circuit configuration of the gate driver 10 in the eighth embodiment is the same as the circuit configuration of the gate driver 10 in the first embodiment. The gate driver 10 comprises a low-voltage circuit module 400 and a high-voltage circuit unit 410. The low-voltage circuit module 400 has the same configuration as the low-voltage circuit module 200 in the sixth embodiment (see Figure 12).

[0182] The high-voltage circuit unit 410 includes a high-voltage circuit 30, a transformer 40, and a capacitor 50. The high-voltage circuit unit 410 allows the high-voltage circuit 30 to receive set signals and reset signals from the low-voltage circuit 20, while isolating the low-voltage circuit 20 from the high-voltage circuit 30.

[0183] Figure 17 shows an example of a schematic cross-sectional structure of the high-voltage circuit unit 410. As shown in Figure 17, the high-voltage circuit unit 410 comprises a high-voltage circuit chip 70, a transformer chip 80, a capacitor chip 120, a low-voltage lead frame 411, a high-voltage lead frame 412, and a sealing resin 420 that seals parts of each lead frame 411, 412 and each chip 70, 80, 120. Therefore, it can also be said that the high-voltage circuit unit 410 comprises an insulating module including the transformer 40 and the capacitor 50. In other words, it can also be said that the high-voltage circuit unit 410 comprises an insulating module and a high-voltage circuit 30 (see Figure 16). This insulating module can also be said to comprise the transformer chip 80 and the capacitor chip 120.

[0184] Each lead frame 411, 412 is made of a conductor, and in the eighth embodiment, it is made of Cu. Each lead frame 411, 412 is provided spanning both the inside and outside of the sealing resin 420. The low-voltage lead frame 411 is a lead frame electrically connected to the low-voltage circuit 20 (see Figure 16), and has a plurality of low-voltage leads 411a arranged across the inside and outside of the sealing resin 420. Each low-voltage lead 411a constitutes an external terminal electrically connected to the low-voltage circuit 20.

[0185] The high-voltage lead frame 412 is a lead frame electrically connected to the high-voltage circuit 30, and has a high-voltage die pad 412a located within the sealing resin 420, and a plurality of high-voltage leads 412b arranged across the inside and outside of the sealing resin 420. Each high-voltage lead 412b constitutes an external terminal electrically connected to the high-voltage circuit 30.

[0186] In the eighth embodiment, a high-voltage circuit chip 70, a transformer chip 80, and a capacitor chip 120 are mounted on a high-voltage die pad 412a. The high-voltage circuit chip 70, the transformer chip 80, and the capacitor chip 120 are spaced apart from each other in the y-direction. In the eighth embodiment, the transformer chip 80, the capacitor chip 120, and the high-voltage circuit chip 70 are arranged in that order from the low-voltage lead 411a to the high-voltage lead 412b. Here, in the transformer chip 80, the first coil 41A is sufficiently far from the high-voltage die pad 412a so that insulation between the transformer chip 80 and the high-voltage die pad 412a can be maintained even if the second reference potential of the high-voltage die pad 412a fluctuates and becomes high.

[0187] The connection configuration of the high-voltage circuit chip 70, transformer chip 80, and capacitor chip 120 by wire W is the same as in the second embodiment. The first electrode pad 81 of the transformer chip 80 is connected to a plurality of low-voltage leads 411a by wire W. According to the eighth embodiment, the effects of (1-1), (1-2), and (1-8) of the first embodiment are obtained.

[0188] [Example of changes] The embodiments described above are illustrative of possible forms of the gate driver, isolation module, low-voltage circuit unit, and high-voltage circuit unit relating to this disclosure, and are not intended to limit their forms. The gate driver, isolation module, low-voltage circuit unit, and high-voltage circuit unit relating to this disclosure may take forms different from those illustrated in the embodiments described above. One example of such forms is a form in which some of the configurations of the embodiments described above are replaced, modified, or omitted, or a form in which new configurations are added to the embodiments described above. Furthermore, the following modifications can be combined with each other as long as they do not conflict with technical standards. In the following modifications, parts common to the embodiments described above are denoted by the same reference numerals as in the embodiments described above, and their descriptions are omitted.

[0189] In the first and second embodiments, a transformer chip 80 was provided separately from the low-voltage circuit chip 60 and the high-voltage circuit chip 70, but this is not limited to this. In one example, the transformer 40 may be incorporated into the low-voltage circuit chip 60.

[0190] When the transformer 40 is incorporated into the low-voltage circuit chip 60, the transformer 40 is positioned, for example, in the y-direction, near the high-voltage circuit chip 70 within the low-voltage circuit chip 60. In a plan view, the transformer 40 is positioned in a location that overlaps with the low-voltage circuit 20. In this case, the transformer 40 is positioned closer to the chip main surface 60s of the low-voltage circuit chip 60 than to the low-voltage circuit 20.

[0191] This configuration allows for a reduction in the number of semiconductor chips in the gate driver 10, thereby reducing the space required for semiconductor chip placement in the semiconductor chip arrangement direction (y-direction). This reduces the size of the encapsulating resin 110 in the y-direction. Consequently, the gate driver 10 can be miniaturized.

[0192] Similarly, in the third and fourth embodiments, the transformer 40 may be incorporated into the high-voltage circuit chip 70 instead of the transformer chip 80. The structure in which the transformer 40 is incorporated into the high-voltage circuit chip 70 is the same as the structure in which the transformer 40 is incorporated into the low-voltage circuit chip 60.

[0193] In the second embodiment, as shown in Figure 18, the capacitor chip 120 may be mounted on the low-voltage die pad 91. That is, both the transformer chip 80 and the capacitor chip 120 may be mounted on the low-voltage die pad 91. In this case, the second electrode 52A of the capacitor chip 120 is sufficiently far from the low-voltage die pad 91 to maintain insulation between the capacitor chip 120 and the low-voltage die pad 91.

[0194] In the second embodiment, as shown in Figure 19, the transformer chip 80 may be mounted on the high-voltage die pad 101. In other words, both the transformer chip 80 and the capacitor chip 120 may be mounted on the high-voltage die pad 101. In this case, the first coil 41A of the transformer chip 80 is sufficiently far from the high-voltage die pad 101, so that even if the second reference potential of the high-voltage die pad 101 fluctuates and becomes high, the insulation between the transformer chip 80 and the high-voltage die pad 101 can be maintained.

[0195] In the fourth embodiment, as shown in Figure 20, the transformer chip 80 may be mounted on the high-voltage die pad 101. That is, the capacitor chip 120 may be mounted on the low-voltage die pad 91, and the transformer chip 80 may be mounted on the high-voltage die pad 101.

[0196] In the fourth embodiment, both the capacitor chip 120 and the transformer chip 80 may be mounted on the high-voltage die pad 101. In this case, the second electrode 52A of the capacitor chip 120 is sufficiently far from the high-voltage die pad 101, so that even if the second reference potential of the high-voltage die pad 101 fluctuates and becomes high, insulation between the capacitor chip 120 and the high-voltage die pad 101 can be maintained.

[0197] In the fifth embodiment, both the first transformer chip 80A and the second transformer chip 80B may be mounted on the low-voltage die pad 91. Here, in the second transformer chip 80B, the second coil 48A is sufficiently far from the low-voltage die pad 91 to maintain insulation between the second transformer chip 80B and the low-voltage die pad 91.

[0198] In the fifth embodiment, both the first transformer chip 80A and the second transformer chip 80B may be mounted on the high-voltage die pad 101. In this case, the first transformer chip 80A is sufficiently far from the high-voltage die pad 101, so that even if the second reference potential of the high-voltage die pad 101 fluctuates and becomes high, the insulation between the first transformer chip 80A and the high-voltage die pad 101 can be maintained.

[0199] In the fifth embodiment, the first transformers 43A and 43B may be incorporated into the low-voltage circuit chip 60. In the fifth embodiment, the second transformers 44A and 44B may be incorporated into the high-voltage circuit chip 70.

[0200] The configuration of the transformer 40 in the fifth embodiment can be combined with the second to fourth embodiments and each of the modifications of the second to fourth embodiments. Furthermore, the configuration of the transformer 40 in the fifth embodiment can be combined with the sixth to eighth embodiments and each of the modifications of the sixth to eighth embodiments, which will be described later.

[0201] In the first example, in the fifth embodiment, the capacitor 50 is omitted from the high-voltage circuit chip 70, while the gate driver 10 may include a capacitor chip 120 that includes the capacitor 50. In this case, the low-voltage circuit chip 60, the first transformer chip 80A, the second transformer chip 80B, the capacitor chip 120, and the high-voltage circuit chip 70 may be arranged in that order from the low-voltage lead 92 to the high-voltage lead 102.

[0202] In the second example, in the fifth embodiment, the capacitor 50A may be provided circuit-wise between the low-voltage circuit 20 and the transformer 40. Specifically, the first electrode 51A of the capacitor 50A is electrically connected to the low-voltage circuit 20, and the second electrode 52A of the capacitor 50A is electrically connected to the first transformer 43A. The capacitor 50A is connected in series with the first transformer 43A. The same applies to the transformer 40B and the capacitor 50B as to the transformer 40A and the capacitor 50A.

[0203] In the second example described above, the capacitor 50 may be incorporated into the low-voltage circuit chip 60. In the second example described above, the first transformer chip 80A may be mounted on the low-voltage die pad 91, and the second transformer chip 80B may be mounted on the high-voltage die pad 101.

[0204] In the second example described above, both the first transformer chip 80A and the second transformer chip 80B may be mounted on either the low-voltage die pad 91 or the high-voltage die pad 101. When both the first transformer chip 80A and the second transformer chip 80B are mounted on the low-voltage die pad 91, the second coil 48A of the second transformer chip 80B is sufficiently far from the low-voltage die pad 91 to maintain insulation between the second transformer chip 80B and the low-voltage die pad 91. Furthermore, when both the first transformer chip 80A and the second transformer chip 80B are mounted on the high-voltage die pad 101, the first coil 45A of the first transformer chip 80A is sufficiently far from the high-voltage die pad 101 to maintain insulation between the first transformer chip 80A and the high-voltage die pad 101 even if the second reference potential of the high-voltage die pad 101 fluctuates and becomes high.

[0205] In the second example described above, the gate driver 10 may include a capacitor chip 120 containing a capacitor 50. In this case, the low-voltage circuit chip 60, capacitor chip 120, first transformer chip 80A, second transformer chip 80B, and high-voltage circuit chip 70 may be arranged in that order from the low-voltage lead 92 to the high-voltage lead 102.

[0206] In the sixth embodiment, instead of the transformer chip 80 and the capacitor chip 120 being mounted on separate die pads, the transformer chip 80 and the capacitor chip 120 may be mounted on a common die pad. In this case, the isolation module 220 includes a common die pad on which the transformer chip 80 and the capacitor chip 120 are mounted, a first lead electrically connected to the transformer 40, and a second lead electrically connected to the capacitor 50. The transformer 40 and the first lead are electrically connected by connecting the transformer chip 80 and the first lead with a wire, and the capacitor 50 and the second lead are electrically connected by connecting the capacitor chip 120 and the second lead with a wire.

[0207] In the sixth embodiment, if the capacitor 50 is circuit-wise provided between the low-voltage circuit 20 and the transformer 40, the transformer chip 80 may be mounted on the high-voltage die pad 222a and the capacitor chip 120 may be mounted on the low-voltage die pad 221a. In this case, the high-voltage die pad 222a corresponds to the first die pad and the low-voltage die pad 221a corresponds to the second die pad. Also, the high-voltage lead 222b corresponds to the first lead and the low-voltage lead 221b corresponds to the second lead.

[0208] In the seventh embodiment, the configuration and arrangement of the chips 60, 80, and 120 from the first to fifth embodiments may be applied to the low-voltage circuit unit 300. In one example, the high-voltage lead frame 302 may have a high-voltage die pad. In this case, the low-voltage circuit chip 60 and the transformer chip 80 may be mounted on the low-voltage die pad 301a, and the capacitor chip 120 may be mounted on the high-voltage die pad.

[0209] In the eighth embodiment, the configuration and arrangement of the chips 70, 80, and 120 from the first to fifth embodiments may be applied to the high-voltage circuit unit 410. For example, the low-voltage lead frame 411 may have a low-voltage die pad. In this case, the high-voltage circuit chip 70 and the capacitor chip 120 may be mounted on the high-voltage die pad 412a, and the transformer chip 80 may be mounted on the low-voltage die pad.

[0210] In the first to third embodiments, the transformer chip 80 may be mounted on the high-voltage die pad 101 of the high-voltage lead frame 100. In this case, the first coil 41A of the transformer chip 80 is sufficiently far from the high-voltage die pad 101 so that insulation between the transformer chip 80 and the high-voltage die pad 101 can be maintained even if the second reference potential of the high-voltage die pad 101 fluctuates and becomes high. In each embodiment, the gate driver 10 had a signal path for transmitting a set signal and a signal path for transmitting a reset signal, but it is not limited to this, and the set signal and the reset signal may be transmitted through a common signal path. In other words, the gate driver 10 may be configured to have one signal path as the signal path for transmitting the signal to drive the switching element 501.

[0211] In each embodiment, the number of capacitors 50A connected in series with transformer 40A and the number of capacitors 50B connected in series with transformer 40B can be arbitrarily changed. For example, multiple capacitors 50A may be provided connected in series with each other. Multiple capacitors 50B may be provided connected in series with each other. Thus, multiple capacitors 50 may be provided connected in series with each other.

[0212] With this configuration, by increasing the number of capacitors 50 connected in series with each other, the dielectric strength of the gate driver 10 can be improved in the event of dielectric breakdown in the transformer 40 due to a short circuit between the first coil 41A (41B) and the second coil 42A (42B).

[0213] In each embodiment, the capacitor 50 may be provided both between the low-voltage circuit 20 and the transformer 40, and between the transformer 40 and the high-voltage circuit 30. Each capacitor 50 is connected in series with the transformer 40.

[0214] In one example, as shown in Figure 21, the capacitor 50 includes low-voltage side capacitors 50AL and 50BL provided between the low-voltage circuit 20 and the transformer 40, and high-voltage side capacitors 50AH and 50BH provided between the transformer 40 and the high-voltage circuit 30.

[0215] The low-voltage side capacitor 50AL has a first electrode 51AL and a second electrode 52AL. The first electrode 51AL is electrically connected to the low-voltage circuit 20, and the second electrode 52AL is electrically connected to the transformer 40A. The second electrode 52AL is electrically connected to the first coil 41A of the transformer 40A. Therefore, it can be said that the low-voltage circuit 20 and the transformer 40A are electrically connected via the low-voltage side capacitor 50AL. Here, the first electrode 51AL corresponds to the first low-voltage side electrode, and the second electrode 52AL corresponds to the second low-voltage side electrode.

[0216] The high-voltage side capacitor 50AH has a first electrode 51AH and a second electrode 52AH. The first electrode 51AH is electrically connected to the transformer 40A, and the second electrode 52AH is electrically connected to the high-voltage circuit 30. The first electrode 51AH is electrically connected to the second coil 42A of the transformer 40A. Therefore, it can be said that the transformer 40A and the high-voltage circuit 30 are electrically connected via the high-voltage side capacitor 50AH. Here, the first electrode 51AH corresponds to the first high-voltage side electrode, and the second electrode 52AH corresponds to the second high-voltage side electrode.

[0217] The low-voltage side capacitor 50BL has a first electrode 51BL and a second electrode 52BL. The high-voltage side capacitor 50BH has a first electrode 51BH and a second electrode 52BH. The connection structure of these capacitors 50BL and 50BH to the low-voltage circuit 20, transformer 40, and high-voltage circuit 30 is the same as that of capacitors 50AL and 50AH, so a detailed explanation is omitted. Here, the first electrode 51BL corresponds to the first low-voltage side electrode, and the second electrode 52BL corresponds to the second low-voltage side electrode. The first electrode 51BH corresponds to the first high-voltage side electrode, and the second electrode 52BH corresponds to the second high-voltage side electrode.

[0218] With this configuration, if dielectric breakdown occurs in the transformer 40 due to a short circuit between the first coil 41A (41B) and the second coil 42A (42B), the high-voltage side capacitors 50AH, 50BH and the low-voltage side capacitors 50AL, 50BL insulate the high-voltage circuit 30 from the low-voltage circuit 20, making it easier to maintain insulation between the low-voltage circuit 20 and the high-voltage circuit 30. In addition, the dielectric strength of each capacitor 50AL, 50AH, 50BL, and 50BH can be reduced.

[0219] In each embodiment, the gate driver 10 may have a signal path for transmitting signals from the high-voltage circuit 30 to the low-voltage circuit 20. As an example, a configuration in which a signal path for transmitting signals from the high-voltage circuit 30 to the low-voltage circuit 20 is added to the gate driver 10 of the first embodiment, as shown in Figure 22, will be described.

[0220] As shown in Figure 22, the first electrode 51A of capacitor 50A is electrically connected to transformer 40A, and the second electrode 52A of capacitor 50A is electrically connected to the high-voltage circuit 30. The first electrode 51B of capacitor 50B is electrically connected to transformer 40B, and the second electrode 52B of capacitor 50B is electrically connected to the high-voltage circuit 30. Therefore, both transformers 40A and 40B correspond to the first transformer, and both capacitors 50A and 50B correspond to the first capacitor. For this reason, it can also be said that the first electrode of the first capacitor is electrically connected to the first transformer, and the second electrode of the first capacitor is electrically connected to the high-voltage circuit.

[0221] Furthermore, since the set signal output from the low-voltage circuit 20 is transmitted to the high-voltage circuit 30 via transformer 40A and capacitor 50A, and the reset signal output from the low-voltage circuit 20 is transmitted to the high-voltage circuit 30 via transformer 40B and capacitor 50B, it can also be said that the first signal output from the low-voltage circuit is transmitted to the high-voltage circuit via the first transformer and first capacitor.

[0222] As shown in Figure 22, the gate driver 10 further comprises a transformer 40C, a capacitor 50C, a low-voltage signal line 21C, and a high-voltage signal line 31C. The capacitor 50C is connected in series with the transformer 40C. Here, the transformer 40C corresponds to a second transformer, and the capacitor 50C corresponds to a second capacitor.

[0223] The transformer 40C transmits a signal from the high-voltage circuit 30 to the low-voltage circuit 20, while isolating the high-voltage circuit 30 from the low-voltage circuit 20. This signal is, for example, a signal to detect a temperature anomaly in the switching element 501, and corresponds to the second signal. The transformer 40C has a first coil 41C and a second coil 42C that is insulated from the first coil 41C and is magnetically coupled.

[0224] The first coil 41C is electrically connected to the high-voltage circuit 30, while also being electrically connected to the ground of the high-voltage circuit 30. In other words, the first end of the first coil 41C is electrically connected to the high-voltage circuit 30 via the capacitor 50C, and the second end of the first coil 41C is electrically connected to the ground of the high-voltage circuit 30. Therefore, the potential at the second end of the first coil 41C becomes the second reference potential. The second reference potential fluctuates with the driving of the inverter device 500, and is, for example, 600V or higher.

[0225] The second coil 42C is electrically connected to the capacitor 50C, while also being electrically connected to the ground of the low-voltage circuit 20. In other words, the first end of the second coil 42C is electrically connected to the capacitor 50C, and the second end of the second coil 42C is electrically connected to the ground of the low-voltage circuit 20. Therefore, the potential at the second end of the second coil 42C becomes the first reference potential. The first reference potential is, for example, 0V.

[0226] Capacitor 50C has a first electrode 51C and a second electrode 52C, and is electrically connected to both the low-voltage circuit 20 and the transformer 40C by a high-voltage signal line 31C. More specifically, the first electrode 51C of capacitor 50C is connected to the first end of the first coil 41C of transformer 40C, and the second electrode 52C of capacitor 50C is connected to the low-voltage circuit 20. Therefore, it can also be said that the first electrode of the second capacitor is electrically connected to the first transformer, and the second electrode of the second capacitor is electrically connected to the low-voltage circuit.

[0227] The signal (second signal) output from the high-voltage circuit 30 is transmitted to the low-voltage circuit 20 via the transformer 40C and the capacitor 50C. In the illustrated example, the transformer 40C and the capacitor 50C are arranged in that order in the direction of signal (second signal) transmission.

[0228] Thus, in the modified example shown in Figure 22, signals are transmitted bidirectionally between the low-voltage circuit 20 and the high-voltage circuit 30. These signals include a first signal transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 and a second signal transmitted from the high-voltage circuit 30 to the low-voltage circuit 20.

[0229] In the gate driver 10 shown in Figure 22, the transformer 40C may be connected to the low-voltage circuit 20 and the capacitor 50C may be connected to the high-voltage circuit 30. In other words, the capacitor 50C and the transformer 40C may be arranged in that order in the direction of signal (second signal) transmission.

[0230] In the modified example shown in Figure 22, capacitor 50C may be included in the low-voltage circuit chip 60. Alternatively, capacitor 50C may be included in a capacitor chip. In this case, the capacitor chip is mounted, for example, on a low-voltage die pad.

[0231] The transformer 40C may be included in the transformer chip 80, or it may be included in a separate transformer chip provided separately from the transformer chip 80. This separate transformer chip is mounted, for example, on the low-voltage die pad 91. Note that when applying a configuration like the modified example in Figure 22 to the third and fifth embodiments, the capacitor 50C and transformer 40C may be similarly modified.

[0232] When applying a configuration like the modified example in Figure 22 to the second embodiment, the capacitor 50C is included in a capacitor chip provided separately from the capacitor chip 120. This separate capacitor chip is mounted, for example, on the low-voltage die pad 91.

[0233] When applying a configuration like the modified example in Figure 22 to the fourth embodiment, the capacitor 50C may be included in the capacitor chip 120. Alternatively, the capacitor 50C may be included in a capacitor chip provided separately from the capacitor chip 120. This separate capacitor chip is mounted, for example, on the low-voltage die pad 91.

[0234] The transformer 40C may be included in the transformer chip 80. Alternatively, the transformer 40C may be included in a separate transformer chip provided separately from the transformer chip 80. This separate transformer chip may be mounted, for example, on the low-voltage die pad 91.

[0235] When applying a configuration like the modified example in Figure 22 to the 6th to 8th embodiments, the capacitor 50C may be included in a capacitor chip provided separately from the capacitor chip 120. This separate capacitor chip is mounted, for example, on the low-voltage die pad 91.

[0236] The transformer 40C may be included in a separate transformer chip from the transformer chip 80. This separate transformer chip is mounted, for example, on the high-voltage die pad 101.

[0237] In the above embodiments, the transformer 40 is used as basic insulation and the capacitor 50 as additional insulation, but the invention is not limited to this, and the capacitor 50 may be used as basic insulation and the transformer 40 as additional insulation.

[0238] [Note] The technical concepts that can be understood from each of the above embodiments and their respective modifications are described below. (Note A1) A gate driver for applying a drive voltage signal to the gate of a switching element, comprising: a low-voltage circuit that operates when a first voltage is applied; a high-voltage circuit that operates when a second voltage higher than the first voltage is applied; a transformer; and a capacitor connected in series with the transformer, wherein the low-voltage circuit and the high-voltage circuit are connected via the transformer and the capacitor, and signals are transmitted via the transformer and the capacitor.

[0239] (Note A2) The gate driver according to Note A1, wherein the transformer includes a first transformer and a second transformer connected in series with each other, the second transformer connects both the first transformer and the high-voltage circuit, and the capacitor has a first electrode and a second electrode, the first electrode is electrically connected to the second transformer, the second electrode is electrically connected to the high-voltage circuit and is connected in series with the second transformer.

[0240] (Appendix A3) The gate driver described in Appendix A2, comprising a high-voltage circuit chip including the high-voltage circuit, wherein the capacitor is incorporated into the high-voltage circuit chip. (Appendix A4) The gate driver according to Appendix A3, comprising: a low-voltage circuit chip including the low-voltage circuit; a first transformer chip including the first transformer; a second transformer chip including the second transformer; a low-voltage die pad on which the low-voltage circuit chip is mounted; and a high-voltage die pad on which the high-voltage circuit chip is mounted, wherein the first transformer chip is mounted on the low-voltage die pad and the second transformer chip is mounted on the high-voltage die pad.

[0241] (Appendix A5) The gate driver according to Appendix A3, comprising a low-voltage circuit chip including the low-voltage circuit, a first transformer chip including the first transformer, a second transformer chip including the second transformer, a low-voltage die pad on which the low-voltage circuit chip is mounted, and a high-voltage die pad on which the high-voltage circuit chip is mounted, wherein both the first transformer chip and the second transformer chip are mounted on the low-voltage die pad or the high-voltage die pad.

[0242] (Note A6) The gate driver according to Note A2, comprising a low-voltage circuit chip including the low-voltage circuit, a high-voltage circuit chip including the high-voltage circuit, a first transformer chip including the first transformer, a second transformer chip including the second transformer, and a capacitor chip including the capacitor, wherein the low-voltage circuit chip, the first transformer chip, the second transformer chip, the capacitor chip, and the high-voltage circuit chip are arranged in this order.

[0243] (Note A7) The gate driver according to Note A1, wherein the transformer includes a first transformer and a second transformer connected in series with each other, the first transformer connects both the second transformer and the low-voltage circuit, and the capacitor has a first electrode and a second electrode, the first electrode is electrically connected to the first transformer, the second electrode is electrically connected to the low-voltage circuit and is connected in series with the first transformer.

[0244] (Appendix A8) The gate driver according to Appendix A7, comprising a low-voltage circuit chip including the low-voltage circuit, wherein the capacitor is incorporated into the low-voltage circuit chip. (Note A9) The gate driver according to Note A8, comprising a high-voltage circuit chip including the high-voltage circuit, a first transformer chip including the first transformer, a second transformer chip including the second transformer, a low-voltage die pad on which the low-voltage circuit chip is mounted, and a high-voltage die pad on which the high-voltage circuit chip is mounted, wherein the first transformer chip is mounted on the low-voltage die pad and the second transformer chip is mounted on the high-voltage die pad.

[0245] (Note A10) The gate driver according to Note A8, comprising a high-voltage circuit chip including the high-voltage circuit, a first transformer chip including the first transformer, a second transformer chip including the second transformer, a low-voltage die pad on which the low-voltage circuit chip is mounted, and a high-voltage die pad on which the high-voltage circuit chip is mounted, wherein both the first transformer chip and the second transformer chip are mounted on the low-voltage die pad or the high-voltage die pad.

[0246] (Note A11) The gate driver described in Note A7, comprising a low-voltage circuit chip including the low-voltage circuit, a high-voltage circuit chip including the high-voltage circuit, a first transformer chip including the first transformer, a second transformer chip including the second transformer, and a capacitor chip including the capacitor, wherein the low-voltage circuit chip, the capacitor chip, the first transformer chip, the second transformer chip, and the high-voltage circuit chip are arranged in this order.

[0247] (Note A12) The gate driver according to any one of Notes A1 to A11, wherein the low-voltage circuit generates a first signal for generating the drive voltage signal based on an external command, and the high-voltage circuit generates the drive voltage signal based on the first signal. (Note A13) The aforementioned capacitors are arranged in multiple units connected in series with each other, and the gate driver is as described in any one of the appendices A1 to A12. (Note A14) The gate driver described in any one of the appendices A1 to A13, wherein the dielectric strength of the capacitor is 200 Vrms or more.

[0248] (Note B1) An isolation module used to isolate a low-voltage circuit and a high-voltage circuit included in a gate driver that applies a drive voltage signal to the gate of a switching element, comprising a transformer and a capacitor connected in series with the transformer, wherein the low-voltage circuit and the high-voltage circuit are connected via the transformer and the capacitor, and the transformer and the capacitor are used to transmit signals between the low-voltage circuit and the high-voltage circuit.

[0249] (Appendix B2) The isolation module according to Appendix B1, comprising a transformer chip including the transformer and a capacitor chip including the capacitor. (Appendix B3) The isolation module described in Appendix B2, comprising a first die pad on which the transformer chip is mounted, a first lead electrically connected to the transformer, a second die pad on which the capacitor chip is mounted, and a second lead electrically connected to the capacitor.

[0250] (Appendix B4) The isolation module described in Appendix B2, comprising a common die pad on which both the transformer chip and the capacitor chip are mounted, a first lead electrically connected to the transformer, and a second lead electrically connected to the capacitor. [Explanation of Symbols]

[0251] 10... Gate Driver 20... Low-voltage circuits 21A, 21B... Low-voltage signal lines 30…High-voltage circuits 31A, 31B… High-voltage signal lines 40…transformer 40A, 40B... Transformers (First Transformer) 40C…Transformer (Second Transformer) 41A, 41B... First coil 42A, 42B... Second coil 50… Capacitor 50A, 50B... Capacitors (First Capacitor) 50C...Capacitor (Second Capacitor) 51A,51B…1st electrode 51AL, 51BL... First electrode (first low-pressure side electrode) 51AH, 51BH... First electrode (first high-voltage side electrode) 52A,52B…Second electrode 52AL, 52BL... Second electrode (second low-pressure side electrode) 52AH, 52BH... Second electrode (second low-pressure side electrode) 60... Low-voltage circuit chip 70…High-voltage circuit chip 80…Transchip 83…Insulating layer 91... Low-voltage die pad 101... High-pressure die pad 120…Capacitor chip 220...Isolation module 300... Low-voltage circuit unit 410…High-voltage circuit unit 501, 502… Switching elements

Claims

1. A gate driver that applies a drive voltage signal to the gate of a switching element, A low-voltage circuit that operates when a first voltage is applied, A high-voltage circuit that operates when a second voltage higher than the first voltage is applied, Transformer and A capacitor connected in series with the aforementioned transformer, A low-voltage circuit chip including the aforementioned low-voltage circuit, A high-voltage circuit chip including the aforementioned high-voltage circuit, A transformer chip including the aforementioned transformer, A capacitor chip including the aforementioned capacitor, A low-voltage die pad on which the low-voltage circuit chip is mounted, A high-voltage die pad on which the aforementioned high-voltage circuit chip is mounted, Equipped with, The low-voltage circuit and the high-voltage circuit are connected via the transformer and the capacitor, and signals are transmitted via the transformer and the capacitor. The transformer chip is mounted on the low-voltage die pad or the high-voltage die pad. The capacitor chip is mounted on the low-voltage die pad or the high-voltage die pad. Gate driver.

2. The capacitor has a first electrode and a second electrode, The first electrode is electrically connected to the transformer, The second electrode is electrically connected to the high-voltage circuit. The gate driver according to claim 1.

3. The transformer chip is mounted on the low-voltage die pad. The gate driver according to claim 1.

4. The low-voltage circuit chip, the transformer chip, the capacitor chip, and the high-voltage circuit chip are arranged in this order. The gate driver according to claim 2.

5. The transformer chip is mounted on the low-voltage die pad, The capacitor chip is mounted on the high-voltage die pad. The gate driver according to claim 4.

6. Both the transformer chip and the capacitor chip are mounted on the low-voltage die pad or the high-voltage die pad. The gate driver according to claim 4.

7. The capacitor has a first electrode and a second electrode, The first electrode is electrically connected to the low-voltage circuit. The second electrode is electrically connected to the transformer. The gate driver according to claim 1.

8. The low-voltage circuit chip, the capacitor chip, the transformer chip, and the high-voltage circuit chip are arranged in this order. The gate driver according to claim 7.

9. Both the capacitor chip and the transformer chip are mounted on the low-voltage die pad. The gate driver according to claim 8.

10. The capacitor chip is mounted on the low-voltage die pad, The transformer chip is mounted on the high-voltage die pad. The gate driver according to claim 8.

11. The capacitor includes a low-voltage side capacitor and a high-voltage side capacitor. The low-voltage side capacitor has a first low-voltage side electrode and a second low-voltage side electrode, The first low-voltage side electrode is electrically connected to the low-voltage circuit. The second low-voltage electrode is electrically connected to the transformer. The high-pressure side capacitor has a first high-pressure side electrode and a second high-pressure side electrode, The first high-voltage side electrode is electrically connected to the transformer. The second high-voltage side electrode is electrically connected to the high-voltage circuit. The gate driver according to claim 1.

12. The capacitor includes a first capacitor and a second capacitor, The transformer includes a first transformer and a second transformer, The first capacitor is connected in series with the first transformer. The signal includes a first signal transmitted from the low-voltage circuit to the high-voltage circuit. The first signal output from the low-voltage circuit is transmitted to the high-voltage circuit via the first transformer and the first capacitor. The second capacitor is connected in series with the second transformer. The signal includes a second signal transmitted from the high-voltage circuit to the low-voltage circuit. The second signal output from the high-voltage circuit is transmitted to the low-voltage circuit via the second transformer and the second capacitor. A gate driver according to any one of claims 1 to 11.

13. The first capacitor and the second capacitor each have a first electrode and a second electrode, The first electrode of the first capacitor is electrically connected to the first transformer. The second electrode of the first capacitor is electrically connected to the high-voltage circuit. The first electrode of the second capacitor is electrically connected to the second transformer. The second electrode of the second capacitor is electrically connected to the low-voltage circuit. The gate driver according to claim 12.

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