Semiconductor equipment

Abstract

To improve the conversion accuracy when using a plurality of DACs with different operating voltages.SOLUTION: A semiconductor device digitally converts an analog input signal by sequentially comparing an analog input signal with a reference voltage. The semiconductor device includes an upper DAC 10 that generates a high voltage region of the reference voltage on the basis of a predetermined code, a lower DAC 20 that generates a low voltage region of the reference voltage on the basis of the code, and an injection DAC 30 having the same configuration as the lower DAC 20 and adjusting the low voltage region of the reference voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device equipped with an error shaping mechanism. [Background technology]

[0002] For example, Non-Patent Document 1 discloses an Analog-to-Digital Converter (ADC) that performs mismatch error shaping (MES) of the reference error of the lower-end DAC (Digital-to-Analog Converter) using successive approximation registers (SAR). Specifically, Non-Patent Document 1 eliminates the reference error of the lower-end DAC using first-order error shaping.

[0003] Non-patent document 2 discloses a technique for eliminating the reference error of a lower-end DAC using second-order error shoeing.

[0004] Non-patent document 3 discloses a configuration in which a 2V reference voltage is applied to the upper DAC and a 1.2V reference voltage is applied to the lower DAC in order to expand the input range. Errors in the reference voltage are eliminated by an error shaping mechanism. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] Y.-S. Shu, “An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS,” [Non-Patent Document 2] J. Liu, “Second-order DAC MES for SAR ADCs,” [Non-Patent Document 3] W.-H Huang, “An Amplifier-Less Calibration-Free SAR ADC Achieving>100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range” [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] To handle high-voltage inputs, for example, higher-end DACs are supplied with high-voltage references, and therefore high-voltage transistors are used. However, high-voltage transistors have a slower response speed than low-voltage transistors, resulting in a decrease in conversion speed and, consequently, a decrease in conversion accuracy.

[0007] This invention has been made in view of the above, and one of its objectives is to provide a semiconductor device that improves the conversion accuracy when using multiple DACs with different operating voltages. [Means for solving the problem]

[0008] A brief overview of some of the representative inventions disclosed in this application is as follows: A typical semiconductor device performs digital conversion of an analog input signal by successive comparison of the analog input signal and a reference voltage. The semiconductor device comprises a higher-level DAC that generates a high-voltage region of the reference voltage based on a predetermined code, a lower-level DAC that generates a low-voltage region of the reference voltage based on the code, and an injection DAC having a similar configuration to the lower-level DAC and adjusting the low-voltage region of the reference voltage. [Effects of the Invention]

[0009] To briefly explain the effects obtained by representative inventions disclosed in this application, it becomes possible to improve the conversion accuracy when using multiple DACs with different operating voltages. [Brief explanation of the drawing]

[0010] [Figure 1] This is a configuration diagram showing an example of a semiconductor device according to Embodiment 1 of the present invention. [Figure 2] This is a flowchart exemplifying the operation of an ADC according to Embodiment 1 of the present invention. [Figure 3] This is a diagram exemplifying the setting status of each DAC in the sampling phase. [Figure 4] This is a diagram exemplifying the setting status of each DAC in the initial state of the comparison phase. [Figure 5] This is a diagram exemplifying the setting status of each DAC at the end of the comparison phase. [Figure 6] This is a configuration diagram showing an example of a semiconductor device according to Embodiment 2 of the present invention. [Figure 7] This is a diagram showing a comparison of the output voltages of each DAC in the comparison phase of Embodiment 2 of the present invention. [Figure 8] This is a diagram exemplifying the system configuration and transfer function of an ADC according to Embodiment 2 of the present invention. [Figure 9] This is a configuration diagram showing an example of a semiconductor device according to Embodiment 3 of the present invention. [Figure 10] This is a diagram for explaining an ADC that is the basis of a multi-channel ADC system according to Embodiment 4 of the present invention. [Figure 11] This is a diagram exemplifying the configuration of a multi-channel ADC system according to Embodiment 4 of the present invention. [Figure 12] This is a diagram for explaining a sampling method according to Embodiment 5 of the present invention.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In all the drawings for explaining the embodiments, the same parts are generally denoted by the same reference numerals, and the repeated explanations thereof are omitted.

[0012] (Embodiment 1) <Configuration of semiconductor device> Figure 1 is a configuration diagram showing an example of a semiconductor device according to Embodiment 1 of the present invention. The analog-to-digital converter (hereinafter also referred to as "ADC") 1 is a semiconductor device that converts an input analog signal into digital and outputs a digital signal after digital conversion (hereinafter also referred to as a digital code). As shown in Figure 1, the analog-to-digital converter (semiconductor device) 1 includes an upper-level DAC (Digital to Analog Converter) 10, a lower-level DAC 20, an injection DAC 30, a comparator 40, a successive comparison processing unit 50, MES registers 61, 62, selectors 71, 72, a level shifter 75, a sampling capacitor 80, switch circuits SW1, SW2, SW3, etc. In the following, the analog-to-digital converter may be referred to as an ADC.

[0013] The sampling capacitor 80 is a circuit that holds the analog input signal input to the ADC. During the sampling phase, for example, when the sampling signal SMP becomes active (e.g., high level), switch circuits SW1 and SW2 are turned on and switch circuit SW3 is turned off, and the analog input signal is held in the sampling capacitor 80. On the other hand, during the comparison phase, for example, when the sampling signal SMP becomes inactive (e.g., low level), switch circuit SW3 is turned on and switch circuits SW1 and SW2 are turned off, and the analog input signal held in the sampling capacitor 80 is supplied to the comparator 40.

[0014] The upper DAC10, lower DAC20, and injection DAC30 are digital-to-analog converters that generate analog signals based on digital codes input from the successive approximation processing unit 50 and MES registers 61 and 62. Specifically, the upper DAC10, lower DAC20, and injection DAC30 generate a reference voltage for comparison with the analog input signal input to ACD1.

[0015] The upper DAC10 generates voltage based on the information of the higher bits of the digital code. The lower DAC20 and injection DAC30 generate voltage based on the information of the lower bits of the digital code. The injection DAC30 has a similar configuration to the lower DAC20. The injection DAC30 can work in conjunction with the lower DAC20 to fine-tune the reference voltage value. The upper DAC10 operates with a high voltage (e.g., 3V) reference. The lower DAC20 and injection DAC30 operate with a constant voltage (e.g., 1V).

[0016] The comparator 40 is a circuit that compares an analog input signal with a reference voltage. The comparator 40 is a circuit that operates at a high voltage (e.g., 3V). For example, the comparator 40 compares the analog input signal with the reference voltage for each sampling cycle Tcy and outputs the comparison result to the successive comparison processing unit 50.

[0017] As shown in Figure 1, the successive comparison processing unit 50 performs a successive comparison process based on the comparison result output from the comparator 40, thereby converting the analog input signal to digital and generating a digital code, which is the output signal. The successive comparison processing unit 50 outputs the generated digital code to, for example, the upper DAC 10, the lower DAC 20, or subsequent circuits (not shown). The successive comparison processing unit 50 also stores the generated digital code in MES registers 61 and 62.

[0018] The MES registers 61 and 62 are memory devices that hold the digital code generated by the successive comparison processing unit 50. The MES registers 61 and 62 each hold the digital code generated in the previous sampling cycle Tcy and the digital code generated in the sampling cycle Tcy two cycles prior, respectively. Here, the MES register 61 holds the digital code generated in the previous sampling cycle Tcy, and the MES register 62 holds the digital code generated in the sampling cycle Tcy two cycles prior.

[0019] Therefore, when the digital code for the current sampling cycle Tcy is generated, the digital code for the two previous sampling cycles Tcy, which was held in MES register 62, is erased, and the digital code for the current sampling cycle Tcy is held. At that time, the digital code for the previous sampling cycle Tcy, which was held in MES register 61, is moved to MES register 62, and the digital code generated this time is held in MES register 61. Note that MES registers 61 and 62 may hold only the lower bits of the corresponding digital code. Note that MES register 62 may hold the inverted code obtained by reversing the corresponding digital code, or the inverted code of the lower bits.

[0020] Selector 71 is a circuit that switches the digital code supplied to the lower-level DAC20 based on the sampling signal SMP. The input side of selector 71 is connected to the successive comparison processing unit 50 and the MES register 61. The output side of selector 71 is connected to the lower-level DAC20.

[0021] Selector 72 is a circuit that switches the digital code supplied to the injection DAC 30 based on the sampling signal SMP. The input side of selector 72 is connected to MES registers 61 and 62. The output side of selector 72 is connected to the injection DAC 30.

[0022] The level shifter 75 is a circuit that converts the voltage of the digital code supplied to the higher-level DAC 10 to a high voltage and supplies a high-voltage digital code. The input side of the level shifter 75 is connected to the successive comparison processing unit 50. The output side of the level shifter 75 is connected to the higher-level DAC 10.

[0023] Next, the A / D conversion process in ADC1 will be described in detail. Figure 2 is a flowchart illustrating the operation of the ADC according to Embodiment 1 of the present invention. Figure 2 includes steps S10 to S40.

[0024] ​First, step S10 is the sampling phase in which input data is sampled. Figure 3 is a diagram illustrating the settings of each DAC during the sampling phase. As shown in Figure 3, the sampling signal SMP becomes active during the sampling phase PHs. At this time, the upper bit (INITIAL CODES1) of a predetermined initial code output from the successive comparison processing unit 50 is set in the upper DAC 10.

[0025] Selector 71 selects MES register 61. This causes the lower DAC20 to receive the lower bits of the previous digital code supplied from MES register 61 (Dout2·Z). -1 ) is set. Selector 72 selects MES register 62. As a result, the injection DAC30 receives the inverted code (-Dout2·Z) of the lower bits of the two previous digital codes. -2 ) is set.

[0026] Then, during the sampling phase PHs, switch circuits SW1 and SW2 are turned on, and an analog input signal is supplied to the sampling capacitor 80, which is then charged. In other words, the sampling capacitor 80 is charged with a digital code set in each DAC.

[0027] When the sampling signal SMP becomes inactive, the sampling phase PHs ends.

[0028] Steps S20-S40 are comparison phases PHc that compare the reference voltage generated by each DAC with the analog input signal.

[0029] Step S20 is the initial state of the comparison phase. Figure 4 illustrates the settings of each DAC in the initial state of the comparison phase. As shown in Figure 4, in the comparison phase PHc, the sampling signal SMP becomes inactive and the clock CLK1 is supplied to the comparator 40.

[0030] At this time, the upper DAC10 remains in the state where the upper bits (INITIAL CODES1) of the predetermined initial code were set in step S10.

[0031] Selector 71 selects the successive comparison processing unit 50. As a result, the lower bits 20 are set to the lower bits (INITIAL CODES2) of a predetermined initial code supplied by the successive comparison processing unit 50. Selector 72 selects the MES register 61. As a result, the injection DAC 30 receives the inverted code (-Dout2·Z) of the lower bits of the previous digital code. -1 The DAC is set. A reference voltage is generated by the analog signals output from each DAC and supplied to the comparator 40.

[0032] Furthermore, during the comparison phase PHc, switch circuits SW1 and SW2 are turned off, and switch circuit SW3 is turned on. As a result, the analog input signal held in the sampling capacitance 80 is supplied to the comparator 40 via switch circuit SW2.

[0033] Step S30 is the first half of the comparison phase PHc, in which a digital code is set for each bit of the upper DAC10.

[0034] When the comparison process by the comparator 40 begins, the sequential comparison processing unit 50 performs digital conversion of the analog input signal based on the comparison result of the comparator 40, and sequentially generates a digital code (output data) from the most significant bit. The generation of the digital code is performed, for example, by detecting the error (quantization error) that occurs when the analog input signal is converted to digital, and performing A / D conversion on the detected quantization error.

[0035] The successive comparison processing unit 50 outputs the generated digital code one bit at a time from the most significant bit each time a successive comparison is completed. Step S30 continues until a digital code has been supplied to each bit of the upper DAC 10. Figure 2 shows the state where a digital code has been supplied to all bits of the upper DAC 10. That is, at the end of step S30, the upper DAC 10 is in a state where the most significant bits of the digital data are set, as shown in Figure 2 (DOUT1).

[0036] Furthermore, in step S30, the lower DAC20 is not yet supplied with digital data, as shown in Figure 2. Therefore, at the end of step S30, the lower DAC20 maintains a state in which the lower bits (INITIAL CODES2) of a predetermined initial code are set. Also, at the end of step S30, the injection DAC30, as shown in Figure 2, has the inverted code (-Dout2·Z) of the lower bits of the previous digital code. -1 The state in which it is set is maintained.

[0037] Step S40 is the latter half of the comparison phase PHc, in which a digital code is set for each bit of the lower DAC20. The successive comparison processing unit 50 continues to perform successive comparisons based on the comparison results and sequentially generates digital codes to be supplied to each bit of the lower DAC20. The successive comparison processing unit 50 sequentially outputs the generated digital codes one bit at a time and supplies them to the lower DAC20.

[0038] Once the digital code settings for the upper DAC10 and lower DAC20 are complete, the comparison phase PHc ends.

[0039] Figure 5 illustrates the settings of each DAC at the end of the comparison phase. At the end of step S40, the upper DAC 10 maintains the state in which the upper bits of the digital data are set (DOUT1), as shown in Figure 5. Also at the end of step S40, the lower DAC 20 is in the state in which the lower bits of the digital data are set (DOUT2), as shown in Figure 5. Also at the end of step S40, the injection DAC 30 is in the state in which the lower bits of the previous digital code are inverted (-Dout2·Z), as shown in Figure 5. -1 The state in which it is set is maintained.

[0040] In this way, processing is performed in one sampling cycle. Then, ADC1 continues to perform the digital conversion process by executing steps S10 to S40 in the next sampling cycle Tcy.

[0041] <Main effects of this embodiment> In this embodiment, the code written to the injection DAC30 is the inverted code of the two previous digital codes in the sampling phase PHs, and the inverted code of the one previous digital code in the comparison phase PHc. As a result, capacitance mismatch in the injection DAC is eliminated by first-order error shaping.

[0042] Furthermore, during the sampling phase PHs, the previous digital code is written to the lower DAC20, eliminating the reference error between the upper DAC10, which operates at high voltage, and the lower DAC20, which operates at low voltage, through second-order error shaping.

[0043] Furthermore, capacitance mismatches in the lower-end DAC20 are eliminated by first-order error shaping. These improvements make it possible to enhance conversion accuracy when using DACs with different operating voltages.

[0044] Furthermore, according to this embodiment, the lower-level DAC20 and the injection DAC30 are written with digital codes that are shifted by one step and inverted. With this configuration, the settling error of the reference can be eliminated by first-order error shaping.

[0045] (Embodiment 2) Next, Embodiment 2 will be described. In Embodiment 1 described above, a low-voltage device cannot be used for the comparator 40 because the dynamic range of the DAC's output voltage is large. Also, when comparing the upper DAC 10, it is necessary to level-shift the digital code to a high voltage using the level shifter 75, so there is a delay time for the level shifter 75.

[0046] Therefore, in this embodiment, the comparison of the upper-level DAC10 is performed by a sub-ADC composed of a sub-DAC and a comparator, and the comparison result of the sub-ADC is used as the code for the upper-level DAC10.

[0047] Figure 6 is a configuration diagram showing an example of a semiconductor device according to Embodiment 2 of the present invention. The ADC1A in Figure 6 has a configuration in which a sub-ADC201 is added to the main ADC101, which is similar to the ADC1 in Figure 1.

[0048] <Main ADC> As shown in Figure 6, the main ADC101 includes an upper DAC10, a lower DAC20, a comparator40, a successive comparison processing unit50, an MES unit160, a selector170, a level shifter75, a sampling capacitor80, and switch circuits SW1, SW2, SW3, etc.

[0049] The comparator 40, based on the clock CLK12 described later, performs a comparison only in the low-voltage region corresponding to the lower-level DAC20 and outputs the comparison result to the sequential comparison processing unit 50. In this embodiment, the comparator 40 operates at a low voltage (for example, 1V).

[0050] The successive comparison processing unit 50 performs successive comparison processing based on the comparison results of the low-voltage region corresponding to the lower-level DAC20 output from the comparator 40, thereby converting the analog input signal to digital and generating the lower bits of the digital code. The lower bits of the digital code generated by the successive comparison processing unit 50 are output together with the upper bits of the digital code generated by the sub-ADC201, which will be described later. The lower bits of the digital code are also stored in the MES unit 160.

[0051] The MES unit 160 is composed of, for example, MES registers as shown in Figure 1. The MES unit 160 holds, for example, the digital code generated in the previous sampling cycle Tcy, the digital code generated in the current sampling cycle Tcy, etc. The MES unit 160 outputs the digital code generated in the previous sampling cycle Tcy to the selector 170 and the sub-lower DAC 220, which will be described later.

[0052] The selector 170 is a circuit that switches the digital code (lower bits) supplied to the lower-level DAC 20 based on the sampling signal SMP. The input side of the selector 170 is connected to the successive comparison processing unit 50 and the MES unit 160. The output side of the selector 170 is connected to the lower-level DAC 20.

[0053] The upper-level DAC 10 is supplied with the higher bits of the digital code output from the sub-ADC 201 (described later), after the level shifter 75 has level-shifted them to a high voltage. The upper-level DAC 10 is equipped with an extended DAC in addition to the main DAC. This extended DAC is used to absorb the previous DAC output voltage injected into the lower-level DAC 20 by the MES unit 160.

[0054] <Sub-ADC> Next, the sub-ADC201A is a circuit that performs a comparison of the upper-level DAC10 with a low-voltage reference and generates the upper bits of the digital code. As shown in Figure 6, the sub-DAC201 includes a sub-upper-level DAC210, a sub-lower-level DAC220, a comparator240, a successive comparison processing unit250, a sampling capacitor280, and switch circuits SW201, SW202, SW203, etc.

[0055] The sub-upper DAC210 is a DAC that corresponds to the upper DAC110. The sub-lower DAC220 is a DAC that corresponds to the lower DAC20. The sub-upper DAC210 and sub-lower DAC220 operate at low voltage (e.g., 1V). The sub-upper DAC210 is equipped with an extension DAC (not shown in the diagram) along with the main DAC. This extension DAC is used to absorb the previous DAC output voltage injected into the sub-lower DAC220 by the MES unit 160.

[0056] Furthermore, the sub-ADC201 may be configured without a sub-lower-level DAC. In this case, the extended DAC for the sub-upper-level DAC210 is not required. This makes it possible to simplify the circuit configuration of the sub-ADC201.

[0057] The comparator 240, based on the clock CLK11 described later, performs comparisons only in the high-voltage region corresponding to the higher-level DAC110 and outputs the comparison results to the sequential comparison processing unit 250. The comparator 240 operates at a low voltage (e.g., 1V).

[0058] The successive approximation processing unit 250 performs successive approximation processing based on the comparison results of the high-voltage region corresponding to the sub-upper DAC 210 output from the comparator 240, thereby converting the analog input signal to digital and generating the upper bits of the digital code. The upper bits of the digital code generated by the successive approximation processing unit 250 are output together with the lower bits of the digital code generated by the main ADC 101. The upper bits of the digital code are also supplied to the sub-upper DAC 210. Furthermore, the upper bits of the digital code are supplied to the upper DAC 110 via the level shifter 75.

[0059] Switch circuits SW201 to SW203 correspond to switch circuits SW1 to SW3 of the main ADC101, respectively. The sampling capacity of 280 corresponds to the sampling capacity of 80 of the main ADC.

[0060] Next, the A / D conversion process in ADC1A will be explained in detail. In the sampling phase PHs, the analog input signal is held at sampling capacities of 80 and 280.

[0061] As shown in Figure 6, the comparison phase PHc includes a first comparison phase PHc1 in which the sub-ADC201 generates the higher bits of the digital code, and a second comparison phase PHc2 in which the main ADC101 generates the lower bits of the digital code.

[0062] In the first comparison phase PHc1, the clock CLK11 is supplied to the comparator 240, and the higher bits of the analog input signal are converted to digital. The successive comparison processing unit 250 sequentially generates digital codes starting from the most significant bit and outputs the generated digital code of each bit to the sub-upper DAC 210 and upper DAC 110.

[0063] Once the digital conversion process of the higher bits of the analog input signal is complete, the supply of clock CLK11 is stopped, and the first comparison phase PHc1 ends.

[0064] Next, in the second comparison phase PHc2, the clock CLK12 is supplied to the comparator 40, and the lower bits of the analog input signal are converted to digital. The successive comparison processing unit 50 sequentially generates digital codes from the most significant bit of the lower DAC20, outputs the digital code of each generated bit, and has it held in the MES unit 160.

[0065] ​When the digital conversion process for the lower bits of the analog input signal is completed, the supply of the clock CLK12 is stopped, and the second comparison phase PHc2 ends. As a result, the comparison phase PHc ends.

[0066] In this way, the processing in one sampling cycle is performed. Then, ADC1A also executes steps S10 to S40 in the next sampling cycle Tcy and continues the digital conversion process.

[0067] FIG. 7 is a diagram showing a comparison of the output voltages of each DAC in the comparison phase of Embodiment 2 of the present invention. First, in the first comparison phase PHc1, the voltage (DACOUT_C) output from the sub-superior DAC210 is at a low voltage. In this way, in the sub-ADC201, a high-voltage (e.g., 3V) input signal is digitally converted with a low-voltage reference, and the upper bits of the digital code are generated.

[0068] Also, in the second comparison phase PHc2, in the main ADC101, since the digital conversion process for the lower bits corresponding to the low-voltage region is performed, the voltage (DACOUT) output from the lower DAC20 is low, as shown in FIG. 7. In the main ADC101, digital conversion is performed on a low-voltage input signal corresponding to the lower bits of the digital code with a low-voltage reference, and the lower bits of the digital code are generated.

[0069] <Transfer function> FIG. 8 is a diagram illustrating a system configuration and a transfer function of an ADC according to Embodiment 2 of the present invention. In the system configuration shown in FIG. 8, if the input is "X" and the output is "Y", the transfer function is represented by Expressions (1) to (3) in FIG. 8. Among these expressions, "(E D1 -z -1 E D3 )(1 - z -1 )", "E ref (1 - z -1 ) 2 " corresponds to "DAC4" in FIG. 8, and "2Z -1 -Z -2These correspond to the lower DAC20 and sub-lower DAC220 in Figure 6.

[0070] In this way, by equipping the sub-ASC201 with a sub-lower DAC220, it is possible to improve the replica accuracy of the sub-ADC201.

[0071] <Main effects of this embodiment> In this embodiment, the sub-ADC201, which performs the digital conversion of the higher bits, and the main ADC101, which performs the digital conversion of the lower bits, are independent. With this configuration, it is possible to attenuate the dynamic range of the comparator 240 of the sub-ADC201 to the withstand voltage of the low-voltage device.

[0072] This allows the sub-higher DAC210 to be driven with a low-voltage reference. This enables the sub-ADC201 to be configured using only low-voltage devices. Furthermore, the sub-ADC201 does not need to perform level shifting when supplying digital code to the sub-higher DAC210. ​​These factors allow for faster comparison processing.

[0073] Sub-ADC201 has a relatively large error, but this error is mitigated by the redundancy of the lower-level DAC20 of the main ADC101. Furthermore, since the sub-lower-level DAC220 operates as a replica of the lower-level DAC20 of the main ADC101 in MES operation, the error of sub-ADC201 can be reduced.

[0074] Furthermore, according to this embodiment, since the main ADC101 compares with the lower-end DAC20, the dynamic range of the comparator 40 can be reduced, and the comparator 40 can be composed only of low-voltage devices.

[0075] (Embodiment 3) Next, Embodiment 3 will be described. In this embodiment, the reference voltage supplied to the upper-level DAC110 of the ADC1A in Embodiment 2 is configured to be switchable between a high voltage (e.g., 3V) and a low voltage (e.g., 1V).

[0076] Figure 9 is a configuration diagram showing an example of a semiconductor device according to Embodiment 3 of the present invention. The ADC1B in Figure 9 has the same configuration as the ADC1A in Figure 6, with the addition of a selector 191, a digital multiplication circuit 292, and a selector 293.

[0077] The digital multiplication circuit 292 has its input side connected to the successive comparison processing unit 250 and its output side connected to the selector 293. The digital multiplication circuit 292 is a circuit that generates a multiplied digital code by digitally multiplying the output data (digital code) of the successive comparison processing unit 250 by a predetermined multiplier (for example, 3 times). The digital multiplication circuit 292 outputs the generated multiplied digital code.

[0078] Selector 293 is a circuit that switches the digital code supplied to the DAC110, which is the upper-level DAC of the main ADC101. The digital code supplied to the DAC110 from the main ADC101 is switched according to the voltage value corresponding to the output data.

[0079] For example, if the voltage value corresponding to the output data is high voltage, the selector 293 selects and outputs the unmultiplied digital code output from the successive comparison processing unit 250. On the other hand, if the voltage value corresponding to the output data is low voltage, the selector 293 selects and outputs the multiplied digital code output from the digital multiplication circuit 292. The digital code selected by the selector 293 is supplied to the higher-level DAC 110 after its voltage level is shifted by the level shifter 75.

[0080] Selector 191 is a circuit that switches the reference voltage supplied to the higher-level DAC110. The reference supplied to the higher-level DAC110 is switched according to the conversion accuracy required for the digital conversion of the analog input signal.

[0081] For example, when medium-precision conversion accuracy is required, selector 191 selects and outputs a low-voltage reference. In this case, the upper DAC 110 and lower DAC 20 are supplied with references at the same potential.

[0082] On the other hand, when high-precision conversion accuracy is required, selector 191 selects and outputs a high-voltage reference. The reference selected by selector 293 is supplied to the upper DAC 110. In this case, similar to Embodiment 1, a high-potential reference is supplied to the upper DAC 110, and a low-voltage reference is supplied to the lower DAC 20.

[0083] According to this embodiment, when medium-precision conversion accuracy is required, the upper DAC110 and lower DAC20 are supplied with references of the same voltage, enabling high-speed digital conversion. On the other hand, when high-precision conversion accuracy is required, the upper DAC110 is supplied with a high-voltage reference, and the lower DAC20 is supplied with a low-voltage reference, improving the accuracy of digital conversion. In this way, a single ADC1B can be given the mutually contradictory characteristics of improved digital conversion speed and improved accuracy.

[0084] (Embodiment 4) Next, Embodiment 4 will be described. This embodiment describes a multi-channel ADC system using the ADC according to the embodiment described above. Such a multi-channel ADC system is mounted on, for example, an MCU (Memory Control Unit) or a SoC (System-on-a-chip).

[0085] First, the ADC that forms the basis of the multi-channel ADC system of this embodiment will be described. Figure 10 is a diagram illustrating the ADC that forms the basis of the multi-channel ADC system according to Embodiment 4 of the present invention. Figure 10(a) shows a conventional ΔΣ ADC, and Figure 10(b) shows the base ADC.

[0086] In conventional ΔΣADCs, integrating each input signal with a common analog integrator causes interference between channels, requiring a separate ΔΣADC for each channel. On the other hand, the ADCs according to the aforementioned embodiments (hereinafter also referred to as HybridADCs) use a DAC-type integrator, allowing the integrator's output data to be handled in the digital domain. HybridADCs prevent interference between channels by providing a register for the integration data for each channel.

[0087] Figure 11 illustrates the configuration of a multi-channel ADC system according to Embodiment 4 of the present invention. Figure 11(a) shows a 2-input, 1-output multi-channel ADC system 401. The multi-channel ADC system 401 is provided with a selector for selecting the input channels. For this reason, the multi-channel ADC system 401 is provided with one integrator register 411 corresponding to one input. Alternatively, the multi-channel ADC system 401 may be provided with two integrator registers corresponding to each of the two channels.

[0088] Figure 11(b) shows a 3-input, 3-output multi-channel ADC system 451. In the configuration shown in Figure 1(b), A / D conversion is performed in parallel for multiple input channels. For this reason, the multi-channel ADC system 451 is provided with three integrator registers 461 to 463, each corresponding to one of the three input channels.

[0089] According to this embodiment, each analog input signal from multiple channels can be digitally converted by a single ADC. This reduces the area of ​​the ADC compared to a ΔΣ ADC. Furthermore, because the amount of data in the integrator register is small, the area of ​​the integrator register can be reduced, thus suppressing the increase in power consumption.

[0090] (Embodiment 5) Next, Embodiment 5 will be described. In this embodiment, a method for performing sampling of multiple channels in parallel in a multi-channel ADC system will be described.

[0091] Figure 12 illustrates a sampling method according to Embodiment 5 of the present invention. Figure 12 shows an example in which sampling of 5 channels (CH1 to CH5) is performed in parallel. Here, sampling is performed in oversampling mode for CH1 to CH3, and in Nyquist mode for CH4 to CH5. In oversampling mode, sampling needs to be performed periodically, whereas in Nyquist mode, sampling can be performed intermittently as needed.

[0092] In this example, four A / D conversion sequences (corresponding to four blocks in Figure 12) are grouped together. The first three A / D conversions are assigned to the oversampling mode channels (CH1-CH3), and the fourth A / D conversion is assigned to the Nyquist mode channel (CH4 or CH5). In other words, the Nyquist mode A / D conversions are assigned in between the oversampling mode A / D conversions.

[0093] Oversampling A / D conversion requires a significant initial delay before obtaining a normal output. This is because many A / D conversions are needed to fill all the taps of the digital filter. Traditionally, a large initial delay had to be waited each time a channel was switched.

[0094] In contrast, in this embodiment, A / D conversion is always performed continuously, so there is no waiting time for the initial response. Furthermore, while an A / D converter operating in Nyquist mode is required to operate intermittently as needed, a system that achieves such operation can be constructed by performing channel allocation as shown in Figure 12.

[0095] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0096] 1, 1A, 1B...ADC, 10, 110...Upper DAC, 20...Lower DAC, 30...Injection DAC, 40, 240...Comparator, 50, 250...Successive comparison processing unit, 61, 62...MES register, 101...Main ADC, 160...MES section, 201...Sub ADC, 210...Sub Upper DAC, 220...Sub Lower DAC.

Claims

1. A semiconductor device that performs digital conversion of an analog input signal by successive comparison of the analog input signal and a reference voltage, A main ADC that performs digital conversion of the analog input signal in the low-voltage region, A sub-ADC that performs digital conversion of the analog input signal in the high-voltage region, Equipped with, The aforementioned main ADC is A higher-level DAC that generates a high-voltage region of the reference voltage based on a predetermined code, A lower-level DAC that generates a low-voltage region of the reference voltage based on the code, The MES section holds the lower bits of the digital code generated in the previous sampling cycle, Equipped with, The aforementioned sub-ADC is A sub-higher-level DAC that generates a high-voltage region of the reference voltage based on a predetermined code, A sub-lower DAC that generates a low-voltage region of the reference voltage based on the code, Equipped with, The aforementioned sub-higher DAC operates with a low-voltage reference that is less than or equal to the voltage of the reference supplied to the higher DAC. The higher-level DAC is supplied with the higher bits of the digital code generated using the sub-higher-level DAC. The MES unit, during the sampling period within the current sampling cycle, supplies the lower bits of the digital code generated in the previous sampling cycle to both the lower DAC and the sub-lower DAC. Semiconductor equipment.

2. In the semiconductor device described in claim 1, When the aforementioned analog input signal is converted to digital with medium precision, a low-voltage reference is supplied to the higher-level DAC. When performing the digital conversion of the aforementioned analog input signal with high precision, a high-voltage reference is supplied to the higher-level DAC. Semiconductor equipment.

3. In the semiconductor device described in claim 2, The system includes a digital multiplication circuit that calculates second data by digitally multiplying the first data, which is the upper bits of the digital code generated using the aforementioned sub-upper-order DAC, by a predetermined value. The above-level DAC is selectively supplied with either the first data or the second data. Semiconductor equipment.

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