Injection molded solder head with improved sealing performance

Abstract

An apparatus is provided for injecting solder material into via holes located on a top surface of a wafer. The apparatus includes an injection head having a contact surface for contacting the top surface of the wafer and at least one opening for injecting the solder material through the injection head into the via holes. The apparatus further includes an exhaust device connected to the injection head for exhausting gas from the via holes. The injection head has a chamfer on an edge of the contact surface that contacts the top surface of the wafer.

Description

Technical Field

[0006]

[0001] The present invention generally relates to integrated circuits, and more particularly to an injection molded solder head having improved sealing performance.

Background Art

[0002] Injection Molded Solder (IMS) technology is a solder bump technology in the field of electronic packaging. In this technology, solder bumps are created by injecting molten solder into vias formed in a photoresist layer on a silicon wafer.

[0003] One of the problems with fine-pitch bumps in IMS is the variation in solder bump height. As the pitch of the bumps decreases, the height of the bumps also decreases. Therefore, even a slight height variation at the micron level becomes significant. Variation in bump height leads to electrical short circuits, poor solder wetting of interconnects, and other mechanical defects.

[0004] The IMS head is made of rubber covered with a thin PTFE sheet. As a result of surface analysis of the IMS head, it was found that the surface roughness of the IMS head can reach several tens of microns at room temperature. Since the height of the solder bump is determined by scraping the molten solder by the IMS head surface, the surface roughness of the head is directly reflected in the variation of the solder bump height.

[0005] Another problem with fine-pitch IMS is the missing solder in the vias. Injecting molten solder into small holes becomes increasingly difficult due to the surface tension of the molten solder and the residual gas pressure in the vias.

[0006] One solution to this problem is to increase the injection pressure. However, increasing the injection pressure also requires increasing the load on the head to prevent solder leakage. Increasing the load improves the vacuum sealing, thus reducing the residual gas pressure in the vias. However, a higher load increases the friction between the head and the wafer, accelerating the deterioration of the head's rubber. [Overview of the project]

[0007] According to an aspect of the present invention, an apparatus for injecting solder material into via holes located on the upper surface of a wafer is provided. The apparatus includes an injection head having a contact surface for contacting the upper surface of the wafer and at least one opening for injecting solder material into via holes through the injection head. The apparatus further includes an exhaust device connected to the injection head for exhausting gas from the via holes. The injection head has a chamfered portion on the edge of the contact surface that contacts the upper surface of the wafer.

[0008] According to another aspect of the present invention, an apparatus for injecting solder material into via holes located on the upper surface of a wafer is provided. The apparatus includes an injection head having a contact surface for contacting the upper surface of the wafer and a plurality of openings for injecting solder material from one or more solder baths of the injection head into via holes. The apparatus further includes an exhaust device connected to the injection head for exhausting gas from the via holes. The injection head has a chamfered portion on the edge of the contact surface that contacts the upper surface of the wafer and at least one chamfered portion that contacts at least one of the plurality of openings.

[0009] According to another aspect of the present invention, a method is provided for injecting solder material into via holes located on the upper surface of a wafer. The method includes exhausting gas from the via holes with an exhaust device. The method further includes injecting solder material into the via holes by an injection head connected to the exhaust device and having a contact surface for contacting the upper surface of the wafer and at least one opening for solder injection to form a solder bump. The method also includes moving the injection head so as to move the chamfered edge of the injection head over the solder bump to grind the solder bump to an intended height.

[0010] According to another aspect of the present invention, a method is provided for injecting solder material into via holes located on the upper surface of a wafer. The method includes exhausting gas from the via holes with an exhaust device. The method further includes injecting solder material into the via holes by an injection head connected to the exhaust device and having a contact surface for contacting the upper surface of the wafer and a plurality of openings for solder injection to form one or more solder bumps. The method also includes moving the injection head such that the chamfered edge of the injection head moves over one or more solder bumps to grind the one or more solder bumps to a desired height.

[0011] These and other features and advantages will become apparent from the following detailed description of exemplary embodiments, which should be read in conjunction with the accompanying drawings.

[0012] The following description details preferred embodiments with reference to the following figures. [Brief explanation of the drawing]

[0013] [Figure 1] This is a block diagram showing an exemplary computing device according to an embodiment of the present invention. [Figure 2] This figure shows an exemplary injection-molded solder (IMS) head on a semiconductor device according to an embodiment of the present invention. [Figure 3] This figure shows a bottom view of the IMS head shown in Figure 2, according to an embodiment of the present invention. [Figure 4] This figure shows another bottom view of the IMS head shown in Figure 2, according to an embodiment of the present invention. [Figure 5] This figure shows yet another bottom view of the IMS head shown in Figure 2, according to an embodiment of the present invention. [Figure 6] This figure shows yet another bottom view of the IMS head shown in Figure 2, according to an embodiment of the present invention. [Figure 7] This figure shows the modified rear end of the IMS head according to an embodiment of the present invention. [Figure 8] This figure shows another modified rear end of the IMS head according to an embodiment of the present invention. [Figure 9] This figure shows another modified rear end of the IMS head according to an embodiment of the present invention. [Figure 10] This figure shows another modified rear end of the IMS head according to an embodiment of the present invention. [Figure 11] This figure shows another modified rear end of the IMS head according to an embodiment of the present invention. [Figure 12] This figure shows the low-friction layer of an IMS head according to an embodiment of the present invention. [Figure 13] This is a flowchart illustrating an exemplary method for injecting solder material into via holes located on the upper surface of a wafer, according to embodiments of the present invention. [Figure 14] This flowchart illustrates another exemplary method for injecting solder material into via holes located on the upper surface of a wafer, according to embodiments of the present invention. [Figure 15] This figure shows yet another bottom view of the IMS head shown in Figure 2, according to an embodiment of the present invention. [Figure 16] This figure shows a modified example of Figure 4, which has one solder injection slit and one vacuum application slit according to an embodiment of the present invention. [Modes for carrying out the invention]

[0014] Embodiments of the present invention relate to an injection molding solder (IMS) head having improved sealing performance.

[0015] The original IMS head has a rectangular edge. It has been found that chamfering can improve the sealing at the edge of the head because chamfering locally increases the vertical stress at the edge. One or more embodiments of the present invention use chamfered edges to solve the two problems described in the background section.

[0016] Regarding the variation in solder bump height, since a high level of vacuum was determined to improve the variation in solder bump height, in embodiments of the present invention, chamfered edges are applied to seal the space between the head and the wafer to improve the vacuum performance. It has also been determined that the higher the contact pressure, the more the variation in bump height is improved. The high vertical stress of the chamfered edge can also be used to flatten the molten solder by shaving.

[0017] [[ID=第十三条]]Regarding the missing solder in the via, embodiments of the present invention add a second injection slit to correct the missing solder in the via. Since a high level of vacuum is required to actuate the second injection slit, in embodiments of the present invention, the edges are chamfered to obtain excellent sealing. Embodiments of the present invention also create a head surface with different roughnesses, creating a rough surface for good conductance and a smooth surface for good sealing.

[0018] FIG. 1 is a block diagram showing an exemplary computing device 100 according to an embodiment of the present invention. The computing device 100 can be used to control an integrated circuit manufacturing line or a portion of a manufacturing line. This computing device 100 is configured to provide an injection molding solder head having improved sealing performance.

[0019] Computing device 100 may be embodied as an unspecified type of computation or computer device capable of performing the functions described herein, and this device includes, but is not limited to, computers, servers, rack-based servers, blade servers, workstations, desktop computers, laptop computers, notebook computers, tablet computers, mobile computing devices, wearable computing devices, network devices, web devices, distributed computing systems, processor-based systems, or consumer electronics devices, or combinations thereof. Additionally or alternatively, computing device 100 may be embodied as one or more computer threads, memory threads, or other components of a rack, thread, computing chassis, or other physically separate computing device. As shown in Figure 1, computing device 100 exemplifies a processor 110, an input / output subsystem 120, memory 130, a data storage device 140, and a communications subsystem 150, or other components and devices commonly found in servers and similar computing devices, or combinations thereof. Naturally, in other embodiments, the computing device 100 may include other or additional components commonly found in server computers (e.g., various input / output devices). In addition, in some embodiments, one or more of the exemplary components may be incorporated into another component or form part of another component. For example, in some embodiments, the memory 130 or a part thereof may be incorporated into the processor 110.

[0020] The processor 110 may be embodied as an unspecified type of processor capable of performing the functions described herein. The processor 110 may be embodied as a single processor, multiple processors, one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more core processors, one or more digital signal processors, one or more microcontrollers, or one or more other processors or processing / control circuits.

[0021] Memory 130 may be embodied as an unspecified type of volatile or non-volatile memory or data storage capable of performing the functions described herein. During operation, memory 130 may store various data and software used during the operation of the computing device 100, such as operating systems, applications, programs, libraries, and drivers. Memory 130 is communicatively coupled to the processor 110 via an input / output subsystem 120, which may be embodied as a circuit or component, or both, to facilitate input / output operations with the processor 110, memory 130, and other components of the computing device 100. For example, the input / output subsystem 120 may be embodied as a memory controller hub, an input / output control hub, a platform controller hub, an integrated control circuit, a firmware device, a communication link (e.g., a point-to-point link, a bus link, wires, cables, optical conduits, printed circuit board traces, etc.), or other components and subsystems, or combinations thereof, to facilitate input / output operations. In some embodiments, the input / output subsystem 120 may form part of a system-on-a-chip (SOC) and be integrated onto a single integrated circuit chip together with the processor 110, memory 130, and other components of the computing device 100.

[0022] The data storage device 140 may be embodied as one or more unspecified types of devices configured for short-term or long-term storage of data, such as memory devices and circuits, memory cards, hard disk drives, fixed drives, or other data storage devices. The data storage device 140 can store program code for providing injection-molded solder heads with improved sealing performance. The communication subsystem 150 of the computing device 100 may be embodied as any network interface controller or other communication circuits, devices, or sets thereof that can enable communication between the computing device 100 and other remote devices on the network. The communication subsystem 150 may be configured to bring about such communication using any one or more communication technologies (e.g., wired or wireless communication) and associated protocols (e.g., Ethernet(R), InfiniBand(R), Bluetooth(R), Wi-Fi(R), WiMAX, etc.).

[0023] As illustrated, the computing device 100 may also include one or more peripheral devices 160. The peripheral devices 160 may include any number of additional input / output devices, interface devices, or other peripheral devices or combinations thereof. For example, in some embodiments, the peripheral devices 160 may include a display, a touch screen, graphics circuitry, a keyboard, a mouse, a speaker system, a microphone, a network interface, or other input / output devices or combinations thereof, interface devices, or peripheral devices or combinations thereof.

[0024] Naturally, the computing device 100 may include other elements (not shown), and may omit certain elements, as can be easily conceived by those skilled in the art. For example, various other input devices or output devices, or both, may be included in the computing device 100 depending on their specific implementation, as can be easily understood by those skilled in the art. For example, various types of wireless or wired or both input or output devices, or both, can be used. Additional processors, controllers, memory, etc., can also be used in various configurations. These and other variations of the processing system 100 will be easily conceived by those skilled in the art, considering the teachings of the present invention as described herein.

[0025] Where adopted herein, the terms “hardware processor subsystem” or “hardware processor” may refer to a processor, memory (including RAM, cache(s), etc.), software (including memory management software), or a combination thereof, working together to perform one or more specified tasks. In useful embodiments, a hardware processor subsystem may include one or more data processing elements (e.g., logic circuits, processing circuits, instruction execution devices, etc.). One or more data processing elements may be included in a central processing unit, a graphics processing unit, or a separate processor or computing element-based controller (e.g., logic gates, etc.), or a combination thereof. A hardware processor subsystem may include one or more onboard memories (e.g., caches, dedicated memory arrays, read-only memory, etc.). In some embodiments, a hardware processor subsystem may be onboard or offboard, or may include one or more memories that are exclusively available to the hardware processor subsystem (e.g., ROM, RAM, basic input / output system (BIOS), etc.).

[0026] In some embodiments, the hardware processor subsystem includes and can execute one or more software elements. These one or more software elements may include an operating system, one or more applications, or specified code, or a combination thereof, to achieve a specified result.

[0027] In other embodiments, the hardware processor subsystem may include specialized circuits dedicated to performing one or more electronic processing functions to achieve a specified result. Such circuits may include one or more application-specific integrated circuits (ASICs), FPGAs, or PLAs, or a combination thereof.

[0028] These and other variations of the hardware processor subsystem are also conceived by embodiments of the present invention.

[0029] Figure 2 shows an exemplary injection-molded solder (IMS) head 200 on a semiconductor device 250 according to an embodiment of the present invention.

[0030] The semiconductor device 250 is on a substrate or wafer 260 Includes , The IMS head is the head body 270 and solder Injection slit 211 and 212 And, vacuum Indication slit 291 and Includes. Element 291 is vacuum Indication slit It is considered that all vias to be filled with solder are first subjected to vacuum, and then the IMS head ga u Ehh 260 As it moves along the surface, the IMS head fills the solder.

[0031] IMS Head Main unit 270 These are solder injection slits 211 and 212 and vacuum application slit 2 9It includes a first solder bath 231, a second solder bath 232, and a vacuum line 244. As shown separately for illustrative purposes, the vacuum line 244 is part of the IMS head 200, as shown in Figures 2 and 3.

[0032] The required pressures include solder pressure 201, solder pressure 202, vacuum 203, and head pressure 204.

[0033] Figure 3 is a bottom view of the IMS head 200 shown in Figure 2, according to an embodiment of the present invention.

[0034] In this figure, the IMS head 200 includes solder injection slits 211 and 212, a vacuum application slit 221, a Si rubber 320, and a chamfered portion 311. A coupled thermomechanical analysis of the IMS head 200 was performed to show scraping by the chamfered edge. The chamfered edge bites into the vias that define the solder height. Since the surface variation at the chamfered edge is smaller than the variation across the entire head surface, the variation in solder height is reduced. In Figure 3, the chamfered portion location is shown as in the other figures, but the actual chamfer is not shown in order to focus on other faces in the figure. Exemplary chamfer configurations are shown and described in detail in Figures 7 to 11.

[0035] Figure 4 is a bottom view of the IMS head 200 shown in Figure 2, according to an embodiment of the present invention.

[0036] In this diagram, the IMS head 200 has solder injection slits 211 and 212, a vacuum application slit 221, and a high average roughness region 41 2 And, low average roughness range 41 1 This includes the chamfered portion 321.

[0037] High mean roughness region 41 2 This corresponds to a high average roughness surface for better conductance. High average roughness region 41 2These can be formed from, for example, Si rubber, polytetrafluoroethylene (PTFE), polyetherimide (PEI), polyetheretherketone (PEEK), polybenzimidazole (PBI), polydicyclopentadiene (PDCPD), and epoxy (EP), but are not limited to these. An exemplary high average roughness region 412 may require an average surface roughness in the range of 32 to 400 microinches (0.8128 to 10.16 μm). The low average roughness region 412 corresponds to a high-stress region with a smooth surface for good sealing properties. Low average roughness region 41 1 These can be formed from low-friction materials, including, but not limited to, polytetrafluoroethylene (PTFE), polyetherimide (PEI), polyetheretherketone (PEEK), polybenzimidazole (PBI), polydicyclopentadiene (PDCPD), and epoxy (EP). Exemplary low average roughness region 41 1 This may require an average surface roughness in the range of 8 to 32 microinches (0.2032 to 0.8128 μm).

[0038] The contact surface can be roughened to minimize friction with the solder ball. Although the solder ball is liquid, it is desirable to prevent wicking along the chamfered surface. If the surface roughness is low (for example, less than approximately 32 microinches (0.8128 μm)), wicking can be minimized.

[0039] In addition, the material options preferably include a dielectric coating. The dielectric coating may include polytetrafluoroethylene (PTFE), polyethylene, or other materials that have a low coefficient of friction and can withstand soldering temperatures without degradation.

[0040] The chamfering, rounding, or both should be sized and configured in such a way as to maintain the surface tension of the solder ball. For example, in one embodiment, the chamfer angle θ can be an acute angle ranging from about 1 degree to about 60 degrees.

[0041] In other embodiments, a non-linear profile or radius is employed, either with or in addition to the chamfer. In one embodiment, the radius is a percentage of the radius of the solder ball, for example, in the range of 10 to 500%, and is between approximately 0.25 and 7.5 mm.

[0042] Figure 5 shows yet another bottom view of the IMS head 200 of Figure 2, according to an embodiment of the present invention.

[0043] In this figure, the IMS head 200 includes solder injection slits 511 and 212, a vacuum application slit 221, and a chamfered portion 321.

[0044] In Figure 5, the solder injection slit 511 is smaller in size than the solder injection slit 212, which works well because it only requires enough solder to correct streaks or other small defects, or a combination thereof, in the initial application. That is, after the primary solder material is deposited in the solder injection slit 212, the secondary solder material is deposited in the solder injection slit 511.

[0045] Figure 6 shows yet another bottom view of the IMS head 200 of Figure 2, according to an embodiment of the present invention.

[0046] In this figure, the IMS head 200 includes solder injection slits 211 and 212, a vacuum application slit 221, and a chamfered portion 321.

[0047] The embodiment in Figure 6 differs from the embodiment in Figure 3 in that different solder materials are used for the solder injection slits 211 and 212. For example, the various solder materials that can be used include, but are not limited to, lead-free solders using tin, indium, tin alloys, or indium alloys containing Ag, Sn, In, Bi, Cu, Sb, Zn, Ni, Pd, Co, Ge, Au, or Fe or combinations thereof.

[0048] Depending on the properties of different solder materials (e.g., viscosity), different filling pressures can be used for different solder materials.

[0049] Figure 7 shows a modified rear end portion 700 of the IMS head according to an embodiment of the present invention.

[0050] The modified rear end portion 700 includes a straight edge chamfer 710. The angle θ ranges from 1 to 60 degrees.

[0051] Wafer 730 and photoresist 740 are also shown.

[0052] Figure 8 shows another modified rear end portion 800 of the IMS head according to an embodiment of the present invention.

[0053] The modified rear end 800 includes a straight section 810 and a section 820 with a radius r = 0.25 mm, for example.

[0054] Wafer 830 and photoresist 840 are also shown.

[0055] Figure 9 shows another modified rear end portion 900 of the IMS head according to an embodiment of the present invention.

[0056] The modified rear end 900 includes a straight section 910 and a rounded section 920 with a radius r = 0.5 mm. The rounded section 920 is twice the size of the rounded section 810.

[0057] Wafer 930 and photoresist 940 are also shown.

[0058] Figure 10 shows another modified rear end portion 1000 of the IMS head according to an embodiment of the present invention.

[0059] The modified rear end 1000 includes a rounded portion 1010 with a radius r = 3.914 mm.

[0060] Wafer 1030 and photoresist 1040 are also shown.

[0061] Figure 11 shows another modified rear end portion 1100 of the IMS head according to an embodiment of the present invention.

[0062] The modified rear end portion 1100 includes a rounded portion 1110 with a radius r = 7.5 mm.

[0063] Wafer 1130 and photoresist 1140 are also shown.

[0064] Figure 12 shows a low-friction layer 412 of an IMS head according to an embodiment of the present invention.

[0065] In addition to the bottom surface, the low-friction layer 412 is formed on the sidewalls, including a chamfered area 1217, to minimize the problem of delamination from the rubber 411 (high-friction area) attached to the metal 1266. The injection slit is indicated by reference no. 1255.

[0066] Figure 13 is a flowchart illustrating an exemplary method 1300 for injecting solder material into via holes located on the upper surface of a wafer, according to an embodiment of the present invention.

[0067] In block 1310, the IMS head is moved over the via hole to be processed.

[0068] In block 1320, the exhaust device of the IMS head discharges gas from the via hole.

[0069] In block 1330, solder material is injected into via holes by an injection head connected to an exhaust device and having a contact surface for contacting the upper surface of the wafer and at least one opening for solder injection to form solder bumps.

[0070] In block 1340, move the injection head, moving the chamfered edge of the injection head over the solder bump to shave the solder bump down to the desired height. Move the injection head from via to via, machining the via as described.

[0071] Figure 14 is a flowchart showing another exemplary method 1400 for injecting solder material into via holes located on the upper surface of a wafer, according to an embodiment of the present invention.

[0072] In block 1410, the IMS head is moved over the via hole to be processed.

[0073] In block 1420, the exhaust device of the IMS head discharges gas from the via holes.

[0074] In block 1430, solder material is injected into via holes by an injection head connected to an exhaust device and having a contact surface for contacting the upper surface of the wafer and a plurality of openings for solder injection to form one or more solder bumps.

[0075] In one embodiment, the multiple openings may include at least a first opening and a second opening, and different filling pressures may be used for the first and second openings.

[0076] In one embodiment, each of the multiple openings can be connected to a common solder bath. In another embodiment, each of the multiple openings can be connected to one of each of the multiple solder baths.

[0077] In one embodiment, the solder material may include a first solder material and a second solder material different from the first solder material. The first solder material can be injected into a first opening, and the second solder material can be injected into a second opening to form a solder bump consisting of the first and second solder materials.

[0078] In block 1440, the injection head is moved so that the chamfered edge of the injection head moves over the solder bumps to machine the solder bumps to the intended height. One or more solder bumps are machined to reduce variations in solder height relative to at least one of the other solder bumps between them. The injection head moves from via to via to machine the vias as described.

[0079] Figure 15 shows yet another bottom view of the IMS head 200 of Figure 2, according to an embodiment of the present invention.

[0080] In comparison with a modified example of the IMS head 200 shown in Figure 4, there is no high average roughness region on the back of the second slit 211. Instead, region 413 is a low average roughness region.

[0081] Figure 16 shows a modified example 1600 of Figure 4, which has one solder injection slit 1511 and one vacuum application slit 1521, according to an embodiment of the present invention.

[0082] Each of the embodiments described herein that include two solder injection slits can also be modified to include a single solder injection slit and a single vacuum application slit, as shown in Figure 16. These and other modifications of the present invention will be readily conceivable to those skilled in the art, given the teachings of the invention described herein.

[0083] The present invention may be a computer program product or combination thereof at any possible technical level of detail of a system, method, or integration. The computer program product may include one or more computer-readable storage media having computer-readable program instructions for causing a processor to perform an aspect of the present invention.

[0084] A computer-readable storage medium can be a tangible device capable of holding and storing instructions used by an instruction execution device. A computer-readable storage medium may, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. A non-exclusive list of more specific examples of computer-readable storage media includes, but is not limited to, portable computer diskettes, hard disks, random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random-access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital general-purpose disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or grooved raised structures on which instructions are recorded, and any suitable combination thereof. The computer-readable storage media used herein are not considered transient signals in themselves, such as radio waves, other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through optical fiber cables), or electrical signals transmitted through wires.

[0085] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or they can be downloaded to an external computer or external storage device via a network such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transfers the computer-readable program instructions for storage on a computer-readable storage medium within each computing / processing device.

[0086] The computer-readable program instructions for performing the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as the C programming language or a similar programming language. The computer-readable program instructions may run entirely on the user's computer, partially on the user's computer, or as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through an unspecified network, including a local area network (LAN) or wide area network (WAN), or it may be connected to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing state information of computer-readable program instructions to individually configure the electronic circuit in order to perform an aspect of the present invention.

[0087] Aspects of the present invention will be described herein with reference to flowcharts or block diagrams, or both, of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block in a flowchart or block diagram, or both, and combinations of blocks in a flowchart or block diagram, or both, are implemented by computer-readable program instructions.

[0088] These computer-readable program instructions are provided to the processors of general-purpose computers, special-purpose computers, or other programmable data processing devices for producing machines, so that when the instructions are executed via the processor of a computer or other programmable data processing device, they create means for performing functions / actions specified in one or more blocks of a flowchart or block diagram, or both. These computer-readable program instructions can also be stored in computer-readable storage media that can be directed to a computer, programmable data processing device, or other device, or a combination thereof, to function in a particular way, so that computer-readable storage media storing instructions include products containing instructions that perform modes of functions / actions specified in one or more blocks of a flowchart or block diagram, or both.

[0089] Furthermore, computer-readable program instructions are implemented on a computer, other programmable data processing device, or other device, and a series of operational steps are performed on the computer, other programmable device, or other device to generate a process implemented on the computer, so that instructions executed on the computer, other programmable device, or other device perform the functions / actions specified in one or more blocks of a flowchart or block diagram, or both.

[0090] The flowcharts and block diagrams in the figures illustrate the architecture, functions, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or part of an instruction, which contains one or more executable instructions for performing a specified logical function. In some alternative implementations, the functions described in a block may occur out of the order shown in the figure. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may be executed in reverse order depending on the related functions. It should also be noted that each block in a block diagram or flowchart, or both, and any combination of blocks in a block diagram or flowchart, or both, can be implemented by a special-purpose hardware-based system that performs a specified function or operation, or executes a combination of special-purpose hardware and computer instructions.

[0091] When the Specification refers to “one embodiment” or “a certain embodiment” of the Invention, as well as other modifications, it means that certain features, structures, characteristics, etc., described in relation to the embodiments are included in at least one embodiment of the Invention. Therefore, the phrase “in one embodiment” or “a certain embodiment,” as well as any other modifications appearing in various places throughout this Specification, do not necessarily all refer to the same embodiment.

[0092] Please understand that in the following cases, for example, “A / B,” “A or B or both,” and “at least one of A and B,” the use of any of “ / ,” “or both,” and “at least one of” is intended to encompass the selection of only the first-listed option (A), or only the second-listed option (B), or both options (A and B). As further examples, in the cases of “A, B, or C or a combination thereof” and “at least one of A, B, and C,” such expressions are intended to encompass the selection of only the first-listed option (A), or only the second-listed option (B), or only the third-listed option (C), or only the first and second-listed options (A and B), or only the first and third-listed options (A and C), or only the second and third-listed options (B and C), or all three options (A, B, and C). This can be expanded to the number of items listed, as can be easily understood by those skilled in the art in this field and related fields.

[0093] While preferred embodiments of the system and method (intended to be illustrative and not limiting) have been described, it should be noted that modifications and variations may be made by those skilled in the art in light of the above teachings. Therefore, it should be understood that modifications may be made in specific embodiments disclosed that fall within the scope of the invention outlined by the appended claims. Thus, while aspects of the invention have been described in detail and specificity as required by patent law, what is claimed and desired and protected by the patent is described in the appended claims.

Claims

1. An apparatus for injecting solder material into via holes located on the upper surface of a wafer, wherein the apparatus: The injection head has a contact surface for contacting the upper surface of the wafer and at least one opening for injecting the solder material into the via hole through the injection head, To discharge gas from the via hole, the system includes an exhaust device connected to the injection head, The injection head has a chamfered portion on the edge of the contact surface that contacts the upper surface of the wafer, The contact surface includes a high average roughness region adjacent to the at least one opening and a low average roughness region surrounding the high average roughness region, wherein the low average roughness region has a lower average roughness than the high average roughness region. Device.

2. The apparatus according to claim 1, wherein the chamfered portion is located on the outer circumference of the injection head.

3. The apparatus according to claim 1, wherein the opening is slit-shaped, and the chamfered portion is positioned on the outer circumference of the injection head on the side of the at least one opening, parallel to the at least one opening.

4. The apparatus according to claim 1, wherein the chamfered portion is located on the trailing edge of the injection head in the forward direction of movement.

5. The apparatus according to claim 1, wherein the chamfered portion of the chamfered part is composed of a straight edge.

6. The apparatus according to claim 1, wherein the chamfered portion of the chamfered part includes a rounded portion.

7. The apparatus according to claim 1, wherein the opening of the injection head includes a first opening and a second opening.

8. The apparatus has at least one soldering bath, The apparatus according to claim 7, wherein the first opening and the second opening are connected to a common solder bath.

9. The apparatus has a plurality of soldering baths, The apparatus according to claim 7, wherein the first opening and the second opening are each connected to different solder baths.

10. The apparatus according to claim 7, wherein the solder material comprises a first solder material and a second solder material different from the first solder material, the first solder material is injected into the first opening and the second solder material is injected into the second opening to form a solder bump comprising the first solder material and the second solder material.

11. The apparatus according to claim 7, wherein the area of ​​the second opening is smaller than the area of ​​the first opening.

12. The apparatus according to claim 1, wherein the injection head includes at least one chamfered portion that contacts the at least one opening.

13. A method for injecting solder material into via holes located on the upper surface of a wafer to form solder bumps, wherein the method is: The exhaust device discharges the gas from the via hole, An injection head, connected to the exhaust device and having a contact surface for contacting the upper surface of the wafer and at least one opening for solder injection to form the solder bump, wherein the contact surface includes a high average roughness region adjacent to the at least one opening and a low average roughness region surrounding the high average roughness region and having a lower average roughness than the high average roughness region, is used to inject the solder material into the via hole. A method comprising moving the injection head such that the chamfered edge of the injection head moves over the injected solder in order to bring the solder bump to an intended height.

14. The opening of the injection head includes a first opening and a second opening, The method according to claim 13, wherein the solder material comprises a first solder material and a second solder material different from the first solder material, the first solder material is injected into the first opening and the second solder material is injected into the second opening to form a solder bump comprising the first solder material and the second solder material.

15. The opening of the injection head includes a first opening and a second opening, The method according to claim 13, wherein the injection includes injecting the solder material into the via hole through the first opening, and then injecting the solder material into the via hole through the second opening.

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