Semiconductor equipment

Abstract

A semiconductor device 1 comprises multiple semiconductor chips and multiple conductive members including multiple inner leads and multiple connectors. The multiple connectors include individual connectors 51, 52, 53, 61, 62, 63 that connect semiconductor chips (diodes 11, 12, 13, 14, 15, 16) to conductive members on a one-to-one basis. In the semiconductor device 1 of the present invention, the distance and inclination between one semiconductor chip and an individual connector no longer significantly affect the distance and inclination between other semiconductor chips and individual connectors. Therefore, the semiconductor device 1 of the present invention is a semiconductor device that can suppress the occurrence of variations in the connection between semiconductor chips and connectors compared to conventional semiconductor devices.

Description

Cross-reference

[0001] This application claims priority based on Japanese Patent Application No. 2024-114766 filed on July 18, 2024 in Japan, and all the contents described in the application are incorporated herein by reference as they are.

Technical Field

[0002] The present invention relates to a semiconductor device.

Background Art

[0003] Conventionally, a semiconductor device including a plurality of semiconductor chips, a plurality of inner leads, a plurality of connectors, and a sealing resin has been known (see, for example, Patent Document 1). In such a semiconductor device, it is common for a plurality of semiconductor chips to be collectively connected to one connector.

[0004] A conventional semiconductor device 900 includes a plurality of semiconductor chips 911, 912, 913, 914, 915, 916, a plurality of inner leads 921, 922, 923, 924, 925, a plurality of connectors 951, 952, and a sealing resin 970 (see FIG. 3). The conventional semiconductor device 900 can also be expressed as a three-phase bridge diode package.

[0005] In the semiconductor device 900, the semiconductor chips 911, 912, 913 are collectively connected to the connector 951. Also, in the semiconductor device 900, the semiconductor chips 914, 915, 916 are collectively connected to the connector 952.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] Incidentally, in conventional semiconductor devices such as the semiconductor device 900, the distance and inclination between a semiconductor chip and a connector have a significant impact on the distance and inclination between other semiconductor chips connected to the same connector and the connector (see Figure 4, especially Figures 4(b) and 4(d)). Although not shown in the diagram, generally, solder (a conductive bonding material) is used to join the semiconductor chip and the connector. Therefore, the "distance and inclination between the semiconductor chip and the connector" mentioned above can also be expressed as "solder thickness and uniformity of solder thickness between the semiconductor chip and the connector" in semiconductor devices that use solder to join their components.

[0008] Therefore, in semiconductor devices like the one described above, depending on the manufacturing method, the connection quality between one semiconductor chip and a connector may affect the connection quality between other semiconductor chips and connectors, potentially resulting in uncorrectable variations in the connections between semiconductor chips and connectors. These variations can primarily affect the electrical characteristics and heat dissipation of the semiconductor device.

[0009] The present invention has been made in view of the above problems, and aims to provide a semiconductor device that can suppress the occurrence of variations in the connection between a semiconductor chip and a connector compared to conventional semiconductor devices. [Means for solving the problem]

[0010] The semiconductor device of the present invention is a semiconductor device comprising a plurality of semiconductor chips and a plurality of conductive members including a plurality of inner leads and a plurality of connectors, wherein the plurality of connectors include individual connectors that connect the semiconductor chips and the conductive members on a one-to-one basis. [Effects of the Invention]

[0011] In the semiconductor device of the present invention, the plurality of connectors include individual connectors that connect semiconductor chips constituting a plurality of semiconductor chips to conductive members on a one-to-one basis. Therefore, in the semiconductor device of the present invention, the distance and inclination between one semiconductor chip and an individual connector does not significantly affect the distance and inclination between other semiconductor chips and individual connectors. Accordingly, the semiconductor device of the present invention is a semiconductor device that can suppress the occurrence of variations in the connection between semiconductor chips and connectors compared to conventional semiconductor devices. [Brief explanation of the drawing]

[0012] [Figure 1] This figure shows the internal configuration of the semiconductor device 1 according to Embodiment 1. Figure 1(a) is a plan view, Figure 1(b) is a cross-sectional view of Figure 1(a) taken along line A1-A1, and Figure 1(c) is a cross-sectional view of Figure 1(a) taken along line A2-A2. In the drawings, "a diagram showing the internal configuration" refers to a diagram showing the components sealed in the sealing resin. For this reason, in Figure 1, only the outer shape of the sealing resin 70 is shown with a dashed line. Also, in Figure 1(a), components hidden by the individual connectors 51, 52, 53, 61, 62, and 63 are shown with dashed lines. Furthermore, in Figures 1(b) and 1(c), only the parts of the components facing the cross-section are shown, and the parts of the components that are located behind the cross-section and do not face the cross-section (for example, the second outer lead 40B in Figure 1(b)) are not shown. In Figures 2(b), 2(c), and 4, the same method of display as in Figures 1(b) and 1(c) is used. [Figure 2] This figure shows the internal configuration of the semiconductor device 2 according to Embodiment 2. Figure 2(a) is a plan view, Figure 2(b) is a cross-sectional view of Figure 2(a) taken along line A3-A3, and Figure 2(c) is a cross-sectional view of Figure 2(a) taken along line A4-A4. In Figure 2, only the outer shape of the sealing resin 70 is shown with a dashed line. Also, in Figure 2(a), components hidden by the individual connectors 51, 52, 61, and 62 are shown with dashed lines. [Figure 3] This is a plan view showing the internal configuration of a conventional semiconductor device 900. [Figure 4]This is a cross-sectional view of AA in Figure 3. Figure 4(a) is a cross-sectional view showing the connector 952 in an upright position, while Figures 4(b) and 4(c) are cross-sectional views showing the connector 952 in an upright position. Note that in Figures 4(b) and 4(c), the inclination of the connector 952 is exaggerated. Therefore, in Figures 4(b) and 4(c), the connector 952 and the semiconductor chips 914, 915, and 916 may appear to be separated. Normally, a conductive bonding material (not shown) is placed between the connector 952 and the semiconductor chips 914, 915, and 916, so even in the cases shown in Figures 4(b) and 4(c), the connection between the connector 952 and the semiconductor chips 914, 915, and 916 is not necessarily lost. [Modes for carrying out the invention]

[0013] The semiconductor device of the present invention will be described below based on the embodiments shown in the figures. In the embodiments described below, components having exactly the same or substantially the same function will be given common reference numerals in each embodiment, even if their shape or other characteristics differ slightly, and explanations that have already been given may be omitted. The embodiments described below do not limit the invention as defined in the claims. Furthermore, not all of the elements and combinations described in each embodiment are necessarily essential to the solution of the present invention.

[0014] [Embodiment 1] 1. Configuration of the semiconductor device 1 according to Embodiment 1 The semiconductor device 1 according to Embodiment 1 comprises a plurality of semiconductor chips, a plurality of conductive members including a plurality of inner leads and a plurality of connectors, and a sealing resin 70 (see Figure 1). The semiconductor device 1 can also be described as a three-phase bridge diode package. The components of the semiconductor device 1 will be described below.

[0015] The plurality of semiconductor chips includes diodes. The plurality of semiconductor chips includes six diodes 11, 12, 13, 14, 15, and 16 as diodes. The diodes 11, 12, 13, 14, 15, and 16 each have electrodes (not shown) on the surface facing the inner lead and the surface facing the connector. The semiconductor chips (diodes 11, 12, 13, 14, 15, and 16) are placed on inner leads (described later) that constitute a plurality of inner leads.

[0016] In this specification, the "conductive member" refers to a member through which current flows when the semiconductor device is specified. The conductive members include, in addition to the inner leads and the connectors, outer leads, pins, bolts, and the like.

[0017] The plurality of inner leads includes a first common inner lead 20, a plurality of individual inner leads, and a second common inner lead 40. The inner leads that constitute the plurality of inner leads are made of a conductive metal plate (for example, a copper plate). Hereinafter, each inner lead will be described.

[0018] The first common inner lead 20 has a portion 20A that extends along a predetermined first direction D1. The first direction D1 in the semiconductor device 1 is parallel to the long side LS (described later) of the encapsulating resin 70. At least two semiconductor chips are placed on the first common inner lead 20 in a state of being arranged along the first direction D1. Three diodes 11, 12, and 13 are placed on the first common inner lead 20.

[0019] In this specification, "a semiconductor chip is placed on an inner lead" means that the semiconductor chip is fixed to the inner lead in a state where the inner lead and the electrode of the semiconductor chip are electrically connected. The semiconductor chip is preferably fixed to the inner lead by a conductive bonding material (so-called "solder (including lead-free solder)") (not shown).

[0020] The first common inner lead 20 is connected to a first outer lead 20B, one end of which is exposed outside the sealing resin 70. The first outer lead 20B in Embodiment 1 extends along a direction substantially perpendicular to the first direction D1 when viewed in plan. In Embodiment 1, the first common inner lead 20 and the first outer lead 20B are integral. Therefore, it can also be expressed that the first common inner lead 20 and the first outer lead 20B constitute a substantially L-shaped lead as a whole.

[0021] The plurality of individual inner leads are arranged along the first direction D1. The plurality of individual inner leads include three individual inner leads 31, 32, and 33. One diode 14, 15, or 16 is placed on each of the individual inner leads 31, 32, and 33. That is, in Embodiment 1, the diode 14 is placed on the individual inner lead 31, the diode 15 is placed on the individual inner lead 32, and the diode 16 is placed on the individual inner lead 33.

[0022] The individual inner leads 31, 32, and 33 are respectively connected to individual outer leads 31B, 32B, and 33B, one end of which is exposed outside the sealing resin 70. The individual outer leads 31B, 32B, and 33B in Embodiment 1 extend along a direction substantially perpendicular to the first direction Dl when viewed in plan.

[0023] In Embodiment 1, the individual inner leads 31, 32, and 33 and the individual outer leads 31B, 32B, and 33B corresponding to the respective individual inner leads are integral. Therefore, it can also be expressed that the individual inner lead 31 and the individual outer lead 31B constitute one lead as a whole. The same applies to the individual inner lead 32 and the individual outer lead 32B, and the individual inner lead 33 and the individual outer lead 33B as to the individual inner lead 31 and the individual outer lead 31B.

[0024] The second common inner lead 40 is positioned between the first common inner lead 20 and the multiple individual inner leads 31, 32, 33, and has a portion 40A that extends along the first direction D1. The second common inner lead 40 is connected to a second outer lead 40B, one end of which is exposed to the outside of the sealing resin 70.

[0025] In Embodiment 1, the second outer lead 40B extends along a direction substantially perpendicular to the first direction D1 when viewed from above. In Embodiment 1, the second common inner lead 40 and the second outer lead 40B are integrated. Therefore, the second common inner lead 40 and the second outer lead 40B can be described as forming a substantially L-shaped lead as a whole.

[0026] Each connector constituting the multiple connectors is made of a conductive metal plate (e.g., a copper plate). The multiple connectors include individual connectors 51, 52, 53, 61, 62, and 63 that connect semiconductor chips and conductive members on a one-to-one basis. In this specification, the term "conductive member" includes individual connectors, but naturally, a particular individual connector is excluded from the conductive member to which a semiconductor chip is connected. As will be described later, the individual connectors 51, 52, 53, 61, 62, and 63 connect semiconductor chips and inner leads.

[0027] The multiple connectors include a number of individual connectors 51, 52, 53, 61, 62, and 63 equal to the number of semiconductor chips (diodes 11, 12, 13, 14, 15, 16) (6 connectors in total). In Embodiment 1, the multiple connectors can also be described as including 6 individual connectors 51, 52, 53, 61, 62, and 63 corresponding to 6 diodes 11, 12, 13, 14, 15, and 16.

[0028] Individual connectors 51, 52, 53, 61, 62, and 63 connect semiconductor chips (diodes 11, 12, 13, 14, 15, and 16) to inner leads other than the inner leads on which the semiconductor chips are mounted. Individual connectors 51, 52, and 53 connect the semiconductor chips (diodes 11, 12, and 13) mounted on the first common inner lead 20 to individual inner leads 31, 32, and 33 on a one-to-one basis. Individual connectors 51, 52, and 53 are each positioned to straddle the second common inner lead 40 and are not connected to the second common inner lead 40. In addition, individual connectors 61, 62, and 63 connect the semiconductor chips (diodes 14, 15, and 16) mounted on individual inner leads 31, 32, and 33 to the second common inner lead 40 on a one-to-one basis.

[0029] In this specification, "to connect" means to connect electrically. Furthermore, with respect to a connector, "one-to-one connection" means that the connector electrically connects two components and is not electrically connected to anything else. It is preferable to use a conductive bonding material (not shown) for the connection using the connector.

[0030] Each individual connector 51, 52, 53, 61, 62, 63 has first connectors 51a, 52a, 53a, 61a, 62a, 63a that are arranged to cover the semiconductor chip (diodes 11, 12, 13, 14, 15, 16) when viewed from above, and second connectors 51b, 52b, 53b, 61b, 62b, 63b that are narrower than the first connectors 51a, 52a, 53a, 61a, 62a, 63a, protrude from the first connectors 51a, 52a, 53a, 61a, 62a, 63a, and have their tips connected to the conductive member.

[0031] When viewed from above, the semiconductor device 1 is configured such that the portion 40A of the second common inner lead 40 extending along the first direction D1 overlaps with the second connecting portions 51b, 52b, 53b, 61b, 62b, 63b of all individual connectors 51, 52, 53, 61, 62, 63.

[0032] Here, the individual connectors 51, 52, and 53 that connect the semiconductor chips (diodes 11, 12, 13) mounted on the first common inner lead 20 to the individual inner leads 31, 32, and 33 are defined as the first connectors. In addition, the individual connectors 61, 62, and 63 that connect the semiconductor chips (diodes 14, 15, 16) mounted on the individual inner leads 31, 32, and 33 to the second common inner lead 40 are defined as the second connectors.

[0033] In this case, the second connecting parts 51b, 52b, and 53b of the first connectors 51, 52, and 53 are adjacent to the second connecting parts 61b, 62b, and 63b of the second connectors 61, 62, and 63 when viewed from above. More specifically, the second connecting part of the first connector is adjacent to the second connecting part of one or two second connectors, and the second connecting part of the second connector is also adjacent to the second connecting part of one or two first connectors.

[0034] In semiconductor device 1, the second connection portion 51b is adjacent to the second connection portion 61b, the second connection portion 61b is adjacent to the second connection portions 51b and 52b, the second connection portion 52b is adjacent to the second connection portions 61b and 62b, the second connection portion 62b is adjacent to the second connection portions 52b and 53b, the second connection portion 53b is adjacent to the second connection portions 62b and 63b, and the second connection portion 63b is adjacent to the second connection portion 53b.

[0035] In semiconductor device 1, when viewed from above, it can be said that the second connection portions 51b, 52b, 53b of the first connectors 51, 52, 53 and the second connection portions 61b, 62b, 63b of the second connectors 61, 62, 63 are arranged alternately. Furthermore, when semiconductor device 1 is viewed from above, the second common inner lead 40 exists without interruption between adjacent second connection portions 51b, 52b, 53b, 61b, 62b, 63b, and there are no other connectors between them.

[0036] Furthermore, there are three second connectors (individual connectors 61, 62, 63) in the semiconductor device 1. The connection points P between the second connectors (individual connectors 61, 62, 63) and the second common inner lead 40 are arranged at equal intervals.

[0037] The sealing resin 70 seals multiple semiconductor chips, a first common inner lead 20, multiple individual inner leads, a second common inner lead 40, and individual connectors 51, 52, 53, 61, 62, and 63. When the semiconductor device 1 is viewed from above, the sealing resin 70 has a shape that can define two parallel long sides LS and two parallel short sides SS that are perpendicular to the long sides LS. The sealing resin 70 can also be described as having a substantially rectangular shape when viewed from above. Note that when considering the long sides and short sides, the presence of additional shapes (notches C in Embodiment 1) is not taken into consideration.

[0038] 2. Effects of the semiconductor device 1 according to Embodiment 1 In the semiconductor device 1 according to Embodiment 1, the plurality of connectors include individual connectors 51, 52, 53, 61, 62, and 63 that connect semiconductor chips (diodes 11, 12, 13, 14) constituting a plurality of semiconductor chips to conductive members on a one-to-one basis. Therefore, in the semiconductor device 1, the distance and inclination between one semiconductor chip and an individual connector does not significantly affect the distance and inclination between other semiconductor chips and individual connectors. Accordingly, the semiconductor device 1 is a semiconductor device that can suppress the occurrence of variations in the connection between semiconductor chips and connectors compared to conventional semiconductor devices.

[0039] Furthermore, in the semiconductor device 1 according to Embodiment 1, the plurality of connectors include individual connectors 51, 52, 53, 61, 62, and 63 in a number equal to the number of semiconductor chips. Therefore, according to the semiconductor device 1 according to Embodiment 1, by connecting all semiconductor chips with individual connectors 51, 52, 53, 61, 62, and 63, it is possible to eliminate the occurrence of hard-to-correct variations in the connection between semiconductor chips and connectors.

[0040] Furthermore, in the semiconductor device 1 according to Embodiment 1, the plurality of semiconductor chips include diodes 11, 12, 13, 14, 15, and 16. Therefore, according to the semiconductor device 1 according to Embodiment 1, it is possible to make the semiconductor device 1 a useful product using diodes 11, 12, 13, 14, 15, and 16.

[0041] Furthermore, in the semiconductor device 1 according to Embodiment 1, the plurality of semiconductor chips include six diodes 11, 12, 13, 14, 15, and 16, and the plurality of connectors include six individual connectors 51, 52, 53, 61, 62, and 63 corresponding to the six diodes 11, 12, 13, 14, 15, and 16. Therefore, according to the semiconductor device 1 according to Embodiment 1, it is possible to make the semiconductor device 1 a useful product as a so-called three-phase bridge diode.

[0042] Furthermore, in the semiconductor device 1 according to Embodiment 1, the semiconductor chip is mounted on an inner lead, and the individual connectors 51, 52, 53, 61, 62, and 63 connect the semiconductor chip to an inner lead other than the inner lead on which the semiconductor chip is mounted. Therefore, according to the semiconductor device 1 according to Embodiment 1, by connecting the individual connectors 51, 52, 53, 61, 62, and 63 to a stable connection point, it is possible to ensure the strength of the internal structure of the semiconductor device 1.

[0043] Furthermore, in the semiconductor device 1 according to Embodiment 1, the plurality of inner leads include a first common inner lead 20, a plurality of individual inner leads (individual inner leads 31, 32, 33), and a second common inner lead 40. In addition, in the semiconductor device 1 according to Embodiment 1, at least two semiconductor chips are mounted on the first common inner lead 20 in an arrangement along the first direction D1, and at least one semiconductor chip is mounted on the individual inner leads 31, 32, 33. Therefore, according to the semiconductor device 1 according to Embodiment 1, the shape and arrangement of the inner leads can be made suitable for connection by individual connectors.

[0044] Furthermore, the semiconductor device 1 according to Embodiment 1 includes a plurality of semiconductor chips, a first common inner lead 20, a plurality of individual inner leads, a second common inner lead 40, and a sealing resin 70 that seals individual connectors 51, 52, 53, 61, 62, and 63. Therefore, according to the semiconductor device 1 of Embodiment 1, the semiconductor device 1 can be made into a product that is useful as a package sealed with sealing resin.

[0045] Furthermore, in the semiconductor device 1 according to Embodiment 1, the first common inner lead 20 is connected to the first outer lead 20B, the individual inner leads 31, 32, and 33 are connected to the individual outer leads 31B, 32B, and 33B, and the second common inner lead 40 is connected to the second outer lead 40B. Therefore, according to the semiconductor device 1 of Embodiment 1, it is possible to appropriately connect the internal structure of the semiconductor device 1 to the outside.

[0046] Furthermore, in the semiconductor device 1 according to Embodiment 1, the individual connectors 51, 52, 53, 61, 62, 63 have first connection portions 51a, 52a, 53a, 61a, 62a, 63a which are arranged to cover the semiconductor chip (diodes 11, 12, 13, 14, 15, 16) when viewed from above, and second connection portions 51b, 52b, 53b, 61b, 62b, 63b which are narrower than the first connection portions 51a, 52a, 53a, 61a, 62a, 63a, protrude from the first connection portions 51a, 52a, 53a, 61a, 62a, 63a and whose tips are connected to a conductive member. Therefore, according to the semiconductor device 1 of Embodiment 1, it is possible to restrict the conduction of heat generated in the multiple semiconductor chips at the second connection parts 51b, 52b, 53b, 61b, 62b, and 63b. As a result, it is possible to suppress thermal turbulence caused by heat generation in the multiple semiconductor chips and suppress localized thermal deformation of the semiconductor device 1.

[0047] Furthermore, in the semiconductor device 1 according to Embodiment 1, the plurality of connectors include a plurality of individual connectors 51, 52, 53, 61, 62, 63, and when viewed from above, the semiconductor device 1 is configured such that the portion 40A of the second common inner lead 40 extending along the first direction D1 overlaps with the second connecting portions 51b, 52b, 53b, 61b, 62b, 63b of all the individual connectors 51, 52, 53, 61, 62, 63. For this reason, in the semiconductor device 1 according to Embodiment 1, the length of the portion 40A of the second common inner lead 40 extending along the first direction D1 is greater than or equal to the arrangement distance of the second connecting portions 51b, 52b, 53b, 61b, 62b, 63b. Accordingly, according to the semiconductor device 1 of Embodiment 1, it is possible to suppress thermal shock caused by heat generation from semiconductor chips (diodes 11, 12, 13, 14, 15, 16) that are connected to individual connectors 51, 52, 53, 61, 62, 63 having second connection portions 51b, 52b, 53b, 61b, 62b, 63b and arranged in a dispersed manner, using the second common inner lead 40 on which the semiconductor chips (diodes 11, 12, 13, 14, 15, 16) are not mounted, thereby suppressing localized thermal deformation of the semiconductor device 1 due to thermal shock.

[0048] Furthermore, in the semiconductor device 1 according to Embodiment 1, the second connection portions 51b, 52b, 53b of the first connectors 51, 52, 53 and the second connection portions 61b, 62b, 63b of the second connectors 61, 62, 63 are adjacent when viewed from above. Therefore, according to the semiconductor device 1 according to Embodiment 1, it is possible to reduce heat concentration by aggregating the bottlenecks caused by heat generation from multiple semiconductor chips, and it is also possible to reduce the mounting area by placing the second connection portions 51b, 52b, 53b, 61b, 62b, 63b of the individual connectors 51, 52, 53, 61, 62, 63 adjacent to each other.

[0049] Furthermore, in the semiconductor device 1 according to Embodiment 1, there are three or more second connectors (individual connectors 61, 62, 63) (three in the semiconductor device 1), and the connection points P between the second connectors (individual connectors 61, 62, 63) and the second common inner lead 40 are arranged at equal intervals. Therefore, according to the semiconductor device 1 according to Embodiment 1, heat concentration can be further reduced.

[0050] [Embodiment 2] The semiconductor device 2 according to Embodiment 2 has basically the same configuration as the semiconductor device 1 according to Embodiment 1, but differs in the number of semiconductor chips (diodes), the number of individual inner leads, and the number of connectors. The configuration of the semiconductor device 2 will be described below, focusing on the differences from the semiconductor device 1.

[0051] The semiconductor device 2 according to Embodiment 2 is the same as the semiconductor device 1 in that it comprises a plurality of semiconductor chips, a plurality of inner leads, a plurality of connectors, and a sealing resin 70 (see Figure 2). The semiconductor device 2 can also be described as a single-phase bridge diode package. The components of the semiconductor device 2 will be described below. In the following description, the description of the components of the semiconductor device 2 that are substantially the same as the components of the corresponding components in the semiconductor device 1 may be omitted.

[0052] In Embodiment 2, the multiple semiconductor chips include four diodes 11, 12, 13, and 14. The difference in configuration between semiconductor device 2 and semiconductor device 1 is mainly due to the number of diodes.

[0053] In Embodiment 2, two diodes 11 and 12 are mounted on the first common inner lead 20. Also in Embodiment 2, the plurality of individual inner leads include two individual inner leads 31 and 32.

[0054] In Embodiment 2, the plurality of connectors include individual connectors 51, 52, 61, and 62 in a number equal to the number of semiconductor chips (diodes 11, 12, 13, 14) (4 pieces).

[0055] The semiconductor device 2 according to Embodiment 2 differs from the semiconductor device 1 according to Embodiment 1 in the number of semiconductor chips (diodes), the number of individual inner leads, and the number of connectors. However, in semiconductor device 2, the multiple connectors include individual connectors 51, 52, 61, and 62 that connect the semiconductor chips (diodes 11, 12, 13, and 14) constituting the multiple semiconductor chips to the conductive members on a one-to-one basis. Therefore, like semiconductor device 1, semiconductor device 2 is a semiconductor device that can suppress the occurrence of variations in the connection between semiconductor chips and connectors compared to conventional semiconductor devices.

[0056] Since the semiconductor device 2 according to Embodiment 2 has basically the same configuration as the semiconductor device 1 according to Embodiment 1, it also has the corresponding effects of the semiconductor device 1.

[0057] Although the present invention has been described above based on the embodiments described above, the present invention is not limited to the embodiments described above. It can be implemented in various forms without departing from the spirit of the invention, and for example, the following modifications are also possible.

[0058] (1) The positions, sizes, shapes, etc. of each component described in the above embodiments and shown in the drawings are illustrative examples and can be changed within the scope that does not impair the effects of the present invention.

[0059] (2) In each of the above embodiments, the plurality of connectors includes individual connectors 51, 52, 53, 61, 62, and 63, but the present invention is not limited thereto. The plurality of connectors may include connectors other than individual connectors.

[0060] (3) In each of the above embodiments, the plurality of semiconductor chips includes diodes 11, 12, 13, 14, 15, and 16, but the present invention is not limited thereto. The plurality of semiconductor chips may also include semiconductor chips other than diodes (for example, MOSFETs and IGBTs).

[0061] (4) In each of the above embodiments, the sealing resin 70 has a substantially rectangular shape when viewed from above, but the present invention is not limited thereto. The sealing resin may have a shape other than a substantially rectangular shape when viewed from above (for example, a square shape).

[0062] (5) In each of the above embodiments, each inner lead was connected to an outer lead, but the present invention is not limited thereto. For example, each inner lead may be connected to a terminal or the like that is separate from each inner lead.

[0063] (6) In each of the above embodiments, the individual connectors 51, 52, 53, 61, 62, and 63 connect the semiconductor chip to the inner lead, but the present invention is not limited thereto. The individual connectors may also connect the semiconductor chip to conductive members other than the inner lead (connectors, outer leads, terminals, etc.).

[0064] (7) In each of the above embodiments, the semiconductor devices 1 and 2 are provided with sealing resin 70, but the present invention is not limited thereto. The semiconductor device may not be provided with sealing resin. [Explanation of Symbols]

[0065] 1,2...Semiconductor device, 11,12,13,14,15,16...Diode, 20...First common inner lead, 20B...First outer lead, 31,32,33...Individual inner leads, 31B,32B,33B...Individual outer leads, 40...Second common inner lead, 40B...Second outer lead, 51,52,53,61,62,63...Individual connectors, First connection part...51a,52a,53a,61a,62a,63a, Second connection part...51b,52b,53b,61b,62b,63b, 70...Sealing resin, D1...First direction

Claims

1. A semiconductor device comprising multiple semiconductor chips and multiple conductive members including multiple inner leads and multiple connectors, The plurality of connectors include individual connectors that connect the semiconductor chip and the conductive member one-to-one. The aforementioned multiple inner leads are A first common inner lead having a portion extending along a predetermined first direction, A plurality of individual inner leads arranged along the first direction, It includes a second common inner lead that is positioned between the first common inner lead and the plurality of individual inner leads and has a portion that extends along the first direction, At least two of the semiconductor chips are mounted on the first common inner lead in an arrangement that follows the first direction. At least one of the semiconductor chips is mounted on the individual inner lead. The aforementioned individual connectors are, A first connection portion is positioned to cover the semiconductor chip when viewed from above, A semiconductor device characterized by having a second connecting portion which is narrower in width than the first connecting portion and protrudes from the first connecting portion, with its tip connected to the conductive member.

2. The semiconductor device according to claim 1, characterized in that the plurality of connectors include a number of individual connectors equal to the number of semiconductor chips.

3. The semiconductor device according to claim 1 or 2, characterized in that the plurality of semiconductor chips include diodes.

4. The plurality of semiconductor chips include six diodes as the diodes, The semiconductor device according to claim 3, characterized in that the plurality of connectors include six individual connectors corresponding to the six diodes.

5. The semiconductor chip is mounted on the inner lead, The semiconductor device according to claim 1, characterized in that the individual connector connects the semiconductor chip to an inner lead other than the inner lead on which the semiconductor chip is mounted.

6. The semiconductor device according to claim 1, further comprising the plurality of semiconductor chips, the first common inner lead, the plurality of individual inner leads, the second common inner lead, and a sealing resin for sealing the individual connector.

7. The first common inner lead is connected to a first outer lead, one end of which is exposed to the outside of the sealing resin. The individual inner lead is connected to an individual outer lead, one end of which is exposed to the outside of the sealing resin. The semiconductor device according to claim 6, characterized in that the second common inner lead is connected to a second outer lead, one end of which is exposed to the outside of the sealing resin.

8. The plurality of connectors include a plurality of the individual connectors, The semiconductor device according to claim 1, characterized in that, when viewed from above, the portion of the second common inner lead extending along the first direction and the second connection portion of all the individual connectors overlap.

9. When the individual piece connector connecting the semiconductor chip mounted on the first common inner lead to the individual piece inner lead is defined as the first connector, and the individual piece connector connecting the semiconductor chip mounted on the individual piece inner lead to the second common inner lead is defined as the second connector, The semiconductor device according to claim 1, characterized in that the second connecting portion of the first connector and the second connecting portion of the second connector are adjacent when viewed from above.

10. There are three or more of the aforementioned second connectors. The semiconductor device according to claim 9, characterized in that the connection points between the second connector and the second common inner lead are arranged at equal intervals.

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