differential amplifier

Abstract

To provide a differential amplifier capable of achieving an improvement in input offset voltage more reliably as compared to conventional measures to improve input offset voltage.SOLUTION: Provided is a differential amplifier in which a first differential pair 101 configured to enable differential amplification using an N channel MOSFET and a second differential pair 102 configured to enable differential amplification using a P channel MOSFET are provided in parallel to an input, and the outputs of the first and second differential pairs can be added. The differential amplifier is provided with a current mirror circuit 105. The current mirror circuit 105 can supply current to each of an output stage of the first differential pair 101 and an output stage of the second differential pair 102, and suppresses voltage fluctuations in the output stages of the first differential pair 101 and the second differential pair 102 due to the operation switching of the first differential pair 101 and the second differential pair 102 with changes in common mode input voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a differential amplifier used in operational amplifiers and comparators, and more particularly to one that improves the input offset voltage with respect to a common-mode input voltage. [Background technology]

[0002] Operational amplifiers and comparators are ideally designed to have a wide common-mode input voltage range and minimal variation in the input offset voltage relative to the common-mode input voltage. Figure 18 shows a circuit diagram of a conventional operational amplifier using a differential amplifier capable of applying a common-mode input voltage from the negative power supply voltage to the positive power supply voltage. The following explanation of this conventional operational amplifier will refer to this figure. This conventional operational amplifier is broadly composed of a first differential pair 101X made up of first and second transistors M1 and M2, a second differential pair 102X made up of third and fourth transistors M3 and M4 and a first constant current source CS1, a folded cascode circuit 103X made up of fifth to eighth transistors M5 to M8, and a tail current supply circuit 104X made up of tenth to twelfth transistors M10 to M12.

[0003] Figure 19 shows the common-mode input voltage characteristics of the input offset voltage in this conventional operational amplifier. The operation of this operational amplifier will be outlined with reference to this figure. This common-mode input voltage characteristic plots the input offset voltage when the common-mode input voltage Vicm is swept from 0V to 5V, with a positive power supply voltage VDD=5V and a negative power supply voltage VSS=0V. As shown in Figure 19, it can be confirmed that the conventional operational amplifier switches between PMOS differential pair operation and NMOS differential pair operation at a common-mode input voltage Vicm = 3.5V. Here, the PMOS differential pair refers to the second differential pair 102X in Figure 18, and the NMOS differential pair refers to the first differential pair 101X in Figure 18. The reason why the operation switches between PMOS differential pair operation and NMOS differential pair operation at a common-mode input voltage Vicm = 3.5V is because a reference voltage Vref1 = 3.5V is supplied to the reference voltage terminal 45X in Figure 18. The operation switches between PMOS differential pair operation and NMOS differential pair operation at the voltage supplied to this reference voltage terminal 45X.

[0004] Therefore, the circuit operation switches as described below, with the common-mode input voltage Vicm = 3.5V as the boundary. First, when the common-mode input voltage Vicm is between the negative power supply voltage VSS and the reference voltage Vref1, the PMOS differential pair operates while the NMOS differential pair remains inactive. Furthermore, when the common-mode input voltage Vicm is between the reference voltage Vref1 and the positive power supply voltage VDD, the PMOS differential pair is in a non-operating state, while the NMOS differential pair is in an operating state.

[0005] Thus, in conventional operational amplifiers, because switching of the operating differential pair occurs, as shown in Figure 19, when the common-mode input voltage Vicm = 3.5V or less, the input offset voltage is almost 0mV, but when the common-mode input voltage Vicm = 3.5V or more, the input offset voltage deteriorates to 0.4mV or more.

[0006] The reason why the input offset voltage deteriorates during NMOS differential pair operation is explained below. To state the conclusion first, the reason for the deterioration of the input offset voltage is that the magnitude of the voltage drop across resistor R4 changes between PMOS differential pair operation and NMOS differential pair operation.

[0007] This matter will be explained in detail below. First, we derive the voltage drop across resistor R4 during PMOS differential pair operation. To determine the voltage drop across resistor R4, we derive the drain current IM6 of transistor M6 during PMOS differential pair operation. This current IM6 is determined using the constant current source CS2, transistors M6 and M9, and resistors R2 and R5 such that it satisfies the relationship shown in Equation 1 below.

[0008] (IM6×R2)+[2×IM6 / {k'P×(W / L)M6}] 1 / 2 =(IM9×R5)+[2×IM9 / {k'P×(W / L)M9}] 1 / 2 ...Formula 1

[0009] Here, IM6 is the drain current of transistor M6, R2 is the resistance value of resistor R2, k'P is the product of the mobility of the PMOS transistor and the gate oxide capacitance per unit area, (W / L)M6 is the value obtained by dividing the channel width W of transistor M6 by the channel length L, IM9 is the drain current of transistor M9, R5 is the resistance value of resistor R5, and (W / L)M9 is the value obtained by dividing the channel width W of transistor M9 by the channel length L.

[0010] In equation 1, if we set R2 = R5 and (W / L)M6 = (W / L)M9, then the drain current IM6 of transistor M6 will be the same magnitude as the drain current IM9 of transistor M9. Also, the drain current IM9 of transistor M9 is equivalent to the current I2 of current source CS2. Therefore, the drain current IM6 of transistor M6 during PMOS differential pair operation will be the current I2 of current source CS2, as shown in equation 2 below.

[0011] IM6 = IM9 = I2 ... Equation 2 during PMOS differential pair operation

[0012] This drain current IM6 flows into resistor R4 via NMOS transistor M8. Furthermore, during PMOS differential pair operation, half of the current I1 from current source CS1 flows into resistor R4 via transistor M4. Therefore, the voltage drop across resistor R4 during PMOS differential pair operation is expressed as shown in Equation 3 below.

[0013] Voltage drop across resistor R4 during PMOS differential pair operation = R4 × (I2 + I1 / 2) ... Equation 3

[0014] Here, as is generally well known, the input offset voltage is generated such that the voltage drop across resistor R4 is equal to the voltage drop across resistor R3, that is, to cancel out the difference in the voltage drops across resistors R4 and R3. In other words, the input offset voltage can be expressed as a function of the voltage drop across resistor R4. Therefore, if the magnitude of the voltage drop across resistor R4 during PMOS differential pair operation, calculated by Equation 3 above, can be maintained during NMOS differential pair operation, the deterioration of the input offset voltage shown in Figure 19 will not occur.

[0015] However, as described below, the conventional operational amplifier shown in Figure 18 cannot maintain the same voltage drop across resistor R4 during NMOS differential pair operation as it does during PMOS differential pair operation, and the input offset voltage deteriorates during NMOS differential pair operation, as shown in Figure 19. First, we will explain the circuit operation during NMOS differential pair operation and then determine the voltage drop across resistor R4. During NMOS differential pair operation, the current I1 from current source CS1 does not flow through transistors M3 and M4 of the PMOS differential pair, but instead flows through PMOS transistor M10 to NMOS transistor M11.

[0016] Here, NMOS transistors M11 and M12 are in a current mirror configuration, and the same current I1 as M11 flows through M12. This current I1 flowing through M12 becomes the tail current of the NMOS differential pair composed of transistors M1 and M2, and operates the NMOS differential pair. Therefore, the magnitude of the current flowing through resistor R2 via NMOS transistor M2 is half of the current I1. Consequently, the drain current of transistor M6 is determined to satisfy the relationship shown in Equation 4 below.

[0017] {(I1 / 2+IM6)×R2}+[2×IM6 / {k'P×(W / L)M6}]1 / 2 =(IM9 × R5) + [2 × IM9 / {k’P × (W / L)M9}] 1 / 2 ··· Equation 4

[0018] Here, when R2 = R5 and (W / L)M6 = (W / L)M9, it can be seen that at least the drain current IM6 of transistor M6 is smaller than the drain current IM9 of transistor M9. Since the drain current IM9 of transistor M9 is equivalent to the current I2 of current source CS2, it can be said that the drain current IM6 of transistor M6 is smaller than the current I2. If the ratio representing how much smaller the current IM6 is than the current I2 is defined as a constant A, it becomes as shown in Equation 5 below.

[0019] IM6 = IM9 / A = I2 / A during NMOS differential pair operation ··· Equation 5

[0020] Here, the constant A is a value greater than 1, and therefore Equation 5 means that the current IM6 is smaller than the current IM9 and the current I2.

[0021] Next, the current flowing from PMOS transistor M4 to resistor R4 will be described. During NMOS differential pair operation, the current I1 from current source CS1 flows into PMOS transistor M10 and does not flow into PMOS transistor M4. Therefore, the voltage drop across resistor R4 during NMOS differential pair operation is represented by Equation 6 below.

[0022] Voltage drop across resistor R4 during NMOS differential pair operation = R4 × (I2 / A) ··· Equation 6

[0023] The voltage drop across resistor R4 during PMOS differential pair operation is as represented by Equation 3 above. On the other hand, the voltage drop across resistor R4 during NMOS differential pair operation is as shown in Equation 6 above and is a different value from that during PMOS differential pair operation. Therefore, as shown in FIG. 19, the input offset voltage deteriorates during NMOS differential pair operation. The difference in voltage drop across resistor R4 between PMOS differential pair operation and NMOS differential pair operation is expressed as the difference between Equation 3 and Equation 6, as shown in Equation 7 below.

[0024] The difference in voltage drop across resistor R4 between PMOS differential pair operation and NMOS differential pair operation = R4 × (I2 + I1 / 2) - R4 × (I2 / A) = R4 × {I2(1 - 1 / A) + I1 / 2} ... Equation 7

[0025] The larger this difference becomes, the worse the input offset voltage will be during NMOS differential pair operation, as shown in Figure 19. As a measure to improve the input offset voltage relative to such a common-mode input voltage, there are, for example, those disclosed in Patent Documents 1 and 2. Patent Document 2 discloses an example of a circuit configuration composed of bipolar transistors, while Patent Document 1 shows an example of a circuit configuration in which bipolar transistors are replaced with CMOS transistors. Figure 20 shows an example of a circuit configuration equivalent to the circuit disclosed in Patent Document 1. The circuit with improved input offset voltage will be described below with reference to this figure.

[0026] The circuit shown in Figure 20 has the same configuration as the circuit shown in Figure 18, but with the addition of an NMOS transistor M100. Figure 21 shows the common-mode input voltage characteristics of the input offset voltage in this circuit configuration. In the figure, the dotted characteristic line shows the change in input offset voltage when using the technology of Patent Document 1, and the dashed-dotted characteristic line shows the change in input offset voltage in the conventional circuit shown in Figure 18. According to Figure 21, it can be confirmed that by using the technology of Patent Document 1, the input offset voltage during NMOS differential pair operation is improved from a voltage level of 0.4mV or higher to about 0.2mV.

[0027] Here, we will briefly explain the operation of the circuit shown in Figure 20. This circuit is characterized by the fact that the NMOS transistor M100 operates and the drain current IM100 flows only when the NMOS differential pair is in operation. Therefore, the drain current IM6 of the PMOS transistor M6 during NMOS differential pair operation is expressed by the following equation 8.

[0028] {(I1 / 2+IM6)×R2}+[2×IM6 / {k'P×(W / L)M6}] 1 / 2 ={(IM100+IM9)×R5}+[2×IM9 / {k'P×(W / L)M9}] 1 / 2 ...Formula 8

[0029] Here, assuming R2=R5 and (W / L)M6=(W / L)M9, and further assuming the drain current IM100 of NMOS transistor M100 = I1 / 2, the drain current IM6 of transistor M6 is the same magnitude as the drain current IM9 of transistor M9. Since the drain current IM9 of transistor M9 is equivalent to the current IM2 of current source CS2, the drain current IM6 of transistor M6 during NMOS differential pair operation is equal to the current IM2 of current source CS2, as shown in equation 9 below.

[0030] IM6=IM9=I2 during NMOS differential pair operation...Equation 9

[0031] Next, we will explain the current flowing from the PMOS transistor M4 to the resistor R4. During NMOS differential pair operation, the current I1 from the current source CS1 flows to the PMOS transistor M10 and not to the PMOS transistor M4. Therefore, the voltage drop across resistor R4 during NMOS differential pair operation is expressed by equation 10 below.

[0032] Voltage drop across resistor R4 during NMOS differential pair operation = R4 × I² ... Equation 10

[0033] On the other hand, the voltage drop across resistor R4 during PMOS differential pair operation is as shown in Equation 3 above. Therefore, the difference in voltage drop across resistor R4 between PMOS differential pair operation and NMOS differential pair operation is as shown in Equation 11 below.

[0034] The difference in voltage drop across resistor R4 between PMOS differential pair operation and NMOS differential pair operation = R4 × (I2 + I1 / 2) - R4 × I2 = R4 × I1 / 2 ... Equation 11

[0035] The difference in voltage drop across resistor R4 between PMOS differential pair operation and NMOS differential pair operation in the circuit of Figure 20 using the technology disclosed in the patent document is smaller than the similar difference (see Equation 7) in the circuit shown in Figure 18. Therefore, the input offset voltage can be improved in the circuit to which the technology disclosed in the patent document is applied, and the degree of improvement is as shown in Figure 21. [Prior art documents] [Patent Documents]

[0036] [Patent Document 1] Japanese Patent Publication No. 2018-7070 [Patent Document 2] Japanese Patent Application Publication No. 8-237051 [Overview of the project] [Problems that the invention aims to solve]

[0037] However, while applying the technology disclosed in the patent documents does indeed improve the input offset voltage as described above, theoretically, it does not completely eliminate the input offset voltage, as shown in Equation 11. Therefore, depending on the selection of circuit constants and other factors in the specific circuit, satisfactory improvement may not always be achieved.

[0038] This invention has been made in view of the above circumstances, and provides a differential amplifier that enables more reliable improvement of the input offset voltage compared to conventional methods for improving the input offset voltage. [Means for solving the problem]

[0039] To achieve the above-mentioned objectives of the present invention, the differential amplifier according to the present invention is In a differential amplifier in which a first differential pair configured to be differentially amplified using N-channel MOSFETs and a second differential pair configured to be differentially amplified using P-channel MOSFETs are provided in parallel with respect to the input, and the outputs of each are configured to be summable, A current mirror circuit is provided, and the current mirror circuit is The output stage of the first differential pair and the output stage of the second differential pair are configured to be able to supply current to each of them. This makes it possible to suppress voltage fluctuations in the output stages of the first and second differential pairs caused by the switching of operation between the first and second differential pairs in response to changes in the common-mode input voltage. 、 A tail current supply circuit is provided to supply the tail current of the first differential pair. The current mirror circuit comprises an input stage transistor using a P-channel MOSFET and first to fourth output stage transistors. The sources of the input stage transistor and the sources of the first to fourth output stage transistors are interconnected to allow a positive power supply voltage to be applied. The gates of the input stage transistor and the gates of the first to fourth output stage transistors are interconnected and connected to the drains of the input stage transistors. The drains of the input stage transistors are connected to the output stage of the tail current supply circuit. The drains of the first and second output stage transistors are connected to the two output stages of the second differential pair, and the drains of the third and fourth output stage transistors are connected to the two output stages of the first differential pair. That's how it is. [Effects of the Invention]

[0040] According to the present invention, since the non-uniformity of the circuit current, which is a cause of input offset voltage fluctuations, is eliminated, the fluctuations of the input offset voltage can be suppressed more reliably compared to conventional countermeasures, resulting in improved characteristics. [Brief explanation of the drawing]

[0041] [Figure 1] This is a circuit diagram showing a first example of a circuit configuration of an operational amplifier using a differential amplifier according to an embodiment of the present invention. [Figure 2] This is a block diagram of the current mirror circuit shown in Figure 1, which is the first example of a circuit configuration. [Figure 3] This is a circuit diagram showing a second example of a circuit configuration for an operational amplifier using a differential amplifier according to an embodiment of the present invention. [Figure 4] This is a circuit diagram showing a third circuit configuration example of an operational amplifier using a differential amplifier according to an embodiment of the present invention. [Figure 5] This is a block diagram of the current mirror circuit shown in Figure 4, which is the third example of a circuit configuration. [Figure 6] This is a circuit diagram showing a fourth example of a circuit configuration for an operational amplifier using a differential amplifier according to an embodiment of the present invention. [Figure 7] This is a circuit diagram showing a fifth example of a circuit configuration for an operational amplifier using a differential amplifier according to an embodiment of the present invention. [Figure 8] This is a circuit diagram showing a sixth example of a circuit configuration for an operational amplifier using a differential amplifier according to an embodiment of the present invention. [Figure 9] Figure 8 is a circuit diagram showing the offset adjustment circuit and current mirror circuit in the sixth circuit configuration example, with the circuits being shown as blocks. [Figure 10] This is a circuit diagram showing a seventh circuit configuration example of an operational amplifier using a differential amplifier according to an embodiment of the present invention. [Figure 11] Figure 10 is a block diagram of the current mirror circuit in the seventh circuit configuration example shown. [Figure 12] This is a circuit diagram showing an eighth example of a circuit configuration for an operational amplifier using a differential amplifier according to an embodiment of the present invention. [Figure 13] This is a circuit diagram showing a ninth example of a circuit configuration for an operational amplifier using a differential amplifier according to an embodiment of the present invention. [Figure 14] This is a circuit diagram showing a tenth example of a circuit configuration for an operational amplifier using a differential amplifier according to an embodiment of the present invention. [Figure 15] Figure 14 is a block diagram of the offset adjustment circuit in the 10th example circuit configuration shown. [Figure 16] This is a circuit diagram showing the case where a bipolar element is used in the circuit configuration shown in Figure 2. [Figure 17] This is a characteristic diagram showing the common-mode input voltage dependence of the input offset voltage of an operational amplifier using a differential amplifier in an embodiment of the present invention. [Figure 18] This is a circuit diagram showing an example of a circuit configuration for an operational amplifier using a conventional differential amplifier. [Figure 19] Figure 18 is a characteristic curve showing the dependence of the input offset voltage on the common-mode input voltage in the conventional circuit. [Figure 20] This circuit diagram shows an example of a circuit configuration for another conventional circuit. [Figure 21] Figure 20 is a characteristic curve showing the dependence of the input offset voltage on the common-mode input voltage in the conventional circuit shown. [Modes for carrying out the invention]

[0042] Hereinafter, embodiments of the present invention will be described with reference to Figures 1 to 17. The components, arrangements, etc., described below are not intended to limit the present invention and can be modified in various ways within the scope of the spirit of the present invention. First, a first example of a circuit configuration of an operational amplifier using a differential amplifier in an embodiment of the present invention will be described with reference to Figure 1. The operational amplifier in this first circuit configuration example is configured by connecting a folded cascode circuit 103 and an output circuit 106 to the differential amplifier DIF1 in the embodiment of the present invention.

[0043] The differential amplifier DIF1 in the embodiment of the present invention comprises a first differential pair 101 composed of first and second transistors (denoted as "M1" and "M2" in Figure 1, respectively) 1 and 2, a second differential pair 102 composed of third and fourth transistors (denoted as "M3" and "M4" in Figure 1, respectively) 3 and 4, and a first constant current source (denoted as "CS1" in Figure 1) 71, and tenth to twelfth transistors (denoted as "M10" in Figure 1, respectively) The circuit is broadly composed of a tail current supply circuit 104, which consists of transistors 10-12 (labeled "M11" and "M12") and the 101st transistor (labeled "M101" in Figure 1) 15, and a current mirror circuit (labeled "CM1" in Figure 1) 105, which consists of transistors 21-25 (labeled "M201", "M202", "M203", "M204", and "M205" respectively in Figure 1).

[0044] In the differential amplifier according to an embodiment of the present invention, the first differential pair 101 and the second differential pair 102 are provided in parallel with respect to the signal input, and their respective outputs are added in a folded cascode circuit 103 and output via an output circuit 106.

[0045] The first and second transistors 1 and 2 constituting the first differential pair 101 (first and second transistors for the first differential pair) are N-channel MOSFETs (N-channel MOS field-effect transistors). For the sake of convenience, "N-channel MOSFET" will be referred to as "NMOSFET" below. Similarly, for the sake of convenience, "P-channel MOSFET" will be referred to as "PMOSFET" below. The drain of the first transistor 1 is connected to the positive power supply voltage terminal 43 via the first resistor (labeled "R1" in Figure 1) 31, and the drain of the second transistor 2 is connected to the positive power supply voltage terminal 43 via the second resistor (labeled "R2" in Figure 1) 32, so that the positive power supply voltage VDD is applied. On the other hand, the sources of the first and second transistors 1 and 2 are interconnected and connected to the drains of the twelfth transistor 12, which uses an NMOSFET. Furthermore, the gate of the first transistor 1 is connected to the inverting input terminal (labeled "INM" in Figure 1) 41, and the gate of the second transistor 2 is connected to the non-inverting input terminal (labeled "INP" in Figure 1) 42.

[0046] PMOSFETs are used for the third and fourth transistors 3 and 4 that constitute the second differential pair 102. The sources of the third and fourth transistors 3 and 4 are interconnected, and a first constant current source (labeled "CS1" in Figure 1) 71 is connected between this connection point and the positive power supply voltage terminal 43.

[0047] Furthermore, the drain of the third transistor 3 is connected to the negative power supply voltage terminal 44 via the third resistor (labeled "R3" in Figure 1) 33, and the drain of the fourth transistor 4 is connected to the negative power supply voltage terminal 44 via the fourth resistor (labeled "R4" in Figure 1) 34, so that the negative power supply voltage VSS is applied. Furthermore, the gate of the third transistor 3 is connected to the gate of the first transistor 1, and the gate of the fourth transistor 4 is connected to the gate of the second transistor 2.

[0048] The current mirror circuit 105 is configured as described below using transistors 21 to 25, numbered 201 to 205, which are PMOSFETs. Transistors 21-25, numbered 201 through 205, have their sources interconnected and are connected to the positive power supply voltage terminal 43 via a common potential terminal P0. Furthermore, transistors 201 to 205, 21 to 25, have their gates interconnected and are connected to the input terminal P1 of the current mirror circuit, along with the drain of transistor 201 (input stage transistor) 21. The drain of the aforementioned transistor 101 is connected to this input terminal P1.

[0049] Furthermore, the drain of the 202nd transistor (first output stage transistor) 22 is connected via the output terminal P2 of the current mirror circuit to the connection point between the drain of the third transistor 3, the third resistor 33, and the source of the seventh transistor 7. Furthermore, the drain of the 203rd transistor (second output stage transistor) 23 is connected to the connection point between the drain of the 4th transistor 4, the 4th resistor 34, and the source of the 8th transistor 8 via the output terminal P3 of the current mirror circuit.

[0050] Furthermore, the drain of the 204th transistor (third output stage transistor) 24 is connected to the connection point between the drain of the second transistor 2, the second resistor 32, and the source of the sixth transistor 6 via the output terminal P4 of the current mirror circuit. Furthermore, the drain of the 205th transistor (the fourth output stage transistor) 25 is connected via the output terminal P5 of the current mirror circuit to the connection point between the drain of the first transistor 1, the first resistor 31, and the source of the fifth transistor 5.

[0051] The 10th transistor 10, which constitutes the tail current supply circuit 104, is a PMOSFET, while the 11th and 12th transistors 11 and 12, and the 101st transistor 15, are all NMOSFETs, forming a current mirror circuit as described below. First, the gate of the tenth transistor 10 is connected to the reference voltage terminal 45 so that a reference voltage Vref1 is applied externally. Furthermore, the source of the 10th transistor 10 is connected to the sources of the 3rd and 4th transistors 3 and 4. Furthermore, the drain of the tenth transistor 10 is connected to the drain of the eleventh transistor 11.

[0052] The 11th and 12th transistors 11 and 12, and the 101st transistor 15, are gate-connected to each other and are connected to the drain of the 11th transistor 11. Furthermore, the sources of the 11th and 12th transistors 11 and 12, and the 101st transistor 15, are both connected to the negative power supply voltage terminal 44, so that the negative power supply voltage VSS is applied. Furthermore, the 11th transistor 11 acts as the current mirror source, and the mirror current is output to the 12th transistor 12 and the 101st transistor 15.

[0053] The folded cascode circuit 103 has the function of connecting the first differential pair 101 and the second differential pair 102. PMOSFETs are used for the fifth and sixth transistors 5 and 6, and NMOSFETs are used for the seventh and eighth transistors 7 and 8. The fifth and sixth transistors 5 and 6 have their gates interconnected, while the source of the fifth transistor 5 is connected to the drain of the first transistor 1, and the source of the sixth transistor 6 is connected to the drain of the second transistor 2.

[0054] Furthermore, the seventh and eighth transistors 7 and 8 are interconnected, with their respective gates connected to the drain of the seventh transistor 7, and also connected to the drain of the fifth transistor 5. Furthermore, the drain of the eighth transistor 8 is connected to the drain of the sixth transistor 6. On the other hand, the source of the seventh transistor 7 is connected to the drain of the third transistor 3, and the source of the eighth transistor 8 is connected to the drain of the fourth transistor 4.

[0055] The output circuit 106 is mainly composed of a ninth transistor (labeled "M9" in Figure 1) 9 using a PMOSFET, a thirteenth transistor (labeled "M13" in Figure 1) 13 using an NMOSFET, and second and third constant current sources (labeled "CS2" and "CS3" respectively in Figure 1) 72 and 73. This output circuit 106 is connected to the folded cascode circuit 103, as described below.

[0056] In the folded cascode circuit 103, the fifth and sixth transistors 5 and 6 use the ninth transistor 9 as the mirror source to form a current mirror circuit with a current mirror ratio of 1:1. In other words, the ninth transistor 9, which serves as a MOS transistor for the mirror source, has its gate and drain connected to each other to form a diode connection, and its connection point is connected to the gates of the fifth and sixth transistors 5 and 6.

[0057] The source of the ninth transistor 9 is connected to the positive power supply voltage terminal 43 via the fifth resistor (labeled "R5" in Figure 1) 35, so that the positive power supply voltage VDD is applied. On the other hand, a second constant current source 72 is connected between the drain of the ninth transistor 9 and the negative power supply voltage terminal 44. Furthermore, the gate of the 13th transistor 13, which is an output transistor, is connected to the mutually connected drains of the 6th and 8th transistors 6 and 8 of the folded cascode circuit 103.

[0058] A third constant current source 73 is connected in series between the drain of the 13th transistor 13 and the positive power supply voltage terminal 43, and the drain is connected to the output terminal 46. On the other hand, the source of the 13th transistor 13 is connected to the negative power supply voltage terminal 44, so that the negative power supply voltage VSS is applied. Furthermore, a phase compensation capacitor (indicated as "Cc" in Figure 1) 40 is connected between the drain and gate of the 13th transistor 13.

[0059] Figure 2 shows a circuit diagram in which the current mirror circuit 105, enclosed by a dotted line in Figure 1, is represented as a block. In the following explanation of circuit operation, please refer to Figure 1, and the explanation of the circuit operation in Figure 1 will be used in place of the explanation of the circuit operation in Figure 2. Next, the circuit operation in this configuration will be described. First, for the sake of clarity, in the following explanation, the first differential pair 101 will be referred to as the "NMOS differential pair," and the second differential pair 102 as the "PMOS differential pair." First, the voltage drop across the fourth resistor 34 during PMOS differential pair operation is basically the same as in the case of the conventional circuit (see Figures 18 and 20), and is expressed as shown in Equation 12 below.

[0060] Voltage drop across the fourth resistor 34 during PMOS differential pair operation = R4 × (I2 + I1 / 2) ... Equation 12

[0061] Here, R4 is the resistance value of the fourth resistor 34. Furthermore, I1 represents the output current of the first constant current source 71, and I2 represents the output current of the second constant current source 72.

[0062] Next, we derive the voltage drop across the fourth resistor 34 during NMOS differential pair operation. During NMOS differential pair operation, a drain current flows through the 11th transistor 11. A drain current also flows through the 101st transistor 15, which forms a current mirror with the 11th transistor 11. Furthermore, drain currents IM202, IM203, IM204, and IM205 flow through the 202nd to 205th transistors 22-25, which form a current mirror with the 201st transistor 21.

[0063] On the other hand, the drain current of the 12th transistor 12 flows through the NMOS differential pair of the first and second transistors 1 and 2. Since this drain current of the 12th transistor 12 is the Miller current of the first constant current source 71, its current value is I1. Therefore, the drain currents flowing through the first and second transistors 1 and 2, respectively, are I1 / 2.

[0064] In this embodiment of the present invention, the drain currents of transistors 204 and 205, 24 and 25, are set to the current values ​​represented by the following formula 13.

[0065] IM204=IM205=I1 / 2...Equation 13

[0066] Thus, the drain currents I1 / 2 of the first and second transistors 1 and 2 are supplied by the drain currents IM204 and IM205 of the 204th and 205th transistors 24 and 25. As a result, the magnitude of the current flowing through the second resistor 32 becomes the drain current IM6 of the sixth transistor 6. The drain current IM6 of this sixth transistor 6 is expressed by the following equation 14.

[0067] (IM6×R2)+[2×IM6 / {k'P×(W / L)M6}] 1 / 2 =(IM9×R5)+[2×IM9 / {k'P×(W / L)M9}] 1 / 2 ...Formula 14

[0068] Here, IM6 is the drain current of the sixth transistor 6, R2 is the resistance of the second resistor 32, k'P is the product of the mobility of the PMOS transistor and the gate oxide capacitance per unit area, (W / L)M6 is the value obtained by dividing the channel width W of the sixth transistor 6 by the channel length L, IM9 is the drain current of the ninth transistor 9, R5 is the resistance of the fifth resistor 35, and (W / L)M9 is the value obtained by dividing the channel width W of the ninth transistor 9 by the channel length L.

[0069] In equation 14, if we set R2=R5 and (W / L)M6=(W / L)M9, the drain current IM6 of the sixth transistor 6 will be the same magnitude as the drain current IM9 of the ninth transistor 9. Also, the drain current IM9 of the ninth transistor 9 will be equivalent to the output current I2 of the second current source 72. Therefore, the drain current IM6 of the sixth transistor 6 during NMOS differential pair operation will be the current I2 of the second current source 72, as shown in equation 15 below.

[0070] IM6=IM9=I2 during NMOS differential pair operation...Equation 15

[0071] This drain current IM6 flows into the fourth resistor 34 via the eighth transistor 8. Furthermore, the drain current IM203 from the 203rd transistor 23 flows into the fourth resistor 34. The magnitude of this drain current IM203 is determined as shown in Equation 16.

[0072] IM203=IM202=I1 / 2...Formula 16

[0073] By defining it in this way, the voltage drop across the fourth resistor 34 during NMOS differential pair operation can be calculated using Equation 17 below.

[0074] Voltage drop across the fourth resistor 34 during NMOS differential pair operation = R4 × (I2 + I1 / 2) ... Equation 17

[0075] Ultimately, the voltage drop across the fourth resistor 34 in the PMOS differential circuit, as shown in Equation 12, is the same magnitude. Therefore, the difference in voltage drop across the fourth resistor 34 between when the PMOS differential pair operates and when the NMOS differential pair operates is zero. As is well known, the closer the difference in voltage drop across the fourth resistor 34 between when the PMOS differential pair operates and when the NMOS differential pair operates is to zero, the more improved the input offset voltage is. However, in the embodiments of the present invention, as described above, mathematically, the difference in voltage drop across the fourth resistor 34 is zero. Therefore, it can be confirmed that the differential amplifier in the embodiments of the present invention can surely improve the input offset voltage more than the conventional circuits applying the techniques of Patent Documents 1 and 2.

[0076] FIG. 17 shows the input offset voltage characteristics of the differential amplifier in the embodiments of the present invention with respect to the non-inverting input voltage, and will be described below with reference to the figure. In the figure, the horizontal axis represents the non-inverting input voltage, and the vertical axis represents the input offset voltage. Also, in FIG. 17, the input offset voltage characteristics of the differential amplifier in the embodiments of the present invention with respect to the non-inverting input voltage are shown by the solid line characteristic curve, the same characteristics of the conventional circuit (see FIG. 18) are shown by the two-dot chain line characteristic curve, and the same characteristics of the circuit applying the technique of the patent document (see FIG. 20) are shown by the dotted line characteristic curve, respectively.

[0077] According to FIG. 17, the input offset voltage of the differential amplifier in the embodiments of the present invention is approximately 0 mV as described above, and a sure improvement in the input offset voltage can be confirmed with respect to the conventional circuits (see FIGS. 18 and 20). In the differential amplifier of the embodiments of the present invention, the circuit constants of the 204th and 205th transistors 24 and 25 need to satisfy the conditions shown in Equation 18 below.

[0078] [2×IM204 / {k’P×(W / L)M204}] 1 / 2 =[2×IM205 / {k’P×(W / L)M205}] 1 / 2 <VR2···Equation 18

[0079] Here, IM204 is the drain current of the 204th transistor 24, k'P is the product of the mobility of the PMOS transistor and the gate oxide capacitance per unit area, (W / L)M204 is the value obtained by dividing the channel width W of the 204th transistor 24 by the channel length L, (W / L)M205 is the value obtained by dividing the channel width W of the 205th transistor 25 by the channel length L, IM205 is the drain current of the 205th transistor 25, and VR2 is the voltage drop across the second resistor 32. Equation 18 means that the overdrive voltages of transistors 204 and 205, 24 and 25, are lower than the voltage drop across the second resistor 32.

[0080] If this condition is not met, transistors 204 and 205 (24 and 25) will operate in the linear region, resulting in the problem that the desired drain currents IM204 and IM205 will not flow. Therefore, in the embodiment of the present invention, the circuit constants of transistors 204 and 205, 24 and 25, must be set under the conditions described above. Thus, the differential amplifier in the embodiment of the present invention can achieve a greater improvement in the input offset voltage compared to the case where the prior art disclosed in the patent documents is applied.

[0081] Next, we will explain the second example of a circuit configuration with reference to Figure 3. Note that components identical to those shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This second circuit configuration example has a configuration in which a current mirror circuit 105A is provided in place of the current mirror circuit 105 in the first circuit configuration example. In other words, the current mirror circuit 105A is constructed using transistors 21 to 28, numbered 201 to 208, which are PMOSFETs. This current mirror circuit 105A is based on the circuit configuration of the current mirror circuit 105 shown in Figure 1, with transistors 206 to 208, 26 to 28, added as described below.

[0082] First, the circuit connections for transistors 201 to 203 (21-23) are identical to those shown in Figure 1, except for the drain side. Similarly, the circuit connections for transistors 204 and 205 (24 and 25) are identical to those shown in Figure 1. Therefore, a detailed explanation of these connections will be omitted, and the following explanation will focus on the differences.

[0083] First, transistors 206 through 208, 26 through 28, have their gates interconnected and are connected to the drain of transistor 206, 26. Furthermore, the source of the 206th transistor (cascode input stage transistor) 26 is connected to the drain of the 201st transistor 21, the source of the 207th transistor (first cascode output stage transistor) 27 is connected to the drain of the 202nd transistor 22, and the source of the 208th transistor (second cascode output stage transistor) 28 is connected to the drain of the 203rd transistor 23.

[0084] Furthermore, the drain of transistor 206 (26) is connected to input terminal P1, the drain of transistor 207 (27) is connected to output terminal P2, and the drain of transistor 208 (28) is connected to output terminal P3. Furthermore, in the circuit diagram shown in Figure 3, the circuit diagram in which the current mirror circuit 105A enclosed by the dotted line is represented as a block is identical to the circuit diagram shown earlier in Figure 2.

[0085] Next, the circuit operation of the second circuit configuration example in the above-described configuration will be explained. In this second example of circuit configuration, the current mirror circuit 105A has a cascode current mirror configuration. Specifically, transistors 201 (21) and 206 (26), 202 (22) and 207 (27), and 203 (23) and 208 (28) are connected in a cascode configuration to form part of the current mirror.

[0086] By adopting this cascode current mirror configuration, the power supply voltage dependence of the currents IM202 and IM203 flowing into the third resistor 33 and the fourth resistor 34 is suppressed, and as a result, the power supply voltage dependence of the input offset voltage is also suppressed. In this second circuit configuration example, as with the first circuit configuration example, the circuit constants of transistors 204 and 205, 24 and 25, must satisfy the conditions shown in Equation 18 above.

[0087] Next, we will explain a third circuit configuration example with reference to Figure 4. Note that components identical to those shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This third circuit configuration example has a configuration in which a first current mirror circuit (indicated as "CM2" in Figure 4) 105B-1 and a second current mirror circuit (indicated as "CM3" in Figure 4) 105B-2 are provided in place of the current mirror circuit 105 in the first circuit configuration example, and a tail current supply circuit 104A is provided in place of the tail current supply circuit 104 in the first circuit configuration example.

[0088] First, the tail current supply circuit 104A has the same configuration as the tail current supply circuit 104 shown in the first circuit configuration example, with the addition of an NMOSFET transistor 102 (labeled "M102" in Figure 4). In other words, the gate of the 102nd transistor 16 is interconnected with the gates of the 101st transistor 15 and the 11th and 12th transistors 11 and 12, and is connected to the drain of the 11th transistor 11. Furthermore, the source of the 102nd transistor 16 is connected to the negative power supply voltage terminal 44, while its drain is connected to the input terminal P11 of the first current mirror circuit 105B-1, which will be described below.

[0089] The first current mirror circuit 105B-1 is composed of transistors 202 and 203 (first and second output stage transistors for the first current mirror) 22 and 23, and transistor 211 (labeled "M211" in Figure 4) 29. Furthermore, the second current mirror circuit 105B-2 is configured to include a 201st transistor (input stage transistor for the second current mirror) 21, and 204th and 205th transistors (first and second output stage transistors for the second current mirror) 24 and 25. Both the first and second current mirror circuits 105B-1 and 105B-2 utilize PMOSFETs.

[0090] In the first current mirror circuit 105B-1, the 211th transistor (the input stage transistor for the first current mirror) 29, and the 202nd and 203rd transistors 22 and 23 have their gates interconnected and are connected to the drain of the 211th transistor 29, which in turn is connected to the input terminal P11. The drain of the aforementioned transistor 102, transistor 16, is connected to this input terminal P11.

[0091] Furthermore, transistor 211 (29), and transistors 202 and 203 (22 and 23) have their sources interconnected and are connected to the positive power supply voltage terminal 43 via a common potential terminal P10. Furthermore, the drain of the 202nd transistor 22 is connected via the output terminal P12 to the connection point between the drain of the third transistor 3, the third resistor 33, and the source of the seventh transistor 7. Furthermore, the drain of the 203rd transistor 23 is connected via the output terminal P13 to the connection point between the drain of the 4th transistor 4, the 4th resistor 34, and the source of the 8th transistor 8.

[0092] Next, in the second current mirror circuit 105B-2, the 201st transistor 21 and the 204th and 205th transistors 24 and 25 have their gates interconnected and are also connected to the drain of the 201st transistor 21. The drain of this 201st transistor 21 is then connected to the drain of the 101st transistor 15 via the input terminal P21.

[0093] Furthermore, transistors 201 (21), 204 (204), and 205 (24, 25) have their sources interconnected and are connected to the positive power supply voltage terminal 43 via a common potential terminal P20. Furthermore, the drain of the 204th transistor 24 is connected via the output terminal P22 to the connection point between the drain of the second transistor 2, the second resistor 32, and the source of the sixth transistor 6.

[0094] Furthermore, the drain of the 205th transistor 25 is connected via the output terminal P23 to the connection point between the drain of the first transistor 1, the first resistor 31, and the source of the fifth transistor 5. Figure 5 shows a circuit diagram in which the first and second current mirror circuits 105B-1 and 105B-2 are represented as blocks. In the following explanation of circuit operation, please refer to Figure 4, and the explanation of the circuit operation in Figure 4 will be used in place of the explanation of the circuit operation in Figure 5.

[0095] In this configuration, the first current mirror circuit 105B-1 has short channel widths W and long channel lengths L for transistors 211 (29), 202 (22), and 203 (23), thereby suppressing the channel length modulation effect. As a result, in this third circuit configuration example, the power supply voltage dependence of the drain currents IM202 and IM203 is suppressed.

[0096] On the other hand, in the second current mirror circuit 105B-2, the channel width W of transistor 201 21, transistor 204 24, and transistor 205 25 is set to be long and the channel length L is set to be short, thereby reducing the overdrive voltage. As a result, it is easier to set the circuit constants that satisfy equation 18 above in order to operate transistors 204 and 205 24 and 25 in a saturated state. Thus, in this third circuit configuration example, by providing two current mirror circuits 105B-1 and 105B-2, the setting of circuit constants is easier compared to the first and second circuit configuration examples described earlier.

[0097] Next, we will explain the fourth circuit configuration example with reference to Figure 6. Note that components identical to those shown in the configuration examples in Figure 1 or Figure 4 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This fourth circuit configuration example has a configuration in which the first current mirror circuit 105C having the following configuration is provided instead of the first current mirror circuit 105B-1 shown in Figure 4. The first current mirror circuit 105C is composed of transistor 211 29, transistors 202 and 203 22 and 23, and resistors 101 to 103 75 to 77 (labeled "R101", "R102", and "R103" respectively in Figure 6).

[0098] This first current mirror circuit 105C has the same configuration as the first current mirror circuit 105B-1 shown in Figure 4, with the addition of resistors 101 to 103 (first to third adjustment resistors) 75 to 77 as described below. In other words, resistors 75-77, numbered 101 through 103, are located between the sources of transistor 29 (numbered 211), transistors 22 and 23 (numbered 202 and 203), and the common potential terminal P10.

[0099] Specifically, resistor 101 75 is connected in series between the source of transistor 29 211 and the common potential terminal P10, resistor 102 76 is connected in series between the source of transistor 202 22 and the common potential terminal P10, and resistor 103 77 is connected in series between the source of transistor 203 23 and the common potential terminal P10. In this configuration, the inclusion of resistors 75-77 numbered 101 to 103 further suppresses the power supply voltage dependence of the drain currents IM202 and IM203 of transistors 202 and 203.

[0100] Next, we will explain the fifth circuit configuration example with reference to Figure 7. Note that components identical to those shown in the configuration examples in Figure 1 or Figure 6 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This fifth circuit configuration example differs from the fourth circuit configuration example shown in Figure 6 in that the resistors 76 and 77 of the 102nd and 103rd resistors (76A and 77A, respectively, are variable resistors with adjustable resistance values) (in Figure 7, they are labeled "R102A" and "R102B," respectively). The remaining parts are basically the same configuration.

[0101] In this configuration, the input offset voltage can be adjusted by trimming the drain currents IM202 and IM203, which flow only during NMOS differential pair operation, using the variable resistors 76A and 77A of the 102nd and 103rd resistors. In other words, this fifth circuit configuration example allows adjustment of only the input offset voltage during NMOS differential pair operation while maintaining the input offset voltage during PMOS differential pair operation.

[0102] Next, we will explain the sixth circuit configuration example with reference to Figure 8. Note that components identical to those shown in the configuration examples in Figure 1 or Figure 4 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This sixth circuit configuration example has the following characteristics: the first current mirror circuit 105B-1 in the third circuit configuration example shown in Figure 4, the first current mirror circuit 105C in the fourth circuit configuration example shown in Figure 6, and the first current mirror circuit 105D in the fifth circuit configuration example shown in Figure 7 are replaced with an offset adjustment circuit 100; and similarly, the tail current supply circuit 104A in each circuit configuration example is replaced with a tail current supply circuit 104.

[0103] In other words, the sixth circuit configuration example has the same configuration as those in Figures 4, 6, and 7, respectively, except for the circuit portion in which the offset adjustment circuit 100 is provided. The specific circuit configuration will be explained below. First, the offset adjustment circuit 100 is configured to be installed between the first constant current source 71 and the output stage of the second differential pair 102.

[0104] This offset adjustment circuit 100 is configured to have 202nd and 203rd transistors (first and second transistors for the offset adjustment circuit) 22, 23. The 202nd and 203rd transistors 22 and 23 have their gates interconnected and are also connected to the gate of the 10th transistor 10 via a common potential terminal P101.

[0105] Furthermore, the sources of transistors 202 and 203, 22 and 23, are interconnected and also connected to the source of transistor 10 via input terminal P102. Furthermore, the drain of the 202nd transistor 22 is connected via the output terminal P103 to the connection point between the drain of the third transistor 3 and the third resistor 33. Furthermore, the drain of the 203rd transistor 23 is connected via the output terminal P104 to the connection point between the drain of the 4th transistor 4 and the 4th resistor 34.

[0106] Figure 9 shows a circuit diagram of the offset adjustment circuit (labeled "OF-AJD" in Figure 9) 100 as a block. In the following explanation of circuit operation, please refer to Figure 8, and the explanation of the circuit operation in Figure 8 will be used in place of the explanation of the circuit operation in Figure 9. This sixth circuit configuration example enables the achievement of low current consumption, as will be described below.

[0107] First, during NMOS differential pair operation, a portion of the current I1 flowing from the first constant current source 71 flows into the offset adjustment circuit 100 as current IP102. This current IP102 is divided by transistors 202 and 203, 22 and 23, to become current IM202 and current IM203, which then flow into the third and fourth resistors 33 and 34. In this way, by using a portion of the current I1 from the first constant current source 71 as the current flowing into the third and fourth resistors 33 and 34, low current consumption is made possible.

[0108] In this sixth circuit configuration example, unlike the previous examples, the magnitudes of the currents IM204 and IM205 flowing through transistors 204 and 205 (204 and 205, respectively) during NMOS differential pair operation are not necessarily half the magnitude of the current I1 of the first constant current source 71. Therefore, the magnitudes of the drain currents IM204 and IM205 need to be adjusted as appropriate using a simulator or similar method.

[0109] Next, we will explain the seventh circuit configuration example with reference to Figure 10. Note that components identical to those shown in the configuration examples in Figure 1 or Figure 4 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This seventh circuit configuration example uses only one of the first current mirror circuits, 105B-1, instead of the configurations using the two current mirror circuits shown in Figures 4, 6, and 7. Figure 11 shows a circuit diagram representing the first current mirror circuit 105B-1 in Figure 10 as a block. In the following explanation of circuit operation, please refer to Figure 10, and the explanation of the circuit operation in Figure 10 will be used in place of the explanation of the circuit operation in Figure 11.

[0110] This seventh circuit configuration example requires fewer components compared to the circuit configuration examples already described, and therefore, the chip area has been reduced. Furthermore, during NMOS differential pair operation, the drain currents IM202 and IM203 flowing through transistors 22 and 23 (numbers 202 and 203) need to be adjusted using a simulator or similar tool to minimize the input offset voltage.

[0111] In the circuit configuration example described earlier, the drain currents IM202 and IM203 were half the current I1 of the first constant current source 71. However, in this seventh circuit configuration example, unlike before, the only additional currents flowing into the differential amplifier during NMOS differential pair operation are the drain currents IM202 and IM203. Therefore, the input offset voltage is adjusted only by the drain currents IM202 and IM203.

[0112] Next, we will explain the eighth example of a circuit configuration with reference to Figure 12. Note that components identical to those shown in the configuration examples in Figures 1, 6, or 10 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This eighth circuit configuration example has a configuration in which the first current mirror circuit 105B-1 in the seventh circuit configuration example above is replaced with the first current mirror circuit 105C (see Figure 6).

[0113] In this eighth circuit configuration example, the inclusion of resistors 75-77, numbered 101 to 103, suppresses the power supply voltage dependence of the drain currents IM202 and IM203 of transistors 202 and 203, numbered 202 and 203. Therefore, this eighth circuit configuration example makes it possible to suppress the power supply voltage dependence of the input offset voltage.

[0114] Next, we will explain the ninth circuit configuration example with reference to Figure 13. Note that components identical to those shown in the configuration examples in Figures 1, 7, or 12 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This ninth circuit configuration example has a configuration in which the first current mirror circuit 105D, shown earlier in Figure 7, is provided instead of the first current mirror circuit 105C in the eighth circuit configuration example shown in Figure 12.

[0115] In this configuration, the input offset voltage can be adjusted by trimming the drain currents IM202 and IM203, which flow only during NMOS differential pair operation, using the variable resistors 76A and 77A of the 102nd and 103rd resistors. In other words, this ninth circuit configuration example allows adjustment of only the input offset voltage during NMOS differential pair operation while maintaining the input offset voltage during PMOS differential pair operation.

[0116] Next, we will explain the tenth example circuit configuration with reference to Figure 14. Note that components identical to those shown in Figure 1 or Figure 8 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This tenth circuit configuration example is obtained by replacing the offset adjustment circuit 100 in the sixth circuit configuration example shown in Figure 8 with the second offset adjustment circuit 200, and replacing the tail current supply circuit 104 with the tail current supply circuit 104B.

[0117] First, the second offset adjustment circuit 200 is configured to have transistors 202 to 205 (first to fourth transistors for the offset adjustment circuit) 22 to 25. Furthermore, the tail current supply circuit 104B is configured to include the 10th to 12th transistors 10 to 12. The specific circuit configuration will be explained below. The second offset adjustment circuit 200 has the gates of transistors 202 to 205 (22-25) interconnected, and is also connected to the gate of transistor 10 (10) via a common potential terminal P101.

[0118] Furthermore, transistors 202 through 205 (22-25) have their sources interconnected and are also connected to the source of transistor 10 (10) via input terminal P102. Furthermore, the drain of the 202nd transistor 22 is connected via the output terminal P103 to the connection point between the drain of the third transistor 3 and the third resistor 33.

[0119] Furthermore, the drain of the 203rd transistor 23 is connected via the output terminal P104 to the connection point between the drain of the 4th transistor 4 and the 4th resistor 34. Furthermore, the drain of the 204th transistor 24 is connected via the output terminal P105 to the connection point between the drain of the first transistor 1 and the first resistor 31. Furthermore, the drain of the 205th transistor 25 is connected via the output terminal P106 to the connection point between the drain of the second transistor 2 and the second resistor 32.

[0120] On the other hand, the tail current supply circuit 104B has a configuration that excludes the 101st transistor 15 in the tail current supply circuit 104 of the first circuit configuration example shown in Figure 1, and a further detailed explanation of the circuit configuration will be omitted here.

[0121] Figure 15 shows a circuit diagram representing the second offset adjustment circuit 200 in Figure 14 as a block. In the following explanation of circuit operation, please refer to Figure 14, and the explanation of circuit operation in Figure 14 will be used in place of the explanation of circuit operation in Figure 15.

[0122] This tenth circuit configuration example enables the creation of a differential amplifier with lower current consumption than the previous examples. The reason for this lower current consumption is explained below. During NMOS differential pair operation, a portion of the current I1 flowing from the first constant current source 71 flows into the second offset adjustment circuit 200 as current IP102. This current IP102 is divided by transistors 202 to 205, numbered 22 to 25, to become currents IM202 to IM205.

[0123] Then, current IM202 flows into the third resistor 33, and current IM203 flows into the fourth resistor 34. Furthermore, the current IM204 flows into the connection point between the first resistor 31, the drain of the first transistor 1, and the source of the fifth transistor 5. Furthermore, the current IM205 flows into the connection point between the second resistor 32, the drain of the second transistor 2, and the source of the sixth transistor 6. Thus, in the tenth circuit configuration example, a portion of the current I1 from the first constant current source 71 is reused as the current supplied to the differential amplifier, thereby enabling reduced current consumption.

[0124] Furthermore, in this tenth circuit configuration example, when setting the constants of transistors 24 and 25 of the 204th and 205th, the conditions of equation 19 below must be satisfied.

[0125] Vref1+VthM204=Vref1+VthM205>VDD-VR2...Formula 19

[0126] Here, Vref1 is the reference voltage applied externally to the reference voltage terminal 45, VthM204 is the absolute value of the threshold voltage of the 204th transistor 24, VthM205 is the absolute value of the threshold voltage of the 205th transistor 25, VDD is the positive power supply voltage, and VR2 is the voltage drop across the second resistor 32.

[0127] The condition in equation 19 indicates that transistors 204 and 205, 24 and 25, operate in the saturation region. The derivation process of Equation 19 is explained below. First, since the gate potential of transistor 24 (No. 204) is Vref1, the source potential is expressed by equation 20 below.

[0128] Source potential of transistor 24 (No. 204) = Vref1 + VgsM204 = Vref1 + VthM204 + VovM204 ... Equation 20

[0129] Here, VgsM204 is the absolute value of the potential difference between the gate and source of transistor 204 24, and VovM204 is the overdrive voltage of transistor 204 24. Therefore, as shown in Equation 21 below, the drain potential of transistor 204 is the source potential of transistor 204 that is lower by the overdrive voltage.

[0130] Drain potential of transistor 24 (No. 204) = Vref1 + VthM204 ... Equation 21

[0131] This is the drain potential of transistor 24, which is the left-hand side of equation 19, the conditional equation required for this tenth circuit configuration example. For example, if the positive power supply voltage VDD = 5V, Vref1 = 3.7V, VthM204 = 0.7V, and VovM204 = 0.2V, the source potential of transistor 204 24 will be 4.6V. Subtracting VovM204 = 0.2V from this source potential gives 4.4V, which is the drain potential of transistor 204 24. This 4.4V can also be derived using equation 21. In this case, the potential at the connection point between the first resistor 31 and transistor 204 24, and the potential at the connection point between the second resistor 32 and transistor 205 25, must be lower than 4.4V. The above explains the meaning of Equation 19.

[0132] Thus, this tenth circuit configuration example allows for lower current consumption compared to the previous circuit configuration examples. Note that during NMOS differential pair operation, the drain currents IM202 to IM204 flowing through transistors 22 to 25 (202 to 205) need to be adjusted using a simulator or similar tool to minimize the input offset voltage.

[0133] In the first to tenth circuit configuration examples described above, circuit configurations using CMOS elements were explained. However, the present invention is not limited to CMOS elements, and can also be configured using bipolar elements. Figure 16 shows circuit diagrams in which the NMOS transistors, which are CMOS elements in the circuit configuration examples shown in Figures 1 and 2, are replaced with NPN bipolar transistors, and similarly, the PMOS transistors are replaced with PNP bipolar transistors. In Figure 1, the letter "M" used to represent a CMOS element is replaced with "Q" in Figure 16 to represent a bipolar transistor.

[0134] Regarding the specific circuit connections, since they are basically the same as the circuit configuration explained earlier in Figures 1 and 2, simply by replacing the gate of the MOS transistor with the base of the bipolar transistor, the source of the MOS transistor with the emitter of the bipolar transistor, and the drain of the MOS transistor with the collector of the bipolar transistor, a further detailed explanation will be omitted here. [Industrial applicability]

[0135] This method can be applied to differential amplifiers where a more reliable improvement in input offset voltage is desired compared to conventional methods for improving input offset voltage. [Explanation of symbols]

[0136] 100...Offset adjustment circuit 101...First differential pair 102...Second differential pair 104, 104A, 104B... Tail current supply circuit 105, 105A, 105C, 105D… Current mirror circuits 105B-1…First current mirror circuit 105B-2…Second current mirror circuit 200...Second offset adjustment circuit

Claims

1. A differential amplifier comprising a first differential pair configured to be differentially amplified using N-channel MOSFETs and a second differential pair configured to be differentially amplified using P-channel MOSFETs, provided in parallel with respect to the input, and configured so that the outputs of each are summable, A current mirror circuit is provided, and the current mirror circuit is The output stage of the first differential pair and the output stage of the second differential pair are configured to be able to supply current to each of them, This makes it possible to suppress voltage fluctuations in the output stages of the first and second differential pairs due to the switching of operation between the first and second differential pairs in response to changes in the common-mode input voltage. A tail current supply circuit is provided to supply the tail current of the first differential pair. The current mirror circuit comprises an input stage transistor using a P-channel MOSFET and first to fourth output stage transistors. The sources of the input stage transistor and the sources of the first to fourth output stage transistors are interconnected to allow a positive power supply voltage to be applied. The gates of the input stage transistor and the gates of the first to fourth output stage transistors are interconnected and connected to the drains of the input stage transistors. The drains of the input stage transistors are connected to the output stage of the tail current supply circuit. A differential amplifier characterized in that the drains of the first and second output stage transistors are connected to the two output stages of the second differential pair, and the drains of the third and fourth output stage transistors are connected to the two output stages of the first differential pair.

2. Between the drain of the input stage transistor and the output stage of the tail current supply circuit, a cascode input stage transistor using a P-channel MOSFET is provided. The source of the cascode input stage transistor is connected to the drain of the input stage transistor, and the drain of the cascode input stage transistor, along with its gate, is connected to the output stage of the tail current supply circuit. A first cascode output stage transistor is provided between the drain of the first output stage transistor and one of the output stages of the second differential pair. The source of the first cascode output stage transistor is connected to the drain of the first output stage transistor, the gate of the first cascode output stage transistor is connected to the gate of the cascode input stage transistor, and the drain of the first cascode output stage transistor is connected to one of the output stages of the second differential pair. The differential amplifier according to claim 1, characterized in that a second cascode output stage transistor is provided between the drain of the second output stage transistor and the other output stage of the second differential pair, the source of the second cascode output stage transistor is connected to the drain of the second output stage transistor, the gate of the second cascode output stage transistor is connected to the gate of the cascode input stage transistor, and the drain of the second cascode output stage transistor is connected to the other output stage of the second differential pair.

3. The first differential pair is configured such that the gate of the first transistor for the first differential pair is connected to the inverting input terminal, and the gate of the second transistor for the first differential pair is connected to the non-inverting input terminal. The positive power supply voltage is applied to the drain of the first transistor for the first differential pair via a first resistor, and to the drain of the second transistor for the first differential pair via a second resistor. The differential amplifier according to claim 1 or 2, characterized in that the overdrive voltage of the fourth output stage transistor connected to the drain of the first differential pair first transistor is equal to the overdrive voltage of the third output stage transistor connected to the drain of the first differential pair second transistor, and is set to be less than or equal to the voltage drop across the second resistor.

4. A differential amplifier comprising a first differential pair configured to be differentially amplified using N-channel MOSFETs and a second differential pair configured to be differentially amplified using P-channel MOSFETs, provided in parallel with respect to the input, and configured so that the outputs of each are summable, A first current mirror circuit and a second current mirror circuit are provided. The first current mirror circuit is configured to supply current to the output stage of the second differential pair, The second current mirror circuit is configured to supply current to the output stage of the first differential pair, This makes it possible to suppress voltage fluctuations in the output stages of the first and second differential pairs due to the switching of operation between the first and second differential pairs in response to changes in the common-mode input voltage. The first and second current mirror circuits described above are made using P-channel MOSFETs. The first current mirror circuit comprises a first current mirror input stage transistor and first and second output stage transistors for the first current mirror. The second current mirror circuit comprises a second current mirror input stage transistor and first and second output stage transistors for the second current mirror. In the first current mirror circuit, the source of the first current mirror input stage transistor and the sources of the first and second output stage transistors for the first current mirror are interconnected so that a positive power supply voltage can be applied. The gate of the first current mirror input stage transistor and the gates of the first and second output stage transistors for the first current mirror are interconnected and connected to the drain of the first current mirror input stage transistor, and the drain of the first current mirror input stage transistor is connected to the output stage of the tail current supply circuit. The drains of the first and second output stage transistors for the first current mirror are connected to the two output stages of the second differential pair, respectively. In the second current mirror circuit, the source of the input stage transistor for the second current mirror and the sources of the first and second output transistors for the second current mirror are interconnected so that a positive power supply voltage can be applied. The gate of the input stage transistor for the second current mirror and the gates of the first and second output stage transistors for the second current mirror are interconnected and connected to the drain of the input stage transistor for the second current mirror, and the drain of the input stage transistor for the second current mirror is connected to the output stage of the tail current supply circuit. A differential amplifier characterized in that the drains of the first and second output stage transistors for the second current mirror are connected to the two output stages of the first differential pair, respectively.

5. The differential amplifier according to claim 4, characterized in that the source of the first current mirror input stage transistor is connected via a first adjustment resistor, the source of the first current mirror first output stage transistor is connected via a second adjustment resistor, and the source of the first current mirror second output stage transistor is connected via a third adjustment resistor, all of which are connected to the positive power supply voltage.

6. The differential amplifier according to claim 5, characterized in that the second and third adjustment resistors are variable resistors configured to have variable resistance values.

7. A differential amplifier comprising a first differential pair configured to be differentially amplified using N-channel MOSFETs and a second differential pair configured to be differentially amplified using P-channel MOSFETs, provided in parallel with respect to the input, and configured so that the outputs of each are summable, An offset adjustment circuit and a second current mirror circuit are provided. The offset adjustment circuit is configured to supply current to the output stage of the second differential pair, The second current mirror circuit is configured to supply current to the output stage of the first differential pair, This makes it possible to suppress voltage fluctuations in the output stages of the first and second differential pairs due to the switching of operation between the first and second differential pairs in response to changes in the common-mode input voltage. The offset adjustment circuit comprises first and second transistors for the offset adjustment circuit, each using a P-channel MOSFET. The gates of the first and second transistors for the offset adjustment circuit are connected to each other so that an external reference voltage can be applied. The sources of the first and second transistors for the offset adjustment circuit are connected to the first constant current source, which is the current source for the second differential pair, The drain of the first transistor for the offset adjustment circuit is connected to one output stage of the second differential pair, and the drain of the second transistor for the offset adjustment circuit is connected to the other output stage of the second differential pair. In the second current mirror circuit, the source of the input stage transistor for the second current mirror and the sources of the first and second output transistors for the second current mirror are interconnected so that a positive power supply voltage can be applied. The gate of the input stage transistor for the second current mirror and the gates of the first and second output stage transistors for the second current mirror are interconnected and connected to the drain of the input stage transistor for the second current mirror, and the drain of the input stage transistor for the second current mirror is connected to the output stage of the tail current supply circuit. A differential amplifier characterized in that the drains of the first and second output stage transistors for the second current mirror are connected to the two output stages of the first differential pair, respectively.

8. The first differential pair is configured such that the gate of the first transistor for the first differential pair is connected to the inverting input terminal, and the gate of the second transistor for the first differential pair is connected to the non-inverting input terminal. The positive power supply voltage is applied to the drain of the first transistor for the first differential pair via a first resistor, and to the drain of the second transistor for the first differential pair via a second resistor. A differential amplifier according to any one of claims 4 to 7, characterized in that the overdrive voltage of the second output stage transistor for the second current mirror, which is connected to the drain of the first differential pair transistor, is equal to the overdrive voltage of the first output stage transistor for the second current mirror, which is connected to the drain of the first differential pair transistor, and is set to be less than or equal to the voltage drop across the second resistor.

9. A differential amplifier comprising a first differential pair configured to be differentially amplified using N-channel MOSFETs and a second differential pair configured to be differentially amplified using P-channel MOSFETs, provided in parallel with respect to the input, and configured so that the outputs of each are summable, A first current mirror circuit is provided. The first current mirror circuit is configured to supply current to the output stage of the second differential pair, A differential amplifier characterized by its ability to suppress voltage fluctuations in the output stages of the first and second differential pairs caused by the switching of operation between the first and second differential pairs in response to changes in the common-mode input voltage.

10. The first current mirror circuit comprises a first current mirror input stage transistor using a P-channel MOSFET, and first and second output stage transistors for the first current mirror. The source of the first current mirror input stage transistor and the sources of the first and second output stage transistors for the first current mirror are interconnected so that the positive power supply voltage can be applied. The gate of the first current mirror input stage transistor and the gates of the first and second output stage transistors for the first current mirror are interconnected and connected to the drain of the first current mirror input stage transistor, and the drain of the first current mirror input stage transistor is connected to the output stage of the tail current supply circuit. The differential amplifier according to claim 9, characterized in that the drains of the first and second output stage transistors for the first current mirror are connected to the two output stages of the second differential pair, respectively.

11. The differential amplifier according to claim 10, characterized in that the source of the first current mirror input stage transistor is connected to a first adjustable resistor, the source of the first current mirror first output stage transistor is connected to a second adjustable resistor, and the source of the first current mirror second output stage transistor is connected to a third adjustable resistor, all of which are connected to the positive power supply voltage.

12. The differential amplifier according to claim 11, characterized in that the second and third adjustment resistors are variable resistors configured to have variable resistance values.

13. A differential amplifier comprising a first differential pair configured to be differentially amplified using N-channel MOSFETs and a second differential pair configured to be differentially amplified using P-channel MOSFETs, provided in parallel with respect to the input, and configured so that the outputs of each are summable, A second offset adjustment circuit is provided. The second offset adjustment circuit is configured to supply current to the output stages of the first and second differential pairs, respectively. This makes it possible to suppress voltage fluctuations in the output stages of the first and second differential pairs due to the switching of operation between the first and second differential pairs in response to changes in the common-mode input voltage. The second offset adjustment circuit comprises first to fourth transistors for the offset adjustment circuit, each using a P-channel MOSFET. The gates of the first to fourth transistors for the offset adjustment circuit are interconnected so that an external reference voltage can be applied to them. The sources of the first to fourth transistors for the offset adjustment circuit are connected to the first constant current source, which is the current source for the second differential pair, The drain of the first transistor for the offset adjustment circuit is connected to one of the output stages of the second differential pair. The drain of the second transistor for the offset adjustment circuit is connected to the output stage of the other side of the second differential pair. The drain of the third transistor for the offset adjustment circuit is connected to one of the output stages of the first differential pair. A differential amplifier characterized in that the drains of the fourth transistor for the offset adjustment circuit are connected to the other output stage of the first differential pair.

14. The first differential pair is configured such that the gate of the first transistor for the first differential pair is connected to the inverting input terminal, and the gate of the second transistor for the first differential pair is connected to the non-inverting input terminal. The positive power supply voltage is applied to the drain of the first transistor for the first differential pair via a first resistor, and to the drain of the second transistor for the first differential pair via a second resistor. The differential amplifier according to claim 13, characterized in that the value obtained by adding the reference voltage to the absolute value of the threshold voltage of the third transistor for the offset adjustment circuit connected to the drain of the first differential pair first transistor is equal to the value obtained by adding the reference voltage to the absolute value of the threshold voltage of the fourth transistor for the offset adjustment circuit connected to the drain of the second transistor for the first differential pair, and is set to be greater than the value obtained by subtracting the voltage drop across the second resistor from the positive power supply voltage.

15. A differential amplifier according to any one of claims 1, 2, 4 to 7, or 9 to 13, characterized in that it uses bipolar elements instead of CMOS elements.

Images